WR Switch gateware

Figure 1 shows the internals of the WR Switch HDL design. It contains numerous modules connected with the Wishbone Crossbar. Each of them has a Wishbone Slave interface and a number of configuration registers that are read/written from main CPU through the CPU EBI/WB bridge (WB Master interface). Blue arrows in the figure represent the WR Frabric interface connections responsible for passing Ethernet frames between the Endpoints, Switching Core and Network Interface Controller.


Fig. 1: Top HDL design of the WR Switch

Real-Time Subsystem

It contains modules responsible for the timekeeping. The components are internally connected through WB crossbar (fig. 2) and controlled from Lattice Mico 32 and main CPU (through primary WB crossbar in the top design).


Fig. 2: Internal layout of Real-Time Subsystem component


Getting Started with switch gateware (HDL) development

If you want to simulate or synthesize the WR switch gateware, have a look at the Getting started with switch gateware development wiki page.


Roadmap for gateware releases

v4.0 v4.2 v5.0 planned after v5.x
Release date 8/08/2014 28/08/2015 16/12/2016
Per-Port statistics x
Endpoint events for PSTATS x
VLAN support x
Improved Ethernet switching performance x
Rewritten ext channel of SoftPLL x
Fixed crashes under burst of frames x
Fixed random port stalls x
Fixed SoftPLL to detect loss of 10MHz reference x
SDB support x
HDL Watchdog module x
Improved PSTATs for timing closure x
Bandwidth throttling for ARM x
Fixed forwarding to active ports only x
Counting frames from ARM x
Faster Multiport Linked List for Switching Core x
Topology Resolution Unit x
Time Aware Traffic Shaper x

For v3.x features please check previous releases wiki page.


16 December 2016

switch_hdl.png (73.9 kB) Grzegorz Daniluk, 2013-05-23 14:25

rt_sub.png (30.5 kB) Grzegorz Daniluk, 2013-05-23 14:25