Grzegorz Daniluk

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  • Registered on: 2011-01-21
  • Last connection: 2016-10-06

Projects

Activity

Reported issues: 147

2017-02-16

16:15 White Rabbit core collection Bug #1510 (Closed): WARNING:HDLCompiler:89 (Black-Box)
16:14 White Rabbit core collection Bug #1533 (Closed): Xilinx ISE fails to infer dpram with byte-write enables
16:13 Software for White Rabbit PTP Core Bug #1360 (Closed): GUI doesn't show IP address before lock
16:12 White Rabbit core collection Feature #1006 (Closed): Improve WRPC synthesis time
16:11 Software for White Rabbit PTP Core Bug #1320 (Resolved): softpll doesn't set Locked flag for the main channel
fixed with commit:
64df75a softpll: write to OCCR register also when main and ext channels are locked (not only aux)

2017-02-14

13:25 White Rabbit core collection Bug #1533 (Closed): Xilinx ISE fails to infer dpram with byte-write enables
general-cores commits:
0973db5 wb_dpram: no need to split into 4 BRAMs with generic_dpram_split inside generic_dpram...
11:28 White Rabbit core collection Bug #1533 (Closed): Xilinx ISE fails to infer dpram with byte-write enables
11:25 White Rabbit core collection Feature #1006 (Closed): Improve WRPC synthesis time
Commit
c283c21: genrams: simplify RAM initialization during synthesis
in general-cores repository changes the forma...

2017-02-03

18:01 White Rabbit core collection Bug #1406 (Resolved): Rewrite Mini NIC with FIFOs
done with a set of commits:
443c058 minic: work in progress, use fifos
to
934eb7f update wrc.ram for new fifo-base...

2017-01-26

16:13 White Rabbit core collection Bug #1225 (Resolved): wr_core: ouput vectors for g_aux_clks=0
got solved together with issue "1124":/issues/1224

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