Grzegorz Daniluk

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  • Registered on: 2011-01-21
  • Last connection: 2017-04-20

Projects

Activity

Reported issues: 153

2017-05-18

17:33 White Rabbit Switch - Software Bug #1574 (New): check syslog logs format
17:30 White Rabbit Switch - Software Bug #1571 (New): case-sensitive input to rtu_stat
17:30 White Rabbit Switch - Software Feature #1569 (New): Include kerberos authentication

2017-05-11

19:23 FPGA & ARM SoC FMC Carrier (FASEC) Revision 953715ab: after synthesis, I should really start putting timing constraints..
18:16 FPGA & ARM SoC FMC Carrier (FASEC) Revision e3139120: submodule cores updated for fasec_hwtest v3.2.2, outputs generated
17:03 FPGA & ARM SoC FMC Carrier (FASEC) Revision 08ab5dcf: output products generated
16:01 FPGA & ARM SoC FMC Carrier (FASEC) Revision bc0eb056: submodule cores updated for fasec_hwtest

2017-04-13

11:15 FPGA & ARM SoC FMC Carrier (FASEC) Revision bbdc1b6c: after synthesis, went well with hdl_lib the same version everywhere

2017-04-10

17:52 White Rabbit core collection Bug #1567 (New): SPEC reference design doesn't work on standalone SPEC
17:07 White Rabbit Wiki edit: FAQwr (#33)
1-wire question moved to WRPC FAQ

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