------------------------------------------------------------------------------- SVEC schematics review 03.02.2012 ------------------------------------------------------------------------------- MEETING SUMMARY + DATE 03.02.2012 14:00 - 15:30 + PLACE CERN Prevessin, Building 864, Room 2-A15 + SUBJECT SVEC Review + SVN http://svn.ohwr.org/svec/trunk/circuit_board/SVEC + REVISION 9 + PARTICIPANTS: Serrano, Javier JS javier.serrano@cern.ch Van der Bij, Erik EVB Erik.van.der.Bij@cern.ch Cattin, Matthieu MC matthieu.cattin@cern.ch Alvarez Sanchez, Pablo PAS pablo.alvarez.sanchez@cern.ch Gousiou, Evangelia EG evangelia.gousiou@cern.ch Wlostowski, Tomasz TW tomasz.wlostowski@cern.ch Voumard, Nicolas NV nicolas.voumard@cern.ch Gil Soriano, Carlos CGS carlos.gil.soriano@cern.ch Pedretti, Davide DP davide.pedretti@cern.ch + SUMMARY The goal of the meeting was to check SVEC in depth. It was foreseen to first check the schematics and then go ahead with the layout review. Due to the fact that some relevant errors/inacuracies were found in the sche matics, the layout review was too brief (as it will be further discuss in a later review). -+ SCHEMATICS Special attention should be taken in the FMCs, adding independent control to the AD5662 chips and solve some unconnected lines in the JTAG sheets. -+ LAYOUT The layout can be clearer and work should be done in the arrangement of the power planes. =============================================================================== | ! : fatal | | + : important | | - : minor | | ? : question | | * : note | =============================================================================== =============================================================================== SCHEMATICS + SVEC_TOP.SchDoc --+ AFPGA.SchDoc --+ AFPGA_power.SchDoc --+ ClkGeneration.SchDoc --+ DDR3.SchDoc --+ DDR3_2.SchDoc --+ FMC_CONNECTORS.SchDoc --+ FPGA_GTP.SchDoc --+ FrontPanel.SchDoc --+ JTAG&CONFIG.SchDoc --+ PowerSupplies.SchDoc --+ SFPGA.SchDoc --+ SFPGA_power.SchDoc --+ USB.SchDoc --+ VMEConnectors.SchDoc --> BOM =============================================================================== -------------------------------------- General: -------------------------------------- [JS] + Use a uniform way of connecting LEDs to the FPGA, i.e. either connect to the cathode or to the anode. [JS] - Clean comments in some of the sheets. Many are the result of copy/paste from other boards. [MC] + Use only A3 size for the schematics sheets. The 'top' sheet probably won't fit on an A3, so keep it A2. [MC] + Use the same naming convention for the active low signals (#, _N, n, N). [MC] + Notation with "_N" suffix is prefered. [MC] + Use the same naming convention for the schematics files (e.g. all in lower case). [MC] - Use consitant naming convention for file names. [MC] - OHR project is called SVEC, Altium project SVFC, top schematics VMEFMC. [MC] - SVEC should be used everywhere to avoid confusion. [MC] - Add the OHL license text on all sheets. Copy this text block from the SPEC schematics [MC] - Avoid leaving big empty space on a sheet. [MC] ? AFPGA firmware is loaded by the driver via the SFPGA. No flash?? > AFPGA uses the same flash as the SFPGA. [MC] ? SFPGA flash is programmed by JTAG via the SFPGA? > Yes, or via VME (for the AFPGA part). [NV] + State clearly the orientation of the ports (reduce the number of bidirectionals) [CGS] + All the VME signal should have the same naming (indicating if they are active low) in the schematics. Follow the VME64, VME64x standard. [CGS] - Check the names of designer, project, reviewers,... of every bottom right box of the project (some are pages from SPEC, VFC,...). [CGS] - Place OHL in the same place in every sheet. [CGS] - All comments should be inside a yellow box. -------------------------------------- SVEC_TOP.SchDoc -------------------------------------- [MC] - RSTn net should be RST_N. [TW] ! AFPGA_DONE: two inputs connected together [TW] + WR_TXDISABLE: it goes from the FPGA to the SFP. [TW] ! FMC1_PGCxM reverse direction [CGS] + Suffixes should be added to VME lines: VME_IACK -> VME_IACK_N VME_IACKIN -> VME_IACKIN_N VME_DS1 -> VME_DS1_N so on... [CGS] - Bold and different colours for "System FPGA (booting)" and "Application FPGA" [CGS] - It could be good include banking voltages in top. -------------------------------------- AFPGA.SchDoc: -------------------------------------- [JS] + Make sure the FPGAs always power up with I/Os tri-stated and fix default levels with external pull-ups and pull-downs. [EVB] + PCB rev resistors are in the wrong order: MSB is on the right. [MC] + FMC1_LA_x0 is a prefered pair for clock signal. Therefore it should be connected to a global clock input (-> swap with FMC1_LA_x2 ?). [MC] + LA_00 to LA_16 should be connected to the same half-bank and LA_17 to LA_33 to the other half-bank. [MC] + Connect LA_00 and LA_17 to global clock inputs, for both FMC slots. [MC] + FMC diff. pairs connection to the AFPGA should be reviewed. See http://www.ohwr.org/attachments/246/ClockingFMCs.pdf [MC] - Comment box "LA pins..." can be removed. [TW] + Wire one of the lemos to the global clock input (for example, swap with FMC_SCL2 line) [TW] + NOGAx lines are inputs, not in-outs. [CGS] - I would include a reference to the SSO for Spartan 6 (document DS162). Odd banks are better in terms of SSO: they should have a been a preferred option for placing both the data and address lines of the VME (if layout allows) and distribute the least likely switching lines between banks for balancing transient load. Same for SFPGA. -------------------------------------- AFPGA_power.SchDoc -------------------------------------- [MC] - Overlapping text around encryption componants. [MC] ? What is the reason to put VCCAUX to P3V3? > VCCAUX should be connected to P2V5 as on SPEC. -------------------------------------- ClkGeneration.SchDoc: -------------------------------------- [JS] ! Do not share the SCLK and DIN lines for IC3 and IC7 in the "CLK Generators" page. Have separate lines from the FPGA for each. [EVB] ! OSC4 must be reloaded from CernLib: Si570 oscillator symbol should be reloaded from the CERN library as the Value parameter isn't correct. [MC] - Overlapping text (C200). [MC] - C40 should be "not mounted". [MC] - R16, OSC1 "not mounted" text is red. [MC] - Comment box "Control voltage..." is duplicated. [MC] - IC12/OUTP3, "No DRC" cross can be removed. [TW] ? why Si571 OE line has 5.1k pullup while SDA/SCL lines have 1.1k resistors (they draw some extra current - 3 mA each) [TW] ? R20, R27: why 100 ohm? (the trace impedance on internal layers is ~40 ohm, so the signal is not source-terminated at all) -------------------------------------- DDR3.SchDoc -------------------------------------- [MC] + DDR_CAS and DDR_RAS are active low signals, add "_N". [MC] - Change GND symbol (C206, C235). [TW] - SFPGA_Power: fix the title. [CGS] ? It should be specified the MR1 of the ODT so that the layout is adapted to that impedance. It seems that it is disabled and the controlled trace is 51 Ohm. Why are they not using ODT? -------------------------------------- DDR3_2.SchDoc: -------------------------------------- [MC] + DDR_2_CAS and DDR_2_RAS are active low signals, add "_N". -------------------------------------- FMC_CONNECTORS.SchDoc: -------------------------------------- [EVB] + d1 flag is wrong direction. [EVB] + d1, I believe it should have a 10K pull up to 3V3 (PGC2M) [EVB] - Comment about Vadj is wrong (both are fixed at 2.5V). Put comment text Vadj above lines h40,g39 [MC] ! 22uF on P12V_FMCx are rated 10V! [MC] - Change page name to "FMC connectors". [MC] - Comment box "NB: the LVDS pairs must ..." can be removed. [MC] - FMCxVrefAM2C could be in capital. [MC] - V3P3AuxFMC can be renamed to P3V3_AUX_FMC. [MC] ? What is the pull-up on FMCx_TRST_L for? [PAS] ! The fmc clocks should follow the recommendations. The latest VFC schematic can be used a reference. [TW] - R212, R240, R215, R214: put on the same schematic sheet to improve readability. [TW] ? FMC1_PGC2M lines (pin D1) - it's an input to the FMC. What is the 4.7k series resistor for? [CGS] ! Capacitors C78 and C79 in P12V_FMC1 and P12V_FMC2 are not 12V rated. Change. [CGS] - Fixed lines such as GND could be set as "locked primities", so Altium will place a warning window when messing around with them. -------------------------------------- FPGA_GTP.SchDoc: -------------------------------------- [MC] - The sheet template doesn't fit the sheet size, the title block is in the middle of the page. [MC] - Comment box "GTP123 can be ..." can be removed. [MC] - Lots of empty space on the page. Re-arange a bit. [MC] ? Shouldn't unused GTP input be connected to GND? [TW] - TYPO in J9 : Straigth -> Straight -------------------------------------- FrontPannel.SchDoc: -------------------------------------- [JS] ! Replace front panel lemo buffer by a copy/paste from the DIO FMC. [MC] ! SFP tx and rx pairs are swapped. [MC] - C202 should be "not mounted". [MC] - Overlapping text (C219, C220, C13). [MC] - Debug LEDs are active high and front pannel LEDs are active low. [MC] - Use the same output drivers as on the FMC DIO for the LEMO I/Os. [TW] ! IC16: with 50 ohm serial termination (R204 and friends), it won't be possible to drive a 50 ohm load at TTL levels (2V Voh), because the driver is powered from 3.3V. -------------------------------------- JTAG&CONFIG.SchDoc: -------------------------------------- [MC] ! IC14 is badly connected to the power supply. * VCC must be connected to P3V3, not floating. * VSS must be connected to GND, not to P3V3. [MC] + The board mustn't contain any jumper, it will reduce the number of mistakes and questions. [MC] - BOOT_SEL0 and BOOT_SEL1 in the comment box should probably be removed. [MC] - Change page name to "JTAG Chain + SFPGA Flash". [TW] ! AFPGA_DONE: two inputs connected together [TW] ! WR_TXDISABLE: it goes from the FPGA to the SFP. [TW] ! FMC1_PGCxM reverse direction -------------------------------------- PowerSupplies.SchDoc: -------------------------------------- [EVB] - Power supply comments should be moved to external file. [MC] ! C24 and C41 are rated 6.3V but connected to 12V!! [MC] - "Power estimation" comment box is too small to display all the content. [MC] - ATX connector could be changed for a power SATA connector (as only 5V and 3.3V are needed). [MC] ? LEDs on all voltage rails should be removed, only one LED to indicate that the board is powered is enough. [MC] ? If possible, use only one inductor type. [MC] ? If possible, use only one fuse type. [MC] ? Are all those comment boxes useful? [MC] ? What is "FORCE PSU ON" comment for? [TW] ! From Tom, all 12V for FMC slots (2x 1A) comes from only one VME pin (1A)! A DC/DC should be used to generate P12V from P5V_VME. [TW] ? "FORCE PSU ON" - what does this mean? -------------------------------------- SFPGA.SchDoc: -------------------------------------- [JS] + Make sure the FPGAs always power up with I/Os tri-stated and fix default levels with external pull-ups and pull-downs. [MC] ? What is the reason to put VCCAUX to P3V3? > should be connected to P2V5, as on the SPEC. [MC] - Page name is "USB interface". [MC] - Add bank supply voltage as a comment next to each block. -------------------------------------- USB.SchDoc -------------------------------------- [MC] - Q1 should be "not mounted". [MC] - USB_TCK, USB_TDI, USB_TDO and USB_TMS ports shouldn't be in the not mounted square, it is confusing. [MC] - overlapping text (R224, R225, ...). [MC] - IC17 power supplies are badly connected. > VIO must be connected to P3V3. > GND and EP must be connected to GND. [MC] - The sheet template doesn't fit the sheet size, the title block is in the middle of the page. -------------------------------------- VmeConnectors.SchDoc: -------------------------------------- [MC] + Remove all BI power rails (V15N0BI, V5N2BI, V2N0BI, V5P0BI, V15P0BI). [MC] - "LVDS pairs" comment should be more generic, like "100ohms diff. pairs". [MC] - Use arrow symbol for voltage rails (as on PowerSupplies sheet). [MC] - Change V12P0VME to P12V_VME. [MC] - Change V12N0VME to M12V_VME. [MC] - Change V5P0VME to P5V_VME. [MC] - Change V5P0STDBYVME to P5V_STDBY_VME. [MC] - Add "_N" to active low signals. [PAS] ! vme_dtack_oe should have a pull down or an or gate. HW_SWAP should be set to high impedance in both fpgas (there is already the possibility to do it through configuration resistors). [PAS] ! idem for vme_d_oe, vme_a_oe, vme_d_dir, vme_a_dir and probably some other line. The problem with these lines is that in normal state both fpgas should leave them floating to avoid conflicts between them. It is possible to define a weak pull up or pull up on the fpga but it is probably cleaner to put it on the pcb. The pull down resistor (or eventually pull up) is then needed to define the default value. This has already been done for the irq lines where we had a glitch while reconfiguring the vfc sfpga. [NV] - Andrea Boccardi it is the name of the designer. Should be changed. [DP] ! In the SVEC top schematic these signals are output for the SFPGA, not bidirectional: {VME_RETRY_OE, VME_DTACK_OE, VME_D_DIR, VME_D_OE_N, VME_IACKOUT, VME_IRQ[7...1], VME_RETRY, VME_BERR, VME_A_OE_N, VME_A_DIR, VME_DTACK} (idem for the AFPGA) the input VME_TDO_OE of the buffer IC27 [DP] ! In the VME buffers the logic is inverted for the VME_BERR and VME_IRQ signals -------------------------------------- SFP -------------------------------------- [TW] ! TX and RX pairs are swapped (wrong pin directions in the symbol)!!!! >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>> BOM >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>> [EVB] ? R232 is a Thin Film Chip resistor and the only one of this value 12K. Please replace by other resistor(s). Some Parts with the same part number (other Designator) appear twice in the BOM. Is this because of the No (not mounted) parameter? =============================================================================== LAYOUT =============================================================================== -------------------------------------- GENERAL: -------------------------------------- [EVB] - Top silkscreen: align OHR and http: texts. [MC] + A lot of traces on the bottom are crossing the planes. [MC] - P5V_VME plane is pretty small. [MC] - Add layer number to layer names. [MC] - P1V2 and P1V5 planes should be reviewed. [MC] ? Conductive cooling? [MC] ? Cutout under FMC slots? > Should be continous, to avoid short cuts in case the PCB is removed. [TW] ! Cleanup required. Vias are touching pads, there are acute bends and loops on many traces. Routing is sometimes very dirty. [TW] + Connect big caps (C13, C241, etc.) to the GND/VCC with more than one 0.2mm/0.4mm via. [TW] + You have 3 different kinds of vias. the biggest ones (0.7mm drill) could be replaced with the mid-sized. [TW] - "SVEC" string looks very UGLY [TW] - Use same font on all component designators [TW] - 18 mils component designators will be almost invisible. There's enough space on the PCB for bigger silk texts. [TW] + Silkscreen width of 2 mils won't be visible (SFPGA PROGRAM) [TW] + Avoid routing lots of traces in between VME connector pins. [TW] + Use single cut width on the power planes (and wider than 5 mils) [TW] + Vias are too close each other. [CGS] + I've seen too many vias are placed in the power supply section. I don't understand why they have placed that much (temperature or current issues) I've check the current issues. My calcs, taking the worst case scenario (Figure C of Figure 6-4) of IPC-2221 are: > Cross sectional area of vias: CS = PI/4*(D^2-H^2) = PI/4*(h^2+2*h*H) D = H + h H = hole size of the via h = D-H = barrel plating thickness >> Case A H = 28mil h = 10mil CS = 660 mil^2 Let's say that we allow the trace to be working 10ºC above the surrounding board temperature: >>> Each via is able to transport upto 7 Amperes >> Case B H = 55.11mil h = 10mil CS = 1200 mil^2 >>> Each via is able to transport more than 7.5 Amperes I doubt that we need 18 vias Case A for 1V2 volts source (let's relax even more and say that a via will be able to carry half the current it will make 63 Amps!!!). [CGS] ? Possible size-effect of placing that many vias? [CGS] ? Don´t understand why they have placed GND vias close to C224 and C225. [CGS] + Near C413, he has placed a lot of vias to ground. He created a polygon pour for that ground that it is almost touching P5V_VME. [CGS] - Top serigraphie for revisions is bad: * pcbrev1... * DBG LED 1... -------------------------------------- VME CONNECTORS: -------------------------------------- [CGS] Strange workarounds in P1, P2 connectors: ! > near a4, a5, a12, z12 pins (have not really check in IPC if it compliant with board edge spacing). + > I would not put traces as close to board edge as VMEPX_IRQ4, VMEPX_IRQ5 and VMEPX_IRQ6. They are close to Z28, Z29, Z30, Z31, Z32 pins. + > Same is happening around MTG1 in between P1 and P2 [CGS] - I would place SW1 quite far away from the border. [CGS] - They can tidy up the DGB LEDs to be all together. [CGS] + I would not superimpose TOP lines with L1 lines (a little crosstalk detail). -------------------------------------- SFP area: -------------------------------------- [TW] + SFP power traces (C220 - SFP socket) are very close to unplated SFP mounting holes (5 mils). Will this be accepted by the PCB manufacturer? -------------------------------------- Main FPGA: -------------------------------------- [TW] + More vias on the FPGA power (there's still a lot of space under the FPGA) -------------------------------------- Power Supplies: -------------------------------------- [TW] + 0.5 mm is way too thin for traces rated for few amps (PSU -> FMC power) P2V5_FMC1, P3V3_FMC2, etc. [TW] + Vias over vias: possible production problems [TW] + What are these zillions of vias on 2.5V for if they all drive a 0.5mm -wide track? [TW] + Remove thin VTT_DDR3 trace (there's a polygon on L2) [CGS] + Power supply in the bottom: * Keep in mind that there's one capacitor with bad rated voltage. * Same problem with the vias. * I wouldn't place capacitors that close to the bottom of the board. Prone to be broken while some operators try to insert the card into the crate. -------------------------------------- FMC1 and FMC2: -------------------------------------- [CGS] + Routing lines can be smoothen. Too many turns [CGS] * Differential track lenght is well equalized -------------------------------------- VME: -------------------------------------- [CGS] * They could have done pin swapping in system FPGA, at least.. [CGS] * Pin swapping in the VMEH22501 could have greatly helped in the layout. -------------------------------------- DDR: -------------------------------------- [CGS] * Well equalized to 1100mil, DQ, DM, DQS and CK are OK -------------------------------------- DDR2: -------------------------------------- [CGS] * Well equalized to 1150mil. Same. -------------------------------------- LEDs: -------------------------------------- [CGS] - Why routing LEDs in L2, L3 layers? -------------------------------------- POWER PLANES: -------------------------------------- [TW] + PWR3.3 can be used for some other voltage. [CGS] - PWR3.3(Multiple nets) > P12V can be done bigger in the upper part of the board. [CGS] + PWR > Don't understand the way they ruted P1V2 plane. In any case, for such a big plane I would place some capacitors all over the board. I would have put the 5V plane in the top of the board. Then, below I would have placed both the P1V2, P1V5 (these two both to the VME connector) and P2V5 (closer to the FMC). A different approach could have been placing the P1V2 and P1V5 in between P1 and P2 (because it transforms from 5V VME) with the OSCONs close to the edge (vias are not affecting VME lines routing) and leave P2V5 where it is now. Pin swapping in VMEH22501 would help.