h1. Simple PCIe FMC carrier (SPEC)

h2. Project description

The FMC PCIe Carrier is an FMC carrier that can hold one FMC card and an SFP connector. On the PCIe side it has a 4-lane interface, while the FMC mezzanine slot uses a low-pin count connector. This board is optimised for cost and will be usable with most of the FMC cards designed within the OHR project (e.g. ADC cards, Fine Delay). For boards needing more possibilities (e.g. programmable clock resources, fast SRAM, fast interconnect between carriers), the "FMC PCIe Carrier":/projects/show/fmc-pci-carrier or its "VME counter part":/projects/show/fmc-vme-carrier can be used.

Other FMC projects and the FMC standard are described in "FMC Projects":/projects/show/fmc-projects.

!spec_v1.1_top.JPG!
*SPEC 1.1 first prototype*

h2. Main Features

    * 4-lane PCIe (Gennum GN4124)
    * FMC slot with low pin count (LPC) connector
          o Vadj fixed to 2.5V
          o No dedicated clock signals from Carrier to FMC (only available on HPC pins)
          o LPC cheaper than HPC and also easier to mount
          o FMC connectivity: all 34 differential pairs connected, 1 GTP transceiver with clock, 2 clock pairs, JTAG
    * 1 Xilinx Spartan6 FPGA (XC6SLX45T)    
    * Simple clocking resources
          o 1 10-280 MHz I2C Programmable XO Oscillator (Silicon Labs Si570)
          o 1 25 MHz TCXO controlled by a DAC with SPI interface (AD5662)
          o 1 20 MHz VCXO controlled by a DAC with SPI interface (AD5662)
          o 1 low-jitter frequency synthesizer (TI CDCM61004, fixed configuration, Fout=125MHz)
    * On board memory
          o A 2Gbit DDR3
          o 1 SPI 32Mbit flash PROM for multiboot FPGA powerup configuration, storage of the FPGA firmware or of critical data 
    * Front panel containing
          o 1 Small Formfactor Pluggable (SFP) cage for fibre-optic transceiver ("WhiteRabbit":/projects/show/white-rabbit support) 
          o Programmable LED
          o FMC front panel
    * Internal connectors
          o 1 JTAG header for Xilinx programming during debugging
          o 2 SATA connector 
          o 1 mini USB AB (USB-UART bridge)
    * FPGA configuration. The FPGA can optionally be programmed from:
           o GN4124 SPRIO interface (loaded by software driver at startup)
           o JTAG header
           o SPI 32Mbit flash PROM
           o selectable by GN4124 GPIO. Default option would be loading via the SPI flash PROM (stand-alone applications).
    * Stand-alone features
           o External 12V power supply connector
           o mini USB connector
           o 4 LEDs
           o 2 buttons
    * Optimised for cost


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h2. Project information

* Official production documentation: "EDMS EDA-02189":http://edms.cern.ch/nav/eda-02189
* CERN LHC Equipment name: CFEIA
** "Controls Configuration Database entry":https://cs-ccr-oas1.cern.ch/pls/htmldb_dbabco/f?p=config_browser:module_type:593526141435::::P41_QUERY,P41_TYPE_NAME:YES,CFEIA
** "Controls EDMS page":https://edms.cern.ch/nav/P:CERN-0000077383:V0/I:HCCFEIA___:V0/TAB4
* [[SysArch|System architecture]]
* [[Users]]
* [[Software]]
* [[FAQ|Frequently Asked Questions]]

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h2. Releases

* Hardware: "SPEC V4":/projects/spec/files

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h2. Contacts

h3. Commercial producers

* "Seven Solutions":http://www.sevensols.com/index.php?seccion=1410&subseccion=1432&lang=en, Spain
* "Creotech":http://creotech.pl/index.php/en/simple-pcie-fmc-carrier-spec, Poland

h3. General question about project

* "Erik van der Bij":mailto:Erik.van.der.Bij@cern.ch - CERN

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h2. Status

|_.Date      |_. Event                                                        |
| 22-06-2010 | Start of project. Design will be done by an external company, based on the "FMC PCIe Carrier":/projects/show/fmc-pci-carrier. 
Reviewing will be done by CERN.                                    |
| 29-06-2010 | Main features reviewed by JS, PA, MC & EB. Design can start. |
| 12-07-2010 | First schematics published. Ready for review.                |
| 16-07-2010 | First review held. Considered as a preliminary review as schematics not finished. |
| 24-07-2010 | Second version schematics published.                         |
| 03-08-2010 | Second schematics review held. FMC to Xilinx bank connections not correct. 
Clock missing. Supply Xilinx wrong. Cleanup required. |
| 03-09-2010 | Schematics corrected. Waiting for a final schematics review from CERN. |
| 07-09-2010 | Third schematics review held. [[review07092010]] |
| 10-09-2010 | Review comments integrated [[review07092010comments]]. Start of PCB layout. |
| 21-09-2010 | PCB layout being made. Will fit on a 6-layer board. |
| 27-09-2010 | PCB layout 'ready'.  |
| 01-10-2010 | PCB layout modified before review. |
| 04-10-2010 | Preliminary PCB layout review requiring modifications to layout. [[review04102010]] |
| 05-10-2010 | PCB layout review held. [[review05102010]] |
| 08-10-2010 | "Order":https://edh.cern.ch/Document/SupplyChain/DAI/4476636 placed for production of three prototypes. |
| 18-10-2010 | Some final mods to the schematics and PCB. Design passses CERN's design office for standard production files.  |
| 19-10-2010 | Board could not generate interrupts. Found before finalising production files. |
| 20-10-2010 | Vias designed next to BGA pads which may cause production problems. Needs rework of layout. |
| 29-10-2010 | Received improved layout. Will pass via CERN's design office. |
| 05-11-2010 | Design finished. Expect ordered boards by -mid December- January. |
| 20-12-2010 | Production of 3 prototype board finished (see photo above) |
| 19-01-2011 | Three prototypes arrived at CERN. |
| 19-01-2011 | Started testing V1 [[TestingV1]] |
| 04-02-2011 | First DDR3 access |
| 04-02-2011 | WhiteRabbit port GTP transceiver working. Packet Tx/Rx in progress... |
| 06-02-2011 | Packet transmission and reception works! |
| 24-02-2011 | All ICs and most slow lines of FMC connector tested. Not yet gigabit lines. |
| 02-03-2011 | Review of "V1.1" schematics and PCB. |
| 07-03-2011 | Ordered 10 "V1.1" boards for CERN. Company will produce extra for "WR":/projects/show/white-rabbit development. |
| 11-04-2011 | Improved version of "V1.1" layout sent for verification by CERN's design office. Planned ready by 29-04-2011. |
| 18-04-2011 | First V1.1 prototypes received, start testing them. |
| 02-05-2011 | V1.1 partly tested. Cleaning up schematics for production. Found missing pull-ups. |
| 09-05-2011 | Review of updated schematics planned to be held on 11-05-2011. [[review11052011]]|
| 16-05-2011 | Schematics, layout and production documents for V2 are available in "EDMS":https://edms.cern.ch/nav/P:EDA-02189:V0/I:EDA-02189-V2-0:V0/TAB4  |
| 20-05-2011 | CERN sent out price enquiry for production of 70 boards. Delivery of pre-series in October. |
| 31-05-2011 | Sent order for 3 production prototypes. "Order":http://edh.cern.ch/Info/Order/CA/1519947 (CERN only).
               Demo of production test software shown. Needs only minor modifications. |
| 16-06-2011 | V2 boards being built. |
| 01-07-2011 | Three V2 boards received. One fully tested OK. Two only shortly tested. |
| 14-07-2011 | Modifications for V3 (OHL v1.1, 1 crossover SATA), [[V3ChangeLog|changelog]]|
| 17-07-2011 | Order placed for 70 SPEC cards at Seven Solutions. First batch expected end October. |
| 25-07-2011 | V3 released. But never built. |
| 23-08-2011 | V4 released. Solves a minor mechanical problem with the SFP connector. |
| 21-11-2011 | Pre-production serie of 10 boards was not compliant to IPC-A-610 (Class 2). |
| 16-01-2012 | Will receive -8- 11 boards by -mid February- 7 March. (Update 24-02-2012), another 59 by end April. |
| 14-03-2012 | CERN accepted the 10 preseries boards that were received on 7 March. |
| 26-04-2012 | Will receive another 27 cards by mid-June. And 33 out of the order of 70 later. |

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Erik van der Bij, Matthieu Cattin, Tomasz Wlostowski - 26 April 2012