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Projects / FMC ADC 100M 14b 4cha
FmcAdc100M14b4cha is a 4 channel 100MSPS 14 bit ADC low pin count FPGA Mezzanine Card (VITA 57). More info at the Wiki page
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Projects / VME64x core
A VHDL core for a VME64x slave. The other side behaves like a Wishbone master.
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Projects / FMC DEL 1ns 4cha
A fine delay generator in FMC format with 1 input and 4 outputs. The resolution is 1 ns. Commercially available. More info at the Wiki page
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Projects / Simple PCIe FMC carrier SPEC
A simple 4-lane PCIe carrier for a low pin count FPGA Mezzanine Card (VITA 57). It supports the White Rabbit timing and control network. Commercially available. Linux and Labview drivers available for some mezzanine cards. More info at the Wiki page
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Projects / FMC DIO 5ch TTL a
FmcDIO5chTTLa is a 5-bit port digital IO card in FMC form-factor. Each single-bit port can be configured individually as input or output. The I/Os on LEMO 00 connectors are TTL compatible. Commercially available. More info at the Wiki page
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Projects / FMC TDC 1ns 5cha
An FPGA Mezzanine Card (FMC) with a Time to Digital Converter chip to perform one-shot sub-nanosecond time interval measurements. Commercially available. More info at the Wiki page
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Projects / fmc dac 600m 12b 1cha dds - Testing
Production and functional tests for fmc-dac-600m-12b-1cha-dds
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Projects / urv-core
The uRV (Micro RISC-V) core is a small-sized implementation of a 32-bit RISC-V core, targeted specifically at FPGAs. More info at the Wiki page
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Projects / Compact Universal Timing Endpoint Based on White Rabbit with Dual Ports Cute-WR-DP
The CUTE-WR-DP is the enhanced version of CUTE-WR with dual WR ports. You can use it as the normal WR node with one SFP port. CUTE-WR-DP can work in chain to support cascade topology. In future, CUTE-WR-DP could support dualport redundancy function for high reliable application. More info at the Wiki page
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Projects / tr-amc
A White Rabbit Timing Receiver in AMC (Advanced Mezzanine Card, AdvancedMC) format. More info at the Wiki page
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Projects / White Rabbit low jitter
Project exploring the current limits of White Rabbit timing distribution and how to obtain the best possible jitter and Allan Deviation performance
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Projects / FMC DIO 10I 8O
FmcDIO10i8o is an I/O card in FMC form-factor. Its 10 inputs use fast differential comparators (propagation delay < 1 ns) with individual 8-bit DACs of minimum 1 MSPS output settling. The 8 outputs are TTL level. More info at the Wiki page
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Projects / tr-pmc
A White Rabbit Timing Receiver in PMC (PCI Mezzanine Card) format. More info at the Wiki page
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Projects / FPGA and ARM SoC FMC Carrier FASEC
A carrier for two low pin count FPGA Mezzanine Cards (VITA 57), analog inputs and fail-safe functionality. It has memory and clocking resources and supports the White Rabbit timing and control network. Stand-alone board for use in a 'pizza-box'. More info at the Wiki page
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Projects / WRAP
WRAP, White RAbbit Pluggable, is a plug-in board providing easy-to-use WR functionality. Among others it provides direct 10MHz and PPS (pulse per second) outputs.
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Projects / EMC2-DP
PC/104 OneBank Carrier for SoC Modules. The EMC2-DP is a PCIe/104 OneBank Carrier for a Trenz compatible SoC Module and has expansion for a VITA57.1 FMC LPC I/O board and also has I/O pins, using a 100-way Samtec RazorBeam connectors system. Board developed with EU funding on the Artemis EMC2 project. More info at the Wiki page
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Projects / SPEC7
A simple 4-lane PCIe carrier for a FPGA Mezzanine Card (VITA 57). It supports the White Rabbit timing and control network. More info at the Wiki page
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Projects / AIDA-2020 TLU - Gateware
FPGA Firmware ( "Gateware" ) for AIDA-2020 TLU and AIDA mini-TLU
Uses "IPBus Build" ( ipbb )
Build instructions at Instructions here
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