Explore projects
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Fanless version of the White Rabbit Switch WRS-3/18 (hardware version 3.4) with the low-jitter daughterboard integrated. More info at the Wiki page
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Project exploring the current limits of White Rabbit timing distribution and how to obtain the best possible jitter and Allan Deviation performance
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WR-HSR is a research project to implement the High-availability Seamless Redundancy (HSR) protocol on White Rabbit switches and dual-port end nodes. The implementation is not part of the roadmap of the White Rabbit project.
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This project focuses on performing with high precision the core WR PTP calculations in fixed-point arithmetic. This will ensure uniform input parameters, code and precision across all WR implementations.
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This project deals with the distribution of RF signals over a White Rabbit network. In particular, it describes ways of extracting the characteristics of an RF signal (I/Q, Amplitude/Phase...) using a WR sampling node and the way to distribute those characteristics through Ethernet frames and generate the RF on the receiving nodes.
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Distribution of clock signals over a White Rabbit network. It uses an PLL with a numerically controlled (DDS) oscillator to extract the characteristics of a signal that in turn are distributed over a White Rabbit network to receiving nodes with a DAC that regenerate exactly the same signal in phase. More info at the Wiki page
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Project containing information about how to calibrate White Rabbit gear. See also https://www.ohwr.org/project/white-rabbit/wikis/Calibration More info at the Wiki page
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WRAP, White RAbbit Pluggable, is a plug-in board providing easy-to-use WR functionality. Among others it provides direct 10MHz and PPS (pulse per second) outputs.
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A VME card that is used to recover RF, bunch and revolution clocks over a white rabbit network.
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Projects / Wishbone slave generator
Affero General Public License v1.0wbgen2 is a tool for generating VHDL/Verilog cores which implement Wishbone bus slaves with certain registers, memory blocks, FIFOs and interrupts. The input is a C-like syntax file with an abstract description of what do we want to have in the slave. As a result, we get:
- Automatically allocated memory layout
- VHDL/Verilog code for the slave module
- C header files for driver development - Nice HTML documentation
Read the wbgen2-Documentation Get the latest version binaries https://www.ohwr.org/attachments/5659/wbgen2-bin.tar.bz2
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White Rabbit is a fully deterministic Ethernet-based network for general purpose data transfer and synchronization. It can synchronize over 1000 nodes with sub-ns accuracy over fiber lengths of up to 10 km. Commercially available. More info at the Wiki page
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A transparent Wishbone bridge between two FPGAs using high-speed serial links. This project is on hold.* More info at the Wiki page
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A High Pin Count FMC carrier in VXS format with two Virtex 5 FPGAs plus a DSP on board.
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A VME rear transition module providing 24 Dry Contact Inputs. Dry contact switch connecting 24V to ground (limited to 20mA). Uses the SVEC as front-module. More info at the Wiki page CANCELLED PROJECT
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Programmable attenuator of RF signals with very high voltage range (50 mV – 1000 V) for protecting digitizers against damage by high voltage signals. Four channels with SMA connectors; Three attenuation values: 0, -20, -40 dB; Bandwidth: DC – 2 GHz. VME form factor with I2C management bus. No VME-bus interface, only power supply used. More info at the Wiki page
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VME board with 36 ADC channels with a sampling rate of 250 kS/s and 16 bits resolution. More info at the Wiki page
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Video Processing Platform (MIXXEO). With 2 HDMI inputs, DVI + VGA output, Spartan 6 FPGA, DDR SDRAM memory and Ethernet.
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VHDL coding style document to be used at ohwr.org The project contains also a tool to automatically check the coding style. More info at the Wiki page
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