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Projects / FMC ADC 100M 14b 4cha
FmcAdc100M14b4cha is a 4 channel 100MSPS 14 bit ADC low pin count FPGA Mezzanine Card (VITA 57). More info at the Wiki page
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Projects / DIOT Zynq Ultrascale-based System Board
DI/OT Zynq Ultrascale-based System Board with White Rabbit support. More info at the Wiki page
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Projects / DIOT Igloo2-based radiation-tolerant System Board
DI/OT Igloo2-based System Board for radiation-exposed DI/OT applications. More info at the Wiki page
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Tom Levens / SVEC BST Receiver
An implementation of a receiver for CERN's Beam Synchronous Timing (BST) on a SVEC.
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Projects / RF over Ethernet - a protocol
RF over Ethernet, a protocol. Based on an extension of IEEE 1914.3 - IEEE Standard for Radio over Ethernet Encapsulations and Mappings. More info at the Wiki page
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Projects / FMC High-Voltage supply - fmc-hv-2ch
FMC LPC card with two High Voltage (HV) outputs and one Low Voltage (5-10V) output. Has mV voltage sensing and mA current sensing capabilities. More info at the Wiki page
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Projects / HPSEC - High Precision Slaved External Clock
High precision, ultra stable Oven Controlled Crystal Oscillator (OCXO) suitable for the Metrology purposes in a 19" format. Can be used to upgrade the performance of the SPEC7.
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Projects / Microstepper
High-resolution frequency/phase-microstepper for timing laboratories. More info at the Wiki page
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Projects / DIOT Monitoring Module
SAMD21-based monitoring module for DI/OT power supply and fan tray.
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Projects / CITY - CarrIer for RFoWR-based Timing sYstems
Zynq CarrIer for Timing sYstems based on radiofrequency over White Rabbit, aka CITY.
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Projects / FMC Projects
FMCprojects shows the FMC Mezzanine and Carrier boards that are developed in the Open Hardware Repository context. Furthermore it gives useful data helping you to design modules complying to this VITA 57.1 standard. This actually is not a hardware project, but is there to help you find your way in the FMC standard and shows you which FMC Mezzanines and Carriers are being developed in the context of the Open Hardware project.
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Projects / OHR Support
OHR project where you can get help and guidelines about OHR. It's a support project for questions/feedback and bugs. More info at the Wiki page
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Projects / OHR Meta Project
A meta project used to discuss and present information about Open Hardware and related subjects. More info at the Wiki page More info about the CERN Open Hardware licence More info about the OHR.org site support
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Projects / TDC core
A Time to Digital Converter core for Spartan 6 FPGAs.
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Projects / FMC ADC 1G 8b 2cha
The FmcAdc1G8b2cha is a 2 channel 1GSPS 8 bit ADC card in FMC (FPGA Mezzanine Card, VITA 57.1) format using a Low Pin-Count (LPC) connector.
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Projects / FMC DIO 5ch TTL a
FmcDIO5chTTLa is a 5-bit port digital IO card in FMC form-factor. Each single-bit port can be configured individually as input or output. The I/Os on LEMO 00 connectors are TTL compatible. Commercially available. More info at the Wiki page
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Projects / FMC TDC 1ns 5cha
An FPGA Mezzanine Card (FMC) with a Time to Digital Converter chip to perform one-shot sub-nanosecond time interval measurements. Commercially available. More info at the Wiki page
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Projects / fmc dac 600m 12b 1cha dds - Testing
Production and functional tests for fmc-dac-600m-12b-1cha-dds
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Projects / urv-core
The uRV (Micro RISC-V) core is a small-sized implementation of a 32-bit RISC-V core, targeted specifically at FPGAs. More info at the Wiki page
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Projects / Compact Universal Timing Endpoint Based on White Rabbit with Dual Ports Cute-WR-DP
The CUTE-WR-DP is the enhanced version of CUTE-WR with dual WR ports. You can use it as the normal WR node with one SFP port. CUTE-WR-DP can work in chain to support cascade topology. In future, CUTE-WR-DP could support dualport redundancy function for high reliable application. More info at the Wiki page
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