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A simple 4-lane PCIe carrier for a FPGA Mezzanine Card (VITA 57). It supports the White Rabbit timing and control network. More info at the Wiki page
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A 4-lane PCIe carrier for a low pin count FPGA Mezzanine Card (VITA 57). SPEC carrier based with a larger FPGA. Commercially available. More info at the Wiki page
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Hardware and software (libraries and GUI) to implement the SFF-8472 standard “Diagnostic Monitoring Interface for Optical Transceivers”. The hardware implements four SFP+s that can be exercised in parallel. To access the I2C interfaces a USB to I2C chip is used. More info at the Wiki page
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SDB (Self-describing Bus) allows to enumerate the cores that are live in the current FPGA binary, either from the host computer or from the internal soft-core CPU in the FPGA itself. The project provides the software support and the specification. More info at the Wiki page
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Stand Alone Carrier with 18 FMC LPC slots based on Spartan FPGAs, mini-ITX board and ATX supply. More info at the Wiki page
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RF over Ethernet, a protocol. Based on an extension of IEEE 1914.3 - IEEE Standard for Radio over Ethernet Encapsulations and Mappings. More info at the Wiki page
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RHINO (Reconfigurable Hardware Interface for computiNg and radiO) is a compute platform consisting of a FPGA element with dedicated memory, high speed communication, and FMC-LPC (Vita 57.1) IO expansion slots, all controlled via an ARM Cortex A8 processor running the BORPH operating system.
For progress updates, follow us on twitter @rhinoplatform
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This is a PCB-design + Arduino firmware for an Ethernet-controlled 1:8 RF-multiplexer. It allows selecting as output one of eight input-channels, as commonly used e.g. in timing-laboratories when one wants to measure many RF-sources (clock outputs like 1PPS or 10MHz) with a single instrument (frequency or time-interval counter). The design is for two independent MUX-boards to fit in a 1U 19” rack enclosure. For more information, see the wiki
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Power supply unit for emergency luminaires that may need to be used in areas with radiation. The power supply consists of a transformer, a diode bridge, capacitors and an optional voltage stabilisation device. It converts a 207V to 253V 50Hz AC to a stable DC voltage and current, as required by the LED load. Due to design constraints this is best for loads under 7-8W. More info at the Wiki page
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Radiation tolerant LED luminaires. Currently in production with two manufacturers. More info at the Wiki page
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Multi-channel Time Interval Counter and fine delay generator. Housed in a 19" module. Research project. More info at the Wiki page
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A QDR II RAM controller for the Virtex 6 FPGA family. This core is compliant with the Wishbone bus.
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A software suite written in Python to help with production tests of PCBs. AKA PTS.
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Projects / PPSi
GNU Lesser General Public License v2.1 onlyA Precise Time Protocol (PTP, IEEE 1588) software stack whose single source code can be compiled for many architectures (POSIX systems, WR switch, WR node, ...) and which is easily extensible.
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FMC carrier equipped with a Power PC embedded processor. In addition to the SPEC it has 2 gigabit Ethernet ports, one mini PCIe connector and USB 2.0 HS. It is supplied from a single 12V and runs Linux. The FPGA is configured from the processor and also interfaced using PCI Express x1 and a local bus. The system boots from on-board NAND or NOR flash memory.
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Linux device driver and associated utilities for PCIe FMC carriers. Aka GnuRabbit.
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High performance pulse and frequency distribution amplifier for time and frequency metrology. The pulse distribution board is an 1:8-channel (1 Hz and up) logic-level distribution amplifier, while the frequency distribution board is an 1:8-channel sine-wave (1-30 MHz) distribution amplifier. Two 1:8 boards fit side-by-sides in a 1U 19" rack enclosure, with either BNC or SMA connectors.
For more information, see the wiki
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PandA Motion Project is a collaboration between SOLEIL and DIAMOND to upgrade their “Position and Acquisition” processing platform. PandA will provide a common encoder processing platform based on Zynq 7030 and supporting multiple encoder standards (incremental, SSI, BISS...). It will deliver synchronous triggering and data capture capabilities.
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Production and functional tests for PandABox.
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Hardware design of the PandABox. Includes schematics, PCB layout and manufacturing files.
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