Fixed clock source pin assignement
This is issue extracted from #43 (closed).
@lerwys wrote:
Nice! I just find it a little unconventional to use an IBUFDS_GTE2 as a regular input buffer for the boot clock. I feel this would be a bit surprising to new users, as (I think) not a lot of boards use this approach. We have been using a clock like that for an auxiliary clock, sampling slow triggers (~KHz) from the MTCA.4 backplane, feeding TCLKA to the FPGA through an IBUFDS_GTE2.
One possible suggestion. Would it be possible to change Clock Switch output 12 (CLK12) to go to the MGT113 REFCLK0 and the 125MHz oscillator directly to the FPGA? Would it hurt protocols like SerialRapidIO or non-White Rabbit Ethernet?
@danielot wrote:
I see @lerwys's points here. I propose we make a final assessment about the 125 MHz clock input when we have a final proposal of the pin assignment. With the latest modifications, where we removed many FMC M2C and BIDIR clocks from MRCC pins, we should have some free MRCC inputs that could be assigned to the 125 MHz clock.
This should give a clearer interface to the user.
If it is not really possible to accommodate all these requirements, we could fallback to the IBUFDS_GTE2-only approach.
@lerwys wrote:
Nice, Thanks! Much appreciated. =]