FMC Powergood to FPGA
Right now, powergood is only routed to the MMC, which makes it harder for the gateware in the FPGA to detect if the board is connected and turned on. Connecting PG_M2C should allow for this.
Some precaution must be taken to allow for detection of the 3.3V safely by the FPGA bank (avoiding latchup, which has already hapenned in other AFC version) without creating problems for the MMC detection. A transistor pulled up to Vadj should suffice, no problem in inverting this logic.
Maybe we could avoid wasting a MRCC pin on this one, maybe we could change some trace in Bank 12 for FMC2 and on bank (better to keep in the same bank as the LPC pins). FMC1 could use J8, for example.