Remove option to route PORT 3 to FPGA I/O pins
Is the optional routing of 4 FPGA pins to PORT3 still required (introduced by #62 (closed))? If not, we can get rid of it and gain additional 4 FPGA I/O pins and simplify the circuit.
In the schematics it is possible to see the label "CERN timing system" on this circuit. We have recently decided to drop FCLK routing to the clock switch (#43 (closed)) when we got to know that CMS experiment wouldn't be interested in using the AFC. If FLCK and PORT3 LVDS requirement come from the same use case at CMS, it seems to be safe to remove this optional routing.
@msowinski could you confirm what was the original use case for this?