FT4232H USB UART / JTAG Improvements
Upon close inspection of the FT4232H-56Q circuitry we at LNLS think that it can be improved in several ways:
- Repurpose the FT4232H-56Q BDBUS as a second JTAG interface exclusive for the MMC, so it can be debugged vi the front panel USB even when the payload is active;
- Move the PRI_UART signals to CDBUS, get rid of AUX_UART (the FPGA really needs 2x USB-UART interfaces ?);
- Use unidirectional voltage level translators as all signals are unidirectional and group it in less ICs (1x SN74AVC8T245PW, 2x SN74AVC4T245PW);
- Remove R401, R402 and the MMC reset mosfet circuitry as it will conflict with the MMC reset solution proposed in #134 (closed) (I think that the RC filter proposed in #134 (closed) should be enough to take care of USB cable insertion transients);
- Implement the necessary logic for when the FT4232 MMC JTAG (BDBUS) is active the MMC is disconnected from the AMC JTAG (use the USB JTAG active signal from BDBUS to force the MMC JTAG out of AMC JTAG). I think it can be implemented with some diode logic (P3V3 OR USB_JTAG_MMC_ACTIVE) in IC46:
What do you think?