M-LVDS bus is not transparent to FPGA configuration
During configuration of the FPGA the M-LVDS lines are randomly triggered and at a certain point of the process are completely frozen (no board plugged to the backplane can receive triggers). Normal operation of the M-LVDS bus is only restored once the gateware is completely loaded.
For applications relying on the M-LVDS operation this may lead to severe failures, thus on-the-fly configuration of the AFC FPGA is not possible at all.