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AsyncArt
Commit a5b78092 authored by Javier D. Garcia-Lasheras's avatar Javier D. Garcia-Lasheras
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First HDL version for AsyncArt components

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hdl/asyncart_delay.vhd 0 → 100644
View file @ a5b78092
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
entity asyncart_delay is
port (
data_out : out std_logic;
data_in : in std_logic;
act : in std_logic;
rst : in std_logic);
end entity;
architecture design of asyncart_delay is
begin
process (rst, data_in, act)
begin
if (rst='1') then
data_out <= '0';
elsif (act='1') then
data_out <= data_in;
end if;
end process;
end design;
hdl/asyncart_demo.vhd 0 → 100644
View file @ a5b78092
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
entity asyncart_demo is
port (
BTNC : in std_logic;
BTND : in std_logic;
LD0 : out std_logic;
LD1 : out std_logic;
LD2 : out std_logic;
LD3 : out std_logic;
LD4 : out std_logic;
LD5 : out std_logic;
LD6 : out std_logic;
LD7 : out std_logic
);
end entity;
architecture demo_hw of asyncart_demo is
component asyncart_source
port (
fire_out : out std_logic;
phase_out : out std_logic;
phase_in_neg : in std_logic;
act : in std_logic;
rst : in std_logic);
end component;
component asyncart_reg is
port (
fire_out : out std_logic;
phase_out : out std_logic;
phase_in_pos : in std_logic;
phase_in_neg : in std_logic;
act : in std_logic;
rst : in std_logic);
end component;
component asyncart_sink
port (
fire_out : out std_logic;
phase_out : out std_logic;
phase_in_pos : in std_logic;
act : in std_logic;
rst : in std_logic);
end component;
-- PIPELINE_DEPTH must be > 2
constant PIPE_DEPTH : integer := 4096;
signal rst, act: std_logic;
type array_data is array (0 to PIPE_DEPTH-1) of std_logic_vector(31 downto 0);
signal data, data_next : array_data;
type array_control is array (0 to PIPE_DEPTH-1) of std_logic;
signal phase, clk : array_control;
-- Begin Architecture
begin
LD0 <= data(PIPE_DEPTH-1)(24);
LD1 <= data(PIPE_DEPTH-1)(25);
LD2 <= data(PIPE_DEPTH-1)(26);
LD3 <= data(PIPE_DEPTH-1)(27);
LD4 <= data(PIPE_DEPTH-1)(28);
LD5 <= data(PIPE_DEPTH-1)(29);
LD6 <= data(PIPE_DEPTH-1)(30);
LD7 <= data(PIPE_DEPTH-1)(31);
rst <= BTND;
act <= BTNC;
----------------------------------
-- Micropipeline description --
----------------------------------
GEN_PIPE: for i in 0 to PIPE_DEPTH-1 generate
-- x PIPE_DEPTH Asynchronous control pipeline elements
SOURCE_STAGE: if (i = 0) generate
source_i: asyncart_source
port map (
fire_out => clk(i),
phase_out => phase(i),
phase_in_neg => phase(i+1),
act => act,
rst => rst
);
end generate SOURCE_STAGE;
REG_STAGE: if ((i > 0) and (i < PIPE_DEPTH-1)) generate
reg_i: asyncart_reg
port map (
fire_out => clk(i),
phase_out => phase(i),
phase_in_pos => phase(i-1),
phase_in_neg => phase(i+1),
act => act,
rst => rst
);
end generate REG_STAGE;
SINK_STAGE: if (i = PIPE_DEPTH-1) generate
sink_i: asyncart_sink
port map (
fire_out => clk(i),
phase_out => phase(i),
phase_in_pos => phase(i-1),
act => act,
rst => rst
);
end generate SINK_STAGE;
-- x PIPE_DEPTH sequential data register pipeline elements
DATA_REG: process (rst, clk(i))
begin
if (rst = '1') then
data(i) <= (others => '0');
else
if (clk(i)'event and clk(i) = '1') then
data(i) <= data_next(i);
end if;
end if;
end process DATA_REG;
-- x PIPE_DEPTH datapath functions pipeline elements
COUNTER_FUNCTION: if (i = 0) generate
data_next(0) <= data(0)+1;
end generate COUNTER_FUNCTION;
MOVE_FUNCTION: if (i > 0) generate
data_next(i) <= data(i-1);
end generate MOVE_FUNCTION;
end generate GEN_PIPE;
end demo_hw;
hdl/asyncart_demo_1d.vhd 0 → 100644
View file @ a5b78092
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
entity asyncart_demo is
port (
--GCLK : in std_logic; -- 100 MHz input clock
BTNC : in std_logic; -- 100 MHz input clock
BTND : in std_logic; -- 100 MHz input clock
--OTG-RESETN : in std_logic;
LD0 : out std_logic;
LD1 : out std_logic;
LD2 : out std_logic;
LD3 : out std_logic;
LD4 : out std_logic;
LD5 : out std_logic;
LD6 : out std_logic;
LD7 : out std_logic
);
end entity;
architecture demo_hw of asyncart_demo is
component asyncart_source
port (
fire_out : out std_logic;
phase_out : out std_logic;
phase_in_neg : in std_logic;
act : in std_logic;
rst : in std_logic);
end component;
component asyncart_delay
port (
data_out : out std_logic;
data_in : in std_logic;
act : in std_logic;
rst : in std_logic);
end component;
component asyncart_sink
port (
fire_out : out std_logic;
phase_out : out std_logic;
phase_in_pos : in std_logic;
act : in std_logic;
rst : in std_logic);
end component;
signal clk_source, clk_sink, rst, act: std_logic;
signal fire_source, phase_source, phase_source_delayed: std_logic;
signal fire_sink, phase_sink: std_logic;
signal counter_source, counter_source_next: std_logic_vector(31 downto 0);
signal counter_sink, counter_sink_next: std_logic_vector(31 downto 0);
-- Begin Architecture
begin
LD0 <= counter_sink(24);
LD1 <= counter_sink(25);
LD2 <= counter_sink(26);
LD3 <= counter_sink(27);
LD4 <= counter_sink(28);
LD5 <= counter_sink(29);
LD6 <= counter_sink(30);
LD7 <= counter_sink(31);
rst <= BTND;
act <= BTNC;
----------------------------------
-- Sequential logic description --
----------------------------------
n1: asyncart_source
port map (
fire_out => clk_source,
phase_out => phase_source,
phase_in_neg => phase_sink,
act => act,
rst => rst
);
n2: asyncart_delay
port map (
data_out => phase_source_delayed,
data_in => phase_source,
act => act,
rst => rst
);
n3: asyncart_sink
port map (
fire_out => clk_sink,
phase_out => phase_sink,
phase_in_pos => phase_source_delayed,
act => act,
rst => rst
);
seq_source: process (rst, clk_source)
begin
if (rst = '1') then
counter_source <= (others => '0');
else
if (clk_source'event and clk_source = '1') then
counter_source <= counter_source_next;
end if;
end if;
end process seq_source;
counter_source_next <= counter_source + 1;
seq_sink: process (rst, clk_sink)
begin
if (rst = '1') then
counter_sink <= (others => '0');
else
if (clk_sink'event and clk_sink = '1') then
counter_sink <= counter_sink_next;
end if;
end if;
end process seq_sink;
counter_sink_next <= counter_source;
end demo_hw;
hdl/asyncart_reg.vhd 0 → 100644
View file @ a5b78092
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
entity asyncart_reg is
port (
fire_out : out std_logic;
phase_out : out std_logic;
phase_in_pos : in std_logic;
phase_in_neg : in std_logic;
act : in std_logic;
rst : in std_logic);
end entity;
architecture design of asyncart_reg is
signal fire, phase, phase_next : std_logic;
begin
reg_fifo: process (rst, fire)
begin
if (rst = '1') then
phase <= '0';
else
if (fire'event and fire = '1') then
phase <= phase_next;
end if;
end if;
end process reg_fifo;
fire <= (phase_in_pos xor phase) and (phase_in_neg xnor phase) and act;
phase_next <= not phase;
phase_out <= phase;
fire_out <= fire;
end design;
hdl/asyncart_sink.vhd 0 → 100644
View file @ a5b78092
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
entity asyncart_sink is
port (
fire_out : out std_logic;
phase_out : out std_logic;
phase_in_pos : in std_logic;
act : in std_logic;
rst : in std_logic);
end entity;
architecture design of asyncart_sink is
signal fire, phase, phase_next : std_logic;
begin
reg_fifo: process (rst, fire)
begin
if (rst = '1') then
phase <= '0';
else
if (fire'event and fire = '1') then
phase <= phase_next;
end if;
end if;
end process reg_fifo;
fire <= (phase_in_pos xor phase) and act;
phase_next <= not phase;
phase_out <= phase;
fire_out <= fire;
end design;
hdl/asyncart_source.vhd 0 → 100644
View file @ a5b78092
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
entity asyncart_source is
port (
fire_out : out std_logic;
phase_out : out std_logic;
phase_in_neg : in std_logic;
act : in std_logic;
rst : in std_logic);
end entity;
architecture design of asyncart_source is
signal fire, phase, phase_next : std_logic;
begin
reg_fifo: process (rst, fire)
begin
if (rst = '1') then
phase <= '0';
else
if (fire'event and fire = '1') then
phase <= phase_next;
end if;
end if;
end process reg_fifo;
fire <= (phase_in_neg xnor phase) and act;
phase_next <= not phase;
phase_out <= phase;
fire_out <= fire;
end design;
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