Altium

Design Rule Verification Report

Date: 11/5/2017
Time: 4:38:49 PM
Elapsed Time: 00:00:08
Filename: C:\Users\smkilani\Documents\atfc\hardware\altium\atfc.PcbDoc
Warnings: 9
Rule Violations: 88

Summary

Warnings Count
3 Net Ties failed verification 3
Zero hole size multi-layer pad(s) detected 3
Multilayer Pads with 0 size Hole found 3
Total 9

Rule Violations Count
Clearance Constraint (Gap=5mil) (All),(All) 0
Short-Circuit Constraint (Allowed=No) (All),(All) 0
Un-Routed Net Constraint ( (All) ) 0
Modified Polygon (Allow modified: No), (Allow shelved: No) 0
Width Constraint (Min=3.937mil) (Max=196.85mil) (Preferred=10mil) (All) 0
Power Plane Connect Rule(Direct Connect )(Expansion=20mil) (Conductor Width=10mil) (Air Gap=10mil) (Entries=4) (All) 0
Hole Size Constraint (Min=1mil) (Max=100mil) (All) 0
Hole To Hole Clearance (Gap=5mil) (All),(All) 0
Minimum Solder Mask Sliver (Gap=1mil) (All),(All) 53
Silk To Solder Mask (Clearance=10mil) (Disabled)(IsPad),(All) 0
Silk to Silk (Clearance=5mil) (All),(All) 17
Net Antennae (Tolerance=0mil) (All) 0
Length Constraint (Min=0mil) (Max=100000mil) (All) 0
Matched Lengths(Tolerance=40mil) (InAnyDifferentialPair) 18
Max Via Stub Length (Back Drilling rule) (Max Stub Length = 15mil) (InAnyDifferentialPair) 0
Room FPGA_PWR (Bounding Region = (1219.614mil, 326.614mil, 1570mil, 568mil) (Disabled)(InComponentClass('FPGA_PWR')) 0
Room FMC (Bounding Region = (0mil, 0mil, 2000mil, 1000mil) (Disabled)(InComponentClass('FMC')) 0
Room PWR_APD5052 (Bounding Region = (1092mil, 127mil, 2233mil, 775mil) (Disabled)(InComponentClass('PWR_APD5052')) 0
Room Config (Bounding Region = (0mil, 0mil, 2000mil, 1000mil) (Disabled)(InComponentClass('Config')) 0
Room FPGA_Banks1 (Bounding Region = (0mil, 0mil, 2000mil, 1000mil) (Disabled)(InComponentClass('FPGA_Banks1')) 0
Room FPGA_Banks2 (Bounding Region = (0mil, 0mil, 2000mil, 1000mil) (Disabled)(InComponentClass('FPGA_Banks2')) 0
Room IO (Bounding Region = (0mil, 0mil, 2000mil, 1000mil) (Disabled)(InComponentClass('IO')) 0
Room SFP (Bounding Region = (0mil, 0mil, 2000mil, 1000mil) (Disabled)(InComponentClass('SFP')) 0
Room Regulators (Bounding Region = (0mil, 0mil, 2000mil, 1000mil) (Disabled)(InComponentClass('Regulators')) 0
Height Constraint (Min=0mil) (Max=1000mil) (Prefered=500mil) (All) 0
Total 88

Warnings

3 Net Ties failed verification
SMT SIP Component R79-LRMAM1206-R02FT5 (1617mil,3431.898mil) on Component Side, SMT SIP Component R79-LRMAM1206-R02FT5 (1617mil,3431.898mil) on Component Side, has isolated copper
SMT SIP Component R62-LRMAM1206-R02FT5 (1782.756mil,1753mil) on Component Side, SMT SIP Component R62-LRMAM1206-R02FT5 (1782.756mil,1753mil) on Component Side, has isolated copper
SMT SIP Component R55-LRMAM1206-R02FT5 (1045mil,4852.898mil) on Component Side, SMT SIP Component R55-LRMAM1206-R02FT5 (1045mil,4852.898mil) on Component Side, has isolated copper
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Zero hole size multi-layer pad(s) detected
Pad J2-1(1046mil,5059.528mil) on Multi-Layer on Net NetJ2_1
Pad J2-2(1046mil,5303.622mil) on Multi-Layer on Net GND
Pad J2-3(849.15mil,5185.512mil) on Multi-Layer on Net GND
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Multilayer Pads with 0 size Hole found
Pad J2-1(1046mil,5059.528mil) on Multi-Layer
Pad J2-2(1046mil,5303.622mil) on Multi-Layer
Pad J2-3(849.15mil,5185.512mil) on Multi-Layer
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Minimum Solder Mask Sliver (Gap=1mil) (All),(All)
Minimum Solder Mask Sliver Constraint: (0.315mil < 1mil) Between Via (3607mil,4382mil) from Component Side to Bottom Side And Pad R87-2(3643mil,4379.528mil) on Component Side [Top Solder] Mask Sliver [0.315mil]
Minimum Solder Mask Sliver Constraint: (0.347mil < 1mil) Between Via (2827.016mil,4306mil) from Component Side to Bottom Side And Pad J3-10(2827.685mil,4363.717mil) on Component Side [Top Solder] Mask Sliver [0.347mil]
Minimum Solder Mask Sliver Constraint: (0.347mil < 1mil) Between Via (2858.512mil,4306mil) from Component Side to Bottom Side And Pad J3-9(2859.181mil,4363.717mil) on Component Side [Top Solder] Mask Sliver [0.347mil]
Minimum Solder Mask Sliver Constraint: (0.347mil < 1mil) Between Via (2921.504mil,4306mil) from Component Side to Bottom Side And Pad J3-7(2922.173mil,4363.717mil) on Component Side [Top Solder] Mask Sliver [0.347mil]
Minimum Solder Mask Sliver Constraint: (0.347mil < 1mil) Between Via (2953mil,4306mil) from Component Side to Bottom Side And Pad J3-6(2953.669mil,4363.717mil) on Component Side [Top Solder] Mask Sliver [0.347mil]
Minimum Solder Mask Sliver Constraint: (0.347mil < 1mil) Between Via (3047.488mil,4306mil) from Component Side to Bottom Side And Pad J3-3(3048.157mil,4363.717mil) on Component Side [Top Solder] Mask Sliver [0.347mil]
Minimum Solder Mask Sliver Constraint: (0.347mil < 1mil) Between Via (3110.48mil,4306mil) from Component Side to Bottom Side And Pad J3-1(3111.15mil,4363.717mil) on Component Side [Top Solder] Mask Sliver [0.347mil]
Minimum Solder Mask Sliver Constraint: (0.975mil < 1mil) Between Via (2640.685mil,1931mil) from Component Side to Bottom Side And Pad R70-1(2662.582mil,1905.284mil) on Component Side [Top Solder] Mask Sliver [0.975mil]
Minimum Solder Mask Sliver Constraint: (0.549mil < 1mil) Between Via (2616.685mil,1944mil) from Component Side to Bottom Side And Pad C96-1(2641.685mil,1966.268mil) on Component Side [Top Solder] Mask Sliver [0.549mil]
Minimum Solder Mask Sliver Constraint: (0.957mil < 1mil) Between Via (2449.685mil,2194mil) from Component Side to Bottom Side And Pad C79-1(2456.685mil,2165.732mil) on Component Side [Top Solder] Mask Sliver [0.957mil]
Minimum Solder Mask Sliver Constraint: (0.496mil < 1mil) Between Pad R62-2(1717.795mil,1753mil) on Component Side And Pad R62-4(1764.756mil,1753mil) on Component Side [Top Solder] Mask Sliver [0.496mil]
Minimum Solder Mask Sliver Constraint: (0.496mil < 1mil) Between Pad R62-1(1847.716mil,1753mil) on Component Side And Pad R62-3(1800.756mil,1753mil) on Component Side [Top Solder] Mask Sliver [0.496mil]
Minimum Solder Mask Sliver Constraint: (0.496mil < 1mil) Between Pad R55-2(1045mil,4787.937mil) on Component Side And Pad R55-4(1045mil,4834.898mil) on Component Side [Top Solder] Mask Sliver [0.496mil]
Minimum Solder Mask Sliver Constraint: (0.496mil < 1mil) Between Pad R55-1(1045mil,4917.858mil) on Component Side And Pad R55-3(1045mil,4870.898mil) on Component Side [Top Solder] Mask Sliver [0.496mil]
Minimum Solder Mask Sliver Constraint: (0.075mil < 1mil) Between Via (1072mil,4734.898mil) from Component Side to Bottom Side And Pad R55-2(1045mil,4787.937mil) on Component Side [Top Solder] Mask Sliver [0.075mil]
Minimum Solder Mask Sliver Constraint: (0.075mil < 1mil) Between Via (1042mil,4734.898mil) from Component Side to Bottom Side And Pad R55-2(1045mil,4787.937mil) on Component Side [Top Solder] Mask Sliver [0.075mil]
Minimum Solder Mask Sliver Constraint: (0.496mil < 1mil) Between Pad R79-2(1681.961mil,3431.898mil) on Component Side And Pad R79-4(1635mil,3431.898mil) on Component Side [Top Solder] Mask Sliver [0.496mil]
Minimum Solder Mask Sliver Constraint: (0.496mil < 1mil) Between Pad R79-1(1552.039mil,3431.898mil) on Component Side And Pad R79-3(1599mil,3431.898mil) on Component Side [Top Solder] Mask Sliver [0.496mil]
Minimum Solder Mask Sliver Constraint: (0.784mil < 1mil) Between Via (2654.685mil,2030mil) from Component Side to Bottom Side And Pad U8-43(2656.157mil,2061.142mil) on Component Side [Top Solder] Mask Sliver [0.784mil]
Minimum Solder Mask Sliver Constraint: (0.196mil < 1mil) Between Via (2681.102mil,2031.496mil) from Component Side to Bottom Side And Pad U8-45(2695.527mil,2061.142mil) on Component Side [Top Solder] Mask Sliver [0.196mil]
Minimum Solder Mask Sliver Constraint: (0.878mil < 1mil) Between Pad Q2-5(2405.338mil,2211.685mil) on Component Side And Pad Q2-6(2366.244mil,2175.347mil) on Component Side [Top Solder] Mask Sliver [0.878mil]
Minimum Solder Mask Sliver Constraint: (0.878mil < 1mil) Between Pad Q2-5(2366.263mil,2223.201mil) on Component Side And Pad Q2-6(2366.244mil,2175.347mil) on Component Side [Top Solder] Mask Sliver [0.878mil]
Minimum Solder Mask Sliver Constraint: (0.858mil < 1mil) Between Pad Q2-6(2405.338mil,2186.882mil) on Component Side And Pad Q2-5(2366.263mil,2223.201mil) on Component Side [Top Solder] Mask Sliver [0.858mil]
Minimum Solder Mask Sliver Constraint: (0.858mil < 1mil) Between Pad Q2-5(2405.338mil,2211.685mil) on Component Side And Pad Q2-5(2405.338mil,2236.488mil) on Component Side [Top Solder] Mask Sliver [0.858mil]
Minimum Solder Mask Sliver Constraint: (0.858mil < 1mil) Between Pad Q2-6(2405.338mil,2186.882mil) on Component Side And Pad Q2-6(2405.338mil,2162.079mil) on Component Side [Top Solder] Mask Sliver [0.858mil]
Minimum Solder Mask Sliver Constraint: (0.858mil < 1mil) Between Pad Q2-5(2405.338mil,2211.685mil) on Component Side And Pad Q2-6(2405.338mil,2186.882mil) on Component Side [Top Solder] Mask Sliver [0.858mil]
Minimum Solder Mask Sliver Constraint: (0.37mil < 1mil) Between Pad C7-1(3063.268mil,3452mil) on Component Side And Pad IC2-5(3023.402mil,3452mil) on Component Side [Top Solder] Mask Sliver [0.37mil]
Minimum Solder Mask Sliver Constraint: (0.37mil < 1mil) Between Pad C6-1(3063.268mil,3409mil) on Component Side And Pad IC2-4(3023.402mil,3409.677mil) on Component Side [Top Solder] Mask Sliver [0.37mil]
Minimum Solder Mask Sliver Constraint: (0.752mil < 1mil) Between Via (4986mil,5240mil) from Component Side to Bottom Side And Pad D5-2(4986mil,5204mil) on Component Side [Top Solder] Mask Sliver [0.752mil]
Minimum Solder Mask Sliver Constraint: (0.931mil < 1mil) Between Via (3945.181mil,5023mil) from Component Side to Bottom Side And Pad U6-6(3920.181mil,4996.803mil) on Component Side [Top Solder] Mask Sliver [0.931mil]
Minimum Solder Mask Sliver Constraint: (0.034mil < 1mil) Between Via (3945.181mil,5023mil) from Component Side to Bottom Side And Pad U6-4(3969mil,4996.803mil) on Component Side [Top Solder] Mask Sliver [0.034mil]
Minimum Solder Mask Sliver Constraint: (0.488mil < 1mil) Between Pad R16-2(1151.528mil,4144mil) on Component Side And Pad B2-3(1197.417mil,4144.496mil) on Component Side [Top Solder] Mask Sliver [0.488mil]
Minimum Solder Mask Sliver Constraint: (0.169mil < 1mil) Between Via (3945mil,5277mil) from Component Side to Bottom Side And Pad U7-6(3969mil,5303.197mil) on Component Side [Top Solder] Mask Sliver [0.169mil]
Minimum Solder Mask Sliver Constraint: (0.791mil < 1mil) Between Via (3945mil,5277mil) from Component Side to Bottom Side And Pad U7-4(3920.181mil,5303.197mil) on Component Side [Top Solder] Mask Sliver [0.791mil]
Minimum Solder Mask Sliver Constraint: (0.843mil < 1mil) Between Via (3610.472mil,4642.472mil) from Component Side to Bottom Side And Pad R93-1(3647mil,4642.472mil) on Component Side [Top Solder] Mask Sliver [0.843mil]
Minimum Solder Mask Sliver Constraint: (0.437mil < 1mil) Between Via (2677.165mil,2389.764mil) from Component Side to Bottom Side And Pad R56-1(2649.417mil,2380mil) on Bottom Side [Bottom Solder] Mask Sliver [0.437mil]
Minimum Solder Mask Sliver Constraint: (0.815mil < 1mil) Between Via (3775mil,2520mil) from Component Side to Bottom Side And Pad C117-2(3815mil,2516.528mil) on Bottom Side [Bottom Solder] Mask Sliver [0.815mil]
Minimum Solder Mask Sliver Constraint: (0.815mil < 1mil) Between Via (3775mil,2457.315mil) from Component Side to Bottom Side And Pad C117-1(3815mil,2457.472mil) on Bottom Side [Bottom Solder] Mask Sliver [0.815mil]
Minimum Solder Mask Sliver Constraint: (0.61mil < 1mil) Between Via (4141mil,3927mil) from Component Side to Bottom Side And Pad C100-1(4139.386mil,3966.795mil) on Bottom Side [Bottom Solder] Mask Sliver [0.61mil]
Minimum Solder Mask Sliver Constraint: (0.815mil < 1mil) Between Via (3995mil,3752mil) from Component Side to Bottom Side And Pad C107-1(4003.591mil,3792mil) on Bottom Side [Bottom Solder] Mask Sliver [0.815mil]
Minimum Solder Mask Sliver Constraint: (0.185mil < 1mil) Between Via (5271.654mil,3354.331mil) from Component Side to Bottom Side And Pad C1-2(5277.559mil,3314.961mil) on Bottom Side [Bottom Solder] Mask Sliver [0.185mil]
Minimum Solder Mask Sliver Constraint: (0.624mil < 1mil) Between Via (3555.118mil,4019.685mil) from Component Side to Bottom Side And Pad R34-1(3585mil,4041.268mil) on Bottom Side [Bottom Solder] Mask Sliver [0.624mil]
Minimum Solder Mask Sliver Constraint: (0.622mil < 1mil) Between Via (1901.575mil,1992.126mil) from Component Side to Bottom Side And Via (1925.197mil,1992.126mil) from Component Side to Bottom Side [Top Solder] Mask Sliver [0.622mil] / [Bottom Solder] Mask Sliver [0.622mil]
Minimum Solder Mask Sliver Constraint: (0.016mil < 1mil) Between Via (1796mil,3485.898mil) from Component Side to Bottom Side And Via (1795mil,3454.898mil) from Component Side to Bottom Side [Top Solder] Mask Sliver [0.016mil] / [Bottom Solder] Mask Sliver [0.016mil]
Minimum Solder Mask Sliver Constraint: (0.4mil < 1mil) Between Via (3607mil,4430.8mil) from Component Side to Bottom Side And Via (3607mil,4455.2mil) from Component Side to Bottom Side [Top Solder] Mask Sliver [0.4mil] / [Bottom Solder] Mask Sliver [0.4mil]
Minimum Solder Mask Sliver Constraint: (0.4mil < 1mil) Between Via (3607mil,4479.6mil) from Component Side to Bottom Side And Via (3607mil,4455.2mil) from Component Side to Bottom Side [Top Solder] Mask Sliver [0.4mil] / [Bottom Solder] Mask Sliver [0.4mil]
Minimum Solder Mask Sliver Constraint: (0.4mil < 1mil) Between Via (3607mil,4382mil) from Component Side to Bottom Side And Via (3607mil,4406.4mil) from Component Side to Bottom Side [Top Solder] Mask Sliver [0.4mil] / [Bottom Solder] Mask Sliver [0.4mil]
Minimum Solder Mask Sliver Constraint: (0.4mil < 1mil) Between Via (3607mil,4430.8mil) from Component Side to Bottom Side And Via (3607mil,4406.4mil) from Component Side to Bottom Side [Top Solder] Mask Sliver [0.4mil] / [Bottom Solder] Mask Sliver [0.4mil]
Minimum Solder Mask Sliver Constraint: (0.4mil < 1mil) Between Via (3607mil,4504mil) from Component Side to Bottom Side And Via (3607mil,4479.6mil) from Component Side to Bottom Side [Top Solder] Mask Sliver [0.4mil] / [Bottom Solder] Mask Sliver [0.4mil]
Minimum Solder Mask Sliver Constraint: (0.016mil < 1mil) Between Via (1011mil,4733.898mil) from Component Side to Bottom Side And Via (1042mil,4734.898mil) from Component Side to Bottom Side [Top Solder] Mask Sliver [0.016mil] / [Bottom Solder] Mask Sliver [0.016mil]
Minimum Solder Mask Sliver Constraint: (0.006mil < 1mil) Between Via (2861.685mil,2318mil) from Component Side to Bottom Side And Via (2884.63mil,2319.685mil) from Component Side to Bottom Side [Top Solder] Mask Sliver [0.006mil] / [Bottom Solder] Mask Sliver [0.006mil]
Minimum Solder Mask Sliver Constraint: (0.685mil < 1mil) Between Via (3775mil,2457.315mil) from Component Side to Bottom Side And Via (3775mil,2489mil) from Component Side to Bottom Side [Top Solder] Mask Sliver [0.685mil] / [Bottom Solder] Mask Sliver [0.685mil]
Minimum Solder Mask Sliver Constraint: (0.496mil < 1mil) Between Via (1578.74mil,2877.953mil) from Component Side to Bottom Side And Via (1547.244mil,2877.953mil) from Component Side to Bottom Side [Top Solder] Mask Sliver [0.496mil] / [Bottom Solder] Mask Sliver [0.496mil]
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Silk to Silk (Clearance=5mil) (All),(All)
Silk To Silk Clearance Constraint: (1.61mil < 5mil) Between Text "*" (1381.89mil,2972.441mil) on Top Overlay And Track (1387mil,2961.898mil)(1387mil,2969.898mil) on Top Overlay Silk Text to Silk Clearance [1.61mil]
Silk To Silk Clearance Constraint: (4.374mil < 5mil) Between Text "C76" (2854.331mil,2161.417mil) on Top Overlay And Track (2889.63mil,2195.284mil)(2897.63mil,2195.284mil) on Top Overlay Silk Text to Silk Clearance [4.374mil]
Silk To Silk Clearance Constraint: (Collision < 5mil) Between Text "C35" (3463.638mil,2839.394mil) on Top Overlay And Track (3462.244mil,2736.244mil)(3462.244mil,3641.756mil) on Top Overlay Silk Text to Silk Clearance [0mil]
Silk To Silk Clearance Constraint: (Collision < 5mil) Between Text "C34" (3462.638mil,2900.449mil) on Top Overlay And Track (3462.244mil,2736.244mil)(3462.244mil,3641.756mil) on Top Overlay Silk Text to Silk Clearance [0mil]
Silk To Silk Clearance Constraint: (4.718mil < 5mil) Between Text "C7" (3061mil,3473mil) on Top Overlay And Track (3076mil,3464mil)(3084mil,3464mil) on Top Overlay Silk Text to Silk Clearance [4.718mil]
Silk To Silk Clearance Constraint: (3.563mil < 5mil) Between Text "9" (4385mil,5084mil) on Top Overlay And Track (4375mil,5054mil)(4375mil,5254mil) on Top Overlay Silk Text to Silk Clearance [3.563mil]
Silk To Silk Clearance Constraint: (3.563mil < 5mil) Between Text "10" (4385mil,5184mil) on Top Overlay And Track (4375mil,5054mil)(4375mil,5254mil) on Top Overlay Silk Text to Silk Clearance [3.563mil]
Silk To Silk Clearance Constraint: (0.469mil < 5mil) Between Text "R53" (2834.646mil,2035.433mil) on Bottom Overlay And Track (2805.685mil,2002mil)(2805.685mil,2010mil) on Bottom Overlay Silk Text to Silk Clearance [0.469mil]
Silk To Silk Clearance Constraint: (3.655mil < 5mil) Between Text "R57" (2767.716mil,1960.63mil) on Bottom Overlay And Track (2734.685mil,1962mil)(2734.685mil,1970mil) on Bottom Overlay Silk Text to Silk Clearance [3.655mil]
Silk To Silk Clearance Constraint: (3.209mil < 5mil) Between Text "C12" (4169.291mil,3511.811mil) on Bottom Overlay And Track (4177mil,3482mil)(4177mil,3490mil) on Bottom Overlay Silk Text to Silk Clearance [3.209mil]
Silk To Silk Clearance Constraint: (2.303mil < 5mil) Between Text "R13" (3925.197mil,2984.252mil) on Bottom Overlay And Track (3931mil,2977mil)(3931mil,2985mil) on Bottom Overlay Silk Text to Silk Clearance [2.303mil]
Silk To Silk Clearance Constraint: (4.355mil < 5mil) Between Text "R69" (2791.685mil,1754mil) on Top Overlay And Text "R70" (2715.685mil,1754mil) on Top Overlay Silk Text to Silk Clearance [4.355mil]
Silk To Silk Clearance Constraint: (4.355mil < 5mil) Between Text "R59" (2639.685mil,1754mil) on Top Overlay And Text "R70" (2715.685mil,1754mil) on Top Overlay Silk Text to Silk Clearance [4.355mil]
Silk To Silk Clearance Constraint: (2.355mil < 5mil) Between Text "R59" (2639.685mil,1754mil) on Top Overlay And Text "R61" (2565.685mil,1754mil) on Top Overlay Silk Text to Silk Clearance [2.355mil]
Silk To Silk Clearance Constraint: (4.008mil < 5mil) Between Text "C87" (2711.74mil,1857.716mil) on Top Overlay And Text "R67" (2745.74mil,1857.716mil) on Top Overlay Silk Text to Silk Clearance [4.008mil]
Silk To Silk Clearance Constraint: (3.675mil < 5mil) Between Text "R10" (4962.333mil,3832mil) on Top Overlay And Text "R11" (4928.667mil,3833mil) on Top Overlay Silk Text to Silk Clearance [3.675mil]
Silk To Silk Clearance Constraint: (2.008mil < 5mil) Between Text "C96" (2630.74mil,1872.716mil) on Top Overlay And Text "C97" (2662.74mil,1874.716mil) on Top Overlay Silk Text to Silk Clearance [2.008mil]
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Matched Lengths(Tolerance=40mil) (InAnyDifferentialPair)
Matched Net Lengths: Between Net FMC_LA33_P And Net FMC_LA33_N Actual Difference against FMC_LA33_N is: 86.156mil, Tolerance : 40mil.
Matched Net Lengths: Between Net FMC_LA32_P And Net FMC_LA32_N Actual Difference against FMC_LA32_N is: 51.539mil, Tolerance : 40mil.
Matched Net Lengths: Between Net FMC_LA30_P And Net FMC_LA30_N Actual Difference against FMC_LA30_N is: 41.532mil, Tolerance : 40mil.
Matched Net Lengths: Between Net FMC_LA28_P And Net FMC_LA28_N Actual Difference against FMC_LA28_N is: 42.302mil, Tolerance : 40mil.
Matched Net Lengths: Between Net FMC_LA27_P And Net FMC_LA27_N Actual Difference against FMC_LA27_N is: 106.255mil, Tolerance : 40mil.
Matched Net Lengths: Between Net FMC_LA24_P And Net FMC_LA24_N Actual Difference against FMC_LA24_N is: 52.386mil, Tolerance : 40mil.
Matched Net Lengths: Between Net FMC_LA22_P And Net FMC_LA22_N Actual Difference against FMC_LA22_N is: 51.683mil, Tolerance : 40mil.
Matched Net Lengths: Between Net FMC_LA21_P And Net FMC_LA21_N Actual Difference against FMC_LA21_N is: 46.474mil, Tolerance : 40mil.
Matched Net Lengths: Between Net FMC_LA19_P And Net FMC_LA19_N Actual Difference against FMC_LA19_N is: 63.501mil, Tolerance : 40mil.
Matched Net Lengths: Between Net FMC_LA17_CC_P And Net FMC_LA17_CC_N Actual Difference against FMC_LA17_CC_N is: 113.374mil, Tolerance : 40mil.
Matched Net Lengths: Between Net FMC_LA16_P And Net FMC_LA16_N Actual Difference against FMC_LA16_N is: 44.441mil, Tolerance : 40mil.
Matched Net Lengths: Between Net FMC_LA13_P And Net FMC_LA13_N Actual Difference against FMC_LA13_N is: 101.152mil, Tolerance : 40mil.
Matched Net Lengths: Between Net FMC_LA10_P And Net FMC_LA10_N Actual Difference against FMC_LA10_N is: 149.104mil, Tolerance : 40mil.
Matched Net Lengths: Between Net FMC_LA09_P And Net FMC_LA09_N Actual Difference against FMC_LA09_N is: 165.454mil, Tolerance : 40mil.
Matched Net Lengths: Between Net FMC_LA08_P And Net FMC_LA08_N Actual Difference against FMC_LA08_N is: 54.383mil, Tolerance : 40mil.
Matched Net Lengths: Between Net FMC_LA05_P And Net FMC_LA05_N Actual Difference against FMC_LA05_N is: 150.538mil, Tolerance : 40mil.
Matched Net Lengths: Between Net FMC_LA00_CC_P And Net FMC_LA00_CC_N Actual Difference against FMC_LA00_CC_N is: 184.609mil, Tolerance : 40mil.
Matched Net Lengths: Between Net FMC_CLK1_M2C_P And Net FMC_CLK1_M2C_N Actual Difference against FMC_CLK1_M2C_N is: 49.544mil, Tolerance : 40mil.
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