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Artix Trivial FMC Carrier ATFC
Commit 411e17ef authored by Samer Kilani's avatar Samer Kilani
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Tidy up.

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hardware/altium/FPGA_Banks1.SchDoc
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hardware/altium/IO.SchDoc
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hardware/altium/Project Logs for atfc/PWR_APD5052 SCH ECO 9-6-2017 3-09-29 PM.LOG 0 → 100644
View file @ 411e17ef
Replace Part J2 PWR2.5 in C:\Users\smkilani\Documents\atfc\hardware\altium\PWR_APD5052.SchDoc with PWR2.5 from atfclib.SchLib
hardware/altium/Project Logs for atfc/atfc PCB ECO 9-6-2017 3-10-02 PM.LOG 0 → 100644
View file @ 411e17ef
Removed Pin From Net: NetName=NetJ2_1 Pin=J2-1A
Removed Pin From Net: NetName=NetJ2_1 Pin=J2-1B
Removed Pin From Net: NetName=GND Pin=J2-2A
Removed Pin From Net: NetName=GND Pin=J2-2B
Removed Pin From Net: NetName=GND Pin=J2-3A
Removed Pin From Net: NetName=GND Pin=J2-3B
Change Component Footprint: Designator=J2 Old Footprint=KLD-0202 New Footprint=KLD2020
Change Component Comment : Designator=J2 Old Comment=694108301002 New Comment=PWR2.5
hardware/altium/Project Logs for atfc/atfc PCB ECO 9-6-2017 4-13-07 PM.LOG 0 → 100644
View file @ 411e17ef
Change Physical Footprint: Designator=P3 Old Footprint=PMOD_12 New Footprint=PMOD_12
Change Physical Footprint: Designator=P4 Old Footprint=PMOD_12 New Footprint=PMOD_12
hardware/altium/Project Logs for atfc/atfc PCB ECO 9-6-2017 4-20-01 PM.LOG 0 → 100644
View file @ 411e17ef
Change Physical Footprint: Designator=U8 Old Footprint=CP_48_13 New Footprint=CP_48_13
hardware/altium/Project Outputs for atfc/Design Rule Check - atfc.drc
View file @ 411e17ef
Protel Design System Design Rule Check
PCB File : C:\Users\smkilani\Documents\atfc\hardware\altium\atfc.PcbDoc
Date : 6/6/2017
Time : 12:17:34 PM
Date : 9/6/2017
Time : 3:13:43 PM
WARNING: 3 Net Ties failed verification
SMT SIP Component R79-LRMAM1206-R02FT5 (41.072mm,87.17mm) on Component Side, SMT SIP Component R79-LRMAM1206-R02FT5 (41.072mm,87.17mm) on Component Side, has isolated copper
SMT SIP Component R62-LRMAM1206-R02FT5 (45.282mm,44.526mm) on Component Side, SMT SIP Component R62-LRMAM1206-R02FT5 (45.282mm,44.526mm) on Component Side, has isolated copper
SMT SIP Component R55-LRMAM1206-R02FT5 (29.643mm,123.464mm) on Component Side, SMT SIP Component R55-LRMAM1206-R02FT5 (29.643mm,123.464mm) on Component Side, has isolated copper
SMT SIP Component R55-LRMAM1206-R02FT5 (1167.047mil,4860.772mil) on Component Side, SMT SIP Component R55-LRMAM1206-R02FT5 (1167.047mil,4860.772mil) on Component Side, has isolated copper
SMT SIP Component R62-LRMAM1206-R02FT5 (1782.756mil,1753mil) on Component Side, SMT SIP Component R62-LRMAM1206-R02FT5 (1782.756mil,1753mil) on Component Side, has isolated copper
SMT SIP Component R79-LRMAM1206-R02FT5 (1617mil,3431.898mil) on Component Side, SMT SIP Component R79-LRMAM1206-R02FT5 (1617mil,3431.898mil) on Component Side, has isolated copper
WARNING: Zero hole size multi-layer pad(s) detected
Pad J2-1(30.3mm,129mm) on Multi-Layer on Net NetJ2_1
Pad J2-2(30.3mm,135.2mm) on Multi-Layer on Net GND
Pad J2-3(25.3mm,132.2mm) on Multi-Layer on Net GND
WARNING: Multilayer Pads with 0 size Hole found
Pad J2-1(30.3mm,129mm) on Multi-Layer
Pad J2-2(30.3mm,135.2mm) on Multi-Layer
Pad J2-3(25.3mm,132.2mm) on Multi-Layer
Processing Rule : Clearance Constraint (Gap=0.152mm) (All),(All)
Processing Rule : Clearance Constraint (Gap=6mil) (All),(All)
Rule Violations :0
Processing Rule : Short-Circuit Constraint (Allowed=No) (All),(All)
......@@ -30,235 +20,233 @@ Rule Violations :0
Processing Rule : Modified Polygon (Allow modified: No), (Allow shelved: No)
Rule Violations :0
Processing Rule : Width Constraint (Min=0.1mm) (Max=5mm) (Preferred=0.254mm) (All)
Rule Violations :0
Processing Rule : Power Plane Connect Rule(Direct Connect )(Expansion=0.508mm) (Conductor Width=0.254mm) (Air Gap=0.254mm) (Entries=4) (All)
Rule Violations :0
Processing Rule : Hole Size Constraint (Min=0.025mm) (Max=2.54mm) (All)
Violation between Hole Size Constraint: (3.2mm > 2.54mm) Pad Free-2(112.928mm,131.267mm) on Multi-Layer Actual Hole Size = 3.2mm
Violation between Hole Size Constraint: (2.7mm > 2.54mm) Pad Free-MH3(175.285mm,39.04mm) on Multi-Layer Actual Hole Size = 2.7mm
Violation between Hole Size Constraint: (2.7mm > 2.54mm) Pad Free-MH3(20.345mm,39.04mm) on Multi-Layer Actual Hole Size = 2.7mm
Violation between Hole Size Constraint: (2.7mm > 2.54mm) Pad Free-MH3(20.345mm,139.37mm) on Multi-Layer Actual Hole Size = 2.7mm
Violation between Hole Size Constraint: (2.7mm > 2.54mm) Pad Free-MH3(175.285mm,139.37mm) on Multi-Layer Actual Hole Size = 2.7mm
Violation between Hole Size Constraint: (2.7mm > 2.54mm) Pad Free-MH3(166.4mm,116.891mm) on Multi-Layer Actual Hole Size = 2.7mm
Violation between Hole Size Constraint: (2.7mm > 2.54mm) Pad Free-MH3(166.4mm,53.891mm) on Multi-Layer Actual Hole Size = 2.7mm
Rule Violations :7
Processing Rule : Hole To Hole Clearance (Gap=0.127mm) (All),(All)
Rule Violations :0
Processing Rule : Minimum Solder Mask Sliver (Gap=0.025mm) (All),(All)
Violation between Minimum Solder Mask Sliver Constraint: (0.01mm < 0.025mm) Between Via (157.353mm,125.298mm) from Component Side to Bottom Side And Pad R111-2(157.422mm,126.015mm) on Component Side [Top Solder] Mask Sliver [0.01mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.021mm < 0.025mm) Between Via (156.606mm,125.287mm) from Component Side to Bottom Side And Pad R109-2(156.606mm,126.015mm) on Component Side [Top Solder] Mask Sliver [0.021mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.012mm < 0.025mm) Between Pad R16-2(29.249mm,105.258mm) on Component Side And Pad B2-3(30.414mm,105.27mm) on Component Side [Top Solder] Mask Sliver [0.012mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.009mm < 0.025mm) Between Pad C7-1(77.807mm,87.681mm) on Component Side And Pad IC2-5(76.794mm,87.681mm) on Component Side [Top Solder] Mask Sliver [0.009mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.009mm < 0.025mm) Between Pad C6-1(77.807mm,86.589mm) on Component Side And Pad IC2-4(76.794mm,86.606mm) on Component Side [Top Solder] Mask Sliver [0.009mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.022mm < 0.025mm) Between Pad Q2-5(61.096mm,56.177mm) on Component Side And Pad Q2-6_2(60.103mm,55.254mm) on Component Side [Top Solder] Mask Sliver [0.022mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.022mm < 0.025mm) Between Pad Q2-5_2(60.103mm,56.469mm) on Component Side And Pad Q2-6_2(60.103mm,55.254mm) on Component Side [Top Solder] Mask Sliver [0.022mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.022mm < 0.025mm) Between Pad Q2-6(61.096mm,55.547mm) on Component Side And Pad Q2-5_2(60.103mm,56.469mm) on Component Side [Top Solder] Mask Sliver [0.022mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.022mm < 0.025mm) Between Pad Q2-5(61.096mm,56.177mm) on Component Side And Pad Q2-6(61.096mm,55.547mm) on Component Side [Top Solder] Mask Sliver [0.022mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.02mm < 0.025mm) Between Via (67.429mm,51.562mm) from Component Side to Bottom Side And Pad U8-43(67.466mm,52.353mm) on Component Side [Top Solder] Mask Sliver [0.02mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.013mm < 0.025mm) Between Pad R79-2(42.722mm,87.17mm) on Component Side And Pad R79-4(41.529mm,87.17mm) on Component Side [Top Solder] Mask Sliver [0.013mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.013mm < 0.025mm) Between Pad R79-1(39.422mm,87.17mm) on Component Side And Pad R79-3(40.615mm,87.17mm) on Component Side [Top Solder] Mask Sliver [0.013mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.011mm < 0.025mm) Between Via (165.67mm,75.621mm) from Component Side to Bottom Side And Pad J1-G13(166.305mm,75.875mm) on Component Side [Top Solder] Mask Sliver [0.011mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.011mm < 0.025mm) Between Via (165.67mm,74.859mm) from Component Side to Bottom Side And Pad J1-G12(166.305mm,74.605mm) on Component Side [Top Solder] Mask Sliver [0.011mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.008mm < 0.025mm) Between Via (165.695mm,67.95mm) from Component Side to Bottom Side And Pad J1-G7(166.305mm,68.255mm) on Component Side [Top Solder] Mask Sliver [0.008mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.008mm < 0.025mm) Between Via (165.695mm,68.56mm) from Component Side to Bottom Side And Pad J1-G7(166.305mm,68.255mm) on Component Side [Top Solder] Mask Sliver [0.008mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.008mm < 0.025mm) Between Via (165.695mm,66.68mm) from Component Side to Bottom Side And Pad J1-G6(166.305mm,66.985mm) on Component Side [Top Solder] Mask Sliver [0.008mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.008mm < 0.025mm) Between Via (165.695mm,67.29mm) from Component Side to Bottom Side And Pad J1-G6(166.305mm,66.985mm) on Component Side [Top Solder] Mask Sliver [0.008mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.011mm < 0.025mm) Between Via (163.13mm,93.401mm) from Component Side to Bottom Side And Pad J1-D27(162.495mm,93.655mm) on Component Side [Top Solder] Mask Sliver [0.011mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.011mm < 0.025mm) Between Via (163.13mm,92.639mm) from Component Side to Bottom Side And Pad J1-D26(162.495mm,92.385mm) on Component Side [Top Solder] Mask Sliver [0.011mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.011mm < 0.025mm) Between Via (163.13mm,78.161mm) from Component Side to Bottom Side And Pad J1-D15(162.495mm,78.415mm) on Component Side [Top Solder] Mask Sliver [0.011mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.011mm < 0.025mm) Between Via (163.13mm,77.399mm) from Component Side to Bottom Side And Pad J1-D14(162.495mm,77.145mm) on Component Side [Top Solder] Mask Sliver [0.011mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.011mm < 0.025mm) Between Via (168.21mm,69.271mm) from Component Side to Bottom Side And Pad J1-H8(167.575mm,69.525mm) on Component Side [Top Solder] Mask Sliver [0.011mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.011mm < 0.025mm) Between Via (168.21mm,68.509mm) from Component Side to Bottom Side And Pad J1-H7(167.575mm,68.255mm) on Component Side [Top Solder] Mask Sliver [0.011mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.011mm < 0.025mm) Between Via (165.67mm,102.291mm) from Component Side to Bottom Side And Pad J1-G34(166.305mm,102.545mm) on Component Side [Top Solder] Mask Sliver [0.011mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.011mm < 0.025mm) Between Via (165.67mm,101.529mm) from Component Side to Bottom Side And Pad J1-G33(166.305mm,101.275mm) on Component Side [Top Solder] Mask Sliver [0.011mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.011mm < 0.025mm) Between Via (165.67mm,98.481mm) from Component Side to Bottom Side And Pad J1-G31(166.305mm,98.735mm) on Component Side [Top Solder] Mask Sliver [0.011mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.011mm < 0.025mm) Between Via (165.67mm,97.719mm) from Component Side to Bottom Side And Pad J1-G30(166.305mm,97.465mm) on Component Side [Top Solder] Mask Sliver [0.011mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.011mm < 0.025mm) Between Via (165.67mm,94.671mm) from Component Side to Bottom Side And Pad J1-G28(166.305mm,94.925mm) on Component Side [Top Solder] Mask Sliver [0.011mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.011mm < 0.025mm) Between Via (165.67mm,93.909mm) from Component Side to Bottom Side And Pad J1-G27(166.305mm,93.655mm) on Component Side [Top Solder] Mask Sliver [0.011mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.011mm < 0.025mm) Between Via (165.67mm,90.861mm) from Component Side to Bottom Side And Pad J1-G25(166.305mm,91.115mm) on Component Side [Top Solder] Mask Sliver [0.011mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.011mm < 0.025mm) Between Via (163.13mm,89.591mm) from Component Side to Bottom Side And Pad J1-D24(162.495mm,89.845mm) on Component Side [Top Solder] Mask Sliver [0.011mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.011mm < 0.025mm) Between Via (165.67mm,90.099mm) from Component Side to Bottom Side And Pad J1-G24(166.305mm,89.845mm) on Component Side [Top Solder] Mask Sliver [0.011mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.011mm < 0.025mm) Between Via (163.13mm,88.829mm) from Component Side to Bottom Side And Pad J1-D23(162.495mm,88.575mm) on Component Side [Top Solder] Mask Sliver [0.011mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.011mm < 0.025mm) Between Via (165.67mm,87.051mm) from Component Side to Bottom Side And Pad J1-G22(166.305mm,87.305mm) on Component Side [Top Solder] Mask Sliver [0.011mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.011mm < 0.025mm) Between Via (165.67mm,86.289mm) from Component Side to Bottom Side And Pad J1-G21(166.305mm,86.035mm) on Component Side [Top Solder] Mask Sliver [0.011mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.011mm < 0.025mm) Between Via (165.67mm,83.241mm) from Component Side to Bottom Side And Pad J1-G19(166.305mm,83.495mm) on Component Side [Top Solder] Mask Sliver [0.011mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.011mm < 0.025mm) Between Via (163.13mm,81.971mm) from Component Side to Bottom Side And Pad J1-D18(162.495mm,82.225mm) on Component Side [Top Solder] Mask Sliver [0.011mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.011mm < 0.025mm) Between Via (165.67mm,82.479mm) from Component Side to Bottom Side And Pad J1-G18(166.305mm,82.225mm) on Component Side [Top Solder] Mask Sliver [0.011mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.011mm < 0.025mm) Between Via (163.13mm,81.209mm) from Component Side to Bottom Side And Pad J1-D17(162.495mm,80.955mm) on Component Side [Top Solder] Mask Sliver [0.011mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.011mm < 0.025mm) Between Via (165.67mm,79.431mm) from Component Side to Bottom Side And Pad J1-G16(166.305mm,79.685mm) on Component Side [Top Solder] Mask Sliver [0.011mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.011mm < 0.025mm) Between Via (165.67mm,78.669mm) from Component Side to Bottom Side And Pad J1-G15(166.305mm,78.415mm) on Component Side [Top Solder] Mask Sliver [0.011mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.011mm < 0.025mm) Between Via (163.13mm,74.351mm) from Component Side to Bottom Side And Pad J1-D12(162.495mm,74.605mm) on Component Side [Top Solder] Mask Sliver [0.011mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.011mm < 0.025mm) Between Via (163.13mm,73.589mm) from Component Side to Bottom Side And Pad J1-D11(162.495mm,73.335mm) on Component Side [Top Solder] Mask Sliver [0.011mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.011mm < 0.025mm) Between Via (165.67mm,71.811mm) from Component Side to Bottom Side And Pad J1-G10(166.305mm,72.065mm) on Component Side [Top Solder] Mask Sliver [0.011mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.011mm < 0.025mm) Between Via (165.67mm,71.049mm) from Component Side to Bottom Side And Pad J1-G9(166.305mm,70.795mm) on Component Side [Top Solder] Mask Sliver [0.011mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.008mm < 0.025mm) Between Via (166.915mm,66.02mm) from Component Side to Bottom Side And Pad J1-G5(166.305mm,65.715mm) on Component Side [Top Solder] Mask Sliver [0.008mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.008mm < 0.025mm) Between Via (166.915mm,64.14mm) from Component Side to Bottom Side And Pad J1-G4(166.305mm,64.445mm) on Component Side [Top Solder] Mask Sliver [0.008mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.025mm < 0.025mm) Between Via (161.865mm,62.205mm) from Component Side to Bottom Side And Pad J1-D2(162.495mm,61.905mm) on Component Side [Top Solder] Mask Sliver [0.025mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.008mm < 0.025mm) Between Via (166.965mm,64.75mm) from Component Side to Bottom Side And Pad J1-H4(167.575mm,64.445mm) on Component Side [Top Solder] Mask Sliver [0.008mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.008mm < 0.025mm) Between Via (166.965mm,65.41mm) from Component Side to Bottom Side And Pad J1-H5(167.575mm,65.715mm) on Component Side [Top Solder] Mask Sliver [0.008mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.021mm < 0.025mm) Between Via (25.425mm,80.058mm) from Component Side to Bottom Side And Pad C102-2(25.756mm,79.23mm) on Component Side [Top Solder] Mask Sliver [0.021mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.021mm < 0.025mm) Between Via (26.162mm,80.058mm) from Component Side to Bottom Side And Pad C102-2(25.756mm,79.23mm) on Component Side [Top Solder] Mask Sliver [0.021mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.012mm < 0.025mm) Between Via (39.091mm,75.842mm) from Component Side to Bottom Side And Pad C106-1(38.322mm,75.842mm) on Component Side [Top Solder] Mask Sliver [0.012mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.024mm < 0.025mm) Between Via (62.222mm,55.728mm) from Component Side to Bottom Side And Pad C79-1(62.4mm,55.01mm) on Component Side [Top Solder] Mask Sliver [0.024mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.024mm < 0.025mm) Between Via (62.588mm,56.21mm) from Component Side to Bottom Side And Pad C85-2(62.425mm,56.928mm) on Component Side [Top Solder] Mask Sliver [0.024mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.014mm < 0.025mm) Between Via (66.464mm,49.378mm) from Component Side to Bottom Side And Pad C96-1(67.099mm,49.943mm) on Component Side [Top Solder] Mask Sliver [0.014mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.009mm < 0.025mm) Between Via (71.806mm,109.372mm) from Component Side to Bottom Side And Pad J3-10(71.823mm,110.838mm) on Component Side [Top Solder] Mask Sliver [0.009mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.009mm < 0.025mm) Between Via (72.606mm,109.372mm) from Component Side to Bottom Side And Pad J3-9(72.623mm,110.838mm) on Component Side [Top Solder] Mask Sliver [0.009mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.009mm < 0.025mm) Between Via (74.206mm,109.372mm) from Component Side to Bottom Side And Pad J3-7(74.223mm,110.838mm) on Component Side [Top Solder] Mask Sliver [0.009mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.009mm < 0.025mm) Between Via (75.006mm,109.372mm) from Component Side to Bottom Side And Pad J3-6(75.023mm,110.838mm) on Component Side [Top Solder] Mask Sliver [0.009mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.009mm < 0.025mm) Between Via (77.406mm,109.372mm) from Component Side to Bottom Side And Pad J3-3(77.423mm,110.838mm) on Component Side [Top Solder] Mask Sliver [0.009mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.009mm < 0.025mm) Between Via (79.006mm,109.372mm) from Component Side to Bottom Side And Pad J3-1(79.023mm,110.838mm) on Component Side [Top Solder] Mask Sliver [0.009mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.008mm < 0.025mm) Between Via (91.618mm,111.303mm) from Component Side to Bottom Side And Pad R87-2(92.532mm,111.24mm) on Component Side [Top Solder] Mask Sliver [0.008mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.021mm < 0.025mm) Between Via (91.706mm,117.919mm) from Component Side to Bottom Side And Pad R93-1(92.634mm,117.919mm) on Component Side [Top Solder] Mask Sliver [0.021mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.025mm < 0.025mm) Between Via (67.073mm,49.047mm) from Component Side to Bottom Side And Pad R70-1(67.63mm,48.394mm) on Component Side [Top Solder] Mask Sliver [0.025mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.013mm < 0.025mm) Between Pad R55-2(29.643mm,121.814mm) on Component Side And Pad R55-4(29.643mm,123.006mm) on Component Side [Top Solder] Mask Sliver [0.013mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.013mm < 0.025mm) Between Pad R55-1(29.643mm,125.114mm) on Component Side And Pad R55-3(29.643mm,123.921mm) on Component Side [Top Solder] Mask Sliver [0.013mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.013mm < 0.025mm) Between Pad R62-2(43.632mm,44.526mm) on Component Side And Pad R62-4(44.825mm,44.526mm) on Component Side [Top Solder] Mask Sliver [0.013mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.013mm < 0.025mm) Between Pad R62-1(46.932mm,44.526mm) on Component Side And Pad R62-3(45.739mm,44.526mm) on Component Side [Top Solder] Mask Sliver [0.013mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.003mm < 0.025mm) Between Via (112.2mm,98.6mm) from Component Side to Bottom Side And Pad IC1-2(112.624mm,99.553mm) on Bottom Side [Bottom Solder] Mask Sliver [0.003mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.01mm < 0.025mm) Between Via (112.2mm,98.6mm) from Component Side to Bottom Side And Pad IC1-1(111.549mm,99.553mm) on Bottom Side [Bottom Solder] Mask Sliver [0.01mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.004mm < 0.025mm) Between Via (112.2mm,98.6mm) from Component Side to Bottom Side And Pad IC1-6(111.549mm,97.653mm) on Bottom Side [Bottom Solder] Mask Sliver [0.004mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.016mm < 0.025mm) Between Via (84.633mm,119.431mm) from Component Side to Bottom Side And Pad L7-1(86.106mm,119.364mm) on Bottom Side [Bottom Solder] Mask Sliver [0.016mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.005mm < 0.025mm) Between Via (36.715mm,51.169mm) from Component Side to Bottom Side And Pad Q1-4(37.323mm,50.669mm) on Bottom Side [Bottom Solder] Mask Sliver [0.005mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.005mm < 0.025mm) Between Via (36.715mm,51.169mm) from Component Side to Bottom Side And Pad Q1-6(37.323mm,51.669mm) on Bottom Side [Bottom Solder] Mask Sliver [0.005mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.023mm < 0.025mm) Between Via (120.1mm,76.6mm) from Component Side to Bottom Side And Pad R3-2(119.744mm,77.38mm) on Bottom Side [Bottom Solder] Mask Sliver [0.023mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.011mm < 0.025mm) Between Via (68mm,60.7mm) from Component Side to Bottom Side And Pad R56-1(67.295mm,60.452mm) on Bottom Side [Bottom Solder] Mask Sliver [0.011mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.011mm < 0.025mm) Between Via (91.2mm,95.5mm) from Component Side to Bottom Side And Pad R78-1(90.5mm,96.075mm) on Bottom Side [Bottom Solder] Mask Sliver [0.011mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.015mm < 0.025mm) Between Via (131.4mm,110.8mm) from Component Side to Bottom Side And Pad U3-5(131.333mm,110.028mm) on Bottom Side [Bottom Solder] Mask Sliver [0.015mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.021mm < 0.025mm) Between Via (105.131mm,98.73mm) from Component Side to Bottom Side And Pad U14-4(104.216mm,98.512mm) on Bottom Side [Bottom Solder] Mask Sliver [0.021mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.002mm < 0.025mm) Between Via (166.965mm,65.41mm) from Component Side to Bottom Side And Via (166.915mm,66.02mm) from Component Side to Bottom Side [Top Solder] Mask Sliver [0.002mm] / [Bottom Solder] Mask Sliver [0.002mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.002mm < 0.025mm) Between Via (166.965mm,64.75mm) from Component Side to Bottom Side And Via (166.915mm,64.14mm) from Component Side to Bottom Side [Top Solder] Mask Sliver [0.002mm] / [Bottom Solder] Mask Sliver [0.002mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.016mm < 0.025mm) Between Via (48.3mm,50.6mm) from Component Side to Bottom Side And Via (48.9mm,50.6mm) from Component Side to Bottom Side [Top Solder] Mask Sliver [0.016mm] / [Bottom Solder] Mask Sliver [0.016mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.003mm < 0.025mm) Between Via (68mm,51.7mm) from Component Side to Bottom Side And Via (67.429mm,51.562mm) from Component Side to Bottom Side [Top Solder] Mask Sliver [0.003mm] / [Bottom Solder] Mask Sliver [0.003mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.022mm < 0.025mm) Between Via (62.588mm,56.21mm) from Component Side to Bottom Side And Via (62.222mm,55.728mm) from Component Side to Bottom Side [Top Solder] Mask Sliver [0.022mm] / [Bottom Solder] Mask Sliver [0.022mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.01mm < 0.025mm) Between Via (110.49mm,64.465mm) from Component Side to Bottom Side And Via (110.49mm,65.187mm) from Component Side to Bottom Side [Top Solder] Mask Sliver [0.01mm] / [Bottom Solder] Mask Sliver [0.01mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.01mm < 0.025mm) Between Via (91.618mm,111.923mm) from Component Side to Bottom Side And Via (91.618mm,111.303mm) from Component Side to Bottom Side [Top Solder] Mask Sliver [0.01mm] / [Bottom Solder] Mask Sliver [0.01mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.01mm < 0.025mm) Between Via (91.618mm,112.542mm) from Component Side to Bottom Side And Via (91.618mm,111.923mm) from Component Side to Bottom Side [Top Solder] Mask Sliver [0.01mm] / [Bottom Solder] Mask Sliver [0.01mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.01mm < 0.025mm) Between Via (91.618mm,113.162mm) from Component Side to Bottom Side And Via (91.618mm,112.542mm) from Component Side to Bottom Side [Top Solder] Mask Sliver [0.01mm] / [Bottom Solder] Mask Sliver [0.01mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.01mm < 0.025mm) Between Via (91.618mm,113.782mm) from Component Side to Bottom Side And Via (91.618mm,113.162mm) from Component Side to Bottom Side [Top Solder] Mask Sliver [0.01mm] / [Bottom Solder] Mask Sliver [0.01mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.01mm < 0.025mm) Between Via (91.618mm,114.402mm) from Component Side to Bottom Side And Via (91.618mm,113.782mm) from Component Side to Bottom Side [Top Solder] Mask Sliver [0.01mm] / [Bottom Solder] Mask Sliver [0.01mm]
Rule Violations :92
Processing Rule : Silk To Solder Mask (Clearance=0.254mm) (Disabled)(IsPad),(All)
Rule Violations :0
Processing Rule : Silk to Silk (Clearance=0.127mm) (All),(All)
Violation between Silk To Silk Clearance Constraint: (Collision < 0.127mm) Between Text "Rout1" (35.8mm,124.4mm) on Top Overlay And Track (38.156mm,122.634mm)(38.156mm,135.634mm) on Top Overlay Silk Text to Silk Clearance [0mm]
Violation between Silk To Silk Clearance Constraint: (Collision < 0.127mm) Between Text "C35" (87.976mm,72.121mm) on Top Overlay And Track (87.941mm,69.501mm)(87.941mm,92.501mm) on Top Overlay Silk Text to Silk Clearance [0mm]
Violation between Silk To Silk Clearance Constraint: (Collision < 0.127mm) Between Text "C34" (87.951mm,73.671mm) on Top Overlay And Track (87.941mm,69.501mm)(87.941mm,92.501mm) on Top Overlay Silk Text to Silk Clearance [0mm]
Violation between Silk To Silk Clearance Constraint: (0.12mm < 0.127mm) Between Text "C7" (77.749mm,88.214mm) on Top Overlay And Track (78.13mm,87.986mm)(78.334mm,87.986mm) on Top Overlay Silk Text to Silk Clearance [0.12mm]
Violation between Silk To Silk Clearance Constraint: (0.041mm < 0.127mm) Between Text "*" (35.1mm,75.5mm) on Top Overlay And Track (35.23mm,75.232mm)(35.23mm,75.435mm) on Top Overlay Silk Text to Silk Clearance [0.041mm]
Violation between Silk To Silk Clearance Constraint: (0.111mm < 0.127mm) Between Text "C76" (72.5mm,54.9mm) on Top Overlay And Track (73.397mm,55.76mm)(73.6mm,55.76mm) on Top Overlay Silk Text to Silk Clearance [0.111mm]
Violation between Silk To Silk Clearance Constraint: (0.082mm < 0.127mm) Between Text "C12" (105.9mm,89.2mm) on Bottom Overlay And Track (106.096mm,88.443mm)(106.096mm,88.646mm) on Bottom Overlay Silk Text to Silk Clearance [0.082mm]
Violation between Silk To Silk Clearance Constraint: (0.058mm < 0.127mm) Between Text "R13" (99.7mm,75.8mm) on Bottom Overlay And Track (99.847mm,75.616mm)(99.847mm,75.819mm) on Bottom Overlay Silk Text to Silk Clearance [0.058mm]
Violation between Silk To Silk Clearance Constraint: (0.102mm < 0.127mm) Between Text "R19" (165.583mm,98.831mm) on Bottom Overlay And Track (163.805mm,99.162mm)(163.805mm,99.365mm) on Bottom Overlay Silk Text to Silk Clearance [0.102mm]
Violation between Silk To Silk Clearance Constraint: (0.123mm < 0.127mm) Between Text "R20" (165.71mm,102.667mm) on Bottom Overlay And Track (163.805mm,103.073mm)(163.805mm,103.276mm) on Bottom Overlay Silk Text to Silk Clearance [0.123mm]
Violation between Silk To Silk Clearance Constraint: (0.012mm < 0.127mm) Between Text "R53" (72mm,51.7mm) on Bottom Overlay And Track (71.264mm,50.851mm)(71.264mm,51.054mm) on Bottom Overlay Silk Text to Silk Clearance [0.012mm]
Violation between Silk To Silk Clearance Constraint: (0.093mm < 0.127mm) Between Text "R57" (70.3mm,49.8mm) on Bottom Overlay And Track (69.461mm,49.835mm)(69.461mm,50.038mm) on Bottom Overlay Silk Text to Silk Clearance [0.093mm]
Violation between Silk To Silk Clearance Constraint: (0.113mm < 0.127mm) Between Text "R100" (135.93mm,122.976mm) on Top Overlay And Text "R103" (135.055mm,122.976mm) on Top Overlay Silk Text to Silk Clearance [0.113mm]
Violation between Silk To Silk Clearance Constraint: (0.113mm < 0.127mm) Between Text "R101" (134.181mm,123.082mm) on Top Overlay And Text "R103" (135.055mm,122.976mm) on Top Overlay Silk Text to Silk Clearance [0.113mm]
Violation between Silk To Silk Clearance Constraint: (0.113mm < 0.127mm) Between Text "R100" (135.93mm,122.976mm) on Top Overlay And Text "R102" (136.804mm,122.976mm) on Top Overlay Silk Text to Silk Clearance [0.113mm]
Violation between Silk To Silk Clearance Constraint: (0.113mm < 0.127mm) Between Text "R98" (133.306mm,123.241mm) on Top Overlay And Text "R101" (134.181mm,123.082mm) on Top Overlay Silk Text to Silk Clearance [0.113mm]
Violation between Silk To Silk Clearance Constraint: (0.113mm < 0.127mm) Between Text "R97" (130.683mm,123.241mm) on Top Overlay And Text "R99" (131.557mm,123.241mm) on Top Overlay Silk Text to Silk Clearance [0.113mm]
Violation between Silk To Silk Clearance Constraint: (0.113mm < 0.127mm) Between Text "R80" (132.432mm,123.241mm) on Top Overlay And Text "R99" (131.557mm,123.241mm) on Top Overlay Silk Text to Silk Clearance [0.113mm]
Violation between Silk To Silk Clearance Constraint: (0.113mm < 0.127mm) Between Text "R80" (132.432mm,123.241mm) on Top Overlay And Text "R98" (133.306mm,123.241mm) on Top Overlay Silk Text to Silk Clearance [0.113mm]
Violation between Silk To Silk Clearance Constraint: (0.111mm < 0.127mm) Between Text "R69" (70.909mm,44.552mm) on Top Overlay And Text "R70" (68.978mm,44.552mm) on Top Overlay Silk Text to Silk Clearance [0.111mm]
Violation between Silk To Silk Clearance Constraint: (0.111mm < 0.127mm) Between Text "R59" (67.048mm,44.552mm) on Top Overlay And Text "R70" (68.978mm,44.552mm) on Top Overlay Silk Text to Silk Clearance [0.111mm]
Violation between Silk To Silk Clearance Constraint: (0.06mm < 0.127mm) Between Text "R59" (67.048mm,44.552mm) on Top Overlay And Text "R61" (65.168mm,44.552mm) on Top Overlay Silk Text to Silk Clearance [0.06mm]
Violation between Silk To Silk Clearance Constraint: (0.102mm < 0.127mm) Between Text "C87" (68.878mm,47.186mm) on Top Overlay And Text "R67" (69.742mm,47.186mm) on Top Overlay Silk Text to Silk Clearance [0.102mm]
Violation between Silk To Silk Clearance Constraint: (0.093mm < 0.127mm) Between Text "R10" (126.043mm,97.333mm) on Top Overlay And Text "R11" (125.188mm,97.358mm) on Top Overlay Silk Text to Silk Clearance [0.093mm]
Violation between Silk To Silk Clearance Constraint: (0.051mm < 0.127mm) Between Text "C96" (66.821mm,47.567mm) on Top Overlay And Text "C97" (67.634mm,47.618mm) on Top Overlay Silk Text to Silk Clearance [0.051mm]
Processing Rule : Width Constraint (Min=3.937mil) (Max=196.85mil) (Preferred=10mil) (All)
Rule Violations :0
Processing Rule : Power Plane Connect Rule(Direct Connect )(Expansion=20mil) (Conductor Width=10mil) (Air Gap=10mil) (Entries=4) (All)
Rule Violations :0
Processing Rule : Hole Size Constraint (Min=1mil) (Max=100mil) (All)
Violation between Hole Size Constraint: (122.047mil > 100mil) Pad J2-3(987.512mil,5204.677mil) on Multi-Layer Actual Slot Hole Width = 122.047mil
Violation between Hole Size Constraint: (125mil > 100mil) Pad J2-2(1176.488mil,5314.913mil) on Multi-Layer Actual Slot Hole Width = 125mil
Violation between Hole Size Constraint: (125mil > 100mil) Pad J2-1(1176.488mil,5086.567mil) on Multi-Layer Actual Slot Hole Width = 125mil
Violation between Hole Size Constraint: (106.299mil > 100mil) Pad Free-MH3(6551.181mil,2121.681mil) on Multi-Layer Actual Hole Size = 106.299mil
Violation between Hole Size Constraint: (106.299mil > 100mil) Pad Free-MH3(6551.181mil,4601.996mil) on Multi-Layer Actual Hole Size = 106.299mil
Violation between Hole Size Constraint: (106.299mil > 100mil) Pad Free-MH3(6901mil,5487mil) on Multi-Layer Actual Hole Size = 106.299mil
Violation between Hole Size Constraint: (106.299mil > 100mil) Pad Free-MH3(801mil,5487mil) on Multi-Layer Actual Hole Size = 106.299mil
Violation between Hole Size Constraint: (106.299mil > 100mil) Pad Free-MH3(801mil,1537mil) on Multi-Layer Actual Hole Size = 106.299mil
Violation between Hole Size Constraint: (106.299mil > 100mil) Pad Free-MH3(6901mil,1537mil) on Multi-Layer Actual Hole Size = 106.299mil
Violation between Hole Size Constraint: (125.984mil > 100mil) Pad Free-2(4446mil,5168mil) on Multi-Layer Actual Hole Size = 125.984mil
Rule Violations :10
Processing Rule : Hole To Hole Clearance (Gap=5mil) (All),(All)
Rule Violations :0
Processing Rule : Minimum Solder Mask Sliver (Gap=1mil) (All),(All)
Violation between Minimum Solder Mask Sliver Constraint: (0.496mil < 1mil) Between Pad R62-4(1764.756mil,1753mil) on Component Side And Pad R62-2(1717.795mil,1753mil) on Component Side [Top Solder] Mask Sliver [0.496mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.496mil < 1mil) Between Pad R62-3(1800.756mil,1753mil) on Component Side And Pad R62-1(1847.716mil,1753mil) on Component Side [Top Solder] Mask Sliver [0.496mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.496mil < 1mil) Between Pad R55-4(1167.047mil,4842.772mil) on Component Side And Pad R55-2(1167.047mil,4795.811mil) on Component Side [Top Solder] Mask Sliver [0.496mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.496mil < 1mil) Between Pad R55-3(1167.047mil,4878.772mil) on Component Side And Pad R55-1(1167.047mil,4925.732mil) on Component Side [Top Solder] Mask Sliver [0.496mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.975mil < 1mil) Between Via (2640.685mil,1931mil) from Component Side to Bottom Side And Pad R70-1(2662.582mil,1905.284mil) on Component Side [Top Solder] Mask Sliver [0.975mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.843mil < 1mil) Between Via (3610.472mil,4642.472mil) from Component Side to Bottom Side And Pad R93-1(3647mil,4642.472mil) on Component Side [Top Solder] Mask Sliver [0.843mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.315mil < 1mil) Between Via (3607mil,4382mil) from Component Side to Bottom Side And Pad R87-2(3643mil,4379.528mil) on Component Side [Top Solder] Mask Sliver [0.315mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.488mil < 1mil) Between Pad B2-3(1197.417mil,4144.496mil) on Component Side And Pad R16-2(1151.528mil,4144mil) on Component Side [Top Solder] Mask Sliver [0.488mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.347mil < 1mil) Between Via (3110.48mil,4306mil) from Component Side to Bottom Side And Pad J3-1(3111.15mil,4363.717mil) on Component Side [Top Solder] Mask Sliver [0.347mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.347mil < 1mil) Between Via (3047.488mil,4306mil) from Component Side to Bottom Side And Pad J3-3(3048.157mil,4363.717mil) on Component Side [Top Solder] Mask Sliver [0.347mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.347mil < 1mil) Between Via (2953mil,4306mil) from Component Side to Bottom Side And Pad J3-6(2953.669mil,4363.717mil) on Component Side [Top Solder] Mask Sliver [0.347mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.347mil < 1mil) Between Via (2921.504mil,4306mil) from Component Side to Bottom Side And Pad J3-7(2922.173mil,4363.717mil) on Component Side [Top Solder] Mask Sliver [0.347mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.347mil < 1mil) Between Via (2858.512mil,4306mil) from Component Side to Bottom Side And Pad J3-9(2859.181mil,4363.717mil) on Component Side [Top Solder] Mask Sliver [0.347mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.347mil < 1mil) Between Via (2827.016mil,4306mil) from Component Side to Bottom Side And Pad J3-10(2827.685mil,4363.717mil) on Component Side [Top Solder] Mask Sliver [0.347mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.549mil < 1mil) Between Via (2616.685mil,1944mil) from Component Side to Bottom Side And Pad C96-1(2641.685mil,1966.268mil) on Component Side [Top Solder] Mask Sliver [0.549mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.957mil < 1mil) Between Via (2464.099mil,2213mil) from Component Side to Bottom Side And Pad C85-2(2457.685mil,2241.268mil) on Component Side [Top Solder] Mask Sliver [0.957mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.957mil < 1mil) Between Via (2449.685mil,2194mil) from Component Side to Bottom Side And Pad C79-1(2456.685mil,2165.732mil) on Component Side [Top Solder] Mask Sliver [0.957mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.457mil < 1mil) Between Via (1539mil,2985.898mil) from Component Side to Bottom Side And Pad C106-1(1508.732mil,2985.898mil) on Component Side [Top Solder] Mask Sliver [0.457mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.819mil < 1mil) Between Via (1001mil,3151.898mil) from Component Side to Bottom Side And Pad C102-2(1014mil,3119.299mil) on Component Side [Top Solder] Mask Sliver [0.819mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.819mil < 1mil) Between Via (1030mil,3151.898mil) from Component Side to Bottom Side And Pad C102-2(1014mil,3119.299mil) on Component Side [Top Solder] Mask Sliver [0.819mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.37mil < 1mil) Between Pad IC2-5(3023.402mil,3452mil) on Component Side And Pad C7-1(3063.268mil,3452mil) on Component Side [Top Solder] Mask Sliver [0.37mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.37mil < 1mil) Between Pad IC2-4(3023.402mil,3409.677mil) on Component Side And Pad C6-1(3063.268mil,3409mil) on Component Side [Top Solder] Mask Sliver [0.37mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.333mil < 1mil) Between Via (6573.441mil,2575.205mil) from Component Side to Bottom Side And Pad J1-H5(6597.441mil,2587.205mil) on Component Side [Top Solder] Mask Sliver [0.333mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.333mil < 1mil) Between Via (6573.441mil,2549.205mil) from Component Side to Bottom Side And Pad J1-H4(6597.441mil,2537.205mil) on Component Side [Top Solder] Mask Sliver [0.333mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.968mil < 1mil) Between Via (6372.638mil,2449.008mil) from Component Side to Bottom Side And Pad J1-D2(6397.441mil,2437.205mil) on Component Side [Top Solder] Mask Sliver [0.968mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.333mil < 1mil) Between Via (6571.441mil,2525.205mil) from Component Side to Bottom Side And Pad J1-G4(6547.441mil,2537.205mil) on Component Side [Top Solder] Mask Sliver [0.333mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.333mil < 1mil) Between Via (6571.441mil,2599.205mil) from Component Side to Bottom Side And Pad J1-G5(6547.441mil,2587.205mil) on Component Side [Top Solder] Mask Sliver [0.333mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.426mil < 1mil) Between Via (6522.441mil,2797.205mil) from Component Side to Bottom Side And Pad J1-G9(6547.441mil,2787.205mil) on Component Side [Top Solder] Mask Sliver [0.426mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.426mil < 1mil) Between Via (6522.441mil,2827.205mil) from Component Side to Bottom Side And Pad J1-G10(6547.441mil,2837.205mil) on Component Side [Top Solder] Mask Sliver [0.426mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.426mil < 1mil) Between Via (6422.441mil,2897.205mil) from Component Side to Bottom Side And Pad J1-D11(6397.441mil,2887.205mil) on Component Side [Top Solder] Mask Sliver [0.426mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.426mil < 1mil) Between Via (6422.441mil,2927.205mil) from Component Side to Bottom Side And Pad J1-D12(6397.441mil,2937.205mil) on Component Side [Top Solder] Mask Sliver [0.426mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.426mil < 1mil) Between Via (6522.441mil,3097.205mil) from Component Side to Bottom Side And Pad J1-G15(6547.441mil,3087.205mil) on Component Side [Top Solder] Mask Sliver [0.426mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.426mil < 1mil) Between Via (6522.441mil,3127.205mil) from Component Side to Bottom Side And Pad J1-G16(6547.441mil,3137.205mil) on Component Side [Top Solder] Mask Sliver [0.426mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.426mil < 1mil) Between Via (6422.441mil,3197.205mil) from Component Side to Bottom Side And Pad J1-D17(6397.441mil,3187.205mil) on Component Side [Top Solder] Mask Sliver [0.426mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.426mil < 1mil) Between Via (6522.441mil,3247.205mil) from Component Side to Bottom Side And Pad J1-G18(6547.441mil,3237.205mil) on Component Side [Top Solder] Mask Sliver [0.426mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.426mil < 1mil) Between Via (6422.441mil,3227.205mil) from Component Side to Bottom Side And Pad J1-D18(6397.441mil,3237.205mil) on Component Side [Top Solder] Mask Sliver [0.426mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.426mil < 1mil) Between Via (6522.441mil,3277.205mil) from Component Side to Bottom Side And Pad J1-G19(6547.441mil,3287.205mil) on Component Side [Top Solder] Mask Sliver [0.426mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.426mil < 1mil) Between Via (6522.441mil,3397.205mil) from Component Side to Bottom Side And Pad J1-G21(6547.441mil,3387.205mil) on Component Side [Top Solder] Mask Sliver [0.426mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.426mil < 1mil) Between Via (6522.441mil,3427.205mil) from Component Side to Bottom Side And Pad J1-G22(6547.441mil,3437.205mil) on Component Side [Top Solder] Mask Sliver [0.426mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.426mil < 1mil) Between Via (6422.441mil,3497.205mil) from Component Side to Bottom Side And Pad J1-D23(6397.441mil,3487.205mil) on Component Side [Top Solder] Mask Sliver [0.426mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.426mil < 1mil) Between Via (6522.441mil,3547.205mil) from Component Side to Bottom Side And Pad J1-G24(6547.441mil,3537.205mil) on Component Side [Top Solder] Mask Sliver [0.426mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.426mil < 1mil) Between Via (6422.441mil,3527.205mil) from Component Side to Bottom Side And Pad J1-D24(6397.441mil,3537.205mil) on Component Side [Top Solder] Mask Sliver [0.426mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.426mil < 1mil) Between Via (6522.441mil,3577.205mil) from Component Side to Bottom Side And Pad J1-G25(6547.441mil,3587.205mil) on Component Side [Top Solder] Mask Sliver [0.426mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.426mil < 1mil) Between Via (6522.441mil,3697.205mil) from Component Side to Bottom Side And Pad J1-G27(6547.441mil,3687.205mil) on Component Side [Top Solder] Mask Sliver [0.426mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.426mil < 1mil) Between Via (6522.441mil,3727.205mil) from Component Side to Bottom Side And Pad J1-G28(6547.441mil,3737.205mil) on Component Side [Top Solder] Mask Sliver [0.426mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.426mil < 1mil) Between Via (6522.441mil,3847.205mil) from Component Side to Bottom Side And Pad J1-G30(6547.441mil,3837.205mil) on Component Side [Top Solder] Mask Sliver [0.426mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.426mil < 1mil) Between Via (6522.441mil,3877.205mil) from Component Side to Bottom Side And Pad J1-G31(6547.441mil,3887.205mil) on Component Side [Top Solder] Mask Sliver [0.426mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.426mil < 1mil) Between Via (6522.441mil,3997.205mil) from Component Side to Bottom Side And Pad J1-G33(6547.441mil,3987.205mil) on Component Side [Top Solder] Mask Sliver [0.426mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.426mil < 1mil) Between Via (6522.441mil,4027.205mil) from Component Side to Bottom Side And Pad J1-G34(6547.441mil,4037.205mil) on Component Side [Top Solder] Mask Sliver [0.426mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.426mil < 1mil) Between Via (6622.441mil,2697.205mil) from Component Side to Bottom Side And Pad J1-H7(6597.441mil,2687.205mil) on Component Side [Top Solder] Mask Sliver [0.426mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.426mil < 1mil) Between Via (6622.441mil,2727.205mil) from Component Side to Bottom Side And Pad J1-H8(6597.441mil,2737.205mil) on Component Side [Top Solder] Mask Sliver [0.426mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.426mil < 1mil) Between Via (6422.441mil,3047.205mil) from Component Side to Bottom Side And Pad J1-D14(6397.441mil,3037.205mil) on Component Side [Top Solder] Mask Sliver [0.426mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.426mil < 1mil) Between Via (6422.441mil,3077.205mil) from Component Side to Bottom Side And Pad J1-D15(6397.441mil,3087.205mil) on Component Side [Top Solder] Mask Sliver [0.426mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.426mil < 1mil) Between Via (6422.441mil,3647.205mil) from Component Side to Bottom Side And Pad J1-D26(6397.441mil,3637.205mil) on Component Side [Top Solder] Mask Sliver [0.426mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.426mil < 1mil) Between Via (6422.441mil,3677.205mil) from Component Side to Bottom Side And Pad J1-D27(6397.441mil,3687.205mil) on Component Side [Top Solder] Mask Sliver [0.426mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.333mil < 1mil) Between Via (6523.441mil,2625.205mil) from Component Side to Bottom Side And Pad J1-G6(6547.441mil,2637.205mil) on Component Side [Top Solder] Mask Sliver [0.333mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.333mil < 1mil) Between Via (6523.441mil,2649.205mil) from Component Side to Bottom Side And Pad J1-G6(6547.441mil,2637.205mil) on Component Side [Top Solder] Mask Sliver [0.333mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.333mil < 1mil) Between Via (6523.441mil,2699.205mil) from Component Side to Bottom Side And Pad J1-G7(6547.441mil,2687.205mil) on Component Side [Top Solder] Mask Sliver [0.333mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.333mil < 1mil) Between Via (6523.441mil,2675.205mil) from Component Side to Bottom Side And Pad J1-G7(6547.441mil,2687.205mil) on Component Side [Top Solder] Mask Sliver [0.333mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.426mil < 1mil) Between Via (6522.441mil,2947.205mil) from Component Side to Bottom Side And Pad J1-G12(6547.441mil,2937.205mil) on Component Side [Top Solder] Mask Sliver [0.426mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.426mil < 1mil) Between Via (6522.441mil,2977.205mil) from Component Side to Bottom Side And Pad J1-G13(6547.441mil,2987.205mil) on Component Side [Top Solder] Mask Sliver [0.426mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.496mil < 1mil) Between Pad R79-4(1635mil,3431.898mil) on Component Side And Pad R79-2(1681.961mil,3431.898mil) on Component Side [Top Solder] Mask Sliver [0.496mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.496mil < 1mil) Between Pad R79-3(1599mil,3431.898mil) on Component Side And Pad R79-1(1552.039mil,3431.898mil) on Component Side [Top Solder] Mask Sliver [0.496mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.784mil < 1mil) Between Via (2654.685mil,2030mil) from Component Side to Bottom Side And Pad U8-43(2656.157mil,2061.142mil) on Component Side [Top Solder] Mask Sliver [0.784mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.858mil < 1mil) Between Pad Q2-6(2405.338mil,2186.882mil) on Component Side And Pad Q2-5(2405.338mil,2211.685mil) on Component Side [Top Solder] Mask Sliver [0.858mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.878mil < 1mil) Between Pad Q2-6_2(2366.244mil,2175.347mil) on Component Side And Pad Q2-5(2405.338mil,2211.685mil) on Component Side [Top Solder] Mask Sliver [0.878mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.858mil < 1mil) Between Pad Q2-5_2(2366.263mil,2223.201mil) on Component Side And Pad Q2-6(2405.338mil,2186.882mil) on Component Side [Top Solder] Mask Sliver [0.858mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.878mil < 1mil) Between Pad Q2-6_2(2366.244mil,2175.347mil) on Component Side And Pad Q2-5_2(2366.263mil,2223.201mil) on Component Side [Top Solder] Mask Sliver [0.878mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.823mil < 1mil) Between Via (6165.571mil,4932.571mil) from Component Side to Bottom Side And Pad R109-2(6165.571mil,4961.205mil) on Component Side [Top Solder] Mask Sliver [0.823mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.394mil < 1mil) Between Via (6195mil,4933mil) from Component Side to Bottom Side And Pad R111-2(6197.714mil,4961.205mil) on Component Side [Top Solder] Mask Sliver [0.394mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.839mil < 1mil) Between Via (4139mil,3887mil) from Component Side to Bottom Side And Pad U14-4(4103mil,3878.41mil) on Bottom Side [Bottom Solder] Mask Sliver [0.839mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.591mil < 1mil) Between Via (5173.228mil,4362.205mil) from Component Side to Bottom Side And Pad U3-5(5170.591mil,4331.803mil) on Bottom Side [Bottom Solder] Mask Sliver [0.591mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.438mil < 1mil) Between Via (2677.165mil,2389.764mil) from Component Side to Bottom Side And Pad R56-1(2649.416mil,2380mil) on Bottom Side [Bottom Solder] Mask Sliver [0.438mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.913mil < 1mil) Between Via (4728.346mil,3015.748mil) from Component Side to Bottom Side And Pad R3-2(4714.347mil,3046.472mil) on Bottom Side [Bottom Solder] Mask Sliver [0.913mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.214mil < 1mil) Between Via (1445.48mil,2014.52mil) from Component Side to Bottom Side And Pad Q1-6(1469.393mil,2034.205mil) on Bottom Side [Bottom Solder] Mask Sliver [0.214mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.214mil < 1mil) Between Via (1445.48mil,2014.52mil) from Component Side to Bottom Side And Pad Q1-4(1469.393mil,1994.835mil) on Bottom Side [Bottom Solder] Mask Sliver [0.214mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.629mil < 1mil) Between Via (3332mil,4702mil) from Component Side to Bottom Side And Pad L7-1(3389.999mil,4699.37mil) on Bottom Side [Bottom Solder] Mask Sliver [0.629mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.163mil < 1mil) Between Via (4417.323mil,3881.89mil) from Component Side to Bottom Side And Pad IC1-6(4391.677mil,3844.598mil) on Bottom Side [Bottom Solder] Mask Sliver [0.163mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.374mil < 1mil) Between Via (4417.323mil,3881.89mil) from Component Side to Bottom Side And Pad IC1-1(4391.677mil,3919.402mil) on Bottom Side [Bottom Solder] Mask Sliver [0.374mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.114mil < 1mil) Between Via (4417.323mil,3881.89mil) from Component Side to Bottom Side And Pad IC1-2(4434mil,3919.402mil) on Bottom Side [Bottom Solder] Mask Sliver [0.114mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.402mil < 1mil) Between Via (4350mil,2566.402mil) from Component Side to Bottom Side And Via (4350mil,2538mil) from Component Side to Bottom Side [Top Solder] Mask Sliver [0.402mil] / [Bottom Solder] Mask Sliver [0.402mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.083mil < 1mil) Between Via (6571.441mil,2525.205mil) from Component Side to Bottom Side And Via (6573.441mil,2549.205mil) from Component Side to Bottom Side [Top Solder] Mask Sliver [0.083mil] / [Bottom Solder] Mask Sliver [0.083mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.083mil < 1mil) Between Via (6571.441mil,2599.205mil) from Component Side to Bottom Side And Via (6573.441mil,2575.205mil) from Component Side to Bottom Side [Top Solder] Mask Sliver [0.083mil] / [Bottom Solder] Mask Sliver [0.083mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.4mil < 1mil) Between Via (3607mil,4479.6mil) from Component Side to Bottom Side And Via (3607mil,4504mil) from Component Side to Bottom Side [Top Solder] Mask Sliver [0.4mil] / [Bottom Solder] Mask Sliver [0.4mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.4mil < 1mil) Between Via (3607mil,4455.2mil) from Component Side to Bottom Side And Via (3607mil,4479.6mil) from Component Side to Bottom Side [Top Solder] Mask Sliver [0.4mil] / [Bottom Solder] Mask Sliver [0.4mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.4mil < 1mil) Between Via (3607mil,4430.8mil) from Component Side to Bottom Side And Via (3607mil,4455.2mil) from Component Side to Bottom Side [Top Solder] Mask Sliver [0.4mil] / [Bottom Solder] Mask Sliver [0.4mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.4mil < 1mil) Between Via (3607mil,4406.4mil) from Component Side to Bottom Side And Via (3607mil,4430.8mil) from Component Side to Bottom Side [Top Solder] Mask Sliver [0.4mil] / [Bottom Solder] Mask Sliver [0.4mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.4mil < 1mil) Between Via (3607mil,4382mil) from Component Side to Bottom Side And Via (3607mil,4406.4mil) from Component Side to Bottom Side [Top Solder] Mask Sliver [0.4mil] / [Bottom Solder] Mask Sliver [0.4mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.121mil < 1mil) Between Via (2654.685mil,2030mil) from Component Side to Bottom Side And Via (2677.16mil,2035.429mil) from Component Side to Bottom Side [Top Solder] Mask Sliver [0.121mil] / [Bottom Solder] Mask Sliver [0.121mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.849mil < 1mil) Between Via (2449.685mil,2194mil) from Component Side to Bottom Side And Via (2464.099mil,2213mil) from Component Side to Bottom Side [Top Solder] Mask Sliver [0.849mil] / [Bottom Solder] Mask Sliver [0.849mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.622mil < 1mil) Between Via (1925.197mil,1992.126mil) from Component Side to Bottom Side And Via (1901.575mil,1992.126mil) from Component Side to Bottom Side [Top Solder] Mask Sliver [0.622mil] / [Bottom Solder] Mask Sliver [0.622mil]
Rule Violations :91
Processing Rule : Silk To Solder Mask (Clearance=10mil) (Disabled)(IsPad),(All)
Rule Violations :0
Processing Rule : Silk to Silk (Clearance=5mil) (All),(All)
Violation between Silk To Silk Clearance Constraint: (4.374mil < 5mil) Between Text "C76" (2854.331mil,2161.417mil) on Top Overlay And Track (2889.63mil,2195.284mil)(2897.63mil,2195.284mil) on Top Overlay Silk Text to Silk Clearance [4.374mil]
Violation between Silk To Silk Clearance Constraint: (1.61mil < 5mil) Between Text "*" (1381.89mil,2972.441mil) on Top Overlay And Track (1387mil,2961.898mil)(1387mil,2969.898mil) on Top Overlay Silk Text to Silk Clearance [1.61mil]
Violation between Silk To Silk Clearance Constraint: (4.718mil < 5mil) Between Text "C7" (3061mil,3473mil) on Top Overlay And Track (3076mil,3464mil)(3084mil,3464mil) on Top Overlay Silk Text to Silk Clearance [4.718mil]
Violation between Silk To Silk Clearance Constraint: (Collision < 5mil) Between Text "Rout1" (1409.449mil,4897.638mil) on Top Overlay And Track (1502.205mil,4828.095mil)(1502.205mil,5339.905mil) on Top Overlay Silk Text to Silk Clearance [0mil]
Violation between Silk To Silk Clearance Constraint: (Collision < 5mil) Between Text "C35" (3463.638mil,2839.394mil) on Top Overlay And Track (3462.244mil,2736.244mil)(3462.244mil,3641.756mil) on Top Overlay Silk Text to Silk Clearance [0mil]
Violation between Silk To Silk Clearance Constraint: (Collision < 5mil) Between Text "C34" (3462.638mil,2900.449mil) on Top Overlay And Track (3462.244mil,2736.244mil)(3462.244mil,3641.756mil) on Top Overlay Silk Text to Silk Clearance [0mil]
Violation between Silk To Silk Clearance Constraint: (3.656mil < 5mil) Between Text "R57" (2767.716mil,1960.63mil) on Bottom Overlay And Track (2734.684mil,1962mil)(2734.684mil,1970mil) on Bottom Overlay Silk Text to Silk Clearance [3.656mil]
Violation between Silk To Silk Clearance Constraint: (0.469mil < 5mil) Between Text "R53" (2834.646mil,2035.433mil) on Bottom Overlay And Track (2805.685mil,2002mil)(2805.685mil,2010mil) on Bottom Overlay Silk Text to Silk Clearance [0.469mil]
Violation between Silk To Silk Clearance Constraint: (4.855mil < 5mil) Between Text "R20" (6524mil,4042mil) on Bottom Overlay And Track (6449mil,4058mil)(6449mil,4066mil) on Bottom Overlay Silk Text to Silk Clearance [4.855mil]
Violation between Silk To Silk Clearance Constraint: (4.02mil < 5mil) Between Text "R19" (6519mil,3891mil) on Bottom Overlay And Track (6449mil,3904mil)(6449mil,3912mil) on Bottom Overlay Silk Text to Silk Clearance [4.02mil]
Violation between Silk To Silk Clearance Constraint: (2.303mil < 5mil) Between Text "R13" (3925.197mil,2984.252mil) on Bottom Overlay And Track (3931mil,2977mil)(3931mil,2985mil) on Bottom Overlay Silk Text to Silk Clearance [2.303mil]
Violation between Silk To Silk Clearance Constraint: (3.209mil < 5mil) Between Text "C12" (4169.291mil,3511.811mil) on Bottom Overlay And Track (4176.999mil,3482mil)(4176.999mil,3490mil) on Bottom Overlay Silk Text to Silk Clearance [3.209mil]
Violation between Silk To Silk Clearance Constraint: (4.008mil < 5mil) Between Text "R67" (2745.74mil,1857.716mil) on Top Overlay And Text "C87" (2711.74mil,1857.716mil) on Top Overlay Silk Text to Silk Clearance [4.008mil]
Violation between Silk To Silk Clearance Constraint: (2.008mil < 5mil) Between Text "C97" (2662.74mil,1874.716mil) on Top Overlay And Text "C96" (2630.74mil,1872.716mil) on Top Overlay Silk Text to Silk Clearance [2.008mil]
Violation between Silk To Silk Clearance Constraint: (3.675mil < 5mil) Between Text "R11" (4928.667mil,3833mil) on Top Overlay And Text "R10" (4962.333mil,3832mil) on Top Overlay Silk Text to Silk Clearance [3.675mil]
Violation between Silk To Silk Clearance Constraint: (2.355mil < 5mil) Between Text "R61" (2565.685mil,1754mil) on Top Overlay And Text "R59" (2639.685mil,1754mil) on Top Overlay Silk Text to Silk Clearance [2.355mil]
Violation between Silk To Silk Clearance Constraint: (4.355mil < 5mil) Between Text "R70" (2715.685mil,1754mil) on Top Overlay And Text "R59" (2639.685mil,1754mil) on Top Overlay Silk Text to Silk Clearance [4.355mil]
Violation between Silk To Silk Clearance Constraint: (4.355mil < 5mil) Between Text "R70" (2715.685mil,1754mil) on Top Overlay And Text "R69" (2791.685mil,1754mil) on Top Overlay Silk Text to Silk Clearance [4.355mil]
Violation between Silk To Silk Clearance Constraint: (4.437mil < 5mil) Between Text "R99" (5179.428mil,4852mil) on Top Overlay And Text "R80" (5213.857mil,4852mil) on Top Overlay Silk Text to Silk Clearance [4.437mil]
Violation between Silk To Silk Clearance Constraint: (4.437mil < 5mil) Between Text "R98" (5248.285mil,4852mil) on Top Overlay And Text "R80" (5213.857mil,4852mil) on Top Overlay Silk Text to Silk Clearance [4.437mil]
Violation between Silk To Silk Clearance Constraint: (4.437mil < 5mil) Between Text "R99" (5179.428mil,4852mil) on Top Overlay And Text "R97" (5145mil,4852mil) on Top Overlay Silk Text to Silk Clearance [4.437mil]
Violation between Silk To Silk Clearance Constraint: (4.437mil < 5mil) Between Text "R101" (5282.714mil,4845.752mil) on Top Overlay And Text "R98" (5248.285mil,4852mil) on Top Overlay Silk Text to Silk Clearance [4.437mil]
Violation between Silk To Silk Clearance Constraint: (4.437mil < 5mil) Between Text "R103" (5317.142mil,4841.587mil) on Top Overlay And Text "R100" (5351.571mil,4841.587mil) on Top Overlay Silk Text to Silk Clearance [4.437mil]
Violation between Silk To Silk Clearance Constraint: (4.437mil < 5mil) Between Text "R102" (5385.999mil,4841.587mil) on Top Overlay And Text "R100" (5351.571mil,4841.587mil) on Top Overlay Silk Text to Silk Clearance [4.437mil]
Violation between Silk To Silk Clearance Constraint: (4.437mil < 5mil) Between Text "R103" (5317.142mil,4841.587mil) on Top Overlay And Text "R101" (5282.714mil,4845.752mil) on Top Overlay Silk Text to Silk Clearance [4.437mil]
Rule Violations :25
Processing Rule : Net Antennae (Tolerance=0mm) (All)
Processing Rule : Net Antennae (Tolerance=0mil) (All)
Rule Violations :0
Processing Rule : Length Constraint (Min=0mm) (Max=2540mm) (All)
Processing Rule : Length Constraint (Min=0mil) (Max=100000mil) (All)
Rule Violations :0
Processing Rule : Matched Lengths(Tolerance=1.016mm) (InAnyDifferentialPair)
Violation between Matched Net Lengths: Between Net PMODB4_P And Net PMODB4_N Actual Difference against PMODB4_N is: 2.263mm, Tolerance : 1.016mm.
Violation between Matched Net Lengths: Between Net PMODB2_P And Net PMODB2_N Actual Difference against PMODB2_N is: 1.791mm, Tolerance : 1.016mm.
Violation between Matched Net Lengths: Between Net PMODB1_P And Net PMODB1_N Actual Difference against PMODB1_N is: 1.255mm, Tolerance : 1.016mm.
Violation between Matched Net Lengths: Between Net PMODA3_P And Net PMODA3_N Actual Difference against PMODA3_N is: 1.485mm, Tolerance : 1.016mm.
Violation between Matched Net Lengths: Between Net PMODA2_P And Net PMODA2_N Actual Difference against PMODA2_N is: 1.513mm, Tolerance : 1.016mm.
Violation between Matched Net Lengths: Between Net PMODA1_P And Net PMODA1_N Actual Difference against PMODA1_N is: 1.475mm, Tolerance : 1.016mm.
Violation between Matched Net Lengths: Between Net SFP2_RD_P And Net SFP2_RD_N Actual Difference against SFP2_RD_N is: 1.062mm, Tolerance : 1.016mm.
Violation between Matched Net Lengths: Between Net FMC_MGT_M2C_P And Net FMC_MGT_M2C_N Actual Difference against FMC_MGT_M2C_N is: 1.673mm, Tolerance : 1.016mm.
Violation between Matched Net Lengths: Between Net FMC_MGT_CLK_P And Net FMC_MGT_CLK_N Actual Difference against FMC_MGT_CLK_N is: 4.058mm, Tolerance : 1.016mm.
Violation between Matched Net Lengths: Between Net FMC_MGT_C2M_P And Net FMC_MGT_C2M_N Actual Difference against FMC_MGT_C2M_N is: 1.614mm, Tolerance : 1.016mm.
Violation between Matched Net Lengths: Between Net FMC_LA32_P And Net FMC_LA32_N Actual Difference against FMC_LA32_N is: 2.188mm, Tolerance : 1.016mm.
Violation between Matched Net Lengths: Between Net FMC_LA31_P And Net FMC_LA31_N Actual Difference against FMC_LA31_N is: 1.278mm, Tolerance : 1.016mm.
Violation between Matched Net Lengths: Between Net FMC_LA30_P And Net FMC_LA30_N Actual Difference against FMC_LA30_N is: 2.188mm, Tolerance : 1.016mm.
Violation between Matched Net Lengths: Between Net FMC_LA29_P And Net FMC_LA29_N Actual Difference against FMC_LA29_N is: 1.328mm, Tolerance : 1.016mm.
Violation between Matched Net Lengths: Between Net FMC_LA28_P And Net FMC_LA28_N Actual Difference against FMC_LA28_N is: 2.188mm, Tolerance : 1.016mm.
Violation between Matched Net Lengths: Between Net FMC_LA27_P And Net FMC_LA27_N Actual Difference against FMC_LA27_N is: 3.049mm, Tolerance : 1.016mm.
Violation between Matched Net Lengths: Between Net FMC_LA26_P And Net FMC_LA26_N Actual Difference against FMC_LA26_N is: 1.759mm, Tolerance : 1.016mm.
Violation between Matched Net Lengths: Between Net FMC_LA25_P And Net FMC_LA25_N Actual Difference against FMC_LA25_N is: 1.936mm, Tolerance : 1.016mm.
Violation between Matched Net Lengths: Between Net FMC_LA24_P And Net FMC_LA24_N Actual Difference against FMC_LA24_N is: 2.306mm, Tolerance : 1.016mm.
Violation between Matched Net Lengths: Between Net FMC_LA23_P And Net FMC_LA23_N Actual Difference against FMC_LA23_N is: 1.355mm, Tolerance : 1.016mm.
Violation between Matched Net Lengths: Between Net FMC_LA22_P And Net FMC_LA22_N Actual Difference against FMC_LA22_N is: 2.008mm, Tolerance : 1.016mm.
Violation between Matched Net Lengths: Between Net FMC_LA21_P And Net FMC_LA21_N Actual Difference against FMC_LA21_N is: 2.188mm, Tolerance : 1.016mm.
Violation between Matched Net Lengths: Between Net FMC_LA20_P And Net FMC_LA20_N Actual Difference against FMC_LA20_N is: 2.478mm, Tolerance : 1.016mm.
Violation between Matched Net Lengths: Between Net FMC_LA19_P And Net FMC_LA19_N Actual Difference against FMC_LA19_N is: 2.228mm, Tolerance : 1.016mm.
Violation between Matched Net Lengths: Between Net FMC_LA17_CC_P And Net FMC_LA17_CC_N Actual Difference against FMC_LA17_CC_N is: 2.188mm, Tolerance : 1.016mm.
Violation between Matched Net Lengths: Between Net FMC_LA16_P And Net FMC_LA16_N Actual Difference against FMC_LA16_N is: 2.187mm, Tolerance : 1.016mm.
Violation between Matched Net Lengths: Between Net FMC_LA15_P And Net FMC_LA15_N Actual Difference against FMC_LA15_N is: 2.188mm, Tolerance : 1.016mm.
Violation between Matched Net Lengths: Between Net FMC_LA14_P And Net FMC_LA14_N Actual Difference against FMC_LA14_N is: 2.095mm, Tolerance : 1.016mm.
Violation between Matched Net Lengths: Between Net FMC_LA13_P And Net FMC_LA13_N Actual Difference against FMC_LA13_N is: 1.686mm, Tolerance : 1.016mm.
Violation between Matched Net Lengths: Between Net FMC_LA12_P And Net FMC_LA12_N Actual Difference against FMC_LA12_N is: 1.963mm, Tolerance : 1.016mm.
Violation between Matched Net Lengths: Between Net FMC_LA10_P And Net FMC_LA10_N Actual Difference against FMC_LA10_N is: 1.762mm, Tolerance : 1.016mm.
Violation between Matched Net Lengths: Between Net FMC_LA09_P And Net FMC_LA09_N Actual Difference against FMC_LA09_N is: 2.389mm, Tolerance : 1.016mm.
Violation between Matched Net Lengths: Between Net FMC_LA08_P And Net FMC_LA08_N Actual Difference against FMC_LA08_N is: 2.183mm, Tolerance : 1.016mm.
Violation between Matched Net Lengths: Between Net FMC_LA06_P And Net FMC_LA06_N Actual Difference against FMC_LA06_N is: 3.017mm, Tolerance : 1.016mm.
Violation between Matched Net Lengths: Between Net FMC_LA05_P And Net FMC_LA05_N Actual Difference against FMC_LA05_N is: 2.16mm, Tolerance : 1.016mm.
Violation between Matched Net Lengths: Between Net FMC_LA03_P And Net FMC_LA03_N Actual Difference against FMC_LA03_N is: 2.241mm, Tolerance : 1.016mm.
Violation between Matched Net Lengths: Between Net FMC_LA02_P And Net FMC_LA02_N Actual Difference against FMC_LA02_N is: 2.725mm, Tolerance : 1.016mm.
Violation between Matched Net Lengths: Between Net FMC_LA01_CC_P And Net FMC_LA01_CC_N Actual Difference against FMC_LA01_CC_N is: 1.666mm, Tolerance : 1.016mm.
Violation between Matched Net Lengths: Between Net FMC_LA00_CC_P And Net FMC_LA00_CC_N Actual Difference against FMC_LA00_CC_N is: 3.977mm, Tolerance : 1.016mm.
Violation between Matched Net Lengths: Between Net FMC_CLK1_M2C_P And Net FMC_CLK1_M2C_N Actual Difference against FMC_CLK1_M2C_N is: 1.657mm, Tolerance : 1.016mm.
Violation between Matched Net Lengths: Between Net FMC_CLK0_M2C_P And Net FMC_CLK0_M2C_N Actual Difference against FMC_CLK0_M2C_N is: 2.504mm, Tolerance : 1.016mm.
Rule Violations :41
Processing Rule : Matched Lengths(Tolerance=40mil) (InAnyDifferentialPair)
Violation between Matched Net Lengths: Between Net FMC_CLK0_M2C_N And Net FMC_CLK0_M2C_P Actual Difference against FMC_CLK0_M2C_P is: 98.038mil, Tolerance : 40mil.
Violation between Matched Net Lengths: Between Net FMC_CLK1_M2C_N And Net FMC_CLK1_M2C_P Actual Difference against FMC_CLK1_M2C_P is: 66.294mil, Tolerance : 40mil.
Violation between Matched Net Lengths: Between Net FMC_LA00_CC_N And Net FMC_LA00_CC_P Actual Difference against FMC_LA00_CC_P is: 156.593mil, Tolerance : 40mil.
Violation between Matched Net Lengths: Between Net FMC_LA01_CC_N And Net FMC_LA01_CC_P Actual Difference against FMC_LA01_CC_P is: 65.434mil, Tolerance : 40mil.
Violation between Matched Net Lengths: Between Net FMC_LA02_N And Net FMC_LA02_P Actual Difference against FMC_LA02_P is: 107.275mil, Tolerance : 40mil.
Violation between Matched Net Lengths: Between Net FMC_LA03_N And Net FMC_LA03_P Actual Difference against FMC_LA03_P is: 88.211mil, Tolerance : 40mil.
Violation between Matched Net Lengths: Between Net FMC_LA05_N And Net FMC_LA05_P Actual Difference against FMC_LA05_P is: 86.856mil, Tolerance : 40mil.
Violation between Matched Net Lengths: Between Net FMC_LA06_N And Net FMC_LA06_P Actual Difference against FMC_LA06_P is: 118.783mil, Tolerance : 40mil.
Violation between Matched Net Lengths: Between Net FMC_LA08_N And Net FMC_LA08_P Actual Difference against FMC_LA08_P is: 85.948mil, Tolerance : 40mil.
Violation between Matched Net Lengths: Between Net FMC_LA09_N And Net FMC_LA09_P Actual Difference against FMC_LA09_P is: 94.045mil, Tolerance : 40mil.
Violation between Matched Net Lengths: Between Net FMC_LA10_N And Net FMC_LA10_P Actual Difference against FMC_LA10_P is: 69.386mil, Tolerance : 40mil.
Violation between Matched Net Lengths: Between Net FMC_LA12_N And Net FMC_LA12_P Actual Difference against FMC_LA12_P is: 78.768mil, Tolerance : 40mil.
Violation between Matched Net Lengths: Between Net FMC_LA13_N And Net FMC_LA13_P Actual Difference against FMC_LA13_P is: 66.915mil, Tolerance : 40mil.
Violation between Matched Net Lengths: Between Net FMC_LA14_N And Net FMC_LA14_P Actual Difference against FMC_LA14_P is: 82.486mil, Tolerance : 40mil.
Violation between Matched Net Lengths: Between Net FMC_LA15_N And Net FMC_LA15_P Actual Difference against FMC_LA15_P is: 86.156mil, Tolerance : 40mil.
Violation between Matched Net Lengths: Between Net FMC_LA16_N And Net FMC_LA16_P Actual Difference against FMC_LA16_P is: 86.931mil, Tolerance : 40mil.
Violation between Matched Net Lengths: Between Net FMC_LA17_CC_N And Net FMC_LA17_CC_P Actual Difference against FMC_LA17_CC_P is: 86.156mil, Tolerance : 40mil.
Violation between Matched Net Lengths: Between Net FMC_LA19_N And Net FMC_LA19_P Actual Difference against FMC_LA19_P is: 87.702mil, Tolerance : 40mil.
Violation between Matched Net Lengths: Between Net FMC_LA20_N And Net FMC_LA20_P Actual Difference against FMC_LA20_P is: 98.346mil, Tolerance : 40mil.
Violation between Matched Net Lengths: Between Net FMC_LA21_N And Net FMC_LA21_P Actual Difference against FMC_LA21_P is: 86.156mil, Tolerance : 40mil.
Violation between Matched Net Lengths: Between Net FMC_LA22_N And Net FMC_LA22_P Actual Difference against FMC_LA22_P is: 79.717mil, Tolerance : 40mil.
Violation between Matched Net Lengths: Between Net FMC_LA23_N And Net FMC_LA23_P Actual Difference against FMC_LA23_P is: 54.254mil, Tolerance : 40mil.
Violation between Matched Net Lengths: Between Net FMC_LA24_N And Net FMC_LA24_P Actual Difference against FMC_LA24_P is: 90.794mil, Tolerance : 40mil.
Violation between Matched Net Lengths: Between Net FMC_LA25_N And Net FMC_LA25_P Actual Difference against FMC_LA25_P is: 77.652mil, Tolerance : 40mil.
Violation between Matched Net Lengths: Between Net FMC_LA26_N And Net FMC_LA26_P Actual Difference against FMC_LA26_P is: 68.842mil, Tolerance : 40mil.
Violation between Matched Net Lengths: Between Net FMC_LA27_N And Net FMC_LA27_P Actual Difference against FMC_LA27_P is: 120.022mil, Tolerance : 40mil.
Violation between Matched Net Lengths: Between Net FMC_LA28_N And Net FMC_LA28_P Actual Difference against FMC_LA28_P is: 86.156mil, Tolerance : 40mil.
Violation between Matched Net Lengths: Between Net FMC_LA29_N And Net FMC_LA29_P Actual Difference against FMC_LA29_P is: 51.253mil, Tolerance : 40mil.
Violation between Matched Net Lengths: Between Net FMC_LA30_N And Net FMC_LA30_P Actual Difference against FMC_LA30_P is: 86.156mil, Tolerance : 40mil.
Violation between Matched Net Lengths: Between Net FMC_LA31_N And Net FMC_LA31_P Actual Difference against FMC_LA31_P is: 50.383mil, Tolerance : 40mil.
Violation between Matched Net Lengths: Between Net FMC_LA32_N And Net FMC_LA32_P Actual Difference against FMC_LA32_P is: 86.156mil, Tolerance : 40mil.
Violation between Matched Net Lengths: Between Net PMODA1_N And Net PMODA1_P Actual Difference against PMODA1_P is: 58.084mil, Tolerance : 40mil.
Violation between Matched Net Lengths: Between Net PMODA2_N And Net PMODA2_P Actual Difference against PMODA2_P is: 59.585mil, Tolerance : 40mil.
Violation between Matched Net Lengths: Between Net PMODA3_N And Net PMODA3_P Actual Difference against PMODA3_P is: 58.489mil, Tolerance : 40mil.
Violation between Matched Net Lengths: Between Net PMODB1_N And Net PMODB1_P Actual Difference against PMODB1_P is: 50.178mil, Tolerance : 40mil.
Violation between Matched Net Lengths: Between Net PMODB2_N And Net PMODB2_P Actual Difference against PMODB2_P is: 70.842mil, Tolerance : 40mil.
Violation between Matched Net Lengths: Between Net PMODB4_N And Net PMODB4_P Actual Difference against PMODB4_P is: 88.308mil, Tolerance : 40mil.
Rule Violations :37
Processing Rule : Max Via Stub Length (Back Drilling rule) (Max Stub Length = 0.381mm) (InAnyDifferentialPair)
Processing Rule : Max Via Stub Length (Back Drilling rule) (Max Stub Length = 15mil) (InAnyDifferentialPair)
Rule Violations :0
Processing Rule : Room SFP (Bounding Region = (0mm, 0mm, 50.8mm, 25.4mm) (Disabled)(InComponentClass('SFP'))
Processing Rule : Room FPGA_Banks2 (Bounding Region = (0mil, 0mil, 2000mil, 1000mil) (Disabled)(InComponentClass('FPGA_Banks2'))
Rule Violations :0
Processing Rule : Room Regulators (Bounding Region = (0mm, 0mm, 50.8mm, 25.4mm) (Disabled)(InComponentClass('Regulators'))
Processing Rule : Room FPGA_Banks1 (Bounding Region = (0mil, 0mil, 2000mil, 1000mil) (Disabled)(InComponentClass('FPGA_Banks1'))
Rule Violations :0
Processing Rule : Room PWR_APD5052 (Bounding Region = (0mm, 0mm, 50.8mm, 25.4mm) (Disabled)(InComponentClass('PWR_APD5052'))
Processing Rule : Room IO (Bounding Region = (0mil, 0mil, 2000mil, 1000mil) (Disabled)(InComponentClass('IO'))
Rule Violations :0
Processing Rule : Room IO (Bounding Region = (0mm, 0mm, 50.8mm, 25.4mm) (Disabled)(InComponentClass('IO'))
Processing Rule : Room FPGA_PWR (Bounding Region = (0mil, 0mil, 2000mil, 1000mil) (Disabled)(InComponentClass('FPGA_PWR'))
Rule Violations :0
Processing Rule : Room FMC (Bounding Region = (0mm, 0mm, 50.8mm, 25.4mm) (Disabled)(InComponentClass('FMC'))
Processing Rule : Room FMC (Bounding Region = (0mil, 0mil, 2000mil, 1000mil) (Disabled)(InComponentClass('FMC'))
Rule Violations :0
Processing Rule : Room Config (Bounding Region = (0mm, 0mm, 50.8mm, 25.4mm) (Disabled)(InComponentClass('Config'))
Processing Rule : Room SFP (Bounding Region = (0mil, 0mil, 2000mil, 1000mil) (Disabled)(InComponentClass('SFP'))
Rule Violations :0
Processing Rule : Room FPGA_Banks1 (Bounding Region = (0mm, 0mm, 50.8mm, 25.4mm) (Disabled)(InComponentClass('FPGA_Banks1'))
Processing Rule : Room Regulators (Bounding Region = (0mil, 0mil, 2000mil, 1000mil) (Disabled)(InComponentClass('Regulators'))
Rule Violations :0
Processing Rule : Room FPGA_PWR (Bounding Region = (0mm, 0mm, 50.8mm, 25.4mm) (Disabled)(InComponentClass('FPGA_PWR'))
Processing Rule : Room Config (Bounding Region = (0mil, 0mil, 2000mil, 1000mil) (Disabled)(InComponentClass('Config'))
Rule Violations :0
Processing Rule : Room FPGA_Banks2 (Bounding Region = (0mm, 0mm, 50.8mm, 25.4mm) (Disabled)(InComponentClass('FPGA_Banks2'))
Processing Rule : Room PWR_APD5052 (Bounding Region = (0mil, 0mil, 2000mil, 1000mil) (Disabled)(InComponentClass('PWR_APD5052'))
Rule Violations :0
Processing Rule : Height Constraint (Min=0mm) (Max=25.4mm) (Prefered=12.7mm) (All)
Processing Rule : Height Constraint (Min=0mil) (Max=1000mil) (Prefered=500mil) (All)
Rule Violations :0
Violations Detected : 165
Violations Detected : 163
Waived Violations : 0
Time Elapsed : 00:00:06
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Time Elapsed : 00:00:07
\ No newline at end of file
hardware/altium/Project Outputs for atfc/Design Rule Check - atfc.html
View file @ 411e17ef
This source diff could not be displayed because it is too large. You can view the blob instead.
hardware/altium/atfc.PrjPcb
View file @ 411e17ef
......@@ -97,7 +97,7 @@ AnnotationIndexControlEnabled=0
AnnotateSuffix=
AnnotateScope=All
AnnotateOrder=4
DoLibraryUpdate=1
DoLibraryUpdate=0
DoDatabaseUpdate=1
ClassGenCCAutoEnabled=1
ClassGenCCAutoRoomEnabled=1
......@@ -131,7 +131,7 @@ AnnotationIndexControlEnabled=0
AnnotateSuffix=
AnnotateScope=All
AnnotateOrder=8
DoLibraryUpdate=1
DoLibraryUpdate=0
DoDatabaseUpdate=1
ClassGenCCAutoEnabled=1
ClassGenCCAutoRoomEnabled=1
......@@ -148,7 +148,7 @@ AnnotationIndexControlEnabled=0
AnnotateSuffix=
AnnotateScope=All
AnnotateOrder=5
DoLibraryUpdate=1
DoLibraryUpdate=0
DoDatabaseUpdate=1
ClassGenCCAutoEnabled=1
ClassGenCCAutoRoomEnabled=1
......@@ -165,7 +165,7 @@ AnnotationIndexControlEnabled=0
AnnotateSuffix=
AnnotateScope=All
AnnotateOrder=1
DoLibraryUpdate=1
DoLibraryUpdate=0
DoDatabaseUpdate=1
ClassGenCCAutoEnabled=1
ClassGenCCAutoRoomEnabled=1
......@@ -182,7 +182,7 @@ AnnotationIndexControlEnabled=0
AnnotateSuffix=
AnnotateScope=All
AnnotateOrder=2
DoLibraryUpdate=1
DoLibraryUpdate=0
DoDatabaseUpdate=1
ClassGenCCAutoEnabled=1
ClassGenCCAutoRoomEnabled=1
......@@ -199,7 +199,7 @@ AnnotationIndexControlEnabled=0
AnnotateSuffix=
AnnotateScope=All
AnnotateOrder=3
DoLibraryUpdate=1
DoLibraryUpdate=0
DoDatabaseUpdate=1
ClassGenCCAutoEnabled=1
ClassGenCCAutoRoomEnabled=1
......@@ -216,7 +216,7 @@ AnnotationIndexControlEnabled=0
AnnotateSuffix=
AnnotateScope=All
AnnotateOrder=7
DoLibraryUpdate=1
DoLibraryUpdate=0
DoDatabaseUpdate=1
ClassGenCCAutoEnabled=1
ClassGenCCAutoRoomEnabled=1
......@@ -233,7 +233,7 @@ AnnotationIndexControlEnabled=0
AnnotateSuffix=
AnnotateScope=All
AnnotateOrder=0
DoLibraryUpdate=1
DoLibraryUpdate=0
DoDatabaseUpdate=1
ClassGenCCAutoEnabled=1
ClassGenCCAutoRoomEnabled=1
......@@ -484,6 +484,20 @@ SaveSettingsToOutJob=-1
[Generic_EDE]
OutputDir=
[Generic_SignalIntegritySimulation]
SignalIntegrityInitialised=-1
TrackImpedance=100
TrackLength=20000000
UseManhattan=-1
UseSupplyNetsRules=-1
SupplyNetsCount=0
UseStimulusRules=-1
StimKind=1
StimLevel=0
StimStartTime=1E-8
StimStopTime=6E-8
StimPeriodTime=1E-7
[OutputGroup1]
Name=Netlist Outputs
Description=
......@@ -1591,32 +1605,32 @@ ComponentUpdate1=0
ComponentIsDeviceSheet1=0
ComponentLibIdentifierKind2=Library Name And Type
ComponentLibraryIdentifier2=atfclib.SchLib
ComponentDesignItemID2=ADP2384ACPZN-R7
ComponentSymbolReference2=ADP2384ACPZN-R7
ComponentDesignItemID2=ADP1752ACPZ-1.0-R7
ComponentSymbolReference2=ADP1752ACPZ-1.0-R7
ComponentUpdate2=0
ComponentIsDeviceSheet2=0
ComponentLibIdentifierKind3=Library Name And Type
ComponentLibraryIdentifier3=atfclib.SchLib
ComponentDesignItemID3=ADP5052ACPZ-R7
ComponentSymbolReference3=ADP5052ACPZ-R7
ComponentDesignItemID3=ADP2384ACPZN-R7
ComponentSymbolReference3=ADP2384ACPZN-R7
ComponentUpdate3=0
ComponentIsDeviceSheet3=0
ComponentLibIdentifierKind4=Library Name And Type
ComponentLibraryIdentifier4=atfclib.SchLib
ComponentDesignItemID4=ADR127BUJZ-REEL7
ComponentSymbolReference4=ADR127BUJZ-REEL7
ComponentDesignItemID4=ADP5052ACPZ-R7
ComponentSymbolReference4=ADP5052ACPZ-R7
ComponentUpdate4=0
ComponentIsDeviceSheet4=0
ComponentLibIdentifierKind5=Library Name And Type
ComponentLibraryIdentifier5=atfclib.SchLib
ComponentDesignItemID5=ASP-134603-01
ComponentSymbolReference5=ASP-134603-01
ComponentDesignItemID5=ADR127BUJZ-REEL7
ComponentSymbolReference5=ADR127BUJZ-REEL7
ComponentUpdate5=0
ComponentIsDeviceSheet5=0
ComponentLibIdentifierKind6=Library Name And Type
ComponentLibraryIdentifier6=atfclib.SchLib
ComponentDesignItemID6=BSO150N03MD G
ComponentSymbolReference6=BSO150N03MD G
ComponentDesignItemID6=ASP-134603-01
ComponentSymbolReference6=ASP-134603-01
ComponentUpdate6=0
ComponentIsDeviceSheet6=0
ComponentLibIdentifierKind7=Library Name And Type
......@@ -1639,9 +1653,9 @@ ComponentUpdate9=0
ComponentIsDeviceSheet9=0
ComponentLibIdentifierKind10=Library Name And Type
ComponentLibraryIdentifier10=atfclib.SchLib
ComponentDesignItemID10=DSC1123CE1-125
ComponentSymbolReference10=DSC1123CE1-125
ComponentUpdate10=1
ComponentDesignItemID10=EM6K6
ComponentSymbolReference10=EM6K6
ComponentUpdate10=0
ComponentIsDeviceSheet10=0
ComponentLibIdentifierKind11=Library Name And Type
ComponentLibraryIdentifier11=atfclib.SchLib
......@@ -1663,82 +1677,118 @@ ComponentUpdate13=0
ComponentIsDeviceSheet13=0
ComponentLibIdentifierKind14=Library Name And Type
ComponentLibraryIdentifier14=atfclib.SchLib
ComponentDesignItemID14=MBR0530
ComponentSymbolReference14=MBR0530
ComponentDesignItemID14=LT6106CS5
ComponentSymbolReference14=LT6106CS5
ComponentUpdate14=0
ComponentIsDeviceSheet14=0
ComponentLibIdentifierKind15=Library Name And Type
ComponentLibraryIdentifier15=atfclib.SchLib
ComponentDesignItemID15=PRTR5V0U4Y
ComponentSymbolReference15=PRTR5V0U4Y
ComponentDesignItemID15=MBR0530
ComponentSymbolReference15=MBR0530
ComponentUpdate15=0
ComponentIsDeviceSheet15=0
ComponentLibIdentifierKind16=Library Name And Type
ComponentLibraryIdentifier16=atfclib.SchLib
ComponentDesignItemID16=Res
ComponentSymbolReference16=Res
ComponentDesignItemID16=PRTR5V0U4Y
ComponentSymbolReference16=PRTR5V0U4Y
ComponentUpdate16=0
ComponentIsDeviceSheet16=0
ComponentLibIdentifierKind17=Library Name And Type
ComponentLibraryIdentifier17=atfclib.SchLib
ComponentDesignItemID17=S25FL128SAGMFI001
ComponentSymbolReference17=S25FL128SAGMFI001
ComponentUpdate17=0
ComponentDesignItemID17=PWR2.5
ComponentSymbolReference17=PWR2.5
ComponentUpdate17=1
ComponentIsDeviceSheet17=0
ComponentLibIdentifierKind18=Library Name And Type
ComponentLibraryIdentifier18=atfclib.SchLib
ComponentDesignItemID18=SFP+
ComponentSymbolReference18=SFP+
ComponentDesignItemID18=Res
ComponentSymbolReference18=Res
ComponentUpdate18=0
ComponentIsDeviceSheet18=0
ComponentLibIdentifierKind19=Library Name And Type
ComponentLibraryIdentifier19=atfclib.SchLib
ComponentDesignItemID19=TS42
ComponentSymbolReference19=TS42
ComponentDesignItemID19=Res_sense
ComponentSymbolReference19=Res_sense
ComponentUpdate19=0
ComponentIsDeviceSheet19=0
ComponentLibIdentifierKind20=Library Name And Type
ComponentLibraryIdentifier20=atfclib.SchLib
ComponentDesignItemID20=XC7A35T-1FGG484C
ComponentSymbolReference20=XC7A35T-1FGG484C
ComponentDesignItemID20=S25FL128SAGMFI001
ComponentSymbolReference20=S25FL128SAGMFI001
ComponentUpdate20=0
ComponentIsDeviceSheet20=0
ComponentLibIdentifierKind21=Library Name And Type
ComponentLibraryIdentifier21=Miscellaneous Connectors.IntLib
ComponentDesignItemID21=Header 4X2
ComponentSymbolReference21=Header 4X2
ComponentLibraryIdentifier21=atfclib.SchLib
ComponentDesignItemID21=SFP+
ComponentSymbolReference21=SFP+
ComponentUpdate21=0
ComponentIsDeviceSheet21=0
ComponentLibIdentifierKind22=Library Name And Type
ComponentLibraryIdentifier22=Miscellaneous Connectors.IntLib
ComponentDesignItemID22=Header 6
ComponentSymbolReference22=Header 6
ComponentUpdate22=0
ComponentLibraryIdentifier22=atfclib.SchLib
ComponentDesignItemID22=SFPcagedual
ComponentSymbolReference22=SFPcagedual
ComponentUpdate22=1
ComponentIsDeviceSheet22=0
ComponentLibIdentifierKind23=Library Name And Type
ComponentLibraryIdentifier23=Miscellaneous Devices.IntLib
ComponentDesignItemID23=Cap Pol3
ComponentSymbolReference23=Cap Pol3
ComponentLibraryIdentifier23=atfclib.SchLib
ComponentDesignItemID23=SI7232DN-T1-GE3
ComponentSymbolReference23=SI7232DN-T1-GE3
ComponentUpdate23=0
ComponentIsDeviceSheet23=0
ComponentLibIdentifierKind24=Library Name And Type
ComponentLibraryIdentifier24=Miscellaneous Devices.IntLib
ComponentDesignItemID24=LED2
ComponentSymbolReference24=LED2
ComponentLibraryIdentifier24=atfclib.SchLib
ComponentDesignItemID24=TS42
ComponentSymbolReference24=TS42
ComponentUpdate24=0
ComponentIsDeviceSheet24=0
ComponentLibIdentifierKind25=Library Name And Type
ComponentLibraryIdentifier25=Miscellaneous Devices.IntLib
ComponentDesignItemID25=SW DIP-4
ComponentSymbolReference25=SW DIP-4
ComponentLibraryIdentifier25=atfclib.SchLib
ComponentDesignItemID25=XC7A35T-1FGG484C
ComponentSymbolReference25=XC7A35T-1FGG484C
ComponentUpdate25=0
ComponentIsDeviceSheet25=0
ComponentLibIdentifierKind26=Library Name And Type
ComponentLibraryIdentifier26=Miscellaneous Devices.IntLib
ComponentDesignItemID26=SW-SPDT
ComponentSymbolReference26=SW-SPDT
ComponentLibraryIdentifier26=Miscellaneous Connectors.IntLib
ComponentDesignItemID26=Header 2
ComponentSymbolReference26=Header 2
ComponentUpdate26=0
ComponentIsDeviceSheet26=0
ComponentLibIdentifierKind27=Library Name And Type
ComponentLibraryIdentifier27=Miscellaneous Connectors.IntLib
ComponentDesignItemID27=Header 6X2
ComponentSymbolReference27=Header 6X2
ComponentUpdate27=0
ComponentIsDeviceSheet27=0
ComponentLibIdentifierKind28=Library Name And Type
ComponentLibraryIdentifier28=Miscellaneous Connectors.IntLib
ComponentDesignItemID28=Header 6X2A
ComponentSymbolReference28=Header 6X2A
ComponentUpdate28=0
ComponentIsDeviceSheet28=0
ComponentLibIdentifierKind29=Library Name And Type
ComponentLibraryIdentifier29=Miscellaneous Connectors.IntLib
ComponentDesignItemID29=Header 7X2
ComponentSymbolReference29=Header 7X2
ComponentUpdate29=0
ComponentIsDeviceSheet29=0
ComponentLibIdentifierKind30=Library Name And Type
ComponentLibraryIdentifier30=Miscellaneous Devices.IntLib
ComponentDesignItemID30=Cap Pol3
ComponentSymbolReference30=Cap Pol3
ComponentUpdate30=0
ComponentIsDeviceSheet30=0
ComponentLibIdentifierKind31=Library Name And Type
ComponentLibraryIdentifier31=Miscellaneous Devices.IntLib
ComponentDesignItemID31=SW DIP-4
ComponentSymbolReference31=SW DIP-4
ComponentUpdate31=0
ComponentIsDeviceSheet31=0
ComponentLibIdentifierKind32=Library Name And Type
ComponentLibraryIdentifier32=Miscellaneous Devices.IntLib
ComponentDesignItemID32=SW-SPDT
ComponentSymbolReference32=SW-SPDT
ComponentUpdate32=0
ComponentIsDeviceSheet32=0
FullReplace=1
UpdateDesignatorLock=1
UpdatePartIDLock=1
......@@ -1754,61 +1804,61 @@ RemoveModels=1
UpdateCurrentModels=1
ParameterName0=Available User I/O
ParameterUpdate0=1
ParameterName1=Clock Mgmt Tiles (CMTs)
ParameterName1=Channels (#)
ParameterUpdate1=1
ParameterName2=Code_IEC
ParameterName2=Clock Mgmt Tiles (CMTs)
ParameterUpdate2=1
ParameterName3=Code_IPC
ParameterName3=Code_IEC
ParameterUpdate3=1
ParameterName4=Code_JEDEC
ParameterName4=Code_IPC
ParameterUpdate4=1
ParameterName5=Code_JEITA
ParameterName5=Code_JEDEC
ParameterUpdate5=1
ParameterName6=Comment
ParameterName6=Code_JEITA
ParameterUpdate6=1
ParameterName7=Component Kind
ParameterName7=Comment
ParameterUpdate7=1
ParameterName8=ComponentLink1Description
ParameterName8=Component Kind
ParameterUpdate8=1
ParameterName9=ComponentLink1URL
ParameterName9=ComponentLink1Description
ParameterUpdate9=1
ParameterName10=ComponentLink2Description
ParameterName10=ComponentLink1URL
ParameterUpdate10=1
ParameterName11=ComponentLink2URL
ParameterName11=ComponentLink2Description
ParameterUpdate11=1
ParameterName12=ComponentLink3Description
ParameterName12=ComponentLink2URL
ParameterUpdate12=1
ParameterName13=ComponentLink3URL
ParameterName13=ComponentLink3Description
ParameterUpdate13=1
ParameterName14=ComponentLink4Description
ParameterName14=ComponentLink3URL
ParameterUpdate14=1
ParameterName15=ComponentLink4URL
ParameterName15=ComponentLink4Description
ParameterUpdate15=1
ParameterName16=ComponentLink5Description
ParameterName16=ComponentLink4URL
ParameterUpdate16=1
ParameterName17=ComponentLink5URL
ParameterName17=ComponentLink5Description
ParameterUpdate17=1
ParameterName18=ComponentLink6Description
ParameterName18=ComponentLink5URL
ParameterUpdate18=1
ParameterName19=ComponentLink6URL
ParameterName19=ComponentLink6Description
ParameterUpdate19=1
ParameterName20=CREATED
ParameterName20=ComponentLink6URL
ParameterUpdate20=1
ParameterName21=DatasheetVersion
ParameterName21=CREATED
ParameterUpdate21=1
ParameterName22=Description
ParameterName22=DatasheetDocument
ParameterUpdate22=1
ParameterName23=Green
ParameterName23=DatasheetVersion
ParameterUpdate23=1
ParameterName24=GTP
ParameterName24=Description
ParameterUpdate24=1
ParameterName25=Halogen-free
ParameterName25=GBW (MHz) Typical
ParameterUpdate25=1
ParameterName26=ID (max)
ParameterName26=GTP
ParameterUpdate26=1
ParameterName27=IDpuls (max)
ParameterName27=Iout max
ParameterUpdate27=1
ParameterName28=Iout max
ParameterName28=Is (mA) Typical
ParameterUpdate28=1
ParameterName29=LatestRevisionDate
ParameterUpdate29=1
......@@ -1816,284 +1866,310 @@ ParameterName30=LatestRevisionNote
ParameterUpdate30=1
ParameterName31=Library Reference
ParameterUpdate31=1
ParameterName32=Logic Cells
ParameterName32=Linear Technology Part Number
ParameterUpdate32=1
ParameterName33=Manufacturer
ParameterName33=Logic Cells
ParameterUpdate33=1
ParameterName34=Max V Supply (V)
ParameterName34=Manufacturer
ParameterUpdate34=1
ParameterName35=Maximum Distributed RAM
ParameterName35=Max V Supply (V)
ParameterUpdate35=1
ParameterName36=Min V Supply (V)
ParameterName36=Maximum Distributed RAM
ParameterUpdate36=1
ParameterName37=MODIFIED
ParameterName37=Min V Supply (V)
ParameterUpdate37=1
ParameterName38=Mounting Technology
ParameterName38=MODIFIED
ParameterUpdate38=1
ParameterName39=NexusDeviceID
ParameterName39=Mounting Technology
ParameterUpdate39=1
ParameterName40=Operating Temp Range
ParameterName40=NexusDeviceID
ParameterUpdate40=1
ParameterName41=Operating Temperature Range
ParameterName41=Operating Temp Range
ParameterUpdate41=1
ParameterName42=PackageDescription
ParameterName42=Operating Temperature Range
ParameterUpdate42=1
ParameterName43=PackageReference
ParameterName43=PackageDescription
ParameterUpdate43=1
ParameterName44=PackageVersion
ParameterName44=PackageReference
ParameterUpdate44=1
ParameterName45=Packing
ParameterName45=PackageVersion
ParameterUpdate45=1
ParameterName46=PartNo
ParameterName46=Packing
ParameterUpdate46=1
ParameterName47=PartNumber
ParameterName47=PartNo
ParameterUpdate47=1
ParameterName48=PCB DECAL
ParameterName48=PartNumber
ParameterUpdate48=1
ParameterName49=Polarity
ParameterName49=PCB DECAL
ParameterUpdate49=1
ParameterName50=Ptot (max)
ParameterName50=Preset Vout Values (V)
ParameterUpdate50=1
ParameterName51=Published
ParameterUpdate51=1
ParameterName52=Publisher
ParameterUpdate52=1
ParameterName53=QG
ParameterName53=Ref Out TC (ppm/C)
ParameterUpdate53=1
ParameterName54=RDS (on) (max)
ParameterName54=RefDes
ParameterUpdate54=1
ParameterName55=RDS (on) (max) (@4.5V)
ParameterName55=Speed Grades
ParameterUpdate55=1
ParameterName56=Ref Out TC (ppm/C)
ParameterName56=Supplier 1
ParameterUpdate56=1
ParameterName57=RefDes
ParameterName57=Supplier 2
ParameterUpdate57=1
ParameterName58=Rth
ParameterName58=Supplier 3
ParameterUpdate58=1
ParameterName59=RthJA (max)
ParameterName59=Supplier 4
ParameterUpdate59=1
ParameterName60=RthJC (max)
ParameterName60=Supplier 5
ParameterUpdate60=1
ParameterName61=Speed Grades
ParameterName61=Supplier 6
ParameterUpdate61=1
ParameterName62=Supplier 1
ParameterName62=Supplier 7
ParameterUpdate62=1
ParameterName63=Supplier 2
ParameterName63=Supplier 8
ParameterUpdate63=1
ParameterName64=Supplier 3
ParameterName64=Supplier Part Number 1
ParameterUpdate64=1
ParameterName65=Supplier 4
ParameterName65=Supplier Part Number 2
ParameterUpdate65=1
ParameterName66=Supplier 5
ParameterName66=Supplier Part Number 3
ParameterUpdate66=1
ParameterName67=Supplier 6
ParameterName67=Supplier Part Number 4
ParameterUpdate67=1
ParameterName68=Supplier 7
ParameterName68=Supplier Part Number 5
ParameterUpdate68=1
ParameterName69=Supplier 8
ParameterName69=Supplier Part Number 6
ParameterUpdate69=1
ParameterName70=Supplier Part Number 1
ParameterName70=Supplier Part Number 7
ParameterUpdate70=1
ParameterName71=Supplier Part Number 2
ParameterName71=Supplier Part Number 8
ParameterUpdate71=1
ParameterName72=Supplier Part Number 3
ParameterName72=Supply Current IGND @ Small Load
ParameterUpdate72=1
ParameterName73=Supplier Part Number 4
ParameterName73=Tolerance
ParameterUpdate73=1
ParameterName74=Supplier Part Number 5
ParameterName74=Total Block RAM
ParameterUpdate74=1
ParameterName75=Supplier Part Number 6
ParameterName75=Type
ParameterUpdate75=1
ParameterName76=Supplier Part Number 7
ParameterName76=Value
ParameterUpdate76=1
ParameterName77=Supplier Part Number 8
ParameterName77=Vin (max) (V)
ParameterUpdate77=1
ParameterName78=Supply Current IGND @ Small Load
ParameterName78=Vin (min) (V)
ParameterUpdate78=1
ParameterName79=Tolerance
ParameterName79=Vos (mV) Guaranteed
ParameterUpdate79=1
ParameterName80=Total Block RAM
ParameterName80=Vos (mV) Typical
ParameterUpdate80=1
ParameterName81=Type
ParameterName81=Vout
ParameterUpdate81=1
ParameterName82=Value
ParameterName82=Vout Adjustable Range
ParameterUpdate82=1
ParameterName83=VDS (max)
ParameterName83=Vs Max (V)
ParameterUpdate83=1
ParameterName84=VGS(th) (max)
ParameterName84=Vs Min (V)
ParameterUpdate84=1
ParameterName85=VGS(th) (min)
ParameterUpdate85=1
ParameterName86=Vin (max) (V)
ParameterUpdate86=1
ParameterName87=Vin (min) (V)
ParameterUpdate87=1
ParameterName88=Vout
ParameterUpdate88=1
ParameterName89=Vout Adjustable Range
ParameterUpdate89=1
ModelTypeGroup0=PCBLIB
ModelTypeUpdate0=1
ModelType0=PCBLIB
ModelName0=1812
ModelName0=1212-8dual
ModelUpdate0=1
ModelType1=PCBLIB
ModelName1=1825
ModelName1=1812
ModelUpdate1=1
ModelType2=PCBLIB
ModelName2=2220
ModelName2=1825
ModelUpdate2=1
ModelType3=PCBLIB
ModelName3=3.2X1.6X1.1
ModelName3=2220
ModelUpdate3=1
ModelType4=PCBLIB
ModelName4=ADI-UJ-5_L
ModelName4=87831-1420
ModelUpdate4=1
ModelType5=PCBLIB
ModelName5=ADI-UJ-5_M
ModelName5=ADI-UJ-5_L
ModelUpdate5=1
ModelType6=PCBLIB
ModelName6=ADI-UJ-5_N
ModelName6=ADI-UJ-5_M
ModelUpdate6=1
ModelType7=PCBLIB
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ModelUpdate7=1
ModelType8=PCBLIB
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ModelUpdate8=1
ModelType9=PCBLIB
ModelName9=ADI-UJ-6_N
ModelName9=ADI-UJ-6_M
ModelUpdate9=1
ModelType10=PCBLIB
ModelName10=ASMB-MTB0-0A3A2
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ModelUpdate10=1
ModelType11=PCBLIB
ModelName11=ASP-134603-01
ModelName11=ASMB-MTB0-0A3A2
ModelUpdate11=1
ModelType12=PCBLIB
ModelName12=B3S-1002
ModelName12=ASP-134603-01
ModelUpdate12=1
ModelType13=PCBLIB
ModelName13=C0402
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ModelUpdate13=1
ModelType14=PCBLIB
ModelName14=C0603
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ModelUpdate14=1
ModelType15=PCBLIB
ModelName15=C0805
ModelName15=C0603
ModelUpdate15=1
ModelType16=PCBLIB
ModelName16=C1206
ModelName16=C0805
ModelUpdate16=1
ModelType17=PCBLIB
ModelName17=C1206_P
ModelName17=C1206
ModelUpdate17=1
ModelType18=PCBLIB
ModelName18=C1210
ModelName18=C1206_P
ModelUpdate18=1
ModelType19=PCBLIB
ModelName19=C2225
ModelName19=C1210
ModelUpdate19=1
ModelType20=PCBLIB
ModelName20=CP_24_12
ModelName20=C2225
ModelUpdate20=1
ModelType21=PCBLIB
ModelName21=CP_48_13
ModelName21=C7343
ModelUpdate21=1
ModelType22=PCBLIB
ModelName22=DSC1123_32_25
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ModelUpdate22=1
ModelType23=PCBLIB
ModelName23=DSC1123_7_5
ModelName23=CP_48_13
ModelUpdate23=1
ModelType24=PCBLIB
ModelName24=FGG484
ModelName24=CP-16-4_L
ModelUpdate24=1
ModelType25=PCBLIB
ModelName25=HDR1X6
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ModelUpdate25=1
ModelType26=PCBLIB
ModelName26=HDR2X4
ModelName26=CP-16-4_N
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ModelName27=INF-PG-DSO-8-16_L
ModelName27=DR0608
ModelUpdate27=1
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ModelName28=DSC1123_32_25
ModelUpdate28=1
ModelType29=PCBLIB
ModelName29=INF-PG-DSO-8-16_N
ModelName29=DSC1123_7_5
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ModelType30=PCBLIB
ModelName30=MCHP-SOT-23-OT6_L
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ModelUpdate30=1
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ModelName31=HDR1X2
ModelUpdate31=1
ModelType32=PCBLIB
ModelName32=MCHP-SOT-23-OT6_N
ModelName32=HDR2X6
ModelUpdate32=1
ModelType33=PCBLIB
ModelName33=MSS1048
ModelName33=KLD2020
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ModelType34=PCBLIB
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ModelType35=PCBLIB
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ModelType36=PCBLIB
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ModelUpdate36=1
ModelType37=PCBLIB
ModelName37=SD43
ModelName37=LT-S5-5-TSOT-23_M
ModelUpdate37=1
ModelType38=PCBLIB
ModelName38=SFP+20
ModelName38=LT-S5-5-TSOT-23_N
ModelUpdate38=1
ModelType39=PCBLIB
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ModelUpdate41=1
ModelType42=PCBLIB
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ModelName42=MFP106D
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ModelType43=PCBLIB
ModelName43=SOIC16
ModelName43=MSS1048
ModelUpdate43=1
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ModelName44=PMOD_12
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ModelType46=PCBLIB
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ModelType48=PCBLIB
ModelName48=SD43
ModelUpdate48=1
ModelTypeGroup2=SIM
ModelTypeUpdate2=1
ModelType49=SIM
ModelName49=CAP
ModelType49=PCBLIB
ModelName49=SFP+20
ModelUpdate49=1
ModelType50=SIM
ModelName50=dpsw4
ModelType50=PCBLIB
ModelName50=SFPcage - dual
ModelUpdate50=1
ModelType51=SIM
ModelName51=LED2
ModelType51=PCBLIB
ModelName51=SO8_L
ModelUpdate51=1
ModelType52=PCBLIB
ModelName52=SO8_M
ModelUpdate52=1
ModelType53=PCBLIB
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ModelUpdate53=1
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ModelUpdate54=1
ModelType55=PCBLIB
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ModelUpdate55=1
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ModelUpdate56=1
ModelType57=PCBLIB
ModelName57=SOT-563
ModelUpdate57=1
ModelType58=PCBLIB
ModelName58=SRP2512
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ModelTypeGroup1=SI
ModelTypeUpdate1=1
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ModelName59=Cap Pol
ModelUpdate59=1
ModelType60=SI
ModelName60=Connector
ModelUpdate60=1
ModelType61=SI
ModelName61=Guessed Model
ModelUpdate61=1
ModelTypeGroup2=SIM
ModelTypeUpdate2=1
ModelType62=SIM
ModelName62=CAP
ModelUpdate62=1
ModelType63=SIM
ModelName63=dpsw4
ModelUpdate63=1
[DatabaseUpdateOptions]
SelectedOnly=0
......
hardware/atfc.ucf 0 → 100644
View file @ 411e17ef
NET "SFP1_MOD_ABS" LOC="A13" | IOSTANDARD=LVCMOS33;
NET "SFP1_TX_EN" LOC="A14" | IOSTANDARD=LVCMOS33;
NET "SFP1_TX_FAULT" LOC="A15" | IOSTANDARD=LVCMOS33;
NET "SFP1_SCL" LOC="A16" | IOSTANDARD=LVCMOS33;
NET "SFP2_MOD_ABS" LOC="A18" | IOSTANDARD=LVCMOS33;
NET "SFP2_TX_EN" LOC="A19" | IOSTANDARD=LVCMOS33;
NET "SFP2_TX_FAULT" LOC="A20" | IOSTANDARD=LVCMOS33;
NET "SFP2_SCL" LOC="A21" | IOSTANDARD=LVCMOS33;
NET "SFP1_SDA" LOC="B15" | IOSTANDARD=LVCMOS33;
NET "SFP1_LOS" LOC="B17" | IOSTANDARD=LVCMOS33;
NET "SFP2_SDA" LOC="B20" | IOSTANDARD=LVCMOS33;
NET "SFP2_LOS" LOC="B21" | IOSTANDARD=LVCMOS33;
NET "PMODA3_N" LOC="B22" | IOSTANDARD=LVCMOS33;
NET "RGB_B1" LOC="C13" | IOSTANDARD=LVCMOS33;
NET "RGB_G1" LOC="C14" | IOSTANDARD=LVCMOS33;
NET "RGB_R1" LOC="C15" | IOSTANDARD=LVCMOS33;
NET "RGB_B2" LOC="C17" | IOSTANDARD=LVCMOS33;
NET "RGB_G2" LOC="C18" | IOSTANDARD=LVCMOS33;
NET "RGB_R2" LOC="C19" | IOSTANDARD=LVCMOS33;
NET "PMODB1_N" LOC="C20" | IOSTANDARD=LVCMOS33;
NET "PMODA3_P" LOC="C22" | IOSTANDARD=LVCMOS33;
NET "PMODB3_P" LOC="D14" | IOSTANDARD=LVCMOS33;
NET "PMODB3_N" LOC="D15" | IOSTANDARD=LVCMOS33;
NET "PMODB4_N" LOC="D16" | IOSTANDARD=LVCMOS33;
NET "SYSCLK" LOC="D17" | IOSTANDARD=LVCMOS33;
NET "PMODB1_P" LOC="D20" | IOSTANDARD=LVCMOS33;
NET "PMODA1_N" LOC="D22" | IOSTANDARD=LVCMOS33;
NET "PMODB2_P" LOC="E13" | IOSTANDARD=LVCMOS33;
NET "PMODB2_N" LOC="E14" | IOSTANDARD=LVCMOS33;
NET "PMODB4_P" LOC="E16" | IOSTANDARD=LVCMOS33;
NET "PMODA1_P" LOC="E22" | IOSTANDARD=LVCMOS33;
NET "LED1" LOC="F20" | IOSTANDARD=LVCMOS33;
NET "LED0" LOC="F21" | IOSTANDARD=LVCMOS33;
NET "PMODA4_P" LOC="G21" | IOSTANDARD=LVCMOS33;
NET "PMODA4_" LOC="G22" | IOSTANDARD=LVCMOS33;
NET "MGTAVCC1V0_MON" LOC="G15" | IOSTANDARD=LVCMOS33;
NET "VCC1V0_MON" LOC="G16" | IOSTANDARD=LVCMOS33;
NET "X_3V3_I_MON" LOC="H14" | IOSTANDARD=LVCMOS33;
NET "X_12V0_I_MON" LOC="H15" | IOSTANDARD=LVCMOS33;
NET "VCC1V8_MON" LOC="H20" | IOSTANDARD=LVCMOS33;
NET "PMODA2_N" LOC="H22" | IOSTANDARD=LVCMOS25;
NET "MGTAVTT1V2_MON" LOC="J14" | IOSTANDARD=LVCMOS33;
NET "VADJ_I_MON" LOC="J15" | IOSTANDARD=LVCMOS33;
NET "PMODA2_P" LOC="J22" | IOSTANDARD=LVCMOS25;
NET "VADJ_MON" LOC="L21" | IOSTANDARD=LVCMOS33;
NET "VCC3V3_MON" LOC="M21" | IOSTANDARD=LVCMOS33;
NET "DIP1" LOC="AA18" | IOSTANDARD=LVCMOS33;
NET "DIP2" LOC="AA19" | IOSTANDARD=LVCMOS33;
NET "DIP3" LOC="AA20" | IOSTANDARD=LVCMOS33;
NET "DIP4" LOC="AA21" | IOSTANDARD=LVCMOS33;
NET "SCL" LOC="AB21" | IOSTANDARD=LVCMOS33;
NET "SDA" LOC="AB22" | IOSTANDARD=LVCMOS33;
#NET "QSPI_IO2" LOC="P21" | IOSTANDARD=CONFIG;
#NET "QSPI_IO0" LOC="P22" | IOSTANDARD=CONFIG;
#NET "QSPI_IO3" LOC="R21" | IOSTANDARD=CONFIG;
#NET "QSPI_IO1" LOC="R22" | IOSTANDARD=CONFIG;
#NET "QSPI_CS" LOC="T19" | IOSTANDARD=CONFIG;
NET "PRESNT_M2C" LOC="T21" | IOSTANDARD=LVCMOS25;
NET "PGOOD_VADJ_R" LOC="U21" | IOSTANDARD=LVCMOS25;
NET "PGOOD_R" LOC="U22" | IOSTANDARD=LVCMOS33;
NET "SFP1_RD_N" LOC="A8";
NET "SFP2_RD_N" LOC="A10";
NET "SFP1_RD_P" LOC="B8";
NET "SFP2_RD_P" LOC="B10";
NET "FMC_MGT_M2C_N" LOC="C9";
NET "FMC_MGT_M2C_P" LOC="D9";
NET "GTP_CLK_N" LOC="E6";
NET "FMC_MGT_CLK_N" LOC="E10";
NET "GTP_CLK_P" LOC="F6";
NET "FMC_MGT_CLK_" LOC="F10";
NET "FMC_LA32_N" LOC="A1 " | IOSTANDARD=LVDS_25;
NET "FMC_LA32_P" LOC="B1 " | IOSTANDARD=LVDS_25;
NET "FMC_LA28_N" LOC="B2 " | IOSTANDARD=LVDS_25;
NET "FMC_LA28_P" LOC="C2 " | IOSTANDARD=LVDS_25;
NET "FMC_LA30_N" LOC="D1 " | IOSTANDARD=LVDS_25;
NET "FMC_LA30_P" LOC="E1 " | IOSTANDARD=LVDS_25;
NET "VREF_A_M2C" LOC="E3 " | IOSTANDARD=LVCMOS25;
NET "FMC_LA24_N" LOC="F1 " | IOSTANDARD=LVDS_25;
NET "FMC_LA24_P" LOC="G1 " | IOSTANDARD=LVDS_25;
NET "FMC_LA03_N" LOC="G2 " | IOSTANDARD=LVDS_25;
NET "FMC_LA17_CC_N" LOC="G4 " | IOSTANDARD=LVDS_25;
NET "FMC_LA03_P" LOC="H2 " | IOSTANDARD=LVDS_25;
NET "FMC_LA17_CC_P" LOC="H4 " | IOSTANDARD=LVDS_25;
NET "FMC_LA21_N" LOC="J1 " | IOSTANDARD=LVDS_25;
NET "FMC_LA08_N" LOC="J2 " | IOSTANDARD=LVDS_25;
NET "FMC_LA18_CC_N" LOC="J4 " | IOSTANDARD=LVDS_25;
NET "FMC_LA21_P" LOC="K1 " | IOSTANDARD=LVDS_25;
NET "FMC_LA08_P" LOC="K2 " | IOSTANDARD=LVDS_25;
NET "FMC_LA02_N" LOC="K3 " | IOSTANDARD=LVDS_25;
NET "FMC_LA18_CC_P" LOC="K4 " | IOSTANDARD=LVDS_25;
NET "FMC_LA19_N" LOC="L1 " | IOSTANDARD=LVDS_25;
NET "FMC_LA02_P" LOC="L3 " | IOSTANDARD=LVDS_25;
NET "FMC_LA31_N" LOC="L4 " | IOSTANDARD=LVDS_25;
NET "FMC_LA31_P" LOC="L5 " | IOSTANDARD=LVDS_25;
NET "FMC_LA19_P" LOC="M1 " | IOSTANDARD=LVDS_25;
NET "FMC_LA05_N" LOC="M2 " | IOSTANDARD=LVDS_25;
NET "FMC_LA05_P" LOC="M3 " | IOSTANDARD=LVDS_25;
NET "FMC_LA12_N" LOC="N3 " | IOSTANDARD=LVDS_25;
NET "FMC_LA12_P" LOC="N4 " | IOSTANDARD=LVDS_25;
NET "FMC_LA15_N" LOC="P1 " | IOSTANDARD=LVDS_25;
NET "FMC_LA15_" LOC="R1 " | IOSTANDARD=LVDS_25;
NET "FMC_LA04_P" LOC="AA1 " | IOSTANDARD=LVDS_25;
NET "FMC_LA13_N" LOC="AA3 " | IOSTANDARD=LVDS_25;
NET "FMC_LA01_CC_N" LOC="AA4 " | IOSTANDARD=LVDS_25;
NET "FMC_LA10_P" LOC="AA5 " | IOSTANDARD=LVDS_25;
NET "FMC_LA22_N" LOC="AA6 " | IOSTANDARD=LVDS_25;
NET "FMC_LA27_P" LOC="AA8 " | IOSTANDARD=LVDS_25;
NET "FMC_LA04_N" LOC="AB1 " | IOSTANDARD=LVDS_25;
NET "FMC_LA06_N" LOC="AB2 " | IOSTANDARD=LVDS_25;
NET "FMC_LA06_P" LOC="AB3 " | IOSTANDARD=LVDS_25;
NET "FMC_LA10_N" LOC="AB5 " | IOSTANDARD=LVDS_25;
NET "FMC_LA14_N" LOC="AB6 " | IOSTANDARD=LVDS_25;
NET "FMC_LA14_P" LOC="AB7 " | IOSTANDARD=LVDS_25;
NET "FMC_LA27_N" LOC="AB8 " | IOSTANDARD=LVDS_25;
NET "FMC_LA09_N" LOC="R2" | IOSTANDARD=LVDS_25;
NET "FMC_LA09_P" LOC="R3" | IOSTANDARD=LVDS_25;
NET "FMC_CLK1_M2C_P" LOC="R4" | IOSTANDARD=LVDS_25;
NET "FMC_LA33_P" LOC="R6" | IOSTANDARD=LVDS_25;
NET "FMC_LA11_P" LOC="T1" | IOSTANDARD=LVDS_25;
NET "FMC_CLK1_M2C_N" LOC="T4" | IOSTANDARD=LVDS_25;
NET "FMC_LA00_CC_P" LOC="T5" | IOSTANDARD=LVDS_25;
NET "FMC_LA33_N" LOC="T6" | IOSTANDARD=LVDS_25;
NET "FMC_LA11_N" LOC="U1" | IOSTANDARD=LVDS_25;
NET "FMC_LA16_P" LOC="U2" | IOSTANDARD=LVDS_25;
NET "FMC_LA00_CC_N" LOC="U5" | IOSTANDARD=LVDS_25;
NET "FMC_LA23_P" LOC="U6" | IOSTANDARD=LVDS_25;
NET "FMC_LA16_N" LOC="V2" | IOSTANDARD=LVDS_25;
NET "FMC_CLK0_M2C_P" LOC="V4" | IOSTANDARD=LVDS_25;
NET "FMC_LA23_N" LOC="V5" | IOSTANDARD=LVDS_25;
NET "FMC_LA26_P" LOC="V7" | IOSTANDARD=LVDS_25;
NET "FMC_LA29_N" LOC="V8" | IOSTANDARD=LVDS_25;
NET "FMC_LA29_P" LOC="V9" | IOSTANDARD=LVDS_25;
NET "FMC_LA07_P" LOC="W1" | IOSTANDARD=LVDS_25;
NET "FMC_CLK0_M2C_N" LOC="W4" | IOSTANDARD=LVDS_25;
NET "FMC_LA20_N" LOC="W5" | IOSTANDARD=LVDS_25;
NET "FMC_LA20_P" LOC="W6" | IOSTANDARD=LVDS_25;
NET "FMC_LA26_N" LOC="W7" | IOSTANDARD=LVDS_25;
NET "FMC_LA25_P" LOC="W9" | IOSTANDARD=LVDS_25;
NET "FMC_LA07_N" LOC="Y1" | IOSTANDARD=LVDS_25;
NET "BTN_RESETN" LOC="Y2" | IOSTANDARD=LVCMOS25;
NET "FMC_LA13_P" LOC="Y3" | IOSTANDARD=LVDS_25;
NET "FMC_LA01_CC_P" LOC="Y4" | IOSTANDARD=LVDS_25;
NET "FMC_LA22_P" LOC="Y6" | IOSTANDARD=LVDS_25;
NET "FMC_LA25_N" LOC="Y9" | IOSTANDARD=LVDS_25;
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