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Artix Trivial FMC Carrier ATFC
Commit e0a54952 authored by Samer Kilani's avatar Samer Kilani
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Removed copper pour from layer 2.

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hardware/altium/Project Outputs for atfc/Design Rule Check - atfc.drc
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Protel Design System Design Rule Check
PCB File : C:\Users\smkilani\Documents\atfc\hardware\altium\atfc.PcbDoc
Date : 19/5/2017
Time : 10:16:51 AM
Date : 6/6/2017
Time : 12:17:34 PM
WARNING: 3 Net Ties failed verification
SMT SIP Component R79-LRMAM1206-R02FT5 (1617mil,3431.898mil) on Component Side, SMT SIP Component R79-LRMAM1206-R02FT5 (1617mil,3431.898mil) on Component Side, has isolated copper
SMT SIP Component R62-LRMAM1206-R02FT5 (1782.756mil,1753mil) on Component Side, SMT SIP Component R62-LRMAM1206-R02FT5 (1782.756mil,1753mil) on Component Side, has isolated copper
SMT SIP Component R55-LRMAM1206-R02FT5 (1167.047mil,4860.772mil) on Component Side, SMT SIP Component R55-LRMAM1206-R02FT5 (1167.047mil,4860.772mil) on Component Side, has isolated copper
SMT SIP Component R79-LRMAM1206-R02FT5 (41.072mm,87.17mm) on Component Side, SMT SIP Component R79-LRMAM1206-R02FT5 (41.072mm,87.17mm) on Component Side, has isolated copper
SMT SIP Component R62-LRMAM1206-R02FT5 (45.282mm,44.526mm) on Component Side, SMT SIP Component R62-LRMAM1206-R02FT5 (45.282mm,44.526mm) on Component Side, has isolated copper
SMT SIP Component R55-LRMAM1206-R02FT5 (29.643mm,123.464mm) on Component Side, SMT SIP Component R55-LRMAM1206-R02FT5 (29.643mm,123.464mm) on Component Side, has isolated copper
WARNING: Zero hole size multi-layer pad(s) detected
Pad J2-1(1192.913mil,5078.74mil) on Multi-Layer on Net NetJ2_1
Pad J2-2(1192.913mil,5322.835mil) on Multi-Layer on Net GND
Pad J2-3(996.063mil,5204.724mil) on Multi-Layer on Net GND
Pad J2-1(30.3mm,129mm) on Multi-Layer on Net NetJ2_1
Pad J2-2(30.3mm,135.2mm) on Multi-Layer on Net GND
Pad J2-3(25.3mm,132.2mm) on Multi-Layer on Net GND
WARNING: Multilayer Pads with 0 size Hole found
Pad J2-1(1192.913mil,5078.74mil) on Multi-Layer
Pad J2-2(1192.913mil,5322.835mil) on Multi-Layer
Pad J2-3(996.063mil,5204.724mil) on Multi-Layer
Pad J2-1(30.3mm,129mm) on Multi-Layer
Pad J2-2(30.3mm,135.2mm) on Multi-Layer
Pad J2-3(25.3mm,132.2mm) on Multi-Layer
Processing Rule : Clearance Constraint (Gap=6mil) (All),(All)
Processing Rule : Clearance Constraint (Gap=0.152mm) (All),(All)
Rule Violations :0
Processing Rule : Short-Circuit Constraint (Allowed=No) (All),(All)
......@@ -30,221 +30,235 @@ Rule Violations :0
Processing Rule : Modified Polygon (Allow modified: No), (Allow shelved: No)
Rule Violations :0
Processing Rule : Width Constraint (Min=3.937mil) (Max=196.85mil) (Preferred=10mil) (All)
Rule Violations :0
Processing Rule : Power Plane Connect Rule(Direct Connect )(Expansion=20mil) (Conductor Width=10mil) (Air Gap=10mil) (Entries=4) (All)
Rule Violations :0
Processing Rule : Hole Size Constraint (Min=1mil) (Max=100mil) (All)
Violation between Hole Size Constraint: (106.299mil > 100mil) Pad Free-MH3(6901mil,1537mil) on Multi-Layer Actual Hole Size = 106.299mil
Violation between Hole Size Constraint: (106.299mil > 100mil) Pad Free-MH3(801mil,1537mil) on Multi-Layer Actual Hole Size = 106.299mil
Violation between Hole Size Constraint: (106.299mil > 100mil) Pad Free-MH3(801mil,5487mil) on Multi-Layer Actual Hole Size = 106.299mil
Violation between Hole Size Constraint: (106.299mil > 100mil) Pad Free-MH3(6901mil,5487mil) on Multi-Layer Actual Hole Size = 106.299mil
Violation between Hole Size Constraint: (106.299mil > 100mil) Pad Free-MH3(6551.181mil,4601.996mil) on Multi-Layer Actual Hole Size = 106.299mil
Violation between Hole Size Constraint: (106.299mil > 100mil) Pad Free-MH3(6551.181mil,2121.681mil) on Multi-Layer Actual Hole Size = 106.299mil
Rule Violations :6
Processing Rule : Hole To Hole Clearance (Gap=5mil) (All),(All)
Rule Violations :0
Processing Rule : Minimum Solder Mask Sliver (Gap=1mil) (All),(All)
Violation between Minimum Solder Mask Sliver Constraint: (0.488mil < 1mil) Between Pad R16-2(1151.528mil,4144mil) on Component Side And Pad B2-3(1197.417mil,4144.496mil) on Component Side [Top Solder] Mask Sliver [0.488mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.37mil < 1mil) Between Pad C7-1(3063.268mil,3452mil) on Component Side And Pad IC2-5(3023.402mil,3452mil) on Component Side [Top Solder] Mask Sliver [0.37mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.37mil < 1mil) Between Pad C6-1(3063.268mil,3409mil) on Component Side And Pad IC2-4(3023.402mil,3409.677mil) on Component Side [Top Solder] Mask Sliver [0.37mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.878mil < 1mil) Between Pad Q2-5(2405.338mil,2211.685mil) on Component Side And Pad Q2-6_2(2366.244mil,2175.347mil) on Component Side [Top Solder] Mask Sliver [0.878mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.878mil < 1mil) Between Pad Q2-5_2(2366.263mil,2223.201mil) on Component Side And Pad Q2-6_2(2366.244mil,2175.347mil) on Component Side [Top Solder] Mask Sliver [0.878mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.858mil < 1mil) Between Pad Q2-6(2405.338mil,2186.882mil) on Component Side And Pad Q2-5_2(2366.263mil,2223.201mil) on Component Side [Top Solder] Mask Sliver [0.858mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.858mil < 1mil) Between Pad Q2-5(2405.338mil,2211.685mil) on Component Side And Pad Q2-6(2405.338mil,2186.882mil) on Component Side [Top Solder] Mask Sliver [0.858mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.784mil < 1mil) Between Via (2654.685mil,2030mil) from Component Side to Bottom Side And Pad U8-43(2656.157mil,2061.142mil) on Component Side [Top Solder] Mask Sliver [0.784mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.496mil < 1mil) Between Pad R79-2(1681.961mil,3431.898mil) on Component Side And Pad R79-4(1635mil,3431.898mil) on Component Side [Top Solder] Mask Sliver [0.496mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.496mil < 1mil) Between Pad R79-1(1552.039mil,3431.898mil) on Component Side And Pad R79-3(1599mil,3431.898mil) on Component Side [Top Solder] Mask Sliver [0.496mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.426mil < 1mil) Between Via (6522.441mil,2977.205mil) from Component Side to Bottom Side And Pad J1-G13(6547.441mil,2987.205mil) on Component Side [Top Solder] Mask Sliver [0.426mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.426mil < 1mil) Between Via (6522.441mil,2947.205mil) from Component Side to Bottom Side And Pad J1-G12(6547.441mil,2937.205mil) on Component Side [Top Solder] Mask Sliver [0.426mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.333mil < 1mil) Between Via (6523.441mil,2675.205mil) from Component Side to Bottom Side And Pad J1-G7(6547.441mil,2687.205mil) on Component Side [Top Solder] Mask Sliver [0.333mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.333mil < 1mil) Between Via (6523.441mil,2699.205mil) from Component Side to Bottom Side And Pad J1-G7(6547.441mil,2687.205mil) on Component Side [Top Solder] Mask Sliver [0.333mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.333mil < 1mil) Between Via (6523.441mil,2625.205mil) from Component Side to Bottom Side And Pad J1-G6(6547.441mil,2637.205mil) on Component Side [Top Solder] Mask Sliver [0.333mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.333mil < 1mil) Between Via (6523.441mil,2649.205mil) from Component Side to Bottom Side And Pad J1-G6(6547.441mil,2637.205mil) on Component Side [Top Solder] Mask Sliver [0.333mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.426mil < 1mil) Between Via (6422.441mil,3677.205mil) from Component Side to Bottom Side And Pad J1-D27(6397.441mil,3687.205mil) on Component Side [Top Solder] Mask Sliver [0.426mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.426mil < 1mil) Between Via (6422.441mil,3647.205mil) from Component Side to Bottom Side And Pad J1-D26(6397.441mil,3637.205mil) on Component Side [Top Solder] Mask Sliver [0.426mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.426mil < 1mil) Between Via (6422.441mil,3077.205mil) from Component Side to Bottom Side And Pad J1-D15(6397.441mil,3087.205mil) on Component Side [Top Solder] Mask Sliver [0.426mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.426mil < 1mil) Between Via (6422.441mil,3047.205mil) from Component Side to Bottom Side And Pad J1-D14(6397.441mil,3037.205mil) on Component Side [Top Solder] Mask Sliver [0.426mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.426mil < 1mil) Between Via (6622.441mil,2727.205mil) from Component Side to Bottom Side And Pad J1-H8(6597.441mil,2737.205mil) on Component Side [Top Solder] Mask Sliver [0.426mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.426mil < 1mil) Between Via (6622.441mil,2697.205mil) from Component Side to Bottom Side And Pad J1-H7(6597.441mil,2687.205mil) on Component Side [Top Solder] Mask Sliver [0.426mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.426mil < 1mil) Between Via (6522.441mil,4027.205mil) from Component Side to Bottom Side And Pad J1-G34(6547.441mil,4037.205mil) on Component Side [Top Solder] Mask Sliver [0.426mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.426mil < 1mil) Between Via (6522.441mil,3997.205mil) from Component Side to Bottom Side And Pad J1-G33(6547.441mil,3987.205mil) on Component Side [Top Solder] Mask Sliver [0.426mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.426mil < 1mil) Between Via (6522.441mil,3877.205mil) from Component Side to Bottom Side And Pad J1-G31(6547.441mil,3887.205mil) on Component Side [Top Solder] Mask Sliver [0.426mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.426mil < 1mil) Between Via (6522.441mil,3847.205mil) from Component Side to Bottom Side And Pad J1-G30(6547.441mil,3837.205mil) on Component Side [Top Solder] Mask Sliver [0.426mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.426mil < 1mil) Between Via (6522.441mil,3727.205mil) from Component Side to Bottom Side And Pad J1-G28(6547.441mil,3737.205mil) on Component Side [Top Solder] Mask Sliver [0.426mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.426mil < 1mil) Between Via (6522.441mil,3697.205mil) from Component Side to Bottom Side And Pad J1-G27(6547.441mil,3687.205mil) on Component Side [Top Solder] Mask Sliver [0.426mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.426mil < 1mil) Between Via (6522.441mil,3577.205mil) from Component Side to Bottom Side And Pad J1-G25(6547.441mil,3587.205mil) on Component Side [Top Solder] Mask Sliver [0.426mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.426mil < 1mil) Between Via (6422.441mil,3527.205mil) from Component Side to Bottom Side And Pad J1-D24(6397.441mil,3537.205mil) on Component Side [Top Solder] Mask Sliver [0.426mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.426mil < 1mil) Between Via (6522.441mil,3547.205mil) from Component Side to Bottom Side And Pad J1-G24(6547.441mil,3537.205mil) on Component Side [Top Solder] Mask Sliver [0.426mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.426mil < 1mil) Between Via (6422.441mil,3497.205mil) from Component Side to Bottom Side And Pad J1-D23(6397.441mil,3487.205mil) on Component Side [Top Solder] Mask Sliver [0.426mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.426mil < 1mil) Between Via (6522.441mil,3427.205mil) from Component Side to Bottom Side And Pad J1-G22(6547.441mil,3437.205mil) on Component Side [Top Solder] Mask Sliver [0.426mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.426mil < 1mil) Between Via (6522.441mil,3397.205mil) from Component Side to Bottom Side And Pad J1-G21(6547.441mil,3387.205mil) on Component Side [Top Solder] Mask Sliver [0.426mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.426mil < 1mil) Between Via (6522.441mil,3277.205mil) from Component Side to Bottom Side And Pad J1-G19(6547.441mil,3287.205mil) on Component Side [Top Solder] Mask Sliver [0.426mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.426mil < 1mil) Between Via (6422.441mil,3227.205mil) from Component Side to Bottom Side And Pad J1-D18(6397.441mil,3237.205mil) on Component Side [Top Solder] Mask Sliver [0.426mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.426mil < 1mil) Between Via (6522.441mil,3247.205mil) from Component Side to Bottom Side And Pad J1-G18(6547.441mil,3237.205mil) on Component Side [Top Solder] Mask Sliver [0.426mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.426mil < 1mil) Between Via (6422.441mil,3197.205mil) from Component Side to Bottom Side And Pad J1-D17(6397.441mil,3187.205mil) on Component Side [Top Solder] Mask Sliver [0.426mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.426mil < 1mil) Between Via (6522.441mil,3127.205mil) from Component Side to Bottom Side And Pad J1-G16(6547.441mil,3137.205mil) on Component Side [Top Solder] Mask Sliver [0.426mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.426mil < 1mil) Between Via (6522.441mil,3097.205mil) from Component Side to Bottom Side And Pad J1-G15(6547.441mil,3087.205mil) on Component Side [Top Solder] Mask Sliver [0.426mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.426mil < 1mil) Between Via (6422.441mil,2927.205mil) from Component Side to Bottom Side And Pad J1-D12(6397.441mil,2937.205mil) on Component Side [Top Solder] Mask Sliver [0.426mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.426mil < 1mil) Between Via (6422.441mil,2897.205mil) from Component Side to Bottom Side And Pad J1-D11(6397.441mil,2887.205mil) on Component Side [Top Solder] Mask Sliver [0.426mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.426mil < 1mil) Between Via (6522.441mil,2827.205mil) from Component Side to Bottom Side And Pad J1-G10(6547.441mil,2837.205mil) on Component Side [Top Solder] Mask Sliver [0.426mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.426mil < 1mil) Between Via (6522.441mil,2797.205mil) from Component Side to Bottom Side And Pad J1-G9(6547.441mil,2787.205mil) on Component Side [Top Solder] Mask Sliver [0.426mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.333mil < 1mil) Between Via (6571.441mil,2599.205mil) from Component Side to Bottom Side And Pad J1-G5(6547.441mil,2587.205mil) on Component Side [Top Solder] Mask Sliver [0.333mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.333mil < 1mil) Between Via (6571.441mil,2525.205mil) from Component Side to Bottom Side And Pad J1-G4(6547.441mil,2537.205mil) on Component Side [Top Solder] Mask Sliver [0.333mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.968mil < 1mil) Between Via (6372.638mil,2449.008mil) from Component Side to Bottom Side And Pad J1-D2(6397.441mil,2437.205mil) on Component Side [Top Solder] Mask Sliver [0.968mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.333mil < 1mil) Between Via (6573.441mil,2549.205mil) from Component Side to Bottom Side And Pad J1-H4(6597.441mil,2537.205mil) on Component Side [Top Solder] Mask Sliver [0.333mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.333mil < 1mil) Between Via (6573.441mil,2575.205mil) from Component Side to Bottom Side And Pad J1-H5(6597.441mil,2587.205mil) on Component Side [Top Solder] Mask Sliver [0.333mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.819mil < 1mil) Between Via (1001mil,3151.898mil) from Component Side to Bottom Side And Pad C102-2(1014mil,3119.299mil) on Component Side [Top Solder] Mask Sliver [0.819mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.819mil < 1mil) Between Via (1030mil,3151.898mil) from Component Side to Bottom Side And Pad C102-2(1014mil,3119.299mil) on Component Side [Top Solder] Mask Sliver [0.819mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.457mil < 1mil) Between Via (1539mil,2985.898mil) from Component Side to Bottom Side And Pad C106-1(1508.732mil,2985.898mil) on Component Side [Top Solder] Mask Sliver [0.457mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.957mil < 1mil) Between Via (2449.685mil,2194mil) from Component Side to Bottom Side And Pad C79-1(2456.685mil,2165.732mil) on Component Side [Top Solder] Mask Sliver [0.957mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.957mil < 1mil) Between Via (2464.099mil,2213mil) from Component Side to Bottom Side And Pad C85-2(2457.685mil,2241.268mil) on Component Side [Top Solder] Mask Sliver [0.957mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.549mil < 1mil) Between Via (2616.685mil,1944mil) from Component Side to Bottom Side And Pad C96-1(2641.685mil,1966.268mil) on Component Side [Top Solder] Mask Sliver [0.549mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.347mil < 1mil) Between Via (2827.016mil,4306mil) from Component Side to Bottom Side And Pad J3-10(2827.685mil,4363.717mil) on Component Side [Top Solder] Mask Sliver [0.347mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.347mil < 1mil) Between Via (2858.512mil,4306mil) from Component Side to Bottom Side And Pad J3-9(2859.181mil,4363.717mil) on Component Side [Top Solder] Mask Sliver [0.347mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.347mil < 1mil) Between Via (2921.504mil,4306mil) from Component Side to Bottom Side And Pad J3-7(2922.173mil,4363.717mil) on Component Side [Top Solder] Mask Sliver [0.347mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.347mil < 1mil) Between Via (2953mil,4306mil) from Component Side to Bottom Side And Pad J3-6(2953.669mil,4363.717mil) on Component Side [Top Solder] Mask Sliver [0.347mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.347mil < 1mil) Between Via (3047.488mil,4306mil) from Component Side to Bottom Side And Pad J3-3(3048.157mil,4363.717mil) on Component Side [Top Solder] Mask Sliver [0.347mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.347mil < 1mil) Between Via (3110.48mil,4306mil) from Component Side to Bottom Side And Pad J3-1(3111.15mil,4363.717mil) on Component Side [Top Solder] Mask Sliver [0.347mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.315mil < 1mil) Between Via (3607mil,4382mil) from Component Side to Bottom Side And Pad R87-2(3643mil,4379.528mil) on Component Side [Top Solder] Mask Sliver [0.315mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.843mil < 1mil) Between Via (3610.472mil,4642.472mil) from Component Side to Bottom Side And Pad R93-1(3647mil,4642.472mil) on Component Side [Top Solder] Mask Sliver [0.843mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.975mil < 1mil) Between Via (2640.685mil,1931mil) from Component Side to Bottom Side And Pad R70-1(2662.582mil,1905.284mil) on Component Side [Top Solder] Mask Sliver [0.975mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.496mil < 1mil) Between Pad R55-2(1167.047mil,4795.811mil) on Component Side And Pad R55-4(1167.047mil,4842.772mil) on Component Side [Top Solder] Mask Sliver [0.496mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.496mil < 1mil) Between Pad R55-1(1167.047mil,4925.732mil) on Component Side And Pad R55-3(1167.047mil,4878.772mil) on Component Side [Top Solder] Mask Sliver [0.496mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.496mil < 1mil) Between Pad R62-2(1717.795mil,1753mil) on Component Side And Pad R62-4(1764.756mil,1753mil) on Component Side [Top Solder] Mask Sliver [0.496mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.496mil < 1mil) Between Pad R62-1(1847.716mil,1753mil) on Component Side And Pad R62-3(1800.756mil,1753mil) on Component Side [Top Solder] Mask Sliver [0.496mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.114mil < 1mil) Between Via (4417.323mil,3881.89mil) from Component Side to Bottom Side And Pad IC1-2(4434mil,3919.402mil) on Bottom Side [Bottom Solder] Mask Sliver [0.114mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.374mil < 1mil) Between Via (4417.323mil,3881.89mil) from Component Side to Bottom Side And Pad IC1-1(4391.677mil,3919.402mil) on Bottom Side [Bottom Solder] Mask Sliver [0.374mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.162mil < 1mil) Between Via (4417.323mil,3881.89mil) from Component Side to Bottom Side And Pad IC1-6(4391.677mil,3844.598mil) on Bottom Side [Bottom Solder] Mask Sliver [0.162mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.629mil < 1mil) Between Via (3332mil,4702mil) from Component Side to Bottom Side And Pad L7-1(3390mil,4699.37mil) on Bottom Side [Bottom Solder] Mask Sliver [0.629mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.214mil < 1mil) Between Via (1445.48mil,2014.52mil) from Component Side to Bottom Side And Pad Q1-4(1469.393mil,1994.835mil) on Bottom Side [Bottom Solder] Mask Sliver [0.214mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.214mil < 1mil) Between Via (1445.48mil,2014.52mil) from Component Side to Bottom Side And Pad Q1-6(1469.393mil,2034.205mil) on Bottom Side [Bottom Solder] Mask Sliver [0.214mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.913mil < 1mil) Between Via (4728.346mil,3015.748mil) from Component Side to Bottom Side And Pad R3-2(4714.347mil,3046.472mil) on Bottom Side [Bottom Solder] Mask Sliver [0.913mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.438mil < 1mil) Between Via (2677.165mil,2389.764mil) from Component Side to Bottom Side And Pad R56-1(2649.417mil,2380mil) on Bottom Side [Bottom Solder] Mask Sliver [0.438mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.448mil < 1mil) Between Via (3590.551mil,3759.843mil) from Component Side to Bottom Side And Pad R78-1(3562.992mil,3782.48mil) on Bottom Side [Bottom Solder] Mask Sliver [0.448mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.591mil < 1mil) Between Via (5173.228mil,4362.205mil) from Component Side to Bottom Side And Pad U3-5(5170.591mil,4331.803mil) on Bottom Side [Bottom Solder] Mask Sliver [0.591mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.839mil < 1mil) Between Via (4139mil,3887mil) from Component Side to Bottom Side And Pad U14-4(4103mil,3878.41mil) on Bottom Side [Bottom Solder] Mask Sliver [0.839mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.083mil < 1mil) Between Via (6573.441mil,2575.205mil) from Component Side to Bottom Side And Via (6571.441mil,2599.205mil) from Component Side to Bottom Side [Top Solder] Mask Sliver [0.083mil] / [Bottom Solder] Mask Sliver [0.083mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.083mil < 1mil) Between Via (6573.441mil,2549.205mil) from Component Side to Bottom Side And Via (6571.441mil,2525.205mil) from Component Side to Bottom Side [Top Solder] Mask Sliver [0.083mil] / [Bottom Solder] Mask Sliver [0.083mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.622mil < 1mil) Between Via (1901.575mil,1992.126mil) from Component Side to Bottom Side And Via (1925.197mil,1992.126mil) from Component Side to Bottom Side [Top Solder] Mask Sliver [0.622mil] / [Bottom Solder] Mask Sliver [0.622mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.121mil < 1mil) Between Via (2677.16mil,2035.429mil) from Component Side to Bottom Side And Via (2654.685mil,2030mil) from Component Side to Bottom Side [Top Solder] Mask Sliver [0.121mil] / [Bottom Solder] Mask Sliver [0.121mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.849mil < 1mil) Between Via (2464.099mil,2213mil) from Component Side to Bottom Side And Via (2449.685mil,2194mil) from Component Side to Bottom Side [Top Solder] Mask Sliver [0.849mil] / [Bottom Solder] Mask Sliver [0.849mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.402mil < 1mil) Between Via (4350mil,2538mil) from Component Side to Bottom Side And Via (4350mil,2566.402mil) from Component Side to Bottom Side [Top Solder] Mask Sliver [0.402mil] / [Bottom Solder] Mask Sliver [0.402mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.4mil < 1mil) Between Via (3607mil,4406.4mil) from Component Side to Bottom Side And Via (3607mil,4382mil) from Component Side to Bottom Side [Top Solder] Mask Sliver [0.4mil] / [Bottom Solder] Mask Sliver [0.4mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.4mil < 1mil) Between Via (3607mil,4430.8mil) from Component Side to Bottom Side And Via (3607mil,4406.4mil) from Component Side to Bottom Side [Top Solder] Mask Sliver [0.4mil] / [Bottom Solder] Mask Sliver [0.4mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.4mil < 1mil) Between Via (3607mil,4455.2mil) from Component Side to Bottom Side And Via (3607mil,4430.8mil) from Component Side to Bottom Side [Top Solder] Mask Sliver [0.4mil] / [Bottom Solder] Mask Sliver [0.4mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.4mil < 1mil) Between Via (3607mil,4479.6mil) from Component Side to Bottom Side And Via (3607mil,4455.2mil) from Component Side to Bottom Side [Top Solder] Mask Sliver [0.4mil] / [Bottom Solder] Mask Sliver [0.4mil]
Violation between Minimum Solder Mask Sliver Constraint: (0.4mil < 1mil) Between Via (3607mil,4504mil) from Component Side to Bottom Side And Via (3607mil,4479.6mil) from Component Side to Bottom Side [Top Solder] Mask Sliver [0.4mil] / [Bottom Solder] Mask Sliver [0.4mil]
Rule Violations :90
Processing Rule : Silk To Solder Mask (Clearance=10mil) (Disabled)(IsPad),(All)
Rule Violations :0
Processing Rule : Silk to Silk (Clearance=5mil) (All),(All)
Violation between Silk To Silk Clearance Constraint: (3.563mil < 5mil) Between Text "9" (4385mil,5084mil) on Top Overlay And Track (4375mil,5054mil)(4375mil,5254mil) on Top Overlay Silk Text to Silk Clearance [3.563mil]
Violation between Silk To Silk Clearance Constraint: (3.563mil < 5mil) Between Text "10" (4385mil,5184mil) on Top Overlay And Track (4375mil,5054mil)(4375mil,5254mil) on Top Overlay Silk Text to Silk Clearance [3.563mil]
Violation between Silk To Silk Clearance Constraint: (Collision < 5mil) Between Text "Rout1" (1409.449mil,4897.638mil) on Top Overlay And Track (1502.205mil,4828.095mil)(1502.205mil,5339.905mil) on Top Overlay Silk Text to Silk Clearance [0mil]
Violation between Silk To Silk Clearance Constraint: (Collision < 5mil) Between Text "C35" (3463.638mil,2839.394mil) on Top Overlay And Track (3462.244mil,2736.244mil)(3462.244mil,3641.756mil) on Top Overlay Silk Text to Silk Clearance [0mil]
Violation between Silk To Silk Clearance Constraint: (Collision < 5mil) Between Text "C34" (3462.638mil,2900.449mil) on Top Overlay And Track (3462.244mil,2736.244mil)(3462.244mil,3641.756mil) on Top Overlay Silk Text to Silk Clearance [0mil]
Violation between Silk To Silk Clearance Constraint: (4.718mil < 5mil) Between Text "C7" (3061mil,3473mil) on Top Overlay And Track (3076mil,3464mil)(3084mil,3464mil) on Top Overlay Silk Text to Silk Clearance [4.718mil]
Violation between Silk To Silk Clearance Constraint: (1.61mil < 5mil) Between Text "*" (1381.89mil,2972.441mil) on Top Overlay And Track (1387mil,2961.898mil)(1387mil,2969.898mil) on Top Overlay Silk Text to Silk Clearance [1.61mil]
Violation between Silk To Silk Clearance Constraint: (4.374mil < 5mil) Between Text "C76" (2854.331mil,2161.417mil) on Top Overlay And Track (2889.63mil,2195.284mil)(2897.63mil,2195.284mil) on Top Overlay Silk Text to Silk Clearance [4.374mil]
Violation between Silk To Silk Clearance Constraint: (3.209mil < 5mil) Between Text "C12" (4169.291mil,3511.811mil) on Bottom Overlay And Track (4177mil,3482mil)(4177mil,3490mil) on Bottom Overlay Silk Text to Silk Clearance [3.209mil]
Violation between Silk To Silk Clearance Constraint: (2.303mil < 5mil) Between Text "R13" (3925.197mil,2984.252mil) on Bottom Overlay And Track (3931mil,2977mil)(3931mil,2985mil) on Bottom Overlay Silk Text to Silk Clearance [2.303mil]
Violation between Silk To Silk Clearance Constraint: (4.02mil < 5mil) Between Text "R19" (6519mil,3891mil) on Bottom Overlay And Track (6449mil,3904mil)(6449mil,3912mil) on Bottom Overlay Silk Text to Silk Clearance [4.02mil]
Violation between Silk To Silk Clearance Constraint: (4.855mil < 5mil) Between Text "R20" (6524mil,4042mil) on Bottom Overlay And Track (6449mil,4058mil)(6449mil,4066mil) on Bottom Overlay Silk Text to Silk Clearance [4.855mil]
Violation between Silk To Silk Clearance Constraint: (0.469mil < 5mil) Between Text "R53" (2834.646mil,2035.433mil) on Bottom Overlay And Track (2805.685mil,2002mil)(2805.685mil,2010mil) on Bottom Overlay Silk Text to Silk Clearance [0.469mil]
Violation between Silk To Silk Clearance Constraint: (3.656mil < 5mil) Between Text "R57" (2767.716mil,1960.63mil) on Bottom Overlay And Track (2734.685mil,1962mil)(2734.685mil,1970mil) on Bottom Overlay Silk Text to Silk Clearance [3.656mil]
Violation between Silk To Silk Clearance Constraint: (4.355mil < 5mil) Between Text "R69" (2791.685mil,1754mil) on Top Overlay And Text "R70" (2715.685mil,1754mil) on Top Overlay Silk Text to Silk Clearance [4.355mil]
Violation between Silk To Silk Clearance Constraint: (4.355mil < 5mil) Between Text "R59" (2639.685mil,1754mil) on Top Overlay And Text "R70" (2715.685mil,1754mil) on Top Overlay Silk Text to Silk Clearance [4.355mil]
Violation between Silk To Silk Clearance Constraint: (2.355mil < 5mil) Between Text "R59" (2639.685mil,1754mil) on Top Overlay And Text "R61" (2565.685mil,1754mil) on Top Overlay Silk Text to Silk Clearance [2.355mil]
Violation between Silk To Silk Clearance Constraint: (4.008mil < 5mil) Between Text "C87" (2711.74mil,1857.716mil) on Top Overlay And Text "R67" (2745.74mil,1857.716mil) on Top Overlay Silk Text to Silk Clearance [4.008mil]
Violation between Silk To Silk Clearance Constraint: (3.675mil < 5mil) Between Text "R10" (4962.333mil,3832mil) on Top Overlay And Text "R11" (4928.667mil,3833mil) on Top Overlay Silk Text to Silk Clearance [3.675mil]
Violation between Silk To Silk Clearance Constraint: (2.008mil < 5mil) Between Text "C96" (2630.74mil,1872.716mil) on Top Overlay And Text "C97" (2662.74mil,1874.716mil) on Top Overlay Silk Text to Silk Clearance [2.008mil]
Rule Violations :20
Processing Rule : Net Antennae (Tolerance=0mil) (All)
Rule Violations :0
Processing Rule : Length Constraint (Min=0mil) (Max=100000mil) (All)
Rule Violations :0
Processing Rule : Matched Lengths(Tolerance=40mil) (InAnyDifferentialPair)
Violation between Matched Net Lengths: Between Net SFP2_RD_P And Net SFP2_RD_N Actual Difference against SFP2_RD_N is: 41.812mil, Tolerance : 40mil.
Violation between Matched Net Lengths: Between Net FMC_MGT_M2C_P And Net FMC_MGT_M2C_N Actual Difference against FMC_MGT_M2C_N is: 65.884mil, Tolerance : 40mil.
Violation between Matched Net Lengths: Between Net FMC_MGT_CLK_P And Net FMC_MGT_CLK_N Actual Difference against FMC_MGT_CLK_N is: 159.759mil, Tolerance : 40mil.
Violation between Matched Net Lengths: Between Net FMC_MGT_C2M_P And Net FMC_MGT_C2M_N Actual Difference against FMC_MGT_C2M_N is: 63.56mil, Tolerance : 40mil.
Violation between Matched Net Lengths: Between Net FMC_LA32_P And Net FMC_LA32_N Actual Difference against FMC_LA32_N is: 86.156mil, Tolerance : 40mil.
Violation between Matched Net Lengths: Between Net FMC_LA31_P And Net FMC_LA31_N Actual Difference against FMC_LA31_N is: 50.309mil, Tolerance : 40mil.
Violation between Matched Net Lengths: Between Net FMC_LA30_P And Net FMC_LA30_N Actual Difference against FMC_LA30_N is: 86.156mil, Tolerance : 40mil.
Violation between Matched Net Lengths: Between Net FMC_LA29_P And Net FMC_LA29_N Actual Difference against FMC_LA29_N is: 52.906mil, Tolerance : 40mil.
Violation between Matched Net Lengths: Between Net FMC_LA28_P And Net FMC_LA28_N Actual Difference against FMC_LA28_N is: 86.156mil, Tolerance : 40mil.
Violation between Matched Net Lengths: Between Net FMC_LA27_P And Net FMC_LA27_N Actual Difference against FMC_LA27_N is: 120.022mil, Tolerance : 40mil.
Violation between Matched Net Lengths: Between Net FMC_LA26_P And Net FMC_LA26_N Actual Difference against FMC_LA26_N is: 69.264mil, Tolerance : 40mil.
Violation between Matched Net Lengths: Between Net FMC_LA25_P And Net FMC_LA25_N Actual Difference against FMC_LA25_N is: 76.229mil, Tolerance : 40mil.
Violation between Matched Net Lengths: Between Net FMC_LA24_P And Net FMC_LA24_N Actual Difference against FMC_LA24_N is: 90.794mil, Tolerance : 40mil.
Violation between Matched Net Lengths: Between Net FMC_LA23_P And Net FMC_LA23_N Actual Difference against FMC_LA23_N is: 53.332mil, Tolerance : 40mil.
Violation between Matched Net Lengths: Between Net FMC_LA22_P And Net FMC_LA22_N Actual Difference against FMC_LA22_N is: 79.055mil, Tolerance : 40mil.
Violation between Matched Net Lengths: Between Net FMC_LA21_P And Net FMC_LA21_N Actual Difference against FMC_LA21_N is: 86.156mil, Tolerance : 40mil.
Violation between Matched Net Lengths: Between Net FMC_LA20_P And Net FMC_LA20_N Actual Difference against FMC_LA20_N is: 97.543mil, Tolerance : 40mil.
Violation between Matched Net Lengths: Between Net FMC_LA19_P And Net FMC_LA19_N Actual Difference against FMC_LA19_N is: 87.702mil, Tolerance : 40mil.
Violation between Matched Net Lengths: Between Net FMC_LA17_CC_P And Net FMC_LA17_CC_N Actual Difference against FMC_LA17_CC_N is: 86.156mil, Tolerance : 40mil.
Violation between Matched Net Lengths: Between Net FMC_LA16_P And Net FMC_LA16_N Actual Difference against FMC_LA16_N is: 86.121mil, Tolerance : 40mil.
Violation between Matched Net Lengths: Between Net FMC_LA15_P And Net FMC_LA15_N Actual Difference against FMC_LA15_N is: 86.156mil, Tolerance : 40mil.
Violation between Matched Net Lengths: Between Net FMC_LA14_P And Net FMC_LA14_N Actual Difference against FMC_LA14_N is: 82.486mil, Tolerance : 40mil.
Violation between Matched Net Lengths: Between Net FMC_LA13_P And Net FMC_LA13_N Actual Difference against FMC_LA13_N is: 66.368mil, Tolerance : 40mil.
Violation between Matched Net Lengths: Between Net FMC_LA12_P And Net FMC_LA12_N Actual Difference against FMC_LA12_N is: 77.286mil, Tolerance : 40mil.
Violation between Matched Net Lengths: Between Net FMC_LA10_P And Net FMC_LA10_N Actual Difference against FMC_LA10_N is: 69.386mil, Tolerance : 40mil.
Violation between Matched Net Lengths: Between Net FMC_LA09_P And Net FMC_LA09_N Actual Difference against FMC_LA09_N is: 94.045mil, Tolerance : 40mil.
Violation between Matched Net Lengths: Between Net FMC_LA08_P And Net FMC_LA08_N Actual Difference against FMC_LA08_N is: 85.948mil, Tolerance : 40mil.
Violation between Matched Net Lengths: Between Net FMC_LA06_P And Net FMC_LA06_N Actual Difference against FMC_LA06_N is: 118.783mil, Tolerance : 40mil.
Violation between Matched Net Lengths: Between Net FMC_LA05_P And Net FMC_LA05_N Actual Difference against FMC_LA05_N is: 82.078mil, Tolerance : 40mil.
Violation between Matched Net Lengths: Between Net FMC_LA03_P And Net FMC_LA03_N Actual Difference against FMC_LA03_N is: 84.924mil, Tolerance : 40mil.
Violation between Matched Net Lengths: Between Net FMC_LA02_P And Net FMC_LA02_N Actual Difference against FMC_LA02_N is: 102.187mil, Tolerance : 40mil.
Violation between Matched Net Lengths: Between Net FMC_LA01_CC_P And Net FMC_LA01_CC_N Actual Difference against FMC_LA01_CC_N is: 65.275mil, Tolerance : 40mil.
Violation between Matched Net Lengths: Between Net FMC_LA00_CC_P And Net FMC_LA00_CC_N Actual Difference against FMC_LA00_CC_N is: 156.593mil, Tolerance : 40mil.
Violation between Matched Net Lengths: Between Net FMC_CLK1_M2C_P And Net FMC_CLK1_M2C_N Actual Difference against FMC_CLK1_M2C_N is: 65.246mil, Tolerance : 40mil.
Violation between Matched Net Lengths: Between Net FMC_CLK0_M2C_P And Net FMC_CLK0_M2C_N Actual Difference against FMC_CLK0_M2C_N is: 105.581mil, Tolerance : 40mil.
Rule Violations :35
Processing Rule : Max Via Stub Length (Back Drilling rule) (Max Stub Length = 15mil) (InAnyDifferentialPair)
Rule Violations :0
Processing Rule : Room SFP (Bounding Region = (0mil, 0mil, 2000mil, 1000mil) (Disabled)(InComponentClass('SFP'))
Processing Rule : Width Constraint (Min=0.1mm) (Max=5mm) (Preferred=0.254mm) (All)
Rule Violations :0
Processing Rule : Room Regulators (Bounding Region = (0mil, 0mil, 2000mil, 1000mil) (Disabled)(InComponentClass('Regulators'))
Processing Rule : Power Plane Connect Rule(Direct Connect )(Expansion=0.508mm) (Conductor Width=0.254mm) (Air Gap=0.254mm) (Entries=4) (All)
Rule Violations :0
Processing Rule : Room PWR_APD5052 (Bounding Region = (0mil, 0mil, 2000mil, 1000mil) (Disabled)(InComponentClass('PWR_APD5052'))
Processing Rule : Hole Size Constraint (Min=0.025mm) (Max=2.54mm) (All)
Violation between Hole Size Constraint: (3.2mm > 2.54mm) Pad Free-2(112.928mm,131.267mm) on Multi-Layer Actual Hole Size = 3.2mm
Violation between Hole Size Constraint: (2.7mm > 2.54mm) Pad Free-MH3(175.285mm,39.04mm) on Multi-Layer Actual Hole Size = 2.7mm
Violation between Hole Size Constraint: (2.7mm > 2.54mm) Pad Free-MH3(20.345mm,39.04mm) on Multi-Layer Actual Hole Size = 2.7mm
Violation between Hole Size Constraint: (2.7mm > 2.54mm) Pad Free-MH3(20.345mm,139.37mm) on Multi-Layer Actual Hole Size = 2.7mm
Violation between Hole Size Constraint: (2.7mm > 2.54mm) Pad Free-MH3(175.285mm,139.37mm) on Multi-Layer Actual Hole Size = 2.7mm
Violation between Hole Size Constraint: (2.7mm > 2.54mm) Pad Free-MH3(166.4mm,116.891mm) on Multi-Layer Actual Hole Size = 2.7mm
Violation between Hole Size Constraint: (2.7mm > 2.54mm) Pad Free-MH3(166.4mm,53.891mm) on Multi-Layer Actual Hole Size = 2.7mm
Rule Violations :7
Processing Rule : Hole To Hole Clearance (Gap=0.127mm) (All),(All)
Rule Violations :0
Processing Rule : Minimum Solder Mask Sliver (Gap=0.025mm) (All),(All)
Violation between Minimum Solder Mask Sliver Constraint: (0.01mm < 0.025mm) Between Via (157.353mm,125.298mm) from Component Side to Bottom Side And Pad R111-2(157.422mm,126.015mm) on Component Side [Top Solder] Mask Sliver [0.01mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.021mm < 0.025mm) Between Via (156.606mm,125.287mm) from Component Side to Bottom Side And Pad R109-2(156.606mm,126.015mm) on Component Side [Top Solder] Mask Sliver [0.021mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.012mm < 0.025mm) Between Pad R16-2(29.249mm,105.258mm) on Component Side And Pad B2-3(30.414mm,105.27mm) on Component Side [Top Solder] Mask Sliver [0.012mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.009mm < 0.025mm) Between Pad C7-1(77.807mm,87.681mm) on Component Side And Pad IC2-5(76.794mm,87.681mm) on Component Side [Top Solder] Mask Sliver [0.009mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.009mm < 0.025mm) Between Pad C6-1(77.807mm,86.589mm) on Component Side And Pad IC2-4(76.794mm,86.606mm) on Component Side [Top Solder] Mask Sliver [0.009mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.022mm < 0.025mm) Between Pad Q2-5(61.096mm,56.177mm) on Component Side And Pad Q2-6_2(60.103mm,55.254mm) on Component Side [Top Solder] Mask Sliver [0.022mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.022mm < 0.025mm) Between Pad Q2-5_2(60.103mm,56.469mm) on Component Side And Pad Q2-6_2(60.103mm,55.254mm) on Component Side [Top Solder] Mask Sliver [0.022mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.022mm < 0.025mm) Between Pad Q2-6(61.096mm,55.547mm) on Component Side And Pad Q2-5_2(60.103mm,56.469mm) on Component Side [Top Solder] Mask Sliver [0.022mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.022mm < 0.025mm) Between Pad Q2-5(61.096mm,56.177mm) on Component Side And Pad Q2-6(61.096mm,55.547mm) on Component Side [Top Solder] Mask Sliver [0.022mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.02mm < 0.025mm) Between Via (67.429mm,51.562mm) from Component Side to Bottom Side And Pad U8-43(67.466mm,52.353mm) on Component Side [Top Solder] Mask Sliver [0.02mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.013mm < 0.025mm) Between Pad R79-2(42.722mm,87.17mm) on Component Side And Pad R79-4(41.529mm,87.17mm) on Component Side [Top Solder] Mask Sliver [0.013mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.013mm < 0.025mm) Between Pad R79-1(39.422mm,87.17mm) on Component Side And Pad R79-3(40.615mm,87.17mm) on Component Side [Top Solder] Mask Sliver [0.013mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.011mm < 0.025mm) Between Via (165.67mm,75.621mm) from Component Side to Bottom Side And Pad J1-G13(166.305mm,75.875mm) on Component Side [Top Solder] Mask Sliver [0.011mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.011mm < 0.025mm) Between Via (165.67mm,74.859mm) from Component Side to Bottom Side And Pad J1-G12(166.305mm,74.605mm) on Component Side [Top Solder] Mask Sliver [0.011mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.008mm < 0.025mm) Between Via (165.695mm,67.95mm) from Component Side to Bottom Side And Pad J1-G7(166.305mm,68.255mm) on Component Side [Top Solder] Mask Sliver [0.008mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.008mm < 0.025mm) Between Via (165.695mm,68.56mm) from Component Side to Bottom Side And Pad J1-G7(166.305mm,68.255mm) on Component Side [Top Solder] Mask Sliver [0.008mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.008mm < 0.025mm) Between Via (165.695mm,66.68mm) from Component Side to Bottom Side And Pad J1-G6(166.305mm,66.985mm) on Component Side [Top Solder] Mask Sliver [0.008mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.008mm < 0.025mm) Between Via (165.695mm,67.29mm) from Component Side to Bottom Side And Pad J1-G6(166.305mm,66.985mm) on Component Side [Top Solder] Mask Sliver [0.008mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.011mm < 0.025mm) Between Via (163.13mm,93.401mm) from Component Side to Bottom Side And Pad J1-D27(162.495mm,93.655mm) on Component Side [Top Solder] Mask Sliver [0.011mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.011mm < 0.025mm) Between Via (163.13mm,92.639mm) from Component Side to Bottom Side And Pad J1-D26(162.495mm,92.385mm) on Component Side [Top Solder] Mask Sliver [0.011mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.011mm < 0.025mm) Between Via (163.13mm,78.161mm) from Component Side to Bottom Side And Pad J1-D15(162.495mm,78.415mm) on Component Side [Top Solder] Mask Sliver [0.011mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.011mm < 0.025mm) Between Via (163.13mm,77.399mm) from Component Side to Bottom Side And Pad J1-D14(162.495mm,77.145mm) on Component Side [Top Solder] Mask Sliver [0.011mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.011mm < 0.025mm) Between Via (168.21mm,69.271mm) from Component Side to Bottom Side And Pad J1-H8(167.575mm,69.525mm) on Component Side [Top Solder] Mask Sliver [0.011mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.011mm < 0.025mm) Between Via (168.21mm,68.509mm) from Component Side to Bottom Side And Pad J1-H7(167.575mm,68.255mm) on Component Side [Top Solder] Mask Sliver [0.011mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.011mm < 0.025mm) Between Via (165.67mm,102.291mm) from Component Side to Bottom Side And Pad J1-G34(166.305mm,102.545mm) on Component Side [Top Solder] Mask Sliver [0.011mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.011mm < 0.025mm) Between Via (165.67mm,101.529mm) from Component Side to Bottom Side And Pad J1-G33(166.305mm,101.275mm) on Component Side [Top Solder] Mask Sliver [0.011mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.011mm < 0.025mm) Between Via (165.67mm,98.481mm) from Component Side to Bottom Side And Pad J1-G31(166.305mm,98.735mm) on Component Side [Top Solder] Mask Sliver [0.011mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.011mm < 0.025mm) Between Via (165.67mm,97.719mm) from Component Side to Bottom Side And Pad J1-G30(166.305mm,97.465mm) on Component Side [Top Solder] Mask Sliver [0.011mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.011mm < 0.025mm) Between Via (165.67mm,94.671mm) from Component Side to Bottom Side And Pad J1-G28(166.305mm,94.925mm) on Component Side [Top Solder] Mask Sliver [0.011mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.011mm < 0.025mm) Between Via (165.67mm,93.909mm) from Component Side to Bottom Side And Pad J1-G27(166.305mm,93.655mm) on Component Side [Top Solder] Mask Sliver [0.011mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.011mm < 0.025mm) Between Via (165.67mm,90.861mm) from Component Side to Bottom Side And Pad J1-G25(166.305mm,91.115mm) on Component Side [Top Solder] Mask Sliver [0.011mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.011mm < 0.025mm) Between Via (163.13mm,89.591mm) from Component Side to Bottom Side And Pad J1-D24(162.495mm,89.845mm) on Component Side [Top Solder] Mask Sliver [0.011mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.011mm < 0.025mm) Between Via (165.67mm,90.099mm) from Component Side to Bottom Side And Pad J1-G24(166.305mm,89.845mm) on Component Side [Top Solder] Mask Sliver [0.011mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.011mm < 0.025mm) Between Via (163.13mm,88.829mm) from Component Side to Bottom Side And Pad J1-D23(162.495mm,88.575mm) on Component Side [Top Solder] Mask Sliver [0.011mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.011mm < 0.025mm) Between Via (165.67mm,87.051mm) from Component Side to Bottom Side And Pad J1-G22(166.305mm,87.305mm) on Component Side [Top Solder] Mask Sliver [0.011mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.011mm < 0.025mm) Between Via (165.67mm,86.289mm) from Component Side to Bottom Side And Pad J1-G21(166.305mm,86.035mm) on Component Side [Top Solder] Mask Sliver [0.011mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.011mm < 0.025mm) Between Via (165.67mm,83.241mm) from Component Side to Bottom Side And Pad J1-G19(166.305mm,83.495mm) on Component Side [Top Solder] Mask Sliver [0.011mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.011mm < 0.025mm) Between Via (163.13mm,81.971mm) from Component Side to Bottom Side And Pad J1-D18(162.495mm,82.225mm) on Component Side [Top Solder] Mask Sliver [0.011mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.011mm < 0.025mm) Between Via (165.67mm,82.479mm) from Component Side to Bottom Side And Pad J1-G18(166.305mm,82.225mm) on Component Side [Top Solder] Mask Sliver [0.011mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.011mm < 0.025mm) Between Via (163.13mm,81.209mm) from Component Side to Bottom Side And Pad J1-D17(162.495mm,80.955mm) on Component Side [Top Solder] Mask Sliver [0.011mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.011mm < 0.025mm) Between Via (165.67mm,79.431mm) from Component Side to Bottom Side And Pad J1-G16(166.305mm,79.685mm) on Component Side [Top Solder] Mask Sliver [0.011mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.011mm < 0.025mm) Between Via (165.67mm,78.669mm) from Component Side to Bottom Side And Pad J1-G15(166.305mm,78.415mm) on Component Side [Top Solder] Mask Sliver [0.011mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.011mm < 0.025mm) Between Via (163.13mm,74.351mm) from Component Side to Bottom Side And Pad J1-D12(162.495mm,74.605mm) on Component Side [Top Solder] Mask Sliver [0.011mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.011mm < 0.025mm) Between Via (163.13mm,73.589mm) from Component Side to Bottom Side And Pad J1-D11(162.495mm,73.335mm) on Component Side [Top Solder] Mask Sliver [0.011mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.011mm < 0.025mm) Between Via (165.67mm,71.811mm) from Component Side to Bottom Side And Pad J1-G10(166.305mm,72.065mm) on Component Side [Top Solder] Mask Sliver [0.011mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.011mm < 0.025mm) Between Via (165.67mm,71.049mm) from Component Side to Bottom Side And Pad J1-G9(166.305mm,70.795mm) on Component Side [Top Solder] Mask Sliver [0.011mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.008mm < 0.025mm) Between Via (166.915mm,66.02mm) from Component Side to Bottom Side And Pad J1-G5(166.305mm,65.715mm) on Component Side [Top Solder] Mask Sliver [0.008mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.008mm < 0.025mm) Between Via (166.915mm,64.14mm) from Component Side to Bottom Side And Pad J1-G4(166.305mm,64.445mm) on Component Side [Top Solder] Mask Sliver [0.008mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.025mm < 0.025mm) Between Via (161.865mm,62.205mm) from Component Side to Bottom Side And Pad J1-D2(162.495mm,61.905mm) on Component Side [Top Solder] Mask Sliver [0.025mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.008mm < 0.025mm) Between Via (166.965mm,64.75mm) from Component Side to Bottom Side And Pad J1-H4(167.575mm,64.445mm) on Component Side [Top Solder] Mask Sliver [0.008mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.008mm < 0.025mm) Between Via (166.965mm,65.41mm) from Component Side to Bottom Side And Pad J1-H5(167.575mm,65.715mm) on Component Side [Top Solder] Mask Sliver [0.008mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.021mm < 0.025mm) Between Via (25.425mm,80.058mm) from Component Side to Bottom Side And Pad C102-2(25.756mm,79.23mm) on Component Side [Top Solder] Mask Sliver [0.021mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.021mm < 0.025mm) Between Via (26.162mm,80.058mm) from Component Side to Bottom Side And Pad C102-2(25.756mm,79.23mm) on Component Side [Top Solder] Mask Sliver [0.021mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.012mm < 0.025mm) Between Via (39.091mm,75.842mm) from Component Side to Bottom Side And Pad C106-1(38.322mm,75.842mm) on Component Side [Top Solder] Mask Sliver [0.012mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.024mm < 0.025mm) Between Via (62.222mm,55.728mm) from Component Side to Bottom Side And Pad C79-1(62.4mm,55.01mm) on Component Side [Top Solder] Mask Sliver [0.024mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.024mm < 0.025mm) Between Via (62.588mm,56.21mm) from Component Side to Bottom Side And Pad C85-2(62.425mm,56.928mm) on Component Side [Top Solder] Mask Sliver [0.024mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.014mm < 0.025mm) Between Via (66.464mm,49.378mm) from Component Side to Bottom Side And Pad C96-1(67.099mm,49.943mm) on Component Side [Top Solder] Mask Sliver [0.014mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.009mm < 0.025mm) Between Via (71.806mm,109.372mm) from Component Side to Bottom Side And Pad J3-10(71.823mm,110.838mm) on Component Side [Top Solder] Mask Sliver [0.009mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.009mm < 0.025mm) Between Via (72.606mm,109.372mm) from Component Side to Bottom Side And Pad J3-9(72.623mm,110.838mm) on Component Side [Top Solder] Mask Sliver [0.009mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.009mm < 0.025mm) Between Via (74.206mm,109.372mm) from Component Side to Bottom Side And Pad J3-7(74.223mm,110.838mm) on Component Side [Top Solder] Mask Sliver [0.009mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.009mm < 0.025mm) Between Via (75.006mm,109.372mm) from Component Side to Bottom Side And Pad J3-6(75.023mm,110.838mm) on Component Side [Top Solder] Mask Sliver [0.009mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.009mm < 0.025mm) Between Via (77.406mm,109.372mm) from Component Side to Bottom Side And Pad J3-3(77.423mm,110.838mm) on Component Side [Top Solder] Mask Sliver [0.009mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.009mm < 0.025mm) Between Via (79.006mm,109.372mm) from Component Side to Bottom Side And Pad J3-1(79.023mm,110.838mm) on Component Side [Top Solder] Mask Sliver [0.009mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.008mm < 0.025mm) Between Via (91.618mm,111.303mm) from Component Side to Bottom Side And Pad R87-2(92.532mm,111.24mm) on Component Side [Top Solder] Mask Sliver [0.008mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.021mm < 0.025mm) Between Via (91.706mm,117.919mm) from Component Side to Bottom Side And Pad R93-1(92.634mm,117.919mm) on Component Side [Top Solder] Mask Sliver [0.021mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.025mm < 0.025mm) Between Via (67.073mm,49.047mm) from Component Side to Bottom Side And Pad R70-1(67.63mm,48.394mm) on Component Side [Top Solder] Mask Sliver [0.025mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.013mm < 0.025mm) Between Pad R55-2(29.643mm,121.814mm) on Component Side And Pad R55-4(29.643mm,123.006mm) on Component Side [Top Solder] Mask Sliver [0.013mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.013mm < 0.025mm) Between Pad R55-1(29.643mm,125.114mm) on Component Side And Pad R55-3(29.643mm,123.921mm) on Component Side [Top Solder] Mask Sliver [0.013mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.013mm < 0.025mm) Between Pad R62-2(43.632mm,44.526mm) on Component Side And Pad R62-4(44.825mm,44.526mm) on Component Side [Top Solder] Mask Sliver [0.013mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.013mm < 0.025mm) Between Pad R62-1(46.932mm,44.526mm) on Component Side And Pad R62-3(45.739mm,44.526mm) on Component Side [Top Solder] Mask Sliver [0.013mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.003mm < 0.025mm) Between Via (112.2mm,98.6mm) from Component Side to Bottom Side And Pad IC1-2(112.624mm,99.553mm) on Bottom Side [Bottom Solder] Mask Sliver [0.003mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.01mm < 0.025mm) Between Via (112.2mm,98.6mm) from Component Side to Bottom Side And Pad IC1-1(111.549mm,99.553mm) on Bottom Side [Bottom Solder] Mask Sliver [0.01mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.004mm < 0.025mm) Between Via (112.2mm,98.6mm) from Component Side to Bottom Side And Pad IC1-6(111.549mm,97.653mm) on Bottom Side [Bottom Solder] Mask Sliver [0.004mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.016mm < 0.025mm) Between Via (84.633mm,119.431mm) from Component Side to Bottom Side And Pad L7-1(86.106mm,119.364mm) on Bottom Side [Bottom Solder] Mask Sliver [0.016mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.005mm < 0.025mm) Between Via (36.715mm,51.169mm) from Component Side to Bottom Side And Pad Q1-4(37.323mm,50.669mm) on Bottom Side [Bottom Solder] Mask Sliver [0.005mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.005mm < 0.025mm) Between Via (36.715mm,51.169mm) from Component Side to Bottom Side And Pad Q1-6(37.323mm,51.669mm) on Bottom Side [Bottom Solder] Mask Sliver [0.005mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.023mm < 0.025mm) Between Via (120.1mm,76.6mm) from Component Side to Bottom Side And Pad R3-2(119.744mm,77.38mm) on Bottom Side [Bottom Solder] Mask Sliver [0.023mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.011mm < 0.025mm) Between Via (68mm,60.7mm) from Component Side to Bottom Side And Pad R56-1(67.295mm,60.452mm) on Bottom Side [Bottom Solder] Mask Sliver [0.011mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.011mm < 0.025mm) Between Via (91.2mm,95.5mm) from Component Side to Bottom Side And Pad R78-1(90.5mm,96.075mm) on Bottom Side [Bottom Solder] Mask Sliver [0.011mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.015mm < 0.025mm) Between Via (131.4mm,110.8mm) from Component Side to Bottom Side And Pad U3-5(131.333mm,110.028mm) on Bottom Side [Bottom Solder] Mask Sliver [0.015mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.021mm < 0.025mm) Between Via (105.131mm,98.73mm) from Component Side to Bottom Side And Pad U14-4(104.216mm,98.512mm) on Bottom Side [Bottom Solder] Mask Sliver [0.021mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.002mm < 0.025mm) Between Via (166.965mm,65.41mm) from Component Side to Bottom Side And Via (166.915mm,66.02mm) from Component Side to Bottom Side [Top Solder] Mask Sliver [0.002mm] / [Bottom Solder] Mask Sliver [0.002mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.002mm < 0.025mm) Between Via (166.965mm,64.75mm) from Component Side to Bottom Side And Via (166.915mm,64.14mm) from Component Side to Bottom Side [Top Solder] Mask Sliver [0.002mm] / [Bottom Solder] Mask Sliver [0.002mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.016mm < 0.025mm) Between Via (48.3mm,50.6mm) from Component Side to Bottom Side And Via (48.9mm,50.6mm) from Component Side to Bottom Side [Top Solder] Mask Sliver [0.016mm] / [Bottom Solder] Mask Sliver [0.016mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.003mm < 0.025mm) Between Via (68mm,51.7mm) from Component Side to Bottom Side And Via (67.429mm,51.562mm) from Component Side to Bottom Side [Top Solder] Mask Sliver [0.003mm] / [Bottom Solder] Mask Sliver [0.003mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.022mm < 0.025mm) Between Via (62.588mm,56.21mm) from Component Side to Bottom Side And Via (62.222mm,55.728mm) from Component Side to Bottom Side [Top Solder] Mask Sliver [0.022mm] / [Bottom Solder] Mask Sliver [0.022mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.01mm < 0.025mm) Between Via (110.49mm,64.465mm) from Component Side to Bottom Side And Via (110.49mm,65.187mm) from Component Side to Bottom Side [Top Solder] Mask Sliver [0.01mm] / [Bottom Solder] Mask Sliver [0.01mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.01mm < 0.025mm) Between Via (91.618mm,111.923mm) from Component Side to Bottom Side And Via (91.618mm,111.303mm) from Component Side to Bottom Side [Top Solder] Mask Sliver [0.01mm] / [Bottom Solder] Mask Sliver [0.01mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.01mm < 0.025mm) Between Via (91.618mm,112.542mm) from Component Side to Bottom Side And Via (91.618mm,111.923mm) from Component Side to Bottom Side [Top Solder] Mask Sliver [0.01mm] / [Bottom Solder] Mask Sliver [0.01mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.01mm < 0.025mm) Between Via (91.618mm,113.162mm) from Component Side to Bottom Side And Via (91.618mm,112.542mm) from Component Side to Bottom Side [Top Solder] Mask Sliver [0.01mm] / [Bottom Solder] Mask Sliver [0.01mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.01mm < 0.025mm) Between Via (91.618mm,113.782mm) from Component Side to Bottom Side And Via (91.618mm,113.162mm) from Component Side to Bottom Side [Top Solder] Mask Sliver [0.01mm] / [Bottom Solder] Mask Sliver [0.01mm]
Violation between Minimum Solder Mask Sliver Constraint: (0.01mm < 0.025mm) Between Via (91.618mm,114.402mm) from Component Side to Bottom Side And Via (91.618mm,113.782mm) from Component Side to Bottom Side [Top Solder] Mask Sliver [0.01mm] / [Bottom Solder] Mask Sliver [0.01mm]
Rule Violations :92
Processing Rule : Silk To Solder Mask (Clearance=0.254mm) (Disabled)(IsPad),(All)
Rule Violations :0
Processing Rule : Silk to Silk (Clearance=0.127mm) (All),(All)
Violation between Silk To Silk Clearance Constraint: (Collision < 0.127mm) Between Text "Rout1" (35.8mm,124.4mm) on Top Overlay And Track (38.156mm,122.634mm)(38.156mm,135.634mm) on Top Overlay Silk Text to Silk Clearance [0mm]
Violation between Silk To Silk Clearance Constraint: (Collision < 0.127mm) Between Text "C35" (87.976mm,72.121mm) on Top Overlay And Track (87.941mm,69.501mm)(87.941mm,92.501mm) on Top Overlay Silk Text to Silk Clearance [0mm]
Violation between Silk To Silk Clearance Constraint: (Collision < 0.127mm) Between Text "C34" (87.951mm,73.671mm) on Top Overlay And Track (87.941mm,69.501mm)(87.941mm,92.501mm) on Top Overlay Silk Text to Silk Clearance [0mm]
Violation between Silk To Silk Clearance Constraint: (0.12mm < 0.127mm) Between Text "C7" (77.749mm,88.214mm) on Top Overlay And Track (78.13mm,87.986mm)(78.334mm,87.986mm) on Top Overlay Silk Text to Silk Clearance [0.12mm]
Violation between Silk To Silk Clearance Constraint: (0.041mm < 0.127mm) Between Text "*" (35.1mm,75.5mm) on Top Overlay And Track (35.23mm,75.232mm)(35.23mm,75.435mm) on Top Overlay Silk Text to Silk Clearance [0.041mm]
Violation between Silk To Silk Clearance Constraint: (0.111mm < 0.127mm) Between Text "C76" (72.5mm,54.9mm) on Top Overlay And Track (73.397mm,55.76mm)(73.6mm,55.76mm) on Top Overlay Silk Text to Silk Clearance [0.111mm]
Violation between Silk To Silk Clearance Constraint: (0.082mm < 0.127mm) Between Text "C12" (105.9mm,89.2mm) on Bottom Overlay And Track (106.096mm,88.443mm)(106.096mm,88.646mm) on Bottom Overlay Silk Text to Silk Clearance [0.082mm]
Violation between Silk To Silk Clearance Constraint: (0.058mm < 0.127mm) Between Text "R13" (99.7mm,75.8mm) on Bottom Overlay And Track (99.847mm,75.616mm)(99.847mm,75.819mm) on Bottom Overlay Silk Text to Silk Clearance [0.058mm]
Violation between Silk To Silk Clearance Constraint: (0.102mm < 0.127mm) Between Text "R19" (165.583mm,98.831mm) on Bottom Overlay And Track (163.805mm,99.162mm)(163.805mm,99.365mm) on Bottom Overlay Silk Text to Silk Clearance [0.102mm]
Violation between Silk To Silk Clearance Constraint: (0.123mm < 0.127mm) Between Text "R20" (165.71mm,102.667mm) on Bottom Overlay And Track (163.805mm,103.073mm)(163.805mm,103.276mm) on Bottom Overlay Silk Text to Silk Clearance [0.123mm]
Violation between Silk To Silk Clearance Constraint: (0.012mm < 0.127mm) Between Text "R53" (72mm,51.7mm) on Bottom Overlay And Track (71.264mm,50.851mm)(71.264mm,51.054mm) on Bottom Overlay Silk Text to Silk Clearance [0.012mm]
Violation between Silk To Silk Clearance Constraint: (0.093mm < 0.127mm) Between Text "R57" (70.3mm,49.8mm) on Bottom Overlay And Track (69.461mm,49.835mm)(69.461mm,50.038mm) on Bottom Overlay Silk Text to Silk Clearance [0.093mm]
Violation between Silk To Silk Clearance Constraint: (0.113mm < 0.127mm) Between Text "R100" (135.93mm,122.976mm) on Top Overlay And Text "R103" (135.055mm,122.976mm) on Top Overlay Silk Text to Silk Clearance [0.113mm]
Violation between Silk To Silk Clearance Constraint: (0.113mm < 0.127mm) Between Text "R101" (134.181mm,123.082mm) on Top Overlay And Text "R103" (135.055mm,122.976mm) on Top Overlay Silk Text to Silk Clearance [0.113mm]
Violation between Silk To Silk Clearance Constraint: (0.113mm < 0.127mm) Between Text "R100" (135.93mm,122.976mm) on Top Overlay And Text "R102" (136.804mm,122.976mm) on Top Overlay Silk Text to Silk Clearance [0.113mm]
Violation between Silk To Silk Clearance Constraint: (0.113mm < 0.127mm) Between Text "R98" (133.306mm,123.241mm) on Top Overlay And Text "R101" (134.181mm,123.082mm) on Top Overlay Silk Text to Silk Clearance [0.113mm]
Violation between Silk To Silk Clearance Constraint: (0.113mm < 0.127mm) Between Text "R97" (130.683mm,123.241mm) on Top Overlay And Text "R99" (131.557mm,123.241mm) on Top Overlay Silk Text to Silk Clearance [0.113mm]
Violation between Silk To Silk Clearance Constraint: (0.113mm < 0.127mm) Between Text "R80" (132.432mm,123.241mm) on Top Overlay And Text "R99" (131.557mm,123.241mm) on Top Overlay Silk Text to Silk Clearance [0.113mm]
Violation between Silk To Silk Clearance Constraint: (0.113mm < 0.127mm) Between Text "R80" (132.432mm,123.241mm) on Top Overlay And Text "R98" (133.306mm,123.241mm) on Top Overlay Silk Text to Silk Clearance [0.113mm]
Violation between Silk To Silk Clearance Constraint: (0.111mm < 0.127mm) Between Text "R69" (70.909mm,44.552mm) on Top Overlay And Text "R70" (68.978mm,44.552mm) on Top Overlay Silk Text to Silk Clearance [0.111mm]
Violation between Silk To Silk Clearance Constraint: (0.111mm < 0.127mm) Between Text "R59" (67.048mm,44.552mm) on Top Overlay And Text "R70" (68.978mm,44.552mm) on Top Overlay Silk Text to Silk Clearance [0.111mm]
Violation between Silk To Silk Clearance Constraint: (0.06mm < 0.127mm) Between Text "R59" (67.048mm,44.552mm) on Top Overlay And Text "R61" (65.168mm,44.552mm) on Top Overlay Silk Text to Silk Clearance [0.06mm]
Violation between Silk To Silk Clearance Constraint: (0.102mm < 0.127mm) Between Text "C87" (68.878mm,47.186mm) on Top Overlay And Text "R67" (69.742mm,47.186mm) on Top Overlay Silk Text to Silk Clearance [0.102mm]
Violation between Silk To Silk Clearance Constraint: (0.093mm < 0.127mm) Between Text "R10" (126.043mm,97.333mm) on Top Overlay And Text "R11" (125.188mm,97.358mm) on Top Overlay Silk Text to Silk Clearance [0.093mm]
Violation between Silk To Silk Clearance Constraint: (0.051mm < 0.127mm) Between Text "C96" (66.821mm,47.567mm) on Top Overlay And Text "C97" (67.634mm,47.618mm) on Top Overlay Silk Text to Silk Clearance [0.051mm]
Rule Violations :25
Processing Rule : Net Antennae (Tolerance=0mm) (All)
Rule Violations :0
Processing Rule : Length Constraint (Min=0mm) (Max=2540mm) (All)
Rule Violations :0
Processing Rule : Matched Lengths(Tolerance=1.016mm) (InAnyDifferentialPair)
Violation between Matched Net Lengths: Between Net PMODB4_P And Net PMODB4_N Actual Difference against PMODB4_N is: 2.263mm, Tolerance : 1.016mm.
Violation between Matched Net Lengths: Between Net PMODB2_P And Net PMODB2_N Actual Difference against PMODB2_N is: 1.791mm, Tolerance : 1.016mm.
Violation between Matched Net Lengths: Between Net PMODB1_P And Net PMODB1_N Actual Difference against PMODB1_N is: 1.255mm, Tolerance : 1.016mm.
Violation between Matched Net Lengths: Between Net PMODA3_P And Net PMODA3_N Actual Difference against PMODA3_N is: 1.485mm, Tolerance : 1.016mm.
Violation between Matched Net Lengths: Between Net PMODA2_P And Net PMODA2_N Actual Difference against PMODA2_N is: 1.513mm, Tolerance : 1.016mm.
Violation between Matched Net Lengths: Between Net PMODA1_P And Net PMODA1_N Actual Difference against PMODA1_N is: 1.475mm, Tolerance : 1.016mm.
Violation between Matched Net Lengths: Between Net SFP2_RD_P And Net SFP2_RD_N Actual Difference against SFP2_RD_N is: 1.062mm, Tolerance : 1.016mm.
Violation between Matched Net Lengths: Between Net FMC_MGT_M2C_P And Net FMC_MGT_M2C_N Actual Difference against FMC_MGT_M2C_N is: 1.673mm, Tolerance : 1.016mm.
Violation between Matched Net Lengths: Between Net FMC_MGT_CLK_P And Net FMC_MGT_CLK_N Actual Difference against FMC_MGT_CLK_N is: 4.058mm, Tolerance : 1.016mm.
Violation between Matched Net Lengths: Between Net FMC_MGT_C2M_P And Net FMC_MGT_C2M_N Actual Difference against FMC_MGT_C2M_N is: 1.614mm, Tolerance : 1.016mm.
Violation between Matched Net Lengths: Between Net FMC_LA32_P And Net FMC_LA32_N Actual Difference against FMC_LA32_N is: 2.188mm, Tolerance : 1.016mm.
Violation between Matched Net Lengths: Between Net FMC_LA31_P And Net FMC_LA31_N Actual Difference against FMC_LA31_N is: 1.278mm, Tolerance : 1.016mm.
Violation between Matched Net Lengths: Between Net FMC_LA30_P And Net FMC_LA30_N Actual Difference against FMC_LA30_N is: 2.188mm, Tolerance : 1.016mm.
Violation between Matched Net Lengths: Between Net FMC_LA29_P And Net FMC_LA29_N Actual Difference against FMC_LA29_N is: 1.328mm, Tolerance : 1.016mm.
Violation between Matched Net Lengths: Between Net FMC_LA28_P And Net FMC_LA28_N Actual Difference against FMC_LA28_N is: 2.188mm, Tolerance : 1.016mm.
Violation between Matched Net Lengths: Between Net FMC_LA27_P And Net FMC_LA27_N Actual Difference against FMC_LA27_N is: 3.049mm, Tolerance : 1.016mm.
Violation between Matched Net Lengths: Between Net FMC_LA26_P And Net FMC_LA26_N Actual Difference against FMC_LA26_N is: 1.759mm, Tolerance : 1.016mm.
Violation between Matched Net Lengths: Between Net FMC_LA25_P And Net FMC_LA25_N Actual Difference against FMC_LA25_N is: 1.936mm, Tolerance : 1.016mm.
Violation between Matched Net Lengths: Between Net FMC_LA24_P And Net FMC_LA24_N Actual Difference against FMC_LA24_N is: 2.306mm, Tolerance : 1.016mm.
Violation between Matched Net Lengths: Between Net FMC_LA23_P And Net FMC_LA23_N Actual Difference against FMC_LA23_N is: 1.355mm, Tolerance : 1.016mm.
Violation between Matched Net Lengths: Between Net FMC_LA22_P And Net FMC_LA22_N Actual Difference against FMC_LA22_N is: 2.008mm, Tolerance : 1.016mm.
Violation between Matched Net Lengths: Between Net FMC_LA21_P And Net FMC_LA21_N Actual Difference against FMC_LA21_N is: 2.188mm, Tolerance : 1.016mm.
Violation between Matched Net Lengths: Between Net FMC_LA20_P And Net FMC_LA20_N Actual Difference against FMC_LA20_N is: 2.478mm, Tolerance : 1.016mm.
Violation between Matched Net Lengths: Between Net FMC_LA19_P And Net FMC_LA19_N Actual Difference against FMC_LA19_N is: 2.228mm, Tolerance : 1.016mm.
Violation between Matched Net Lengths: Between Net FMC_LA17_CC_P And Net FMC_LA17_CC_N Actual Difference against FMC_LA17_CC_N is: 2.188mm, Tolerance : 1.016mm.
Violation between Matched Net Lengths: Between Net FMC_LA16_P And Net FMC_LA16_N Actual Difference against FMC_LA16_N is: 2.187mm, Tolerance : 1.016mm.
Violation between Matched Net Lengths: Between Net FMC_LA15_P And Net FMC_LA15_N Actual Difference against FMC_LA15_N is: 2.188mm, Tolerance : 1.016mm.
Violation between Matched Net Lengths: Between Net FMC_LA14_P And Net FMC_LA14_N Actual Difference against FMC_LA14_N is: 2.095mm, Tolerance : 1.016mm.
Violation between Matched Net Lengths: Between Net FMC_LA13_P And Net FMC_LA13_N Actual Difference against FMC_LA13_N is: 1.686mm, Tolerance : 1.016mm.
Violation between Matched Net Lengths: Between Net FMC_LA12_P And Net FMC_LA12_N Actual Difference against FMC_LA12_N is: 1.963mm, Tolerance : 1.016mm.
Violation between Matched Net Lengths: Between Net FMC_LA10_P And Net FMC_LA10_N Actual Difference against FMC_LA10_N is: 1.762mm, Tolerance : 1.016mm.
Violation between Matched Net Lengths: Between Net FMC_LA09_P And Net FMC_LA09_N Actual Difference against FMC_LA09_N is: 2.389mm, Tolerance : 1.016mm.
Violation between Matched Net Lengths: Between Net FMC_LA08_P And Net FMC_LA08_N Actual Difference against FMC_LA08_N is: 2.183mm, Tolerance : 1.016mm.
Violation between Matched Net Lengths: Between Net FMC_LA06_P And Net FMC_LA06_N Actual Difference against FMC_LA06_N is: 3.017mm, Tolerance : 1.016mm.
Violation between Matched Net Lengths: Between Net FMC_LA05_P And Net FMC_LA05_N Actual Difference against FMC_LA05_N is: 2.16mm, Tolerance : 1.016mm.
Violation between Matched Net Lengths: Between Net FMC_LA03_P And Net FMC_LA03_N Actual Difference against FMC_LA03_N is: 2.241mm, Tolerance : 1.016mm.
Violation between Matched Net Lengths: Between Net FMC_LA02_P And Net FMC_LA02_N Actual Difference against FMC_LA02_N is: 2.725mm, Tolerance : 1.016mm.
Violation between Matched Net Lengths: Between Net FMC_LA01_CC_P And Net FMC_LA01_CC_N Actual Difference against FMC_LA01_CC_N is: 1.666mm, Tolerance : 1.016mm.
Violation between Matched Net Lengths: Between Net FMC_LA00_CC_P And Net FMC_LA00_CC_N Actual Difference against FMC_LA00_CC_N is: 3.977mm, Tolerance : 1.016mm.
Violation between Matched Net Lengths: Between Net FMC_CLK1_M2C_P And Net FMC_CLK1_M2C_N Actual Difference against FMC_CLK1_M2C_N is: 1.657mm, Tolerance : 1.016mm.
Violation between Matched Net Lengths: Between Net FMC_CLK0_M2C_P And Net FMC_CLK0_M2C_N Actual Difference against FMC_CLK0_M2C_N is: 2.504mm, Tolerance : 1.016mm.
Rule Violations :41
Processing Rule : Max Via Stub Length (Back Drilling rule) (Max Stub Length = 0.381mm) (InAnyDifferentialPair)
Rule Violations :0
Processing Rule : Room SFP (Bounding Region = (0mm, 0mm, 50.8mm, 25.4mm) (Disabled)(InComponentClass('SFP'))
Rule Violations :0
Processing Rule : Room Regulators (Bounding Region = (0mm, 0mm, 50.8mm, 25.4mm) (Disabled)(InComponentClass('Regulators'))
Rule Violations :0
Processing Rule : Room PWR_APD5052 (Bounding Region = (0mm, 0mm, 50.8mm, 25.4mm) (Disabled)(InComponentClass('PWR_APD5052'))
Rule Violations :0
Processing Rule : Room IO (Bounding Region = (0mil, 0mil, 2000mil, 1000mil) (Disabled)(InComponentClass('IO'))
Processing Rule : Room IO (Bounding Region = (0mm, 0mm, 50.8mm, 25.4mm) (Disabled)(InComponentClass('IO'))
Rule Violations :0
Processing Rule : Room FMC (Bounding Region = (0mil, 0mil, 2000mil, 1000mil) (Disabled)(InComponentClass('FMC'))
Processing Rule : Room FMC (Bounding Region = (0mm, 0mm, 50.8mm, 25.4mm) (Disabled)(InComponentClass('FMC'))
Rule Violations :0
Processing Rule : Room Config (Bounding Region = (0mil, 0mil, 2000mil, 1000mil) (Disabled)(InComponentClass('Config'))
Processing Rule : Room Config (Bounding Region = (0mm, 0mm, 50.8mm, 25.4mm) (Disabled)(InComponentClass('Config'))
Rule Violations :0
Processing Rule : Room FPGA_Banks1 (Bounding Region = (0mil, 0mil, 2000mil, 1000mil) (Disabled)(InComponentClass('FPGA_Banks1'))
Processing Rule : Room FPGA_Banks1 (Bounding Region = (0mm, 0mm, 50.8mm, 25.4mm) (Disabled)(InComponentClass('FPGA_Banks1'))
Rule Violations :0
Processing Rule : Room FPGA_PWR (Bounding Region = (0mil, 0mil, 2000mil, 1000mil) (Disabled)(InComponentClass('FPGA_PWR'))
Processing Rule : Room FPGA_PWR (Bounding Region = (0mm, 0mm, 50.8mm, 25.4mm) (Disabled)(InComponentClass('FPGA_PWR'))
Rule Violations :0
Processing Rule : Room FPGA_Banks2 (Bounding Region = (0mil, 0mil, 2000mil, 1000mil) (Disabled)(InComponentClass('FPGA_Banks2'))
Processing Rule : Room FPGA_Banks2 (Bounding Region = (0mm, 0mm, 50.8mm, 25.4mm) (Disabled)(InComponentClass('FPGA_Banks2'))
Rule Violations :0
Processing Rule : Height Constraint (Min=0mil) (Max=1000mil) (Prefered=500mil) (All)
Processing Rule : Height Constraint (Min=0mm) (Max=25.4mm) (Prefered=12.7mm) (All)
Rule Violations :0
Violations Detected : 151
Violations Detected : 165
Waived Violations : 0
Time Elapsed : 00:00:08
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Time Elapsed : 00:00:06
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hardware/altium/Project Outputs for atfc/Design Rule Check - atfc.html
View file @ e0a54952
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