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-- Title          : Wishbone slave core for Control and status register for the MLVDS trigger
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-- File           : wb_trigger_mux_regs_pkg.vhd
-- Author         : auto-generated by wbgen2 from wb_trigger_mux.wb
-- Created        : Wed May 11 18:21:31 2016
-- Standard       : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wb_trigger_mux.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

package wb_trig_mux_wbgen2_pkg is


  -- Input registers (user design -> WB slave)

  type t_wb_trig_mux_in_registers is record
    ch0_dummy_i                              : std_logic_vector(31 downto 0);
    ch1_dummy_i                              : std_logic_vector(31 downto 0);
    ch2_dummy_i                              : std_logic_vector(31 downto 0);
    ch3_dummy_i                              : std_logic_vector(31 downto 0);
    ch4_dummy_i                              : std_logic_vector(31 downto 0);
    ch5_dummy_i                              : std_logic_vector(31 downto 0);
    ch6_dummy_i                              : std_logic_vector(31 downto 0);
    ch7_dummy_i                              : std_logic_vector(31 downto 0);
    ch8_dummy_i                              : std_logic_vector(31 downto 0);
    ch9_dummy_i                              : std_logic_vector(31 downto 0);
    ch10_dummy_i                             : std_logic_vector(31 downto 0);
    ch11_dummy_i                             : std_logic_vector(31 downto 0);
    ch12_dummy_i                             : std_logic_vector(31 downto 0);
    ch13_dummy_i                             : std_logic_vector(31 downto 0);
    ch14_dummy_i                             : std_logic_vector(31 downto 0);
    ch15_dummy_i                             : std_logic_vector(31 downto 0);
    ch16_dummy_i                             : std_logic_vector(31 downto 0);
    ch17_dummy_i                             : std_logic_vector(31 downto 0);
    ch18_dummy_i                             : std_logic_vector(31 downto 0);
    ch19_dummy_i                             : std_logic_vector(31 downto 0);
    ch20_dummy_i                             : std_logic_vector(31 downto 0);
    ch21_dummy_i                             : std_logic_vector(31 downto 0);
    ch22_dummy_i                             : std_logic_vector(31 downto 0);
    ch23_dummy_i                             : std_logic_vector(31 downto 0);
    end record;

  constant c_wb_trig_mux_in_registers_init_value: t_wb_trig_mux_in_registers := (
    ch0_dummy_i => (others => '0'),
    ch1_dummy_i => (others => '0'),
    ch2_dummy_i => (others => '0'),
    ch3_dummy_i => (others => '0'),
    ch4_dummy_i => (others => '0'),
    ch5_dummy_i => (others => '0'),
    ch6_dummy_i => (others => '0'),
    ch7_dummy_i => (others => '0'),
    ch8_dummy_i => (others => '0'),
    ch9_dummy_i => (others => '0'),
    ch10_dummy_i => (others => '0'),
    ch11_dummy_i => (others => '0'),
    ch12_dummy_i => (others => '0'),
    ch13_dummy_i => (others => '0'),
    ch14_dummy_i => (others => '0'),
    ch15_dummy_i => (others => '0'),
    ch16_dummy_i => (others => '0'),
    ch17_dummy_i => (others => '0'),
    ch18_dummy_i => (others => '0'),
    ch19_dummy_i => (others => '0'),
    ch20_dummy_i => (others => '0'),
    ch21_dummy_i => (others => '0'),
    ch22_dummy_i => (others => '0'),
    ch23_dummy_i => (others => '0')
    );

    -- Output registers (WB slave -> user design)

    type t_wb_trig_mux_out_registers is record
      ch0_ctl_rcv_src_o                        : std_logic;
      ch0_ctl_rcv_in_sel_o                     : std_logic_vector(7 downto 0);
      ch0_ctl_transm_src_o                     : std_logic;
      ch0_ctl_transm_out_sel_o                 : std_logic_vector(7 downto 0);
      ch1_ctl_rcv_src_o                        : std_logic;
      ch1_ctl_rcv_in_sel_o                     : std_logic_vector(7 downto 0);
      ch1_ctl_transm_src_o                     : std_logic;
      ch1_ctl_transm_out_sel_o                 : std_logic_vector(7 downto 0);
      ch2_ctl_rcv_src_o                        : std_logic;
      ch2_ctl_rcv_in_sel_o                     : std_logic_vector(7 downto 0);
      ch2_ctl_transm_src_o                     : std_logic;
      ch2_ctl_transm_out_sel_o                 : std_logic_vector(7 downto 0);
      ch3_ctl_rcv_src_o                        : std_logic;
      ch3_ctl_rcv_in_sel_o                     : std_logic_vector(7 downto 0);
      ch3_ctl_transm_src_o                     : std_logic;
      ch3_ctl_transm_out_sel_o                 : std_logic_vector(7 downto 0);
      ch4_ctl_rcv_src_o                        : std_logic;
      ch4_ctl_rcv_in_sel_o                     : std_logic_vector(7 downto 0);
      ch4_ctl_transm_src_o                     : std_logic;
      ch4_ctl_transm_out_sel_o                 : std_logic_vector(7 downto 0);
      ch5_ctl_rcv_src_o                        : std_logic;
      ch5_ctl_rcv_in_sel_o                     : std_logic_vector(7 downto 0);
      ch5_ctl_transm_src_o                     : std_logic;
      ch5_ctl_transm_out_sel_o                 : std_logic_vector(7 downto 0);
      ch6_ctl_rcv_src_o                        : std_logic;
      ch6_ctl_rcv_in_sel_o                     : std_logic_vector(7 downto 0);
      ch6_ctl_transm_src_o                     : std_logic;
      ch6_ctl_transm_out_sel_o                 : std_logic_vector(7 downto 0);
      ch7_ctl_rcv_src_o                        : std_logic;
      ch7_ctl_rcv_in_sel_o                     : std_logic_vector(7 downto 0);
      ch7_ctl_transm_src_o                     : std_logic;
      ch7_ctl_transm_out_sel_o                 : std_logic_vector(7 downto 0);
      ch8_ctl_rcv_src_o                        : std_logic;
      ch8_ctl_rcv_in_sel_o                     : std_logic_vector(7 downto 0);
      ch8_ctl_transm_src_o                     : std_logic;
      ch8_ctl_transm_out_sel_o                 : std_logic_vector(7 downto 0);
      ch9_ctl_rcv_src_o                        : std_logic;
      ch9_ctl_rcv_in_sel_o                     : std_logic_vector(7 downto 0);
      ch9_ctl_transm_src_o                     : std_logic;
      ch9_ctl_transm_out_sel_o                 : std_logic_vector(7 downto 0);
      ch10_ctl_rcv_src_o                       : std_logic;
      ch10_ctl_rcv_in_sel_o                    : std_logic_vector(7 downto 0);
      ch10_ctl_transm_src_o                    : std_logic;
      ch10_ctl_transm_out_sel_o                : std_logic_vector(7 downto 0);
      ch11_ctl_rcv_src_o                       : std_logic;
      ch11_ctl_rcv_in_sel_o                    : std_logic_vector(7 downto 0);
      ch11_ctl_transm_src_o                    : std_logic;
      ch11_ctl_transm_out_sel_o                : std_logic_vector(7 downto 0);
      ch12_ctl_rcv_src_o                       : std_logic;
      ch12_ctl_rcv_in_sel_o                    : std_logic_vector(7 downto 0);
      ch12_ctl_transm_src_o                    : std_logic;
      ch12_ctl_transm_out_sel_o                : std_logic_vector(7 downto 0);
      ch13_ctl_rcv_src_o                       : std_logic;
      ch13_ctl_rcv_in_sel_o                    : std_logic_vector(7 downto 0);
      ch13_ctl_transm_src_o                    : std_logic;
      ch13_ctl_transm_out_sel_o                : std_logic_vector(7 downto 0);
      ch14_ctl_rcv_src_o                       : std_logic;
      ch14_ctl_rcv_in_sel_o                    : std_logic_vector(7 downto 0);
      ch14_ctl_transm_src_o                    : std_logic;
      ch14_ctl_transm_out_sel_o                : std_logic_vector(7 downto 0);
      ch15_ctl_rcv_src_o                       : std_logic;
      ch15_ctl_rcv_in_sel_o                    : std_logic_vector(7 downto 0);
      ch15_ctl_transm_src_o                    : std_logic;
      ch15_ctl_transm_out_sel_o                : std_logic_vector(7 downto 0);
      ch16_ctl_rcv_src_o                       : std_logic;
      ch16_ctl_rcv_in_sel_o                    : std_logic_vector(7 downto 0);
      ch16_ctl_transm_src_o                    : std_logic;
      ch16_ctl_transm_out_sel_o                : std_logic_vector(7 downto 0);
      ch17_ctl_rcv_src_o                       : std_logic;
      ch17_ctl_rcv_in_sel_o                    : std_logic_vector(7 downto 0);
      ch17_ctl_transm_src_o                    : std_logic;
      ch17_ctl_transm_out_sel_o                : std_logic_vector(7 downto 0);
      ch18_ctl_rcv_src_o                       : std_logic;
      ch18_ctl_rcv_in_sel_o                    : std_logic_vector(7 downto 0);
      ch18_ctl_transm_src_o                    : std_logic;
      ch18_ctl_transm_out_sel_o                : std_logic_vector(7 downto 0);
      ch19_ctl_rcv_src_o                       : std_logic;
      ch19_ctl_rcv_in_sel_o                    : std_logic_vector(7 downto 0);
      ch19_ctl_transm_src_o                    : std_logic;
      ch19_ctl_transm_out_sel_o                : std_logic_vector(7 downto 0);
      ch20_ctl_rcv_src_o                       : std_logic;
      ch20_ctl_rcv_in_sel_o                    : std_logic_vector(7 downto 0);
      ch20_ctl_transm_src_o                    : std_logic;
      ch20_ctl_transm_out_sel_o                : std_logic_vector(7 downto 0);
      ch21_ctl_rcv_src_o                       : std_logic;
      ch21_ctl_rcv_in_sel_o                    : std_logic_vector(7 downto 0);
      ch21_ctl_transm_src_o                    : std_logic;
      ch21_ctl_transm_out_sel_o                : std_logic_vector(7 downto 0);
      ch22_ctl_rcv_src_o                       : std_logic;
      ch22_ctl_rcv_in_sel_o                    : std_logic_vector(7 downto 0);
      ch22_ctl_transm_src_o                    : std_logic;
      ch22_ctl_transm_out_sel_o                : std_logic_vector(7 downto 0);
      ch23_ctl_rcv_src_o                       : std_logic;
      ch23_ctl_rcv_in_sel_o                    : std_logic_vector(7 downto 0);
      ch23_ctl_transm_src_o                    : std_logic;
      ch23_ctl_transm_out_sel_o                : std_logic_vector(7 downto 0);
      end record;

    constant c_wb_trig_mux_out_registers_init_value: t_wb_trig_mux_out_registers := (
      ch0_ctl_rcv_src_o => '0',
      ch0_ctl_rcv_in_sel_o => (others => '0'),
      ch0_ctl_transm_src_o => '0',
      ch0_ctl_transm_out_sel_o => (others => '0'),
      ch1_ctl_rcv_src_o => '0',
      ch1_ctl_rcv_in_sel_o => (others => '0'),
      ch1_ctl_transm_src_o => '0',
      ch1_ctl_transm_out_sel_o => (others => '0'),
      ch2_ctl_rcv_src_o => '0',
      ch2_ctl_rcv_in_sel_o => (others => '0'),
      ch2_ctl_transm_src_o => '0',
      ch2_ctl_transm_out_sel_o => (others => '0'),
      ch3_ctl_rcv_src_o => '0',
      ch3_ctl_rcv_in_sel_o => (others => '0'),
      ch3_ctl_transm_src_o => '0',
      ch3_ctl_transm_out_sel_o => (others => '0'),
      ch4_ctl_rcv_src_o => '0',
      ch4_ctl_rcv_in_sel_o => (others => '0'),
      ch4_ctl_transm_src_o => '0',
      ch4_ctl_transm_out_sel_o => (others => '0'),
      ch5_ctl_rcv_src_o => '0',
      ch5_ctl_rcv_in_sel_o => (others => '0'),
      ch5_ctl_transm_src_o => '0',
      ch5_ctl_transm_out_sel_o => (others => '0'),
      ch6_ctl_rcv_src_o => '0',
      ch6_ctl_rcv_in_sel_o => (others => '0'),
      ch6_ctl_transm_src_o => '0',
      ch6_ctl_transm_out_sel_o => (others => '0'),
      ch7_ctl_rcv_src_o => '0',
      ch7_ctl_rcv_in_sel_o => (others => '0'),
      ch7_ctl_transm_src_o => '0',
      ch7_ctl_transm_out_sel_o => (others => '0'),
      ch8_ctl_rcv_src_o => '0',
      ch8_ctl_rcv_in_sel_o => (others => '0'),
      ch8_ctl_transm_src_o => '0',
      ch8_ctl_transm_out_sel_o => (others => '0'),
      ch9_ctl_rcv_src_o => '0',
      ch9_ctl_rcv_in_sel_o => (others => '0'),
      ch9_ctl_transm_src_o => '0',
      ch9_ctl_transm_out_sel_o => (others => '0'),
      ch10_ctl_rcv_src_o => '0',
      ch10_ctl_rcv_in_sel_o => (others => '0'),
      ch10_ctl_transm_src_o => '0',
      ch10_ctl_transm_out_sel_o => (others => '0'),
      ch11_ctl_rcv_src_o => '0',
      ch11_ctl_rcv_in_sel_o => (others => '0'),
      ch11_ctl_transm_src_o => '0',
      ch11_ctl_transm_out_sel_o => (others => '0'),
      ch12_ctl_rcv_src_o => '0',
      ch12_ctl_rcv_in_sel_o => (others => '0'),
      ch12_ctl_transm_src_o => '0',
      ch12_ctl_transm_out_sel_o => (others => '0'),
      ch13_ctl_rcv_src_o => '0',
      ch13_ctl_rcv_in_sel_o => (others => '0'),
      ch13_ctl_transm_src_o => '0',
      ch13_ctl_transm_out_sel_o => (others => '0'),
      ch14_ctl_rcv_src_o => '0',
      ch14_ctl_rcv_in_sel_o => (others => '0'),
      ch14_ctl_transm_src_o => '0',
      ch14_ctl_transm_out_sel_o => (others => '0'),
      ch15_ctl_rcv_src_o => '0',
      ch15_ctl_rcv_in_sel_o => (others => '0'),
      ch15_ctl_transm_src_o => '0',
      ch15_ctl_transm_out_sel_o => (others => '0'),
      ch16_ctl_rcv_src_o => '0',
      ch16_ctl_rcv_in_sel_o => (others => '0'),
      ch16_ctl_transm_src_o => '0',
      ch16_ctl_transm_out_sel_o => (others => '0'),
      ch17_ctl_rcv_src_o => '0',
      ch17_ctl_rcv_in_sel_o => (others => '0'),
      ch17_ctl_transm_src_o => '0',
      ch17_ctl_transm_out_sel_o => (others => '0'),
      ch18_ctl_rcv_src_o => '0',
      ch18_ctl_rcv_in_sel_o => (others => '0'),
      ch18_ctl_transm_src_o => '0',
      ch18_ctl_transm_out_sel_o => (others => '0'),
      ch19_ctl_rcv_src_o => '0',
      ch19_ctl_rcv_in_sel_o => (others => '0'),
      ch19_ctl_transm_src_o => '0',
      ch19_ctl_transm_out_sel_o => (others => '0'),
      ch20_ctl_rcv_src_o => '0',
      ch20_ctl_rcv_in_sel_o => (others => '0'),
      ch20_ctl_transm_src_o => '0',
      ch20_ctl_transm_out_sel_o => (others => '0'),
      ch21_ctl_rcv_src_o => '0',
      ch21_ctl_rcv_in_sel_o => (others => '0'),
      ch21_ctl_transm_src_o => '0',
      ch21_ctl_transm_out_sel_o => (others => '0'),
      ch22_ctl_rcv_src_o => '0',
      ch22_ctl_rcv_in_sel_o => (others => '0'),
      ch22_ctl_transm_src_o => '0',
      ch22_ctl_transm_out_sel_o => (others => '0'),
      ch23_ctl_rcv_src_o => '0',
      ch23_ctl_rcv_in_sel_o => (others => '0'),
      ch23_ctl_transm_src_o => '0',
      ch23_ctl_transm_out_sel_o => (others => '0')
      );
    function "or" (left, right: t_wb_trig_mux_in_registers) return t_wb_trig_mux_in_registers;
    function f_x_to_zero (x:std_logic) return std_logic;
    function f_x_to_zero (x:std_logic_vector) return std_logic_vector;
end package;

package body wb_trig_mux_wbgen2_pkg is
function f_x_to_zero (x:std_logic) return std_logic is
begin
if x = '1' then
return '1';
else
return '0';
end if;
end function;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector is
variable tmp: std_logic_vector(x'length-1 downto 0);
begin
for i in 0 to x'length-1 loop
if(x(i) = 'X' or x(i) = 'U') then
tmp(i):= '0';
else
tmp(i):=x(i);
end if;
end loop;
return tmp;
end function;
function "or" (left, right: t_wb_trig_mux_in_registers) return t_wb_trig_mux_in_registers is
variable tmp: t_wb_trig_mux_in_registers;
begin
tmp.ch0_dummy_i := f_x_to_zero(left.ch0_dummy_i) or f_x_to_zero(right.ch0_dummy_i);
tmp.ch1_dummy_i := f_x_to_zero(left.ch1_dummy_i) or f_x_to_zero(right.ch1_dummy_i);
tmp.ch2_dummy_i := f_x_to_zero(left.ch2_dummy_i) or f_x_to_zero(right.ch2_dummy_i);
tmp.ch3_dummy_i := f_x_to_zero(left.ch3_dummy_i) or f_x_to_zero(right.ch3_dummy_i);
tmp.ch4_dummy_i := f_x_to_zero(left.ch4_dummy_i) or f_x_to_zero(right.ch4_dummy_i);
tmp.ch5_dummy_i := f_x_to_zero(left.ch5_dummy_i) or f_x_to_zero(right.ch5_dummy_i);
tmp.ch6_dummy_i := f_x_to_zero(left.ch6_dummy_i) or f_x_to_zero(right.ch6_dummy_i);
tmp.ch7_dummy_i := f_x_to_zero(left.ch7_dummy_i) or f_x_to_zero(right.ch7_dummy_i);
tmp.ch8_dummy_i := f_x_to_zero(left.ch8_dummy_i) or f_x_to_zero(right.ch8_dummy_i);
tmp.ch9_dummy_i := f_x_to_zero(left.ch9_dummy_i) or f_x_to_zero(right.ch9_dummy_i);
tmp.ch10_dummy_i := f_x_to_zero(left.ch10_dummy_i) or f_x_to_zero(right.ch10_dummy_i);
tmp.ch11_dummy_i := f_x_to_zero(left.ch11_dummy_i) or f_x_to_zero(right.ch11_dummy_i);
tmp.ch12_dummy_i := f_x_to_zero(left.ch12_dummy_i) or f_x_to_zero(right.ch12_dummy_i);
tmp.ch13_dummy_i := f_x_to_zero(left.ch13_dummy_i) or f_x_to_zero(right.ch13_dummy_i);
tmp.ch14_dummy_i := f_x_to_zero(left.ch14_dummy_i) or f_x_to_zero(right.ch14_dummy_i);
tmp.ch15_dummy_i := f_x_to_zero(left.ch15_dummy_i) or f_x_to_zero(right.ch15_dummy_i);
tmp.ch16_dummy_i := f_x_to_zero(left.ch16_dummy_i) or f_x_to_zero(right.ch16_dummy_i);
tmp.ch17_dummy_i := f_x_to_zero(left.ch17_dummy_i) or f_x_to_zero(right.ch17_dummy_i);
tmp.ch18_dummy_i := f_x_to_zero(left.ch18_dummy_i) or f_x_to_zero(right.ch18_dummy_i);
tmp.ch19_dummy_i := f_x_to_zero(left.ch19_dummy_i) or f_x_to_zero(right.ch19_dummy_i);
tmp.ch20_dummy_i := f_x_to_zero(left.ch20_dummy_i) or f_x_to_zero(right.ch20_dummy_i);
tmp.ch21_dummy_i := f_x_to_zero(left.ch21_dummy_i) or f_x_to_zero(right.ch21_dummy_i);
tmp.ch22_dummy_i := f_x_to_zero(left.ch22_dummy_i) or f_x_to_zero(right.ch22_dummy_i);
tmp.ch23_dummy_i := f_x_to_zero(left.ch23_dummy_i) or f_x_to_zero(right.ch23_dummy_i);
return tmp;
end function;
end package body;
