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-- Title          : Wishbone slave core for FMC ADC 250MS/s core registers
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-- File           : wb_fmc250m_4ch_regs.vhd
-- Author         : auto-generated by wbgen2 from wb_fmc250m_4ch_regs.wb
-- Created        : Thu Oct  6 16:55:33 2016
-- Standard       : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wb_fmc250m_4ch_regs.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

use work.wb_fmc_250m_4ch_csr_wbgen2_pkg.all;


entity wb_fmc_250m_4ch_csr is
  port (
    rst_n_i                                  : in     std_logic;
    clk_sys_i                                : in     std_logic;
    wb_adr_i                                 : in     std_logic_vector(4 downto 0);
    wb_dat_i                                 : in     std_logic_vector(31 downto 0);
    wb_dat_o                                 : out    std_logic_vector(31 downto 0);
    wb_cyc_i                                 : in     std_logic;
    wb_sel_i                                 : in     std_logic_vector(3 downto 0);
    wb_stb_i                                 : in     std_logic;
    wb_we_i                                  : in     std_logic;
    wb_ack_o                                 : out    std_logic;
    wb_stall_o                               : out    std_logic;
    fs_clk_i                                 : in     std_logic;
    regs_i                                   : in     t_wb_fmc_250m_4ch_csr_in_registers;
    regs_o                                   : out    t_wb_fmc_250m_4ch_csr_out_registers
  );
end wb_fmc_250m_4ch_csr;

architecture syn of wb_fmc_250m_4ch_csr is

signal wb_fmc_250m_4ch_csr_adc_ctl_update_clk_dly_dly0 : std_logic      ;
signal wb_fmc_250m_4ch_csr_adc_ctl_update_clk_dly_int : std_logic      ;
signal wb_fmc_250m_4ch_csr_adc_ctl_update_data_dly_dly0 : std_logic      ;
signal wb_fmc_250m_4ch_csr_adc_ctl_update_data_dly_int : std_logic      ;
signal wb_fmc_250m_4ch_csr_adc_ctl_rst_adcs_int : std_logic      ;
signal wb_fmc_250m_4ch_csr_adc_ctl_rst_adcs_int_delay : std_logic      ;
signal wb_fmc_250m_4ch_csr_adc_ctl_rst_adcs_sync0 : std_logic      ;
signal wb_fmc_250m_4ch_csr_adc_ctl_rst_adcs_sync1 : std_logic      ;
signal wb_fmc_250m_4ch_csr_adc_ctl_rst_adcs_sync2 : std_logic      ;
signal wb_fmc_250m_4ch_csr_adc_ctl_rst_div_adcs_int : std_logic      ;
signal wb_fmc_250m_4ch_csr_adc_ctl_rst_div_adcs_int_delay : std_logic      ;
signal wb_fmc_250m_4ch_csr_adc_ctl_rst_div_adcs_sync0 : std_logic      ;
signal wb_fmc_250m_4ch_csr_adc_ctl_rst_div_adcs_sync1 : std_logic      ;
signal wb_fmc_250m_4ch_csr_adc_ctl_rst_div_adcs_sync2 : std_logic      ;
signal wb_fmc_250m_4ch_csr_adc_ctl_sleep_adcs_int : std_logic      ;
signal wb_fmc_250m_4ch_csr_adc_ctl_sleep_adcs_sync0 : std_logic      ;
signal wb_fmc_250m_4ch_csr_adc_ctl_sleep_adcs_sync1 : std_logic      ;
signal wb_fmc_250m_4ch_csr_ch0_sta_val_int      : std_logic_vector(15 downto 0);
signal wb_fmc_250m_4ch_csr_ch0_sta_val_lwb      : std_logic      ;
signal wb_fmc_250m_4ch_csr_ch0_sta_val_lwb_delay : std_logic      ;
signal wb_fmc_250m_4ch_csr_ch0_sta_val_lwb_in_progress : std_logic      ;
signal wb_fmc_250m_4ch_csr_ch0_sta_val_lwb_s0   : std_logic      ;
signal wb_fmc_250m_4ch_csr_ch0_sta_val_lwb_s1   : std_logic      ;
signal wb_fmc_250m_4ch_csr_ch0_sta_val_lwb_s2   : std_logic      ;
signal wb_fmc_250m_4ch_csr_ch0_fn_dly_inc_clk_chain_dly_dly0 : std_logic      ;
signal wb_fmc_250m_4ch_csr_ch0_fn_dly_inc_clk_chain_dly_int : std_logic      ;
signal wb_fmc_250m_4ch_csr_ch0_fn_dly_dec_clk_chain_dly_dly0 : std_logic      ;
signal wb_fmc_250m_4ch_csr_ch0_fn_dly_dec_clk_chain_dly_int : std_logic      ;
signal wb_fmc_250m_4ch_csr_ch0_fn_dly_reserved_clk_incdec_dly_int : std_logic_vector(5 downto 0);
signal wb_fmc_250m_4ch_csr_ch0_fn_dly_inc_data_chain_dly_dly0 : std_logic      ;
signal wb_fmc_250m_4ch_csr_ch0_fn_dly_inc_data_chain_dly_int : std_logic      ;
signal wb_fmc_250m_4ch_csr_ch0_fn_dly_dec_data_chain_dly_dly0 : std_logic      ;
signal wb_fmc_250m_4ch_csr_ch0_fn_dly_dec_data_chain_dly_int : std_logic      ;
signal wb_fmc_250m_4ch_csr_ch0_fn_dly_reserved_data_incdec_dly_int : std_logic_vector(5 downto 0);
signal wb_fmc_250m_4ch_csr_ch0_fn_sel_line_int  : std_logic_vector(16 downto 0);
signal wb_fmc_250m_4ch_csr_ch0_cs_dly_fe_dly_int : std_logic_vector(1 downto 0);
signal wb_fmc_250m_4ch_csr_ch0_cs_dly_fe_dly_swb : std_logic      ;
signal wb_fmc_250m_4ch_csr_ch0_cs_dly_fe_dly_swb_delay : std_logic      ;
signal wb_fmc_250m_4ch_csr_ch0_cs_dly_fe_dly_swb_s0 : std_logic      ;
signal wb_fmc_250m_4ch_csr_ch0_cs_dly_fe_dly_swb_s1 : std_logic      ;
signal wb_fmc_250m_4ch_csr_ch0_cs_dly_fe_dly_swb_s2 : std_logic      ;
signal wb_fmc_250m_4ch_csr_ch0_cs_dly_reserved_fe_dly_int : std_logic_vector(5 downto 0);
signal wb_fmc_250m_4ch_csr_ch0_cs_dly_rg_dly_int : std_logic_vector(1 downto 0);
signal wb_fmc_250m_4ch_csr_ch0_cs_dly_rg_dly_swb : std_logic      ;
signal wb_fmc_250m_4ch_csr_ch0_cs_dly_rg_dly_swb_delay : std_logic      ;
signal wb_fmc_250m_4ch_csr_ch0_cs_dly_rg_dly_swb_s0 : std_logic      ;
signal wb_fmc_250m_4ch_csr_ch0_cs_dly_rg_dly_swb_s1 : std_logic      ;
signal wb_fmc_250m_4ch_csr_ch0_cs_dly_rg_dly_swb_s2 : std_logic      ;
signal wb_fmc_250m_4ch_csr_ch0_cs_dly_reserved_rg_dly_int : std_logic_vector(21 downto 0);
signal wb_fmc_250m_4ch_csr_ch1_sta_val_int      : std_logic_vector(15 downto 0);
signal wb_fmc_250m_4ch_csr_ch1_sta_val_lwb      : std_logic      ;
signal wb_fmc_250m_4ch_csr_ch1_sta_val_lwb_delay : std_logic      ;
signal wb_fmc_250m_4ch_csr_ch1_sta_val_lwb_in_progress : std_logic      ;
signal wb_fmc_250m_4ch_csr_ch1_sta_val_lwb_s0   : std_logic      ;
signal wb_fmc_250m_4ch_csr_ch1_sta_val_lwb_s1   : std_logic      ;
signal wb_fmc_250m_4ch_csr_ch1_sta_val_lwb_s2   : std_logic      ;
signal wb_fmc_250m_4ch_csr_ch1_fn_dly_inc_clk_chain_dly_dly0 : std_logic      ;
signal wb_fmc_250m_4ch_csr_ch1_fn_dly_inc_clk_chain_dly_int : std_logic      ;
signal wb_fmc_250m_4ch_csr_ch1_fn_dly_dec_clk_chain_dly_dly0 : std_logic      ;
signal wb_fmc_250m_4ch_csr_ch1_fn_dly_dec_clk_chain_dly_int : std_logic      ;
signal wb_fmc_250m_4ch_csr_ch1_fn_dly_reserved_clk_incdec_dly_int : std_logic_vector(5 downto 0);
signal wb_fmc_250m_4ch_csr_ch1_fn_dly_inc_data_chain_dly_dly0 : std_logic      ;
signal wb_fmc_250m_4ch_csr_ch1_fn_dly_inc_data_chain_dly_int : std_logic      ;
signal wb_fmc_250m_4ch_csr_ch1_fn_dly_dec_data_chain_dly_dly0 : std_logic      ;
signal wb_fmc_250m_4ch_csr_ch1_fn_dly_dec_data_chain_dly_int : std_logic      ;
signal wb_fmc_250m_4ch_csr_ch1_fn_dly_reserved_data_incdec_dly_int : std_logic_vector(5 downto 0);
signal wb_fmc_250m_4ch_csr_ch1_fn_sel_line_int  : std_logic_vector(16 downto 0);
signal wb_fmc_250m_4ch_csr_ch1_cs_dly_fe_dly_int : std_logic_vector(1 downto 0);
signal wb_fmc_250m_4ch_csr_ch1_cs_dly_fe_dly_swb : std_logic      ;
signal wb_fmc_250m_4ch_csr_ch1_cs_dly_fe_dly_swb_delay : std_logic      ;
signal wb_fmc_250m_4ch_csr_ch1_cs_dly_fe_dly_swb_s0 : std_logic      ;
signal wb_fmc_250m_4ch_csr_ch1_cs_dly_fe_dly_swb_s1 : std_logic      ;
signal wb_fmc_250m_4ch_csr_ch1_cs_dly_fe_dly_swb_s2 : std_logic      ;
signal wb_fmc_250m_4ch_csr_ch1_cs_dly_reserved_fe_dly_int : std_logic_vector(5 downto 0);
signal wb_fmc_250m_4ch_csr_ch1_cs_dly_rg_dly_int : std_logic_vector(1 downto 0);
signal wb_fmc_250m_4ch_csr_ch1_cs_dly_rg_dly_swb : std_logic      ;
signal wb_fmc_250m_4ch_csr_ch1_cs_dly_rg_dly_swb_delay : std_logic      ;
signal wb_fmc_250m_4ch_csr_ch1_cs_dly_rg_dly_swb_s0 : std_logic      ;
signal wb_fmc_250m_4ch_csr_ch1_cs_dly_rg_dly_swb_s1 : std_logic      ;
signal wb_fmc_250m_4ch_csr_ch1_cs_dly_rg_dly_swb_s2 : std_logic      ;
signal wb_fmc_250m_4ch_csr_ch1_cs_dly_reserved_rg_dly_int : std_logic_vector(21 downto 0);
signal wb_fmc_250m_4ch_csr_ch2_sta_val_int      : std_logic_vector(15 downto 0);
signal wb_fmc_250m_4ch_csr_ch2_sta_val_lwb      : std_logic      ;
signal wb_fmc_250m_4ch_csr_ch2_sta_val_lwb_delay : std_logic      ;
signal wb_fmc_250m_4ch_csr_ch2_sta_val_lwb_in_progress : std_logic      ;
signal wb_fmc_250m_4ch_csr_ch2_sta_val_lwb_s0   : std_logic      ;
signal wb_fmc_250m_4ch_csr_ch2_sta_val_lwb_s1   : std_logic      ;
signal wb_fmc_250m_4ch_csr_ch2_sta_val_lwb_s2   : std_logic      ;
signal wb_fmc_250m_4ch_csr_ch2_fn_dly_inc_clk_chain_dly_dly0 : std_logic      ;
signal wb_fmc_250m_4ch_csr_ch2_fn_dly_inc_clk_chain_dly_int : std_logic      ;
signal wb_fmc_250m_4ch_csr_ch2_fn_dly_dec_clk_chain_dly_dly0 : std_logic      ;
signal wb_fmc_250m_4ch_csr_ch2_fn_dly_dec_clk_chain_dly_int : std_logic      ;
signal wb_fmc_250m_4ch_csr_ch2_fn_dly_reserved_clk_incdec_dly_int : std_logic_vector(5 downto 0);
signal wb_fmc_250m_4ch_csr_ch2_fn_dly_inc_data_chain_dly_dly0 : std_logic      ;
signal wb_fmc_250m_4ch_csr_ch2_fn_dly_inc_data_chain_dly_int : std_logic      ;
signal wb_fmc_250m_4ch_csr_ch2_fn_dly_dec_data_chain_dly_dly0 : std_logic      ;
signal wb_fmc_250m_4ch_csr_ch2_fn_dly_dec_data_chain_dly_int : std_logic      ;
signal wb_fmc_250m_4ch_csr_ch2_fn_dly_reserved_data_incdec_dly_int : std_logic_vector(5 downto 0);
signal wb_fmc_250m_4ch_csr_ch2_fn_sel_line_int  : std_logic_vector(16 downto 0);
signal wb_fmc_250m_4ch_csr_ch2_cs_dly_fe_dly_int : std_logic_vector(1 downto 0);
signal wb_fmc_250m_4ch_csr_ch2_cs_dly_fe_dly_swb : std_logic      ;
signal wb_fmc_250m_4ch_csr_ch2_cs_dly_fe_dly_swb_delay : std_logic      ;
signal wb_fmc_250m_4ch_csr_ch2_cs_dly_fe_dly_swb_s0 : std_logic      ;
signal wb_fmc_250m_4ch_csr_ch2_cs_dly_fe_dly_swb_s1 : std_logic      ;
signal wb_fmc_250m_4ch_csr_ch2_cs_dly_fe_dly_swb_s2 : std_logic      ;
signal wb_fmc_250m_4ch_csr_ch2_cs_dly_reserved_fe_dly_int : std_logic_vector(5 downto 0);
signal wb_fmc_250m_4ch_csr_ch2_cs_dly_rg_dly_int : std_logic_vector(1 downto 0);
signal wb_fmc_250m_4ch_csr_ch2_cs_dly_rg_dly_swb : std_logic      ;
signal wb_fmc_250m_4ch_csr_ch2_cs_dly_rg_dly_swb_delay : std_logic      ;
signal wb_fmc_250m_4ch_csr_ch2_cs_dly_rg_dly_swb_s0 : std_logic      ;
signal wb_fmc_250m_4ch_csr_ch2_cs_dly_rg_dly_swb_s1 : std_logic      ;
signal wb_fmc_250m_4ch_csr_ch2_cs_dly_rg_dly_swb_s2 : std_logic      ;
signal wb_fmc_250m_4ch_csr_ch2_cs_dly_reserved_rg_dly_int : std_logic_vector(21 downto 0);
signal wb_fmc_250m_4ch_csr_ch3_sta_val_int      : std_logic_vector(15 downto 0);
signal wb_fmc_250m_4ch_csr_ch3_sta_val_lwb      : std_logic      ;
signal wb_fmc_250m_4ch_csr_ch3_sta_val_lwb_delay : std_logic      ;
signal wb_fmc_250m_4ch_csr_ch3_sta_val_lwb_in_progress : std_logic      ;
signal wb_fmc_250m_4ch_csr_ch3_sta_val_lwb_s0   : std_logic      ;
signal wb_fmc_250m_4ch_csr_ch3_sta_val_lwb_s1   : std_logic      ;
signal wb_fmc_250m_4ch_csr_ch3_sta_val_lwb_s2   : std_logic      ;
signal wb_fmc_250m_4ch_csr_ch3_fn_dly_inc_clk_chain_dly_dly0 : std_logic      ;
signal wb_fmc_250m_4ch_csr_ch3_fn_dly_inc_clk_chain_dly_int : std_logic      ;
signal wb_fmc_250m_4ch_csr_ch3_fn_dly_dec_clk_chain_dly_dly0 : std_logic      ;
signal wb_fmc_250m_4ch_csr_ch3_fn_dly_dec_clk_chain_dly_int : std_logic      ;
signal wb_fmc_250m_4ch_csr_ch3_fn_dly_reserved_clk_incdec_dly_int : std_logic_vector(5 downto 0);
signal wb_fmc_250m_4ch_csr_ch3_fn_dly_inc_data_chain_dly_dly0 : std_logic      ;
signal wb_fmc_250m_4ch_csr_ch3_fn_dly_inc_data_chain_dly_int : std_logic      ;
signal wb_fmc_250m_4ch_csr_ch3_fn_dly_dec_data_chain_dly_dly0 : std_logic      ;
signal wb_fmc_250m_4ch_csr_ch3_fn_dly_dec_data_chain_dly_int : std_logic      ;
signal wb_fmc_250m_4ch_csr_ch3_fn_dly_reserved_data_incdec_dly_int : std_logic_vector(5 downto 0);
signal wb_fmc_250m_4ch_csr_ch3_fn_sel_line_int  : std_logic_vector(16 downto 0);
signal wb_fmc_250m_4ch_csr_ch3_cs_dly_fe_dly_int : std_logic_vector(1 downto 0);
signal wb_fmc_250m_4ch_csr_ch3_cs_dly_fe_dly_swb : std_logic      ;
signal wb_fmc_250m_4ch_csr_ch3_cs_dly_fe_dly_swb_delay : std_logic      ;
signal wb_fmc_250m_4ch_csr_ch3_cs_dly_fe_dly_swb_s0 : std_logic      ;
signal wb_fmc_250m_4ch_csr_ch3_cs_dly_fe_dly_swb_s1 : std_logic      ;
signal wb_fmc_250m_4ch_csr_ch3_cs_dly_fe_dly_swb_s2 : std_logic      ;
signal wb_fmc_250m_4ch_csr_ch3_cs_dly_reserved_fe_dly_int : std_logic_vector(5 downto 0);
signal wb_fmc_250m_4ch_csr_ch3_cs_dly_rg_dly_int : std_logic_vector(1 downto 0);
signal wb_fmc_250m_4ch_csr_ch3_cs_dly_rg_dly_swb : std_logic      ;
signal wb_fmc_250m_4ch_csr_ch3_cs_dly_rg_dly_swb_delay : std_logic      ;
signal wb_fmc_250m_4ch_csr_ch3_cs_dly_rg_dly_swb_s0 : std_logic      ;
signal wb_fmc_250m_4ch_csr_ch3_cs_dly_rg_dly_swb_s1 : std_logic      ;
signal wb_fmc_250m_4ch_csr_ch3_cs_dly_rg_dly_swb_s2 : std_logic      ;
signal wb_fmc_250m_4ch_csr_ch3_cs_dly_reserved_rg_dly_int : std_logic_vector(21 downto 0);
signal ack_sreg                                 : std_logic_vector(9 downto 0);
signal rddata_reg                               : std_logic_vector(31 downto 0);
signal wrdata_reg                               : std_logic_vector(31 downto 0);
signal bwsel_reg                                : std_logic_vector(3 downto 0);
signal rwaddr_reg                               : std_logic_vector(4 downto 0);
signal ack_in_progress                          : std_logic      ;
signal wr_int                                   : std_logic      ;
signal rd_int                                   : std_logic      ;
signal allones                                  : std_logic_vector(31 downto 0);
signal allzeros                                 : std_logic_vector(31 downto 0);

begin
-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
  wrdata_reg <= wb_dat_i;
  bwsel_reg <= wb_sel_i;
  rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
  wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
  allones <= (others => '1');
  allzeros <= (others => '0');
-- 
-- Main register bank access process.
  process (clk_sys_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      ack_sreg <= "0000000000";
      ack_in_progress <= '0';
      rddata_reg <= "00000000000000000000000000000000";
      wb_fmc_250m_4ch_csr_adc_ctl_update_clk_dly_int <= '0';
      wb_fmc_250m_4ch_csr_adc_ctl_update_data_dly_int <= '0';
      wb_fmc_250m_4ch_csr_adc_ctl_rst_adcs_int <= '0';
      wb_fmc_250m_4ch_csr_adc_ctl_rst_adcs_int_delay <= '0';
      wb_fmc_250m_4ch_csr_adc_ctl_rst_div_adcs_int <= '0';
      wb_fmc_250m_4ch_csr_adc_ctl_rst_div_adcs_int_delay <= '0';
      wb_fmc_250m_4ch_csr_adc_ctl_sleep_adcs_int <= '0';
      wb_fmc_250m_4ch_csr_ch0_sta_val_lwb <= '0';
      wb_fmc_250m_4ch_csr_ch0_sta_val_lwb_delay <= '0';
      wb_fmc_250m_4ch_csr_ch0_sta_val_lwb_in_progress <= '0';
      regs_o.ch0_fn_dly_clk_chain_dly_load_o <= '0';
      regs_o.ch0_fn_dly_data_chain_dly_load_o <= '0';
      wb_fmc_250m_4ch_csr_ch0_fn_dly_inc_clk_chain_dly_int <= '0';
      wb_fmc_250m_4ch_csr_ch0_fn_dly_dec_clk_chain_dly_int <= '0';
      wb_fmc_250m_4ch_csr_ch0_fn_dly_reserved_clk_incdec_dly_int <= "000000";
      wb_fmc_250m_4ch_csr_ch0_fn_dly_inc_data_chain_dly_int <= '0';
      wb_fmc_250m_4ch_csr_ch0_fn_dly_dec_data_chain_dly_int <= '0';
      wb_fmc_250m_4ch_csr_ch0_fn_dly_reserved_data_incdec_dly_int <= "000000";
      wb_fmc_250m_4ch_csr_ch0_fn_sel_line_int <= "00000000000000000";
      wb_fmc_250m_4ch_csr_ch0_cs_dly_fe_dly_int <= "00";
      wb_fmc_250m_4ch_csr_ch0_cs_dly_fe_dly_swb <= '0';
      wb_fmc_250m_4ch_csr_ch0_cs_dly_fe_dly_swb_delay <= '0';
      wb_fmc_250m_4ch_csr_ch0_cs_dly_reserved_fe_dly_int <= "000000";
      wb_fmc_250m_4ch_csr_ch0_cs_dly_rg_dly_int <= "00";
      wb_fmc_250m_4ch_csr_ch0_cs_dly_rg_dly_swb <= '0';
      wb_fmc_250m_4ch_csr_ch0_cs_dly_rg_dly_swb_delay <= '0';
      wb_fmc_250m_4ch_csr_ch0_cs_dly_reserved_rg_dly_int <= "0000000000000000000000";
      wb_fmc_250m_4ch_csr_ch1_sta_val_lwb <= '0';
      wb_fmc_250m_4ch_csr_ch1_sta_val_lwb_delay <= '0';
      wb_fmc_250m_4ch_csr_ch1_sta_val_lwb_in_progress <= '0';
      regs_o.ch1_fn_dly_clk_chain_dly_load_o <= '0';
      regs_o.ch1_fn_dly_data_chain_dly_load_o <= '0';
      wb_fmc_250m_4ch_csr_ch1_fn_dly_inc_clk_chain_dly_int <= '0';
      wb_fmc_250m_4ch_csr_ch1_fn_dly_dec_clk_chain_dly_int <= '0';
      wb_fmc_250m_4ch_csr_ch1_fn_dly_reserved_clk_incdec_dly_int <= "000000";
      wb_fmc_250m_4ch_csr_ch1_fn_dly_inc_data_chain_dly_int <= '0';
      wb_fmc_250m_4ch_csr_ch1_fn_dly_dec_data_chain_dly_int <= '0';
      wb_fmc_250m_4ch_csr_ch1_fn_dly_reserved_data_incdec_dly_int <= "000000";
      wb_fmc_250m_4ch_csr_ch1_fn_sel_line_int <= "00000000000000000";
      wb_fmc_250m_4ch_csr_ch1_cs_dly_fe_dly_int <= "00";
      wb_fmc_250m_4ch_csr_ch1_cs_dly_fe_dly_swb <= '0';
      wb_fmc_250m_4ch_csr_ch1_cs_dly_fe_dly_swb_delay <= '0';
      wb_fmc_250m_4ch_csr_ch1_cs_dly_reserved_fe_dly_int <= "000000";
      wb_fmc_250m_4ch_csr_ch1_cs_dly_rg_dly_int <= "00";
      wb_fmc_250m_4ch_csr_ch1_cs_dly_rg_dly_swb <= '0';
      wb_fmc_250m_4ch_csr_ch1_cs_dly_rg_dly_swb_delay <= '0';
      wb_fmc_250m_4ch_csr_ch1_cs_dly_reserved_rg_dly_int <= "0000000000000000000000";
      wb_fmc_250m_4ch_csr_ch2_sta_val_lwb <= '0';
      wb_fmc_250m_4ch_csr_ch2_sta_val_lwb_delay <= '0';
      wb_fmc_250m_4ch_csr_ch2_sta_val_lwb_in_progress <= '0';
      regs_o.ch2_fn_dly_clk_chain_dly_load_o <= '0';
      regs_o.ch2_fn_dly_data_chain_dly_load_o <= '0';
      wb_fmc_250m_4ch_csr_ch2_fn_dly_inc_clk_chain_dly_int <= '0';
      wb_fmc_250m_4ch_csr_ch2_fn_dly_dec_clk_chain_dly_int <= '0';
      wb_fmc_250m_4ch_csr_ch2_fn_dly_reserved_clk_incdec_dly_int <= "000000";
      wb_fmc_250m_4ch_csr_ch2_fn_dly_inc_data_chain_dly_int <= '0';
      wb_fmc_250m_4ch_csr_ch2_fn_dly_dec_data_chain_dly_int <= '0';
      wb_fmc_250m_4ch_csr_ch2_fn_dly_reserved_data_incdec_dly_int <= "000000";
      wb_fmc_250m_4ch_csr_ch2_fn_sel_line_int <= "00000000000000000";
      wb_fmc_250m_4ch_csr_ch2_cs_dly_fe_dly_int <= "00";
      wb_fmc_250m_4ch_csr_ch2_cs_dly_fe_dly_swb <= '0';
      wb_fmc_250m_4ch_csr_ch2_cs_dly_fe_dly_swb_delay <= '0';
      wb_fmc_250m_4ch_csr_ch2_cs_dly_reserved_fe_dly_int <= "000000";
      wb_fmc_250m_4ch_csr_ch2_cs_dly_rg_dly_int <= "00";
      wb_fmc_250m_4ch_csr_ch2_cs_dly_rg_dly_swb <= '0';
      wb_fmc_250m_4ch_csr_ch2_cs_dly_rg_dly_swb_delay <= '0';
      wb_fmc_250m_4ch_csr_ch2_cs_dly_reserved_rg_dly_int <= "0000000000000000000000";
      wb_fmc_250m_4ch_csr_ch3_sta_val_lwb <= '0';
      wb_fmc_250m_4ch_csr_ch3_sta_val_lwb_delay <= '0';
      wb_fmc_250m_4ch_csr_ch3_sta_val_lwb_in_progress <= '0';
      regs_o.ch3_fn_dly_clk_chain_dly_load_o <= '0';
      regs_o.ch3_fn_dly_data_chain_dly_load_o <= '0';
      wb_fmc_250m_4ch_csr_ch3_fn_dly_inc_clk_chain_dly_int <= '0';
      wb_fmc_250m_4ch_csr_ch3_fn_dly_dec_clk_chain_dly_int <= '0';
      wb_fmc_250m_4ch_csr_ch3_fn_dly_reserved_clk_incdec_dly_int <= "000000";
      wb_fmc_250m_4ch_csr_ch3_fn_dly_inc_data_chain_dly_int <= '0';
      wb_fmc_250m_4ch_csr_ch3_fn_dly_dec_data_chain_dly_int <= '0';
      wb_fmc_250m_4ch_csr_ch3_fn_dly_reserved_data_incdec_dly_int <= "000000";
      wb_fmc_250m_4ch_csr_ch3_fn_sel_line_int <= "00000000000000000";
      wb_fmc_250m_4ch_csr_ch3_cs_dly_fe_dly_int <= "00";
      wb_fmc_250m_4ch_csr_ch3_cs_dly_fe_dly_swb <= '0';
      wb_fmc_250m_4ch_csr_ch3_cs_dly_fe_dly_swb_delay <= '0';
      wb_fmc_250m_4ch_csr_ch3_cs_dly_reserved_fe_dly_int <= "000000";
      wb_fmc_250m_4ch_csr_ch3_cs_dly_rg_dly_int <= "00";
      wb_fmc_250m_4ch_csr_ch3_cs_dly_rg_dly_swb <= '0';
      wb_fmc_250m_4ch_csr_ch3_cs_dly_rg_dly_swb_delay <= '0';
      wb_fmc_250m_4ch_csr_ch3_cs_dly_reserved_rg_dly_int <= "0000000000000000000000";
    elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
      ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
      ack_sreg(9) <= '0';
      if (ack_in_progress = '1') then
        if (ack_sreg(0) = '1') then
          wb_fmc_250m_4ch_csr_adc_ctl_update_clk_dly_int <= '0';
          wb_fmc_250m_4ch_csr_adc_ctl_update_data_dly_int <= '0';
          regs_o.ch0_fn_dly_clk_chain_dly_load_o <= '0';
          regs_o.ch0_fn_dly_data_chain_dly_load_o <= '0';
          wb_fmc_250m_4ch_csr_ch0_fn_dly_inc_clk_chain_dly_int <= '0';
          wb_fmc_250m_4ch_csr_ch0_fn_dly_dec_clk_chain_dly_int <= '0';
          wb_fmc_250m_4ch_csr_ch0_fn_dly_inc_data_chain_dly_int <= '0';
          wb_fmc_250m_4ch_csr_ch0_fn_dly_dec_data_chain_dly_int <= '0';
          regs_o.ch1_fn_dly_clk_chain_dly_load_o <= '0';
          regs_o.ch1_fn_dly_data_chain_dly_load_o <= '0';
          wb_fmc_250m_4ch_csr_ch1_fn_dly_inc_clk_chain_dly_int <= '0';
          wb_fmc_250m_4ch_csr_ch1_fn_dly_dec_clk_chain_dly_int <= '0';
          wb_fmc_250m_4ch_csr_ch1_fn_dly_inc_data_chain_dly_int <= '0';
          wb_fmc_250m_4ch_csr_ch1_fn_dly_dec_data_chain_dly_int <= '0';
          regs_o.ch2_fn_dly_clk_chain_dly_load_o <= '0';
          regs_o.ch2_fn_dly_data_chain_dly_load_o <= '0';
          wb_fmc_250m_4ch_csr_ch2_fn_dly_inc_clk_chain_dly_int <= '0';
          wb_fmc_250m_4ch_csr_ch2_fn_dly_dec_clk_chain_dly_int <= '0';
          wb_fmc_250m_4ch_csr_ch2_fn_dly_inc_data_chain_dly_int <= '0';
          wb_fmc_250m_4ch_csr_ch2_fn_dly_dec_data_chain_dly_int <= '0';
          regs_o.ch3_fn_dly_clk_chain_dly_load_o <= '0';
          regs_o.ch3_fn_dly_data_chain_dly_load_o <= '0';
          wb_fmc_250m_4ch_csr_ch3_fn_dly_inc_clk_chain_dly_int <= '0';
          wb_fmc_250m_4ch_csr_ch3_fn_dly_dec_clk_chain_dly_int <= '0';
          wb_fmc_250m_4ch_csr_ch3_fn_dly_inc_data_chain_dly_int <= '0';
          wb_fmc_250m_4ch_csr_ch3_fn_dly_dec_data_chain_dly_int <= '0';
          ack_in_progress <= '0';
        else
          wb_fmc_250m_4ch_csr_adc_ctl_rst_adcs_int <= wb_fmc_250m_4ch_csr_adc_ctl_rst_adcs_int_delay;
          wb_fmc_250m_4ch_csr_adc_ctl_rst_adcs_int_delay <= '0';
          wb_fmc_250m_4ch_csr_adc_ctl_rst_div_adcs_int <= wb_fmc_250m_4ch_csr_adc_ctl_rst_div_adcs_int_delay;
          wb_fmc_250m_4ch_csr_adc_ctl_rst_div_adcs_int_delay <= '0';
          wb_fmc_250m_4ch_csr_ch0_sta_val_lwb <= wb_fmc_250m_4ch_csr_ch0_sta_val_lwb_delay;
          wb_fmc_250m_4ch_csr_ch0_sta_val_lwb_delay <= '0';
          if ((ack_sreg(1) = '1') and (wb_fmc_250m_4ch_csr_ch0_sta_val_lwb_in_progress = '1')) then
            rddata_reg(15 downto 0) <= wb_fmc_250m_4ch_csr_ch0_sta_val_int;
            wb_fmc_250m_4ch_csr_ch0_sta_val_lwb_in_progress <= '0';
          end if;
          regs_o.ch0_fn_dly_clk_chain_dly_load_o <= '0';
          regs_o.ch0_fn_dly_data_chain_dly_load_o <= '0';
          wb_fmc_250m_4ch_csr_ch0_cs_dly_fe_dly_swb <= wb_fmc_250m_4ch_csr_ch0_cs_dly_fe_dly_swb_delay;
          wb_fmc_250m_4ch_csr_ch0_cs_dly_fe_dly_swb_delay <= '0';
          wb_fmc_250m_4ch_csr_ch0_cs_dly_rg_dly_swb <= wb_fmc_250m_4ch_csr_ch0_cs_dly_rg_dly_swb_delay;
          wb_fmc_250m_4ch_csr_ch0_cs_dly_rg_dly_swb_delay <= '0';
          wb_fmc_250m_4ch_csr_ch1_sta_val_lwb <= wb_fmc_250m_4ch_csr_ch1_sta_val_lwb_delay;
          wb_fmc_250m_4ch_csr_ch1_sta_val_lwb_delay <= '0';
          if ((ack_sreg(1) = '1') and (wb_fmc_250m_4ch_csr_ch1_sta_val_lwb_in_progress = '1')) then
            rddata_reg(15 downto 0) <= wb_fmc_250m_4ch_csr_ch1_sta_val_int;
            wb_fmc_250m_4ch_csr_ch1_sta_val_lwb_in_progress <= '0';
          end if;
          regs_o.ch1_fn_dly_clk_chain_dly_load_o <= '0';
          regs_o.ch1_fn_dly_data_chain_dly_load_o <= '0';
          wb_fmc_250m_4ch_csr_ch1_cs_dly_fe_dly_swb <= wb_fmc_250m_4ch_csr_ch1_cs_dly_fe_dly_swb_delay;
          wb_fmc_250m_4ch_csr_ch1_cs_dly_fe_dly_swb_delay <= '0';
          wb_fmc_250m_4ch_csr_ch1_cs_dly_rg_dly_swb <= wb_fmc_250m_4ch_csr_ch1_cs_dly_rg_dly_swb_delay;
          wb_fmc_250m_4ch_csr_ch1_cs_dly_rg_dly_swb_delay <= '0';
          wb_fmc_250m_4ch_csr_ch2_sta_val_lwb <= wb_fmc_250m_4ch_csr_ch2_sta_val_lwb_delay;
          wb_fmc_250m_4ch_csr_ch2_sta_val_lwb_delay <= '0';
          if ((ack_sreg(1) = '1') and (wb_fmc_250m_4ch_csr_ch2_sta_val_lwb_in_progress = '1')) then
            rddata_reg(15 downto 0) <= wb_fmc_250m_4ch_csr_ch2_sta_val_int;
            wb_fmc_250m_4ch_csr_ch2_sta_val_lwb_in_progress <= '0';
          end if;
          regs_o.ch2_fn_dly_clk_chain_dly_load_o <= '0';
          regs_o.ch2_fn_dly_data_chain_dly_load_o <= '0';
          wb_fmc_250m_4ch_csr_ch2_cs_dly_fe_dly_swb <= wb_fmc_250m_4ch_csr_ch2_cs_dly_fe_dly_swb_delay;
          wb_fmc_250m_4ch_csr_ch2_cs_dly_fe_dly_swb_delay <= '0';
          wb_fmc_250m_4ch_csr_ch2_cs_dly_rg_dly_swb <= wb_fmc_250m_4ch_csr_ch2_cs_dly_rg_dly_swb_delay;
          wb_fmc_250m_4ch_csr_ch2_cs_dly_rg_dly_swb_delay <= '0';
          wb_fmc_250m_4ch_csr_ch3_sta_val_lwb <= wb_fmc_250m_4ch_csr_ch3_sta_val_lwb_delay;
          wb_fmc_250m_4ch_csr_ch3_sta_val_lwb_delay <= '0';
          if ((ack_sreg(1) = '1') and (wb_fmc_250m_4ch_csr_ch3_sta_val_lwb_in_progress = '1')) then
            rddata_reg(15 downto 0) <= wb_fmc_250m_4ch_csr_ch3_sta_val_int;
            wb_fmc_250m_4ch_csr_ch3_sta_val_lwb_in_progress <= '0';
          end if;
          regs_o.ch3_fn_dly_clk_chain_dly_load_o <= '0';
          regs_o.ch3_fn_dly_data_chain_dly_load_o <= '0';
          wb_fmc_250m_4ch_csr_ch3_cs_dly_fe_dly_swb <= wb_fmc_250m_4ch_csr_ch3_cs_dly_fe_dly_swb_delay;
          wb_fmc_250m_4ch_csr_ch3_cs_dly_fe_dly_swb_delay <= '0';
          wb_fmc_250m_4ch_csr_ch3_cs_dly_rg_dly_swb <= wb_fmc_250m_4ch_csr_ch3_cs_dly_rg_dly_swb_delay;
          wb_fmc_250m_4ch_csr_ch3_cs_dly_rg_dly_swb_delay <= '0';
        end if;
      else
        if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
          case rwaddr_reg(4 downto 0) is
          when "00000" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(3 downto 0) <= regs_i.adc_sta_clk_chains_i;
            rddata_reg(7 downto 4) <= regs_i.adc_sta_reserved_clk_chains_i;
            rddata_reg(11 downto 8) <= regs_i.adc_sta_data_chains_i;
            rddata_reg(15 downto 12) <= regs_i.adc_sta_reserved_data_chains_i;
            rddata_reg(31 downto 16) <= regs_i.adc_sta_adc_pkt_size_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "00001" => 
            if (wb_we_i = '1') then
              wb_fmc_250m_4ch_csr_adc_ctl_update_clk_dly_int <= wrdata_reg(0);
              wb_fmc_250m_4ch_csr_adc_ctl_update_data_dly_int <= wrdata_reg(1);
              wb_fmc_250m_4ch_csr_adc_ctl_rst_adcs_int <= wrdata_reg(2);
              wb_fmc_250m_4ch_csr_adc_ctl_rst_adcs_int_delay <= wrdata_reg(2);
              wb_fmc_250m_4ch_csr_adc_ctl_rst_div_adcs_int <= wrdata_reg(3);
              wb_fmc_250m_4ch_csr_adc_ctl_rst_div_adcs_int_delay <= wrdata_reg(3);
              wb_fmc_250m_4ch_csr_adc_ctl_sleep_adcs_int <= wrdata_reg(4);
            end if;
            rddata_reg(0) <= '0';
            rddata_reg(1) <= '0';
            rddata_reg(2) <= '0';
            rddata_reg(3) <= '0';
            rddata_reg(4) <= wb_fmc_250m_4ch_csr_adc_ctl_sleep_adcs_int;
            rddata_reg(31 downto 5) <= regs_i.adc_ctl_reserved_i;
            ack_sreg(4) <= '1';
            ack_in_progress <= '1';
          when "00010" => 
            if (wb_we_i = '1') then
            end if;
            if (wb_we_i = '0') then
              wb_fmc_250m_4ch_csr_ch0_sta_val_lwb <= '1';
              wb_fmc_250m_4ch_csr_ch0_sta_val_lwb_delay <= '1';
              wb_fmc_250m_4ch_csr_ch0_sta_val_lwb_in_progress <= '1';
            end if;
            rddata_reg(31 downto 16) <= regs_i.ch0_sta_reserved_i;
            ack_sreg(5) <= '1';
            ack_in_progress <= '1';
          when "00011" => 
            if (wb_we_i = '1') then
              regs_o.ch0_fn_dly_clk_chain_dly_load_o <= '1';
              regs_o.ch0_fn_dly_data_chain_dly_load_o <= '1';
              wb_fmc_250m_4ch_csr_ch0_fn_dly_inc_clk_chain_dly_int <= wrdata_reg(16);
              wb_fmc_250m_4ch_csr_ch0_fn_dly_dec_clk_chain_dly_int <= wrdata_reg(17);
              wb_fmc_250m_4ch_csr_ch0_fn_dly_reserved_clk_incdec_dly_int <= wrdata_reg(23 downto 18);
              wb_fmc_250m_4ch_csr_ch0_fn_dly_inc_data_chain_dly_int <= wrdata_reg(24);
              wb_fmc_250m_4ch_csr_ch0_fn_dly_dec_data_chain_dly_int <= wrdata_reg(25);
              wb_fmc_250m_4ch_csr_ch0_fn_dly_reserved_data_incdec_dly_int <= wrdata_reg(31 downto 26);
            end if;
            rddata_reg(4 downto 0) <= regs_i.ch0_fn_dly_clk_chain_dly_i;
            rddata_reg(7 downto 5) <= regs_i.ch0_fn_dly_reserved_clk_chain_dly_i;
            rddata_reg(12 downto 8) <= regs_i.ch0_fn_dly_data_chain_dly_i;
            rddata_reg(15 downto 13) <= regs_i.ch0_fn_dly_reserved_data_chain_dly_i;
            rddata_reg(16) <= '0';
            rddata_reg(17) <= '0';
            rddata_reg(23 downto 18) <= wb_fmc_250m_4ch_csr_ch0_fn_dly_reserved_clk_incdec_dly_int;
            rddata_reg(24) <= '0';
            rddata_reg(25) <= '0';
            rddata_reg(31 downto 26) <= wb_fmc_250m_4ch_csr_ch0_fn_dly_reserved_data_incdec_dly_int;
            ack_sreg(2) <= '1';
            ack_in_progress <= '1';
          when "00100" => 
            if (wb_we_i = '1') then
              wb_fmc_250m_4ch_csr_ch0_fn_sel_line_int <= wrdata_reg(16 downto 0);
            end if;
            rddata_reg(16 downto 0) <= wb_fmc_250m_4ch_csr_ch0_fn_sel_line_int;
            rddata_reg(31 downto 17) <= regs_i.ch0_fn_sel_reserved_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "00101" => 
            if (wb_we_i = '1') then
              wb_fmc_250m_4ch_csr_ch0_cs_dly_fe_dly_int <= wrdata_reg(1 downto 0);
              wb_fmc_250m_4ch_csr_ch0_cs_dly_fe_dly_swb <= '1';
              wb_fmc_250m_4ch_csr_ch0_cs_dly_fe_dly_swb_delay <= '1';
              wb_fmc_250m_4ch_csr_ch0_cs_dly_reserved_fe_dly_int <= wrdata_reg(7 downto 2);
              wb_fmc_250m_4ch_csr_ch0_cs_dly_rg_dly_int <= wrdata_reg(9 downto 8);
              wb_fmc_250m_4ch_csr_ch0_cs_dly_rg_dly_swb <= '1';
              wb_fmc_250m_4ch_csr_ch0_cs_dly_rg_dly_swb_delay <= '1';
              wb_fmc_250m_4ch_csr_ch0_cs_dly_reserved_rg_dly_int <= wrdata_reg(31 downto 10);
            end if;
            rddata_reg(1 downto 0) <= wb_fmc_250m_4ch_csr_ch0_cs_dly_fe_dly_int;
            rddata_reg(7 downto 2) <= wb_fmc_250m_4ch_csr_ch0_cs_dly_reserved_fe_dly_int;
            rddata_reg(9 downto 8) <= wb_fmc_250m_4ch_csr_ch0_cs_dly_rg_dly_int;
            rddata_reg(31 downto 10) <= wb_fmc_250m_4ch_csr_ch0_cs_dly_reserved_rg_dly_int;
            ack_sreg(3) <= '1';
            ack_in_progress <= '1';
          when "00110" => 
            if (wb_we_i = '1') then
            end if;
            if (wb_we_i = '0') then
              wb_fmc_250m_4ch_csr_ch1_sta_val_lwb <= '1';
              wb_fmc_250m_4ch_csr_ch1_sta_val_lwb_delay <= '1';
              wb_fmc_250m_4ch_csr_ch1_sta_val_lwb_in_progress <= '1';
            end if;
            rddata_reg(31 downto 16) <= regs_i.ch1_sta_reserved_i;
            ack_sreg(5) <= '1';
            ack_in_progress <= '1';
          when "00111" => 
            if (wb_we_i = '1') then
              regs_o.ch1_fn_dly_clk_chain_dly_load_o <= '1';
              regs_o.ch1_fn_dly_data_chain_dly_load_o <= '1';
              wb_fmc_250m_4ch_csr_ch1_fn_dly_inc_clk_chain_dly_int <= wrdata_reg(16);
              wb_fmc_250m_4ch_csr_ch1_fn_dly_dec_clk_chain_dly_int <= wrdata_reg(17);
              wb_fmc_250m_4ch_csr_ch1_fn_dly_reserved_clk_incdec_dly_int <= wrdata_reg(23 downto 18);
              wb_fmc_250m_4ch_csr_ch1_fn_dly_inc_data_chain_dly_int <= wrdata_reg(24);
              wb_fmc_250m_4ch_csr_ch1_fn_dly_dec_data_chain_dly_int <= wrdata_reg(25);
              wb_fmc_250m_4ch_csr_ch1_fn_dly_reserved_data_incdec_dly_int <= wrdata_reg(31 downto 26);
            end if;
            rddata_reg(4 downto 0) <= regs_i.ch1_fn_dly_clk_chain_dly_i;
            rddata_reg(7 downto 5) <= regs_i.ch1_fn_dly_reserved_clk_chain_dly_i;
            rddata_reg(12 downto 8) <= regs_i.ch1_fn_dly_data_chain_dly_i;
            rddata_reg(15 downto 13) <= regs_i.ch1_fn_dly_reserved_data_chain_dly_i;
            rddata_reg(16) <= '0';
            rddata_reg(17) <= '0';
            rddata_reg(23 downto 18) <= wb_fmc_250m_4ch_csr_ch1_fn_dly_reserved_clk_incdec_dly_int;
            rddata_reg(24) <= '0';
            rddata_reg(25) <= '0';
            rddata_reg(31 downto 26) <= wb_fmc_250m_4ch_csr_ch1_fn_dly_reserved_data_incdec_dly_int;
            ack_sreg(2) <= '1';
            ack_in_progress <= '1';
          when "01000" => 
            if (wb_we_i = '1') then
              wb_fmc_250m_4ch_csr_ch1_fn_sel_line_int <= wrdata_reg(16 downto 0);
            end if;
            rddata_reg(16 downto 0) <= wb_fmc_250m_4ch_csr_ch1_fn_sel_line_int;
            rddata_reg(31 downto 17) <= regs_i.ch1_fn_sel_reserved_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "01001" => 
            if (wb_we_i = '1') then
              wb_fmc_250m_4ch_csr_ch1_cs_dly_fe_dly_int <= wrdata_reg(1 downto 0);
              wb_fmc_250m_4ch_csr_ch1_cs_dly_fe_dly_swb <= '1';
              wb_fmc_250m_4ch_csr_ch1_cs_dly_fe_dly_swb_delay <= '1';
              wb_fmc_250m_4ch_csr_ch1_cs_dly_reserved_fe_dly_int <= wrdata_reg(7 downto 2);
              wb_fmc_250m_4ch_csr_ch1_cs_dly_rg_dly_int <= wrdata_reg(9 downto 8);
              wb_fmc_250m_4ch_csr_ch1_cs_dly_rg_dly_swb <= '1';
              wb_fmc_250m_4ch_csr_ch1_cs_dly_rg_dly_swb_delay <= '1';
              wb_fmc_250m_4ch_csr_ch1_cs_dly_reserved_rg_dly_int <= wrdata_reg(31 downto 10);
            end if;
            rddata_reg(1 downto 0) <= wb_fmc_250m_4ch_csr_ch1_cs_dly_fe_dly_int;
            rddata_reg(7 downto 2) <= wb_fmc_250m_4ch_csr_ch1_cs_dly_reserved_fe_dly_int;
            rddata_reg(9 downto 8) <= wb_fmc_250m_4ch_csr_ch1_cs_dly_rg_dly_int;
            rddata_reg(31 downto 10) <= wb_fmc_250m_4ch_csr_ch1_cs_dly_reserved_rg_dly_int;
            ack_sreg(3) <= '1';
            ack_in_progress <= '1';
          when "01010" => 
            if (wb_we_i = '1') then
            end if;
            if (wb_we_i = '0') then
              wb_fmc_250m_4ch_csr_ch2_sta_val_lwb <= '1';
              wb_fmc_250m_4ch_csr_ch2_sta_val_lwb_delay <= '1';
              wb_fmc_250m_4ch_csr_ch2_sta_val_lwb_in_progress <= '1';
            end if;
            rddata_reg(31 downto 16) <= regs_i.ch2_sta_reserved_i;
            ack_sreg(5) <= '1';
            ack_in_progress <= '1';
          when "01011" => 
            if (wb_we_i = '1') then
              regs_o.ch2_fn_dly_clk_chain_dly_load_o <= '1';
              regs_o.ch2_fn_dly_data_chain_dly_load_o <= '1';
              wb_fmc_250m_4ch_csr_ch2_fn_dly_inc_clk_chain_dly_int <= wrdata_reg(16);
              wb_fmc_250m_4ch_csr_ch2_fn_dly_dec_clk_chain_dly_int <= wrdata_reg(17);
              wb_fmc_250m_4ch_csr_ch2_fn_dly_reserved_clk_incdec_dly_int <= wrdata_reg(23 downto 18);
              wb_fmc_250m_4ch_csr_ch2_fn_dly_inc_data_chain_dly_int <= wrdata_reg(24);
              wb_fmc_250m_4ch_csr_ch2_fn_dly_dec_data_chain_dly_int <= wrdata_reg(25);
              wb_fmc_250m_4ch_csr_ch2_fn_dly_reserved_data_incdec_dly_int <= wrdata_reg(31 downto 26);
            end if;
            rddata_reg(4 downto 0) <= regs_i.ch2_fn_dly_clk_chain_dly_i;
            rddata_reg(7 downto 5) <= regs_i.ch2_fn_dly_reserved_clk_chain_dly_i;
            rddata_reg(12 downto 8) <= regs_i.ch2_fn_dly_data_chain_dly_i;
            rddata_reg(15 downto 13) <= regs_i.ch2_fn_dly_reserved_data_chain_dly_i;
            rddata_reg(16) <= '0';
            rddata_reg(17) <= '0';
            rddata_reg(23 downto 18) <= wb_fmc_250m_4ch_csr_ch2_fn_dly_reserved_clk_incdec_dly_int;
            rddata_reg(24) <= '0';
            rddata_reg(25) <= '0';
            rddata_reg(31 downto 26) <= wb_fmc_250m_4ch_csr_ch2_fn_dly_reserved_data_incdec_dly_int;
            ack_sreg(2) <= '1';
            ack_in_progress <= '1';
          when "01100" => 
            if (wb_we_i = '1') then
              wb_fmc_250m_4ch_csr_ch2_fn_sel_line_int <= wrdata_reg(16 downto 0);
            end if;
            rddata_reg(16 downto 0) <= wb_fmc_250m_4ch_csr_ch2_fn_sel_line_int;
            rddata_reg(31 downto 17) <= regs_i.ch2_fn_sel_reserved_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "01101" => 
            if (wb_we_i = '1') then
              wb_fmc_250m_4ch_csr_ch2_cs_dly_fe_dly_int <= wrdata_reg(1 downto 0);
              wb_fmc_250m_4ch_csr_ch2_cs_dly_fe_dly_swb <= '1';
              wb_fmc_250m_4ch_csr_ch2_cs_dly_fe_dly_swb_delay <= '1';
              wb_fmc_250m_4ch_csr_ch2_cs_dly_reserved_fe_dly_int <= wrdata_reg(7 downto 2);
              wb_fmc_250m_4ch_csr_ch2_cs_dly_rg_dly_int <= wrdata_reg(9 downto 8);
              wb_fmc_250m_4ch_csr_ch2_cs_dly_rg_dly_swb <= '1';
              wb_fmc_250m_4ch_csr_ch2_cs_dly_rg_dly_swb_delay <= '1';
              wb_fmc_250m_4ch_csr_ch2_cs_dly_reserved_rg_dly_int <= wrdata_reg(31 downto 10);
            end if;
            rddata_reg(1 downto 0) <= wb_fmc_250m_4ch_csr_ch2_cs_dly_fe_dly_int;
            rddata_reg(7 downto 2) <= wb_fmc_250m_4ch_csr_ch2_cs_dly_reserved_fe_dly_int;
            rddata_reg(9 downto 8) <= wb_fmc_250m_4ch_csr_ch2_cs_dly_rg_dly_int;
            rddata_reg(31 downto 10) <= wb_fmc_250m_4ch_csr_ch2_cs_dly_reserved_rg_dly_int;
            ack_sreg(3) <= '1';
            ack_in_progress <= '1';
          when "01110" => 
            if (wb_we_i = '1') then
            end if;
            if (wb_we_i = '0') then
              wb_fmc_250m_4ch_csr_ch3_sta_val_lwb <= '1';
              wb_fmc_250m_4ch_csr_ch3_sta_val_lwb_delay <= '1';
              wb_fmc_250m_4ch_csr_ch3_sta_val_lwb_in_progress <= '1';
            end if;
            rddata_reg(31 downto 16) <= regs_i.ch3_sta_reserved_i;
            ack_sreg(5) <= '1';
            ack_in_progress <= '1';
          when "01111" => 
            if (wb_we_i = '1') then
              regs_o.ch3_fn_dly_clk_chain_dly_load_o <= '1';
              regs_o.ch3_fn_dly_data_chain_dly_load_o <= '1';
              wb_fmc_250m_4ch_csr_ch3_fn_dly_inc_clk_chain_dly_int <= wrdata_reg(16);
              wb_fmc_250m_4ch_csr_ch3_fn_dly_dec_clk_chain_dly_int <= wrdata_reg(17);
              wb_fmc_250m_4ch_csr_ch3_fn_dly_reserved_clk_incdec_dly_int <= wrdata_reg(23 downto 18);
              wb_fmc_250m_4ch_csr_ch3_fn_dly_inc_data_chain_dly_int <= wrdata_reg(24);
              wb_fmc_250m_4ch_csr_ch3_fn_dly_dec_data_chain_dly_int <= wrdata_reg(25);
              wb_fmc_250m_4ch_csr_ch3_fn_dly_reserved_data_incdec_dly_int <= wrdata_reg(31 downto 26);
            end if;
            rddata_reg(4 downto 0) <= regs_i.ch3_fn_dly_clk_chain_dly_i;
            rddata_reg(7 downto 5) <= regs_i.ch3_fn_dly_reserved_clk_chain_dly_i;
            rddata_reg(12 downto 8) <= regs_i.ch3_fn_dly_data_chain_dly_i;
            rddata_reg(15 downto 13) <= regs_i.ch3_fn_dly_reserved_data_chain_dly_i;
            rddata_reg(16) <= '0';
            rddata_reg(17) <= '0';
            rddata_reg(23 downto 18) <= wb_fmc_250m_4ch_csr_ch3_fn_dly_reserved_clk_incdec_dly_int;
            rddata_reg(24) <= '0';
            rddata_reg(25) <= '0';
            rddata_reg(31 downto 26) <= wb_fmc_250m_4ch_csr_ch3_fn_dly_reserved_data_incdec_dly_int;
            ack_sreg(2) <= '1';
            ack_in_progress <= '1';
          when "10000" => 
            if (wb_we_i = '1') then
              wb_fmc_250m_4ch_csr_ch3_fn_sel_line_int <= wrdata_reg(16 downto 0);
            end if;
            rddata_reg(16 downto 0) <= wb_fmc_250m_4ch_csr_ch3_fn_sel_line_int;
            rddata_reg(31 downto 17) <= regs_i.ch3_fn_sel_reserved_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "10001" => 
            if (wb_we_i = '1') then
              wb_fmc_250m_4ch_csr_ch3_cs_dly_fe_dly_int <= wrdata_reg(1 downto 0);
              wb_fmc_250m_4ch_csr_ch3_cs_dly_fe_dly_swb <= '1';
              wb_fmc_250m_4ch_csr_ch3_cs_dly_fe_dly_swb_delay <= '1';
              wb_fmc_250m_4ch_csr_ch3_cs_dly_reserved_fe_dly_int <= wrdata_reg(7 downto 2);
              wb_fmc_250m_4ch_csr_ch3_cs_dly_rg_dly_int <= wrdata_reg(9 downto 8);
              wb_fmc_250m_4ch_csr_ch3_cs_dly_rg_dly_swb <= '1';
              wb_fmc_250m_4ch_csr_ch3_cs_dly_rg_dly_swb_delay <= '1';
              wb_fmc_250m_4ch_csr_ch3_cs_dly_reserved_rg_dly_int <= wrdata_reg(31 downto 10);
            end if;
            rddata_reg(1 downto 0) <= wb_fmc_250m_4ch_csr_ch3_cs_dly_fe_dly_int;
            rddata_reg(7 downto 2) <= wb_fmc_250m_4ch_csr_ch3_cs_dly_reserved_fe_dly_int;
            rddata_reg(9 downto 8) <= wb_fmc_250m_4ch_csr_ch3_cs_dly_rg_dly_int;
            rddata_reg(31 downto 10) <= wb_fmc_250m_4ch_csr_ch3_cs_dly_reserved_rg_dly_int;
            ack_sreg(3) <= '1';
            ack_in_progress <= '1';
          when "10010" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(0) <= regs_i.temp_mon_dev_i;
            rddata_reg(1) <= 'X';
            rddata_reg(2) <= 'X';
            rddata_reg(3) <= 'X';
            rddata_reg(4) <= 'X';
            rddata_reg(5) <= 'X';
            rddata_reg(6) <= 'X';
            rddata_reg(7) <= 'X';
            rddata_reg(8) <= 'X';
            rddata_reg(9) <= 'X';
            rddata_reg(10) <= 'X';
            rddata_reg(11) <= 'X';
            rddata_reg(12) <= 'X';
            rddata_reg(13) <= 'X';
            rddata_reg(14) <= 'X';
            rddata_reg(15) <= 'X';
            rddata_reg(16) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            rddata_reg(24) <= 'X';
            rddata_reg(25) <= 'X';
            rddata_reg(26) <= 'X';
            rddata_reg(27) <= 'X';
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when others =>
-- prevent the slave from hanging the bus on invalid address
            ack_in_progress <= '1';
            ack_sreg(0) <= '1';
          end case;
        end if;
      end if;
    end if;
  end process;
  
  
-- Drive the data output bus
  wb_dat_o <= rddata_reg;
-- FMC ADC clock chains
-- Reserved
-- FMC ADC Data chains
-- Reserved
-- FMC ADC packet size
-- Reset/Update ADC clock chains delay
  process (clk_sys_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_fmc_250m_4ch_csr_adc_ctl_update_clk_dly_dly0 <= '0';
      regs_o.adc_ctl_update_clk_dly_o <= '0';
    elsif rising_edge(clk_sys_i) then
      wb_fmc_250m_4ch_csr_adc_ctl_update_clk_dly_dly0 <= wb_fmc_250m_4ch_csr_adc_ctl_update_clk_dly_int;
      regs_o.adc_ctl_update_clk_dly_o <= wb_fmc_250m_4ch_csr_adc_ctl_update_clk_dly_int and (not wb_fmc_250m_4ch_csr_adc_ctl_update_clk_dly_dly0);
    end if;
  end process;
  
  
-- Reset/Update ADC data chains delay
  process (clk_sys_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_fmc_250m_4ch_csr_adc_ctl_update_data_dly_dly0 <= '0';
      regs_o.adc_ctl_update_data_dly_o <= '0';
    elsif rising_edge(clk_sys_i) then
      wb_fmc_250m_4ch_csr_adc_ctl_update_data_dly_dly0 <= wb_fmc_250m_4ch_csr_adc_ctl_update_data_dly_int;
      regs_o.adc_ctl_update_data_dly_o <= wb_fmc_250m_4ch_csr_adc_ctl_update_data_dly_int and (not wb_fmc_250m_4ch_csr_adc_ctl_update_data_dly_dly0);
    end if;
  end process;
  
  
-- Reset ADCs
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      regs_o.adc_ctl_rst_adcs_o <= '0';
      wb_fmc_250m_4ch_csr_adc_ctl_rst_adcs_sync0 <= '0';
      wb_fmc_250m_4ch_csr_adc_ctl_rst_adcs_sync1 <= '0';
      wb_fmc_250m_4ch_csr_adc_ctl_rst_adcs_sync2 <= '0';
    elsif rising_edge(fs_clk_i) then
      wb_fmc_250m_4ch_csr_adc_ctl_rst_adcs_sync0 <= wb_fmc_250m_4ch_csr_adc_ctl_rst_adcs_int;
      wb_fmc_250m_4ch_csr_adc_ctl_rst_adcs_sync1 <= wb_fmc_250m_4ch_csr_adc_ctl_rst_adcs_sync0;
      wb_fmc_250m_4ch_csr_adc_ctl_rst_adcs_sync2 <= wb_fmc_250m_4ch_csr_adc_ctl_rst_adcs_sync1;
      regs_o.adc_ctl_rst_adcs_o <= wb_fmc_250m_4ch_csr_adc_ctl_rst_adcs_sync2 and (not wb_fmc_250m_4ch_csr_adc_ctl_rst_adcs_sync1);
    end if;
  end process;
  
  
-- Reset Div ADCs
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      regs_o.adc_ctl_rst_div_adcs_o <= '0';
      wb_fmc_250m_4ch_csr_adc_ctl_rst_div_adcs_sync0 <= '0';
      wb_fmc_250m_4ch_csr_adc_ctl_rst_div_adcs_sync1 <= '0';
      wb_fmc_250m_4ch_csr_adc_ctl_rst_div_adcs_sync2 <= '0';
    elsif rising_edge(fs_clk_i) then
      wb_fmc_250m_4ch_csr_adc_ctl_rst_div_adcs_sync0 <= wb_fmc_250m_4ch_csr_adc_ctl_rst_div_adcs_int;
      wb_fmc_250m_4ch_csr_adc_ctl_rst_div_adcs_sync1 <= wb_fmc_250m_4ch_csr_adc_ctl_rst_div_adcs_sync0;
      wb_fmc_250m_4ch_csr_adc_ctl_rst_div_adcs_sync2 <= wb_fmc_250m_4ch_csr_adc_ctl_rst_div_adcs_sync1;
      regs_o.adc_ctl_rst_div_adcs_o <= wb_fmc_250m_4ch_csr_adc_ctl_rst_div_adcs_sync2 and (not wb_fmc_250m_4ch_csr_adc_ctl_rst_div_adcs_sync1);
    end if;
  end process;
  
  
-- Sleep ADCs
-- synchronizer chain for field : Sleep ADCs (type RW/RO, clk_sys_i <-> fs_clk_i)
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      regs_o.adc_ctl_sleep_adcs_o <= '0';
      wb_fmc_250m_4ch_csr_adc_ctl_sleep_adcs_sync0 <= '0';
      wb_fmc_250m_4ch_csr_adc_ctl_sleep_adcs_sync1 <= '0';
    elsif rising_edge(fs_clk_i) then
      wb_fmc_250m_4ch_csr_adc_ctl_sleep_adcs_sync0 <= wb_fmc_250m_4ch_csr_adc_ctl_sleep_adcs_int;
      wb_fmc_250m_4ch_csr_adc_ctl_sleep_adcs_sync1 <= wb_fmc_250m_4ch_csr_adc_ctl_sleep_adcs_sync0;
      regs_o.adc_ctl_sleep_adcs_o <= wb_fmc_250m_4ch_csr_adc_ctl_sleep_adcs_sync1;
    end if;
  end process;
  
  
-- Reserved
-- Channel 0 current ADC value
-- asynchronous std_logic_vector register : Channel 0 current ADC value (type RO/WO, fs_clk_i <-> clk_sys_i)
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_fmc_250m_4ch_csr_ch0_sta_val_lwb_s0 <= '0';
      wb_fmc_250m_4ch_csr_ch0_sta_val_lwb_s1 <= '0';
      wb_fmc_250m_4ch_csr_ch0_sta_val_lwb_s2 <= '0';
      wb_fmc_250m_4ch_csr_ch0_sta_val_int <= "0000000000000000";
    elsif rising_edge(fs_clk_i) then
      wb_fmc_250m_4ch_csr_ch0_sta_val_lwb_s0 <= wb_fmc_250m_4ch_csr_ch0_sta_val_lwb;
      wb_fmc_250m_4ch_csr_ch0_sta_val_lwb_s1 <= wb_fmc_250m_4ch_csr_ch0_sta_val_lwb_s0;
      wb_fmc_250m_4ch_csr_ch0_sta_val_lwb_s2 <= wb_fmc_250m_4ch_csr_ch0_sta_val_lwb_s1;
      if ((wb_fmc_250m_4ch_csr_ch0_sta_val_lwb_s1 = '1') and (wb_fmc_250m_4ch_csr_ch0_sta_val_lwb_s2 = '0')) then
        wb_fmc_250m_4ch_csr_ch0_sta_val_int <= regs_i.ch0_sta_val_i;
      end if;
    end if;
  end process;
  
  
-- Reserved
-- ADC clock chain delay
  regs_o.ch0_fn_dly_clk_chain_dly_o <= wrdata_reg(4 downto 0);
-- Reserved
-- ADC data chain delay
  regs_o.ch0_fn_dly_data_chain_dly_o <= wrdata_reg(12 downto 8);
-- Reserved
-- Increment ADC clock chains delay
  process (clk_sys_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_fmc_250m_4ch_csr_ch0_fn_dly_inc_clk_chain_dly_dly0 <= '0';
      regs_o.ch0_fn_dly_inc_clk_chain_dly_o <= '0';
    elsif rising_edge(clk_sys_i) then
      wb_fmc_250m_4ch_csr_ch0_fn_dly_inc_clk_chain_dly_dly0 <= wb_fmc_250m_4ch_csr_ch0_fn_dly_inc_clk_chain_dly_int;
      regs_o.ch0_fn_dly_inc_clk_chain_dly_o <= wb_fmc_250m_4ch_csr_ch0_fn_dly_inc_clk_chain_dly_int and (not wb_fmc_250m_4ch_csr_ch0_fn_dly_inc_clk_chain_dly_dly0);
    end if;
  end process;
  
  
-- Decrement ADC clock chains delay
  process (clk_sys_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_fmc_250m_4ch_csr_ch0_fn_dly_dec_clk_chain_dly_dly0 <= '0';
      regs_o.ch0_fn_dly_dec_clk_chain_dly_o <= '0';
    elsif rising_edge(clk_sys_i) then
      wb_fmc_250m_4ch_csr_ch0_fn_dly_dec_clk_chain_dly_dly0 <= wb_fmc_250m_4ch_csr_ch0_fn_dly_dec_clk_chain_dly_int;
      regs_o.ch0_fn_dly_dec_clk_chain_dly_o <= wb_fmc_250m_4ch_csr_ch0_fn_dly_dec_clk_chain_dly_int and (not wb_fmc_250m_4ch_csr_ch0_fn_dly_dec_clk_chain_dly_dly0);
    end if;
  end process;
  
  
-- Reserved
  regs_o.ch0_fn_dly_reserved_clk_incdec_dly_o <= wb_fmc_250m_4ch_csr_ch0_fn_dly_reserved_clk_incdec_dly_int;
-- Increment ADC data chains delay
  process (clk_sys_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_fmc_250m_4ch_csr_ch0_fn_dly_inc_data_chain_dly_dly0 <= '0';
      regs_o.ch0_fn_dly_inc_data_chain_dly_o <= '0';
    elsif rising_edge(clk_sys_i) then
      wb_fmc_250m_4ch_csr_ch0_fn_dly_inc_data_chain_dly_dly0 <= wb_fmc_250m_4ch_csr_ch0_fn_dly_inc_data_chain_dly_int;
      regs_o.ch0_fn_dly_inc_data_chain_dly_o <= wb_fmc_250m_4ch_csr_ch0_fn_dly_inc_data_chain_dly_int and (not wb_fmc_250m_4ch_csr_ch0_fn_dly_inc_data_chain_dly_dly0);
    end if;
  end process;
  
  
-- Decrement ADC data chains delay
  process (clk_sys_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_fmc_250m_4ch_csr_ch0_fn_dly_dec_data_chain_dly_dly0 <= '0';
      regs_o.ch0_fn_dly_dec_data_chain_dly_o <= '0';
    elsif rising_edge(clk_sys_i) then
      wb_fmc_250m_4ch_csr_ch0_fn_dly_dec_data_chain_dly_dly0 <= wb_fmc_250m_4ch_csr_ch0_fn_dly_dec_data_chain_dly_int;
      regs_o.ch0_fn_dly_dec_data_chain_dly_o <= wb_fmc_250m_4ch_csr_ch0_fn_dly_dec_data_chain_dly_int and (not wb_fmc_250m_4ch_csr_ch0_fn_dly_dec_data_chain_dly_dly0);
    end if;
  end process;
  
  
-- Reserved
  regs_o.ch0_fn_dly_reserved_data_incdec_dly_o <= wb_fmc_250m_4ch_csr_ch0_fn_dly_reserved_data_incdec_dly_int;
-- LINE
  regs_o.ch0_fn_sel_line_o <= wb_fmc_250m_4ch_csr_ch0_fn_sel_line_int;
-- Reserved
-- Falling edge data delay
-- asynchronous std_logic_vector register : Falling edge data delay (type RW/RO, fs_clk_i <-> clk_sys_i)
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_fmc_250m_4ch_csr_ch0_cs_dly_fe_dly_swb_s0 <= '0';
      wb_fmc_250m_4ch_csr_ch0_cs_dly_fe_dly_swb_s1 <= '0';
      wb_fmc_250m_4ch_csr_ch0_cs_dly_fe_dly_swb_s2 <= '0';
      regs_o.ch0_cs_dly_fe_dly_o <= "00";
    elsif rising_edge(fs_clk_i) then
      wb_fmc_250m_4ch_csr_ch0_cs_dly_fe_dly_swb_s0 <= wb_fmc_250m_4ch_csr_ch0_cs_dly_fe_dly_swb;
      wb_fmc_250m_4ch_csr_ch0_cs_dly_fe_dly_swb_s1 <= wb_fmc_250m_4ch_csr_ch0_cs_dly_fe_dly_swb_s0;
      wb_fmc_250m_4ch_csr_ch0_cs_dly_fe_dly_swb_s2 <= wb_fmc_250m_4ch_csr_ch0_cs_dly_fe_dly_swb_s1;
      if ((wb_fmc_250m_4ch_csr_ch0_cs_dly_fe_dly_swb_s2 = '0') and (wb_fmc_250m_4ch_csr_ch0_cs_dly_fe_dly_swb_s1 = '1')) then
        regs_o.ch0_cs_dly_fe_dly_o <= wb_fmc_250m_4ch_csr_ch0_cs_dly_fe_dly_int;
      end if;
    end if;
  end process;
  
  
-- Reserved
  regs_o.ch0_cs_dly_reserved_fe_dly_o <= wb_fmc_250m_4ch_csr_ch0_cs_dly_reserved_fe_dly_int;
-- Regular data delay
-- asynchronous std_logic_vector register : Regular data delay (type RW/RO, fs_clk_i <-> clk_sys_i)
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_fmc_250m_4ch_csr_ch0_cs_dly_rg_dly_swb_s0 <= '0';
      wb_fmc_250m_4ch_csr_ch0_cs_dly_rg_dly_swb_s1 <= '0';
      wb_fmc_250m_4ch_csr_ch0_cs_dly_rg_dly_swb_s2 <= '0';
      regs_o.ch0_cs_dly_rg_dly_o <= "00";
    elsif rising_edge(fs_clk_i) then
      wb_fmc_250m_4ch_csr_ch0_cs_dly_rg_dly_swb_s0 <= wb_fmc_250m_4ch_csr_ch0_cs_dly_rg_dly_swb;
      wb_fmc_250m_4ch_csr_ch0_cs_dly_rg_dly_swb_s1 <= wb_fmc_250m_4ch_csr_ch0_cs_dly_rg_dly_swb_s0;
      wb_fmc_250m_4ch_csr_ch0_cs_dly_rg_dly_swb_s2 <= wb_fmc_250m_4ch_csr_ch0_cs_dly_rg_dly_swb_s1;
      if ((wb_fmc_250m_4ch_csr_ch0_cs_dly_rg_dly_swb_s2 = '0') and (wb_fmc_250m_4ch_csr_ch0_cs_dly_rg_dly_swb_s1 = '1')) then
        regs_o.ch0_cs_dly_rg_dly_o <= wb_fmc_250m_4ch_csr_ch0_cs_dly_rg_dly_int;
      end if;
    end if;
  end process;
  
  
-- Reserved
  regs_o.ch0_cs_dly_reserved_rg_dly_o <= wb_fmc_250m_4ch_csr_ch0_cs_dly_reserved_rg_dly_int;
-- Channel 1 current ADC value
-- asynchronous std_logic_vector register : Channel 1 current ADC value (type RO/WO, fs_clk_i <-> clk_sys_i)
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_fmc_250m_4ch_csr_ch1_sta_val_lwb_s0 <= '0';
      wb_fmc_250m_4ch_csr_ch1_sta_val_lwb_s1 <= '0';
      wb_fmc_250m_4ch_csr_ch1_sta_val_lwb_s2 <= '0';
      wb_fmc_250m_4ch_csr_ch1_sta_val_int <= "0000000000000000";
    elsif rising_edge(fs_clk_i) then
      wb_fmc_250m_4ch_csr_ch1_sta_val_lwb_s0 <= wb_fmc_250m_4ch_csr_ch1_sta_val_lwb;
      wb_fmc_250m_4ch_csr_ch1_sta_val_lwb_s1 <= wb_fmc_250m_4ch_csr_ch1_sta_val_lwb_s0;
      wb_fmc_250m_4ch_csr_ch1_sta_val_lwb_s2 <= wb_fmc_250m_4ch_csr_ch1_sta_val_lwb_s1;
      if ((wb_fmc_250m_4ch_csr_ch1_sta_val_lwb_s1 = '1') and (wb_fmc_250m_4ch_csr_ch1_sta_val_lwb_s2 = '0')) then
        wb_fmc_250m_4ch_csr_ch1_sta_val_int <= regs_i.ch1_sta_val_i;
      end if;
    end if;
  end process;
  
  
-- Reserved
-- ADC clock chain delay
  regs_o.ch1_fn_dly_clk_chain_dly_o <= wrdata_reg(4 downto 0);
-- Reserved
-- ADC data chain delay
  regs_o.ch1_fn_dly_data_chain_dly_o <= wrdata_reg(12 downto 8);
-- Reserved
-- Increment ADC clock chains delay
  process (clk_sys_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_fmc_250m_4ch_csr_ch1_fn_dly_inc_clk_chain_dly_dly0 <= '0';
      regs_o.ch1_fn_dly_inc_clk_chain_dly_o <= '0';
    elsif rising_edge(clk_sys_i) then
      wb_fmc_250m_4ch_csr_ch1_fn_dly_inc_clk_chain_dly_dly0 <= wb_fmc_250m_4ch_csr_ch1_fn_dly_inc_clk_chain_dly_int;
      regs_o.ch1_fn_dly_inc_clk_chain_dly_o <= wb_fmc_250m_4ch_csr_ch1_fn_dly_inc_clk_chain_dly_int and (not wb_fmc_250m_4ch_csr_ch1_fn_dly_inc_clk_chain_dly_dly0);
    end if;
  end process;
  
  
-- Decrement ADC clock chains delay
  process (clk_sys_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_fmc_250m_4ch_csr_ch1_fn_dly_dec_clk_chain_dly_dly0 <= '0';
      regs_o.ch1_fn_dly_dec_clk_chain_dly_o <= '0';
    elsif rising_edge(clk_sys_i) then
      wb_fmc_250m_4ch_csr_ch1_fn_dly_dec_clk_chain_dly_dly0 <= wb_fmc_250m_4ch_csr_ch1_fn_dly_dec_clk_chain_dly_int;
      regs_o.ch1_fn_dly_dec_clk_chain_dly_o <= wb_fmc_250m_4ch_csr_ch1_fn_dly_dec_clk_chain_dly_int and (not wb_fmc_250m_4ch_csr_ch1_fn_dly_dec_clk_chain_dly_dly0);
    end if;
  end process;
  
  
-- Reserved
  regs_o.ch1_fn_dly_reserved_clk_incdec_dly_o <= wb_fmc_250m_4ch_csr_ch1_fn_dly_reserved_clk_incdec_dly_int;
-- Increment ADC data chains delay
  process (clk_sys_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_fmc_250m_4ch_csr_ch1_fn_dly_inc_data_chain_dly_dly0 <= '0';
      regs_o.ch1_fn_dly_inc_data_chain_dly_o <= '0';
    elsif rising_edge(clk_sys_i) then
      wb_fmc_250m_4ch_csr_ch1_fn_dly_inc_data_chain_dly_dly0 <= wb_fmc_250m_4ch_csr_ch1_fn_dly_inc_data_chain_dly_int;
      regs_o.ch1_fn_dly_inc_data_chain_dly_o <= wb_fmc_250m_4ch_csr_ch1_fn_dly_inc_data_chain_dly_int and (not wb_fmc_250m_4ch_csr_ch1_fn_dly_inc_data_chain_dly_dly0);
    end if;
  end process;
  
  
-- Decrement ADC data chains delay
  process (clk_sys_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_fmc_250m_4ch_csr_ch1_fn_dly_dec_data_chain_dly_dly0 <= '0';
      regs_o.ch1_fn_dly_dec_data_chain_dly_o <= '0';
    elsif rising_edge(clk_sys_i) then
      wb_fmc_250m_4ch_csr_ch1_fn_dly_dec_data_chain_dly_dly0 <= wb_fmc_250m_4ch_csr_ch1_fn_dly_dec_data_chain_dly_int;
      regs_o.ch1_fn_dly_dec_data_chain_dly_o <= wb_fmc_250m_4ch_csr_ch1_fn_dly_dec_data_chain_dly_int and (not wb_fmc_250m_4ch_csr_ch1_fn_dly_dec_data_chain_dly_dly0);
    end if;
  end process;
  
  
-- Reserved
  regs_o.ch1_fn_dly_reserved_data_incdec_dly_o <= wb_fmc_250m_4ch_csr_ch1_fn_dly_reserved_data_incdec_dly_int;
-- LINE
  regs_o.ch1_fn_sel_line_o <= wb_fmc_250m_4ch_csr_ch1_fn_sel_line_int;
-- Reserved
-- Falling edge data delay
-- asynchronous std_logic_vector register : Falling edge data delay (type RW/RO, fs_clk_i <-> clk_sys_i)
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_fmc_250m_4ch_csr_ch1_cs_dly_fe_dly_swb_s0 <= '0';
      wb_fmc_250m_4ch_csr_ch1_cs_dly_fe_dly_swb_s1 <= '0';
      wb_fmc_250m_4ch_csr_ch1_cs_dly_fe_dly_swb_s2 <= '0';
      regs_o.ch1_cs_dly_fe_dly_o <= "00";
    elsif rising_edge(fs_clk_i) then
      wb_fmc_250m_4ch_csr_ch1_cs_dly_fe_dly_swb_s0 <= wb_fmc_250m_4ch_csr_ch1_cs_dly_fe_dly_swb;
      wb_fmc_250m_4ch_csr_ch1_cs_dly_fe_dly_swb_s1 <= wb_fmc_250m_4ch_csr_ch1_cs_dly_fe_dly_swb_s0;
      wb_fmc_250m_4ch_csr_ch1_cs_dly_fe_dly_swb_s2 <= wb_fmc_250m_4ch_csr_ch1_cs_dly_fe_dly_swb_s1;
      if ((wb_fmc_250m_4ch_csr_ch1_cs_dly_fe_dly_swb_s2 = '0') and (wb_fmc_250m_4ch_csr_ch1_cs_dly_fe_dly_swb_s1 = '1')) then
        regs_o.ch1_cs_dly_fe_dly_o <= wb_fmc_250m_4ch_csr_ch1_cs_dly_fe_dly_int;
      end if;
    end if;
  end process;
  
  
-- Reserved
  regs_o.ch1_cs_dly_reserved_fe_dly_o <= wb_fmc_250m_4ch_csr_ch1_cs_dly_reserved_fe_dly_int;
-- Regular data delay
-- asynchronous std_logic_vector register : Regular data delay (type RW/RO, fs_clk_i <-> clk_sys_i)
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_fmc_250m_4ch_csr_ch1_cs_dly_rg_dly_swb_s0 <= '0';
      wb_fmc_250m_4ch_csr_ch1_cs_dly_rg_dly_swb_s1 <= '0';
      wb_fmc_250m_4ch_csr_ch1_cs_dly_rg_dly_swb_s2 <= '0';
      regs_o.ch1_cs_dly_rg_dly_o <= "00";
    elsif rising_edge(fs_clk_i) then
      wb_fmc_250m_4ch_csr_ch1_cs_dly_rg_dly_swb_s0 <= wb_fmc_250m_4ch_csr_ch1_cs_dly_rg_dly_swb;
      wb_fmc_250m_4ch_csr_ch1_cs_dly_rg_dly_swb_s1 <= wb_fmc_250m_4ch_csr_ch1_cs_dly_rg_dly_swb_s0;
      wb_fmc_250m_4ch_csr_ch1_cs_dly_rg_dly_swb_s2 <= wb_fmc_250m_4ch_csr_ch1_cs_dly_rg_dly_swb_s1;
      if ((wb_fmc_250m_4ch_csr_ch1_cs_dly_rg_dly_swb_s2 = '0') and (wb_fmc_250m_4ch_csr_ch1_cs_dly_rg_dly_swb_s1 = '1')) then
        regs_o.ch1_cs_dly_rg_dly_o <= wb_fmc_250m_4ch_csr_ch1_cs_dly_rg_dly_int;
      end if;
    end if;
  end process;
  
  
-- Reserved
  regs_o.ch1_cs_dly_reserved_rg_dly_o <= wb_fmc_250m_4ch_csr_ch1_cs_dly_reserved_rg_dly_int;
-- Channel 2 current ADC value
-- asynchronous std_logic_vector register : Channel 2 current ADC value (type RO/WO, fs_clk_i <-> clk_sys_i)
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_fmc_250m_4ch_csr_ch2_sta_val_lwb_s0 <= '0';
      wb_fmc_250m_4ch_csr_ch2_sta_val_lwb_s1 <= '0';
      wb_fmc_250m_4ch_csr_ch2_sta_val_lwb_s2 <= '0';
      wb_fmc_250m_4ch_csr_ch2_sta_val_int <= "0000000000000000";
    elsif rising_edge(fs_clk_i) then
      wb_fmc_250m_4ch_csr_ch2_sta_val_lwb_s0 <= wb_fmc_250m_4ch_csr_ch2_sta_val_lwb;
      wb_fmc_250m_4ch_csr_ch2_sta_val_lwb_s1 <= wb_fmc_250m_4ch_csr_ch2_sta_val_lwb_s0;
      wb_fmc_250m_4ch_csr_ch2_sta_val_lwb_s2 <= wb_fmc_250m_4ch_csr_ch2_sta_val_lwb_s1;
      if ((wb_fmc_250m_4ch_csr_ch2_sta_val_lwb_s1 = '1') and (wb_fmc_250m_4ch_csr_ch2_sta_val_lwb_s2 = '0')) then
        wb_fmc_250m_4ch_csr_ch2_sta_val_int <= regs_i.ch2_sta_val_i;
      end if;
    end if;
  end process;
  
  
-- Reserved
-- ADC clock chain delay
  regs_o.ch2_fn_dly_clk_chain_dly_o <= wrdata_reg(4 downto 0);
-- Reserved
-- ADC data chain delay
  regs_o.ch2_fn_dly_data_chain_dly_o <= wrdata_reg(12 downto 8);
-- Reserved
-- Increment ADC clock chains delay
  process (clk_sys_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_fmc_250m_4ch_csr_ch2_fn_dly_inc_clk_chain_dly_dly0 <= '0';
      regs_o.ch2_fn_dly_inc_clk_chain_dly_o <= '0';
    elsif rising_edge(clk_sys_i) then
      wb_fmc_250m_4ch_csr_ch2_fn_dly_inc_clk_chain_dly_dly0 <= wb_fmc_250m_4ch_csr_ch2_fn_dly_inc_clk_chain_dly_int;
      regs_o.ch2_fn_dly_inc_clk_chain_dly_o <= wb_fmc_250m_4ch_csr_ch2_fn_dly_inc_clk_chain_dly_int and (not wb_fmc_250m_4ch_csr_ch2_fn_dly_inc_clk_chain_dly_dly0);
    end if;
  end process;
  
  
-- Decrement ADC clock chains delay
  process (clk_sys_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_fmc_250m_4ch_csr_ch2_fn_dly_dec_clk_chain_dly_dly0 <= '0';
      regs_o.ch2_fn_dly_dec_clk_chain_dly_o <= '0';
    elsif rising_edge(clk_sys_i) then
      wb_fmc_250m_4ch_csr_ch2_fn_dly_dec_clk_chain_dly_dly0 <= wb_fmc_250m_4ch_csr_ch2_fn_dly_dec_clk_chain_dly_int;
      regs_o.ch2_fn_dly_dec_clk_chain_dly_o <= wb_fmc_250m_4ch_csr_ch2_fn_dly_dec_clk_chain_dly_int and (not wb_fmc_250m_4ch_csr_ch2_fn_dly_dec_clk_chain_dly_dly0);
    end if;
  end process;
  
  
-- Reserved
  regs_o.ch2_fn_dly_reserved_clk_incdec_dly_o <= wb_fmc_250m_4ch_csr_ch2_fn_dly_reserved_clk_incdec_dly_int;
-- Increment ADC data chains delay
  process (clk_sys_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_fmc_250m_4ch_csr_ch2_fn_dly_inc_data_chain_dly_dly0 <= '0';
      regs_o.ch2_fn_dly_inc_data_chain_dly_o <= '0';
    elsif rising_edge(clk_sys_i) then
      wb_fmc_250m_4ch_csr_ch2_fn_dly_inc_data_chain_dly_dly0 <= wb_fmc_250m_4ch_csr_ch2_fn_dly_inc_data_chain_dly_int;
      regs_o.ch2_fn_dly_inc_data_chain_dly_o <= wb_fmc_250m_4ch_csr_ch2_fn_dly_inc_data_chain_dly_int and (not wb_fmc_250m_4ch_csr_ch2_fn_dly_inc_data_chain_dly_dly0);
    end if;
  end process;
  
  
-- Decrement ADC data chains delay
  process (clk_sys_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_fmc_250m_4ch_csr_ch2_fn_dly_dec_data_chain_dly_dly0 <= '0';
      regs_o.ch2_fn_dly_dec_data_chain_dly_o <= '0';
    elsif rising_edge(clk_sys_i) then
      wb_fmc_250m_4ch_csr_ch2_fn_dly_dec_data_chain_dly_dly0 <= wb_fmc_250m_4ch_csr_ch2_fn_dly_dec_data_chain_dly_int;
      regs_o.ch2_fn_dly_dec_data_chain_dly_o <= wb_fmc_250m_4ch_csr_ch2_fn_dly_dec_data_chain_dly_int and (not wb_fmc_250m_4ch_csr_ch2_fn_dly_dec_data_chain_dly_dly0);
    end if;
  end process;
  
  
-- Reserved
  regs_o.ch2_fn_dly_reserved_data_incdec_dly_o <= wb_fmc_250m_4ch_csr_ch2_fn_dly_reserved_data_incdec_dly_int;
-- LINE
  regs_o.ch2_fn_sel_line_o <= wb_fmc_250m_4ch_csr_ch2_fn_sel_line_int;
-- Reserved
-- Falling edge data delay
-- asynchronous std_logic_vector register : Falling edge data delay (type RW/RO, fs_clk_i <-> clk_sys_i)
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_fmc_250m_4ch_csr_ch2_cs_dly_fe_dly_swb_s0 <= '0';
      wb_fmc_250m_4ch_csr_ch2_cs_dly_fe_dly_swb_s1 <= '0';
      wb_fmc_250m_4ch_csr_ch2_cs_dly_fe_dly_swb_s2 <= '0';
      regs_o.ch2_cs_dly_fe_dly_o <= "00";
    elsif rising_edge(fs_clk_i) then
      wb_fmc_250m_4ch_csr_ch2_cs_dly_fe_dly_swb_s0 <= wb_fmc_250m_4ch_csr_ch2_cs_dly_fe_dly_swb;
      wb_fmc_250m_4ch_csr_ch2_cs_dly_fe_dly_swb_s1 <= wb_fmc_250m_4ch_csr_ch2_cs_dly_fe_dly_swb_s0;
      wb_fmc_250m_4ch_csr_ch2_cs_dly_fe_dly_swb_s2 <= wb_fmc_250m_4ch_csr_ch2_cs_dly_fe_dly_swb_s1;
      if ((wb_fmc_250m_4ch_csr_ch2_cs_dly_fe_dly_swb_s2 = '0') and (wb_fmc_250m_4ch_csr_ch2_cs_dly_fe_dly_swb_s1 = '1')) then
        regs_o.ch2_cs_dly_fe_dly_o <= wb_fmc_250m_4ch_csr_ch2_cs_dly_fe_dly_int;
      end if;
    end if;
  end process;
  
  
-- Reserved
  regs_o.ch2_cs_dly_reserved_fe_dly_o <= wb_fmc_250m_4ch_csr_ch2_cs_dly_reserved_fe_dly_int;
-- Regular data delay
-- asynchronous std_logic_vector register : Regular data delay (type RW/RO, fs_clk_i <-> clk_sys_i)
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_fmc_250m_4ch_csr_ch2_cs_dly_rg_dly_swb_s0 <= '0';
      wb_fmc_250m_4ch_csr_ch2_cs_dly_rg_dly_swb_s1 <= '0';
      wb_fmc_250m_4ch_csr_ch2_cs_dly_rg_dly_swb_s2 <= '0';
      regs_o.ch2_cs_dly_rg_dly_o <= "00";
    elsif rising_edge(fs_clk_i) then
      wb_fmc_250m_4ch_csr_ch2_cs_dly_rg_dly_swb_s0 <= wb_fmc_250m_4ch_csr_ch2_cs_dly_rg_dly_swb;
      wb_fmc_250m_4ch_csr_ch2_cs_dly_rg_dly_swb_s1 <= wb_fmc_250m_4ch_csr_ch2_cs_dly_rg_dly_swb_s0;
      wb_fmc_250m_4ch_csr_ch2_cs_dly_rg_dly_swb_s2 <= wb_fmc_250m_4ch_csr_ch2_cs_dly_rg_dly_swb_s1;
      if ((wb_fmc_250m_4ch_csr_ch2_cs_dly_rg_dly_swb_s2 = '0') and (wb_fmc_250m_4ch_csr_ch2_cs_dly_rg_dly_swb_s1 = '1')) then
        regs_o.ch2_cs_dly_rg_dly_o <= wb_fmc_250m_4ch_csr_ch2_cs_dly_rg_dly_int;
      end if;
    end if;
  end process;
  
  
-- Reserved
  regs_o.ch2_cs_dly_reserved_rg_dly_o <= wb_fmc_250m_4ch_csr_ch2_cs_dly_reserved_rg_dly_int;
-- Channel 3 current ADC value
-- asynchronous std_logic_vector register : Channel 3 current ADC value (type RO/WO, fs_clk_i <-> clk_sys_i)
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_fmc_250m_4ch_csr_ch3_sta_val_lwb_s0 <= '0';
      wb_fmc_250m_4ch_csr_ch3_sta_val_lwb_s1 <= '0';
      wb_fmc_250m_4ch_csr_ch3_sta_val_lwb_s2 <= '0';
      wb_fmc_250m_4ch_csr_ch3_sta_val_int <= "0000000000000000";
    elsif rising_edge(fs_clk_i) then
      wb_fmc_250m_4ch_csr_ch3_sta_val_lwb_s0 <= wb_fmc_250m_4ch_csr_ch3_sta_val_lwb;
      wb_fmc_250m_4ch_csr_ch3_sta_val_lwb_s1 <= wb_fmc_250m_4ch_csr_ch3_sta_val_lwb_s0;
      wb_fmc_250m_4ch_csr_ch3_sta_val_lwb_s2 <= wb_fmc_250m_4ch_csr_ch3_sta_val_lwb_s1;
      if ((wb_fmc_250m_4ch_csr_ch3_sta_val_lwb_s1 = '1') and (wb_fmc_250m_4ch_csr_ch3_sta_val_lwb_s2 = '0')) then
        wb_fmc_250m_4ch_csr_ch3_sta_val_int <= regs_i.ch3_sta_val_i;
      end if;
    end if;
  end process;
  
  
-- Reserved
-- ADC clock chain delay
  regs_o.ch3_fn_dly_clk_chain_dly_o <= wrdata_reg(4 downto 0);
-- Reserved
-- ADC data chain delay
  regs_o.ch3_fn_dly_data_chain_dly_o <= wrdata_reg(12 downto 8);
-- Reserved
-- Increment ADC clock chains delay
  process (clk_sys_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_fmc_250m_4ch_csr_ch3_fn_dly_inc_clk_chain_dly_dly0 <= '0';
      regs_o.ch3_fn_dly_inc_clk_chain_dly_o <= '0';
    elsif rising_edge(clk_sys_i) then
      wb_fmc_250m_4ch_csr_ch3_fn_dly_inc_clk_chain_dly_dly0 <= wb_fmc_250m_4ch_csr_ch3_fn_dly_inc_clk_chain_dly_int;
      regs_o.ch3_fn_dly_inc_clk_chain_dly_o <= wb_fmc_250m_4ch_csr_ch3_fn_dly_inc_clk_chain_dly_int and (not wb_fmc_250m_4ch_csr_ch3_fn_dly_inc_clk_chain_dly_dly0);
    end if;
  end process;
  
  
-- Decrement ADC clock chains delay
  process (clk_sys_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_fmc_250m_4ch_csr_ch3_fn_dly_dec_clk_chain_dly_dly0 <= '0';
      regs_o.ch3_fn_dly_dec_clk_chain_dly_o <= '0';
    elsif rising_edge(clk_sys_i) then
      wb_fmc_250m_4ch_csr_ch3_fn_dly_dec_clk_chain_dly_dly0 <= wb_fmc_250m_4ch_csr_ch3_fn_dly_dec_clk_chain_dly_int;
      regs_o.ch3_fn_dly_dec_clk_chain_dly_o <= wb_fmc_250m_4ch_csr_ch3_fn_dly_dec_clk_chain_dly_int and (not wb_fmc_250m_4ch_csr_ch3_fn_dly_dec_clk_chain_dly_dly0);
    end if;
  end process;
  
  
-- Reserved
  regs_o.ch3_fn_dly_reserved_clk_incdec_dly_o <= wb_fmc_250m_4ch_csr_ch3_fn_dly_reserved_clk_incdec_dly_int;
-- Increment ADC data chains delay
  process (clk_sys_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_fmc_250m_4ch_csr_ch3_fn_dly_inc_data_chain_dly_dly0 <= '0';
      regs_o.ch3_fn_dly_inc_data_chain_dly_o <= '0';
    elsif rising_edge(clk_sys_i) then
      wb_fmc_250m_4ch_csr_ch3_fn_dly_inc_data_chain_dly_dly0 <= wb_fmc_250m_4ch_csr_ch3_fn_dly_inc_data_chain_dly_int;
      regs_o.ch3_fn_dly_inc_data_chain_dly_o <= wb_fmc_250m_4ch_csr_ch3_fn_dly_inc_data_chain_dly_int and (not wb_fmc_250m_4ch_csr_ch3_fn_dly_inc_data_chain_dly_dly0);
    end if;
  end process;
  
  
-- Decrement ADC data chains delay
  process (clk_sys_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_fmc_250m_4ch_csr_ch3_fn_dly_dec_data_chain_dly_dly0 <= '0';
      regs_o.ch3_fn_dly_dec_data_chain_dly_o <= '0';
    elsif rising_edge(clk_sys_i) then
      wb_fmc_250m_4ch_csr_ch3_fn_dly_dec_data_chain_dly_dly0 <= wb_fmc_250m_4ch_csr_ch3_fn_dly_dec_data_chain_dly_int;
      regs_o.ch3_fn_dly_dec_data_chain_dly_o <= wb_fmc_250m_4ch_csr_ch3_fn_dly_dec_data_chain_dly_int and (not wb_fmc_250m_4ch_csr_ch3_fn_dly_dec_data_chain_dly_dly0);
    end if;
  end process;
  
  
-- Reserved
  regs_o.ch3_fn_dly_reserved_data_incdec_dly_o <= wb_fmc_250m_4ch_csr_ch3_fn_dly_reserved_data_incdec_dly_int;
-- LINE
  regs_o.ch3_fn_sel_line_o <= wb_fmc_250m_4ch_csr_ch3_fn_sel_line_int;
-- Reserved
-- Falling edge data delay
-- asynchronous std_logic_vector register : Falling edge data delay (type RW/RO, fs_clk_i <-> clk_sys_i)
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_fmc_250m_4ch_csr_ch3_cs_dly_fe_dly_swb_s0 <= '0';
      wb_fmc_250m_4ch_csr_ch3_cs_dly_fe_dly_swb_s1 <= '0';
      wb_fmc_250m_4ch_csr_ch3_cs_dly_fe_dly_swb_s2 <= '0';
      regs_o.ch3_cs_dly_fe_dly_o <= "00";
    elsif rising_edge(fs_clk_i) then
      wb_fmc_250m_4ch_csr_ch3_cs_dly_fe_dly_swb_s0 <= wb_fmc_250m_4ch_csr_ch3_cs_dly_fe_dly_swb;
      wb_fmc_250m_4ch_csr_ch3_cs_dly_fe_dly_swb_s1 <= wb_fmc_250m_4ch_csr_ch3_cs_dly_fe_dly_swb_s0;
      wb_fmc_250m_4ch_csr_ch3_cs_dly_fe_dly_swb_s2 <= wb_fmc_250m_4ch_csr_ch3_cs_dly_fe_dly_swb_s1;
      if ((wb_fmc_250m_4ch_csr_ch3_cs_dly_fe_dly_swb_s2 = '0') and (wb_fmc_250m_4ch_csr_ch3_cs_dly_fe_dly_swb_s1 = '1')) then
        regs_o.ch3_cs_dly_fe_dly_o <= wb_fmc_250m_4ch_csr_ch3_cs_dly_fe_dly_int;
      end if;
    end if;
  end process;
  
  
-- Reserved
  regs_o.ch3_cs_dly_reserved_fe_dly_o <= wb_fmc_250m_4ch_csr_ch3_cs_dly_reserved_fe_dly_int;
-- Regular data delay
-- asynchronous std_logic_vector register : Regular data delay (type RW/RO, fs_clk_i <-> clk_sys_i)
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_fmc_250m_4ch_csr_ch3_cs_dly_rg_dly_swb_s0 <= '0';
      wb_fmc_250m_4ch_csr_ch3_cs_dly_rg_dly_swb_s1 <= '0';
      wb_fmc_250m_4ch_csr_ch3_cs_dly_rg_dly_swb_s2 <= '0';
      regs_o.ch3_cs_dly_rg_dly_o <= "00";
    elsif rising_edge(fs_clk_i) then
      wb_fmc_250m_4ch_csr_ch3_cs_dly_rg_dly_swb_s0 <= wb_fmc_250m_4ch_csr_ch3_cs_dly_rg_dly_swb;
      wb_fmc_250m_4ch_csr_ch3_cs_dly_rg_dly_swb_s1 <= wb_fmc_250m_4ch_csr_ch3_cs_dly_rg_dly_swb_s0;
      wb_fmc_250m_4ch_csr_ch3_cs_dly_rg_dly_swb_s2 <= wb_fmc_250m_4ch_csr_ch3_cs_dly_rg_dly_swb_s1;
      if ((wb_fmc_250m_4ch_csr_ch3_cs_dly_rg_dly_swb_s2 = '0') and (wb_fmc_250m_4ch_csr_ch3_cs_dly_rg_dly_swb_s1 = '1')) then
        regs_o.ch3_cs_dly_rg_dly_o <= wb_fmc_250m_4ch_csr_ch3_cs_dly_rg_dly_int;
      end if;
    end if;
  end process;
  
  
-- Reserved
  regs_o.ch3_cs_dly_reserved_rg_dly_o <= wb_fmc_250m_4ch_csr_ch3_cs_dly_reserved_rg_dly_int;
-- Monitor device
  rwaddr_reg <= wb_adr_i;
  wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
-- ACK signal generation. Just pass the LSB of ACK counter.
  wb_ack_o <= ack_sreg(0);
end syn;
