/*
  Register definitions for slave core: Control and status registers for FMC 130M 4CH

  * File           : wb_fmc130m_4ch_regs.h
  * Author         : auto-generated by wbgen2 from fmc_130m_4ch_regs.wb
  * Created        : Mon Apr 18 15:10:45 2016
  * Standard       : ANSI C

    THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fmc_130m_4ch_regs.wb
    DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!

*/

#ifndef __WBGEN2_REGDEFS_FMC_130M_4CH_REGS_WB
#define __WBGEN2_REGDEFS_FMC_130M_4CH_REGS_WB

#include <inttypes.h>

#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
#else
#error "Unsupported compiler?"
#endif

#ifndef __WBGEN2_MACROS_DEFINED__
#define __WBGEN2_MACROS_DEFINED__
#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
#endif


/* definitions for register: ADC LTC2208 control register (4 chips) */

/* definitions for field: RAND in reg: ADC LTC2208 control register (4 chips) */
#define WB_FMC_130M_4CH_CSR_ADC_RAND          WBGEN2_GEN_MASK(0, 1)

/* definitions for field: DITH in reg: ADC LTC2208 control register (4 chips) */
#define WB_FMC_130M_4CH_CSR_ADC_DITH          WBGEN2_GEN_MASK(1, 1)

/* definitions for field: SHDN in reg: ADC LTC2208 control register (4 chips) */
#define WB_FMC_130M_4CH_CSR_ADC_SHDN          WBGEN2_GEN_MASK(2, 1)

/* definitions for field: PGA in reg: ADC LTC2208 control register (4 chips) */
#define WB_FMC_130M_4CH_CSR_ADC_PGA           WBGEN2_GEN_MASK(3, 1)

/* definitions for field: Reserved in reg: ADC LTC2208 control register (4 chips) */
#define WB_FMC_130M_4CH_CSR_ADC_RESERVED_MASK WBGEN2_GEN_MASK(4, 28)
#define WB_FMC_130M_4CH_CSR_ADC_RESERVED_SHIFT 4
#define WB_FMC_130M_4CH_CSR_ADC_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 4, 28)
#define WB_FMC_130M_4CH_CSR_ADC_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 4, 28)

/* definitions for register: FPGA control */

/* definitions for field: FMC_IDELAY_RST in reg: FPGA control */
#define WB_FMC_130M_4CH_CSR_FPGA_CTRL_FMC_IDELAY_RST WBGEN2_GEN_MASK(0, 1)

/* definitions for field: FMC_FIFO_RST in reg: FPGA control */
#define WB_FMC_130M_4CH_CSR_FPGA_CTRL_FMC_FIFO_RST WBGEN2_GEN_MASK(1, 1)

/* definitions for field: FMC_IDELAY0_RDY in reg: FPGA control */
#define WB_FMC_130M_4CH_CSR_FPGA_CTRL_FMC_IDELAY0_RDY WBGEN2_GEN_MASK(2, 1)

/* definitions for field: FMC_IDELAY1_RDY in reg: FPGA control */
#define WB_FMC_130M_4CH_CSR_FPGA_CTRL_FMC_IDELAY1_RDY WBGEN2_GEN_MASK(3, 1)

/* definitions for field: FMC_IDELAY2_RDY in reg: FPGA control */
#define WB_FMC_130M_4CH_CSR_FPGA_CTRL_FMC_IDELAY2_RDY WBGEN2_GEN_MASK(4, 1)

/* definitions for field: FMC_IDELAY3_RDY in reg: FPGA control */
#define WB_FMC_130M_4CH_CSR_FPGA_CTRL_FMC_IDELAY3_RDY WBGEN2_GEN_MASK(5, 1)

/* definitions for field: Reserved in reg: FPGA control */
#define WB_FMC_130M_4CH_CSR_FPGA_CTRL_RESERVED1_MASK WBGEN2_GEN_MASK(6, 2)
#define WB_FMC_130M_4CH_CSR_FPGA_CTRL_RESERVED1_SHIFT 6
#define WB_FMC_130M_4CH_CSR_FPGA_CTRL_RESERVED1_W(value) WBGEN2_GEN_WRITE(value, 6, 2)
#define WB_FMC_130M_4CH_CSR_FPGA_CTRL_RESERVED1_R(reg) WBGEN2_GEN_READ(reg, 6, 2)

/* definitions for field: Temperature Alarm in reg: FPGA control */
#define WB_FMC_130M_4CH_CSR_FPGA_CTRL_TEMP_ALARM WBGEN2_GEN_MASK(8, 1)

/* definitions for field: Reserved in reg: FPGA control */
#define WB_FMC_130M_4CH_CSR_FPGA_CTRL_RESERVED2_MASK WBGEN2_GEN_MASK(9, 23)
#define WB_FMC_130M_4CH_CSR_FPGA_CTRL_RESERVED2_SHIFT 9
#define WB_FMC_130M_4CH_CSR_FPGA_CTRL_RESERVED2_W(value) WBGEN2_GEN_WRITE(value, 9, 23)
#define WB_FMC_130M_4CH_CSR_FPGA_CTRL_RESERVED2_R(reg) WBGEN2_GEN_READ(reg, 9, 23)

/* definitions for register: IDELAY ADC0 calibration */

/* definitions for field: UPDATE in reg: IDELAY ADC0 calibration */
#define WB_FMC_130M_4CH_CSR_IDELAY0_CAL_UPDATE WBGEN2_GEN_MASK(0, 1)

/* definitions for field: LINE in reg: IDELAY ADC0 calibration */
#define WB_FMC_130M_4CH_CSR_IDELAY0_CAL_LINE_MASK WBGEN2_GEN_MASK(1, 17)
#define WB_FMC_130M_4CH_CSR_IDELAY0_CAL_LINE_SHIFT 1
#define WB_FMC_130M_4CH_CSR_IDELAY0_CAL_LINE_W(value) WBGEN2_GEN_WRITE(value, 1, 17)
#define WB_FMC_130M_4CH_CSR_IDELAY0_CAL_LINE_R(reg) WBGEN2_GEN_READ(reg, 1, 17)

/* definitions for field: VAL in reg: IDELAY ADC0 calibration */
#define WB_FMC_130M_4CH_CSR_IDELAY0_CAL_VAL_MASK WBGEN2_GEN_MASK(18, 5)
#define WB_FMC_130M_4CH_CSR_IDELAY0_CAL_VAL_SHIFT 18
#define WB_FMC_130M_4CH_CSR_IDELAY0_CAL_VAL_W(value) WBGEN2_GEN_WRITE(value, 18, 5)
#define WB_FMC_130M_4CH_CSR_IDELAY0_CAL_VAL_R(reg) WBGEN2_GEN_READ(reg, 18, 5)

/* definitions for field: Reserved in reg: IDELAY ADC0 calibration */
#define WB_FMC_130M_4CH_CSR_IDELAY0_CAL_RESERVED_MASK WBGEN2_GEN_MASK(23, 9)
#define WB_FMC_130M_4CH_CSR_IDELAY0_CAL_RESERVED_SHIFT 23
#define WB_FMC_130M_4CH_CSR_IDELAY0_CAL_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 23, 9)
#define WB_FMC_130M_4CH_CSR_IDELAY0_CAL_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 23, 9)

/* definitions for register: IDELAY ADC1 calibration */

/* definitions for field: UPDATE in reg: IDELAY ADC1 calibration */
#define WB_FMC_130M_4CH_CSR_IDELAY1_CAL_UPDATE WBGEN2_GEN_MASK(0, 1)

/* definitions for field: LINE in reg: IDELAY ADC1 calibration */
#define WB_FMC_130M_4CH_CSR_IDELAY1_CAL_LINE_MASK WBGEN2_GEN_MASK(1, 17)
#define WB_FMC_130M_4CH_CSR_IDELAY1_CAL_LINE_SHIFT 1
#define WB_FMC_130M_4CH_CSR_IDELAY1_CAL_LINE_W(value) WBGEN2_GEN_WRITE(value, 1, 17)
#define WB_FMC_130M_4CH_CSR_IDELAY1_CAL_LINE_R(reg) WBGEN2_GEN_READ(reg, 1, 17)

/* definitions for field: VAL in reg: IDELAY ADC1 calibration */
#define WB_FMC_130M_4CH_CSR_IDELAY1_CAL_VAL_MASK WBGEN2_GEN_MASK(18, 5)
#define WB_FMC_130M_4CH_CSR_IDELAY1_CAL_VAL_SHIFT 18
#define WB_FMC_130M_4CH_CSR_IDELAY1_CAL_VAL_W(value) WBGEN2_GEN_WRITE(value, 18, 5)
#define WB_FMC_130M_4CH_CSR_IDELAY1_CAL_VAL_R(reg) WBGEN2_GEN_READ(reg, 18, 5)

/* definitions for field: Reserved in reg: IDELAY ADC1 calibration */
#define WB_FMC_130M_4CH_CSR_IDELAY1_CAL_RESERVED_MASK WBGEN2_GEN_MASK(23, 9)
#define WB_FMC_130M_4CH_CSR_IDELAY1_CAL_RESERVED_SHIFT 23
#define WB_FMC_130M_4CH_CSR_IDELAY1_CAL_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 23, 9)
#define WB_FMC_130M_4CH_CSR_IDELAY1_CAL_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 23, 9)

/* definitions for register: IDELAY ADC2 calibration */

/* definitions for field: UPDATE in reg: IDELAY ADC2 calibration */
#define WB_FMC_130M_4CH_CSR_IDELAY2_CAL_UPDATE WBGEN2_GEN_MASK(0, 1)

/* definitions for field: LINE in reg: IDELAY ADC2 calibration */
#define WB_FMC_130M_4CH_CSR_IDELAY2_CAL_LINE_MASK WBGEN2_GEN_MASK(1, 17)
#define WB_FMC_130M_4CH_CSR_IDELAY2_CAL_LINE_SHIFT 1
#define WB_FMC_130M_4CH_CSR_IDELAY2_CAL_LINE_W(value) WBGEN2_GEN_WRITE(value, 1, 17)
#define WB_FMC_130M_4CH_CSR_IDELAY2_CAL_LINE_R(reg) WBGEN2_GEN_READ(reg, 1, 17)

/* definitions for field: VAL in reg: IDELAY ADC2 calibration */
#define WB_FMC_130M_4CH_CSR_IDELAY2_CAL_VAL_MASK WBGEN2_GEN_MASK(18, 5)
#define WB_FMC_130M_4CH_CSR_IDELAY2_CAL_VAL_SHIFT 18
#define WB_FMC_130M_4CH_CSR_IDELAY2_CAL_VAL_W(value) WBGEN2_GEN_WRITE(value, 18, 5)
#define WB_FMC_130M_4CH_CSR_IDELAY2_CAL_VAL_R(reg) WBGEN2_GEN_READ(reg, 18, 5)

/* definitions for field: Reserved in reg: IDELAY ADC2 calibration */
#define WB_FMC_130M_4CH_CSR_IDELAY2_CAL_RESERVED_MASK WBGEN2_GEN_MASK(23, 9)
#define WB_FMC_130M_4CH_CSR_IDELAY2_CAL_RESERVED_SHIFT 23
#define WB_FMC_130M_4CH_CSR_IDELAY2_CAL_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 23, 9)
#define WB_FMC_130M_4CH_CSR_IDELAY2_CAL_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 23, 9)

/* definitions for register: IDELAY ADC3 calibration */

/* definitions for field: UPDATE in reg: IDELAY ADC3 calibration */
#define WB_FMC_130M_4CH_CSR_IDELAY3_CAL_UPDATE WBGEN2_GEN_MASK(0, 1)

/* definitions for field: LINE in reg: IDELAY ADC3 calibration */
#define WB_FMC_130M_4CH_CSR_IDELAY3_CAL_LINE_MASK WBGEN2_GEN_MASK(1, 17)
#define WB_FMC_130M_4CH_CSR_IDELAY3_CAL_LINE_SHIFT 1
#define WB_FMC_130M_4CH_CSR_IDELAY3_CAL_LINE_W(value) WBGEN2_GEN_WRITE(value, 1, 17)
#define WB_FMC_130M_4CH_CSR_IDELAY3_CAL_LINE_R(reg) WBGEN2_GEN_READ(reg, 1, 17)

/* definitions for field: VAL in reg: IDELAY ADC3 calibration */
#define WB_FMC_130M_4CH_CSR_IDELAY3_CAL_VAL_MASK WBGEN2_GEN_MASK(18, 5)
#define WB_FMC_130M_4CH_CSR_IDELAY3_CAL_VAL_SHIFT 18
#define WB_FMC_130M_4CH_CSR_IDELAY3_CAL_VAL_W(value) WBGEN2_GEN_WRITE(value, 18, 5)
#define WB_FMC_130M_4CH_CSR_IDELAY3_CAL_VAL_R(reg) WBGEN2_GEN_READ(reg, 18, 5)

/* definitions for field: Reserved in reg: IDELAY ADC3 calibration */
#define WB_FMC_130M_4CH_CSR_IDELAY3_CAL_RESERVED_MASK WBGEN2_GEN_MASK(23, 9)
#define WB_FMC_130M_4CH_CSR_IDELAY3_CAL_RESERVED_SHIFT 23
#define WB_FMC_130M_4CH_CSR_IDELAY3_CAL_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 23, 9)
#define WB_FMC_130M_4CH_CSR_IDELAY3_CAL_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 23, 9)

/* definitions for register: ADC Data Channel 0 */

/* definitions for field: DATA0 in reg: ADC Data Channel 0 */
#define WB_FMC_130M_4CH_CSR_DATA0_VAL_MASK    WBGEN2_GEN_MASK(0, 32)
#define WB_FMC_130M_4CH_CSR_DATA0_VAL_SHIFT   0
#define WB_FMC_130M_4CH_CSR_DATA0_VAL_W(value) WBGEN2_GEN_WRITE(value, 0, 32)
#define WB_FMC_130M_4CH_CSR_DATA0_VAL_R(reg)  WBGEN2_GEN_READ(reg, 0, 32)

/* definitions for register: ADC Data Channel 1 */

/* definitions for field: DATA1 in reg: ADC Data Channel 1 */
#define WB_FMC_130M_4CH_CSR_DATA1_VAL_MASK    WBGEN2_GEN_MASK(0, 32)
#define WB_FMC_130M_4CH_CSR_DATA1_VAL_SHIFT   0
#define WB_FMC_130M_4CH_CSR_DATA1_VAL_W(value) WBGEN2_GEN_WRITE(value, 0, 32)
#define WB_FMC_130M_4CH_CSR_DATA1_VAL_R(reg)  WBGEN2_GEN_READ(reg, 0, 32)

/* definitions for register: ADC Data Channel 2 */

/* definitions for field: DATA2 in reg: ADC Data Channel 2 */
#define WB_FMC_130M_4CH_CSR_DATA2_VAL_MASK    WBGEN2_GEN_MASK(0, 32)
#define WB_FMC_130M_4CH_CSR_DATA2_VAL_SHIFT   0
#define WB_FMC_130M_4CH_CSR_DATA2_VAL_W(value) WBGEN2_GEN_WRITE(value, 0, 32)
#define WB_FMC_130M_4CH_CSR_DATA2_VAL_R(reg)  WBGEN2_GEN_READ(reg, 0, 32)

/* definitions for register: ADC Data Channel 3 */

/* definitions for field: DATA3 in reg: ADC Data Channel 3 */
#define WB_FMC_130M_4CH_CSR_DATA3_VAL_MASK    WBGEN2_GEN_MASK(0, 32)
#define WB_FMC_130M_4CH_CSR_DATA3_VAL_SHIFT   0
#define WB_FMC_130M_4CH_CSR_DATA3_VAL_W(value) WBGEN2_GEN_WRITE(value, 0, 32)
#define WB_FMC_130M_4CH_CSR_DATA3_VAL_R(reg)  WBGEN2_GEN_READ(reg, 0, 32)

/* definitions for register: ADC DCM control */

/* definitions for field: ADC_DCM in reg: ADC DCM control */
#define WB_FMC_130M_4CH_CSR_DCM_ADC_EN        WBGEN2_GEN_MASK(0, 1)

/* definitions for field: ADC_PHASE_INC in reg: ADC DCM control */
#define WB_FMC_130M_4CH_CSR_DCM_ADC_PHASE     WBGEN2_GEN_MASK(1, 1)

/* definitions for field: ADC_DCM_DONE in reg: ADC DCM control */
#define WB_FMC_130M_4CH_CSR_DCM_ADC_DONE      WBGEN2_GEN_MASK(2, 1)

/* definitions for field: ADC_DCM_STATUS0 in reg: ADC DCM control */
#define WB_FMC_130M_4CH_CSR_DCM_ADC_STATUS0   WBGEN2_GEN_MASK(3, 1)

/* definitions for field: ADC_RESET in reg: ADC DCM control */
#define WB_FMC_130M_4CH_CSR_DCM_ADC_RESET     WBGEN2_GEN_MASK(4, 1)

/* definitions for field: Reserved in reg: ADC DCM control */
#define WB_FMC_130M_4CH_CSR_DCM_RESERVED_MASK WBGEN2_GEN_MASK(5, 27)
#define WB_FMC_130M_4CH_CSR_DCM_RESERVED_SHIFT 5
#define WB_FMC_130M_4CH_CSR_DCM_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 5, 27)
#define WB_FMC_130M_4CH_CSR_DCM_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 5, 27)
/* [0x0]: REG ADC LTC2208 control register (4 chips) */
#define WB_FMC_130M_4CH_CSR_REG_ADC 0x00000000
/* [0x4]: REG FPGA control */
#define WB_FMC_130M_4CH_CSR_REG_FPGA_CTRL 0x00000004
/* [0x8]: REG IDELAY ADC0 calibration */
#define WB_FMC_130M_4CH_CSR_REG_IDELAY0_CAL 0x00000008
/* [0xc]: REG IDELAY ADC1 calibration */
#define WB_FMC_130M_4CH_CSR_REG_IDELAY1_CAL 0x0000000c
/* [0x10]: REG IDELAY ADC2 calibration */
#define WB_FMC_130M_4CH_CSR_REG_IDELAY2_CAL 0x00000010
/* [0x14]: REG IDELAY ADC3 calibration */
#define WB_FMC_130M_4CH_CSR_REG_IDELAY3_CAL 0x00000014
/* [0x18]: REG ADC Data Channel 0 */
#define WB_FMC_130M_4CH_CSR_REG_DATA0 0x00000018
/* [0x1c]: REG ADC Data Channel 1 */
#define WB_FMC_130M_4CH_CSR_REG_DATA1 0x0000001c
/* [0x20]: REG ADC Data Channel 2 */
#define WB_FMC_130M_4CH_CSR_REG_DATA2 0x00000020
/* [0x24]: REG ADC Data Channel 3 */
#define WB_FMC_130M_4CH_CSR_REG_DATA3 0x00000024
/* [0x28]: REG ADC DCM control */
#define WB_FMC_130M_4CH_CSR_REG_DCM 0x00000028
#endif
