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-- Title          : Wishbone slave core for FMC Active Clock registers
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-- File           : wb_fmc_active_clk_regs_pkg.vhd
-- Author         : auto-generated by wbgen2 from wb_fmc_active_clk_regs.wb
-- Created        : Mon Apr 18 10:20:28 2016
-- Standard       : VHDL'87
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-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wb_fmc_active_clk_regs.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

package wb_fmc_active_clk_csr_wbgen2_pkg is
  
  
  -- Input registers (user design -> WB slave)
  
  type t_wb_fmc_active_clk_csr_in_registers is record
    clk_distrib_pll_status_i                 : std_logic;
    clk_distrib_reserved_i                   : std_logic_vector(27 downto 0);
    dummy_reserved_i                         : std_logic_vector(31 downto 0);
    end record;
  
  constant c_wb_fmc_active_clk_csr_in_registers_init_value: t_wb_fmc_active_clk_csr_in_registers := (
    clk_distrib_pll_status_i => '0',
    clk_distrib_reserved_i => (others => '0'),
    dummy_reserved_i => (others => '0')
    );
    
    -- Output registers (WB slave -> user design)
    
    type t_wb_fmc_active_clk_csr_out_registers is record
      clk_distrib_si571_oe_o                   : std_logic;
      clk_distrib_pll_function_o               : std_logic;
      clk_distrib_clk_sel_o                    : std_logic;
      end record;
    
    constant c_wb_fmc_active_clk_csr_out_registers_init_value: t_wb_fmc_active_clk_csr_out_registers := (
      clk_distrib_si571_oe_o => '0',
      clk_distrib_pll_function_o => '0',
      clk_distrib_clk_sel_o => '0'
      );
    function "or" (left, right: t_wb_fmc_active_clk_csr_in_registers) return t_wb_fmc_active_clk_csr_in_registers;
    function f_x_to_zero (x:std_logic) return std_logic;
    function f_x_to_zero (x:std_logic_vector) return std_logic_vector;
end package;

package body wb_fmc_active_clk_csr_wbgen2_pkg is
function f_x_to_zero (x:std_logic) return std_logic is
begin
if x = '1' then
return '1';
else
return '0';
end if;
end function;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector is
variable tmp: std_logic_vector(x'length-1 downto 0);
begin
for i in 0 to x'length-1 loop
if(x(i) = 'X' or x(i) = 'U') then
tmp(i):= '0';
else
tmp(i):=x(i);
end if; 
end loop; 
return tmp;
end function;
function "or" (left, right: t_wb_fmc_active_clk_csr_in_registers) return t_wb_fmc_active_clk_csr_in_registers is
variable tmp: t_wb_fmc_active_clk_csr_in_registers;
begin
tmp.clk_distrib_pll_status_i := f_x_to_zero(left.clk_distrib_pll_status_i) or f_x_to_zero(right.clk_distrib_pll_status_i);
tmp.clk_distrib_reserved_i := f_x_to_zero(left.clk_distrib_reserved_i) or f_x_to_zero(right.clk_distrib_reserved_i);
tmp.dummy_reserved_i := f_x_to_zero(left.dummy_reserved_i) or f_x_to_zero(right.dummy_reserved_i);
return tmp;
end function;
end package body;
