/*
  Register definitions for slave core: FMC ADC Common registers

  * File           : wb_fmc_adc_common_regs.h
  * Author         : auto-generated by wbgen2 from wb_fmc_adc_common_regs.wb
  * Created        : Mon Apr 18 09:02:33 2016
  * Standard       : ANSI C

    THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wb_fmc_adc_common_regs.wb
    DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!

*/

#ifndef __WBGEN2_REGDEFS_WB_FMC_ADC_COMMON_REGS_WB
#define __WBGEN2_REGDEFS_WB_FMC_ADC_COMMON_REGS_WB

#include <inttypes.h>

#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
#else
#error "Unsupported compiler?"
#endif

#ifndef __WBGEN2_MACROS_DEFINED__
#define __WBGEN2_MACROS_DEFINED__
#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
#endif


/* definitions for register: Status register */

/* definitions for field: MMCM locked status in reg: Status register */
#define WB_FMC_ADC_COMMON_CSR_FMC_STATUS_MMCM_LOCKED WBGEN2_GEN_MASK(0, 1)

/* definitions for field: FMC power good status in reg: Status register */
#define WB_FMC_ADC_COMMON_CSR_FMC_STATUS_PWR_GOOD WBGEN2_GEN_MASK(1, 1)

/* definitions for field: FMC board present status in reg: Status register */
#define WB_FMC_ADC_COMMON_CSR_FMC_STATUS_PRST WBGEN2_GEN_MASK(2, 1)

/* definitions for field: Reserved in reg: Status register */
#define WB_FMC_ADC_COMMON_CSR_FMC_STATUS_RESERVED_MASK WBGEN2_GEN_MASK(3, 28)
#define WB_FMC_ADC_COMMON_CSR_FMC_STATUS_RESERVED_SHIFT 3
#define WB_FMC_ADC_COMMON_CSR_FMC_STATUS_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 3, 28)
#define WB_FMC_ADC_COMMON_CSR_FMC_STATUS_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 3, 28)

/* definitions for register: Trigger control */

/* definitions for field: Direction in reg: Trigger control */
#define WB_FMC_ADC_COMMON_CSR_TRIGGER_DIR     WBGEN2_GEN_MASK(0, 1)

/* definitions for field: Termination Control in reg: Trigger control */
#define WB_FMC_ADC_COMMON_CSR_TRIGGER_TERM    WBGEN2_GEN_MASK(1, 1)

/* definitions for field: Trigger Value in reg: Trigger control */
#define WB_FMC_ADC_COMMON_CSR_TRIGGER_TRIG_VAL WBGEN2_GEN_MASK(2, 1)

/* definitions for field: Reserved in reg: Trigger control */
#define WB_FMC_ADC_COMMON_CSR_TRIGGER_RESERVED_MASK WBGEN2_GEN_MASK(3, 29)
#define WB_FMC_ADC_COMMON_CSR_TRIGGER_RESERVED_SHIFT 3
#define WB_FMC_ADC_COMMON_CSR_TRIGGER_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 3, 29)
#define WB_FMC_ADC_COMMON_CSR_TRIGGER_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 3, 29)

/* definitions for register: Monitor and FMC status control register */

/* definitions for field: Enable test data in reg: Monitor and FMC status control register */
#define WB_FMC_ADC_COMMON_CSR_MONITOR_TEST_DATA_EN WBGEN2_GEN_MASK(0, 1)

/* definitions for field: Led 1 in reg: Monitor and FMC status control register */
#define WB_FMC_ADC_COMMON_CSR_MONITOR_LED1    WBGEN2_GEN_MASK(1, 1)

/* definitions for field: Led 2 in reg: Monitor and FMC status control register */
#define WB_FMC_ADC_COMMON_CSR_MONITOR_LED2    WBGEN2_GEN_MASK(2, 1)

/* definitions for field: Led 3 in reg: Monitor and FMC status control register */
#define WB_FMC_ADC_COMMON_CSR_MONITOR_LED3    WBGEN2_GEN_MASK(3, 1)

/* definitions for field: Reserved in reg: Monitor and FMC status control register */
#define WB_FMC_ADC_COMMON_CSR_MONITOR_RESERVED_MASK WBGEN2_GEN_MASK(4, 28)
#define WB_FMC_ADC_COMMON_CSR_MONITOR_RESERVED_SHIFT 4
#define WB_FMC_ADC_COMMON_CSR_MONITOR_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 4, 28)
#define WB_FMC_ADC_COMMON_CSR_MONITOR_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 4, 28)
/* [0x0]: REG Status register */
#define WB_FMC_ADC_COMMON_CSR_REG_FMC_STATUS 0x00000000
/* [0x4]: REG Trigger control */
#define WB_FMC_ADC_COMMON_CSR_REG_TRIGGER 0x00000004
/* [0x8]: REG Monitor and FMC status control register */
#define WB_FMC_ADC_COMMON_CSR_REG_MONITOR 0x00000008
#endif
