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-- Title          : Wishbone slave core for Control and status register for the MLVDS trigger
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-- File           : wb_trigger_iface_regs.vhd
-- Author         : auto-generated by wbgen2 from wb_trigger_iface.wb
-- Created        : Fri May 20 13:37:25 2016
-- Standard       : VHDL'87
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-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wb_trigger_iface.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

use work.wb_trig_iface_wbgen2_pkg.all;


entity wb_trigger_iface_regs is
  port (
    rst_n_i                                  : in     std_logic;
    clk_sys_i                                : in     std_logic;
    wb_adr_i                                 : in     std_logic_vector(6 downto 0);
    wb_dat_i                                 : in     std_logic_vector(31 downto 0);
    wb_dat_o                                 : out    std_logic_vector(31 downto 0);
    wb_cyc_i                                 : in     std_logic;
    wb_sel_i                                 : in     std_logic_vector(3 downto 0);
    wb_stb_i                                 : in     std_logic;
    wb_we_i                                  : in     std_logic;
    wb_ack_o                                 : out    std_logic;
    wb_stall_o                               : out    std_logic;
    fs_clk_i                                 : in     std_logic;
    wb_clk_i                                 : in     std_logic;
    regs_i                                   : in     t_wb_trig_iface_in_registers;
    regs_o                                   : out    t_wb_trig_iface_out_registers
  );
end wb_trigger_iface_regs;

architecture syn of wb_trigger_iface_regs is

signal wb_trig_iface_ch0_ctl_dir_int            : std_logic      ;
signal wb_trig_iface_ch0_ctl_dir_pol_int        : std_logic      ;
signal wb_trig_iface_ch0_ctl_rcv_count_rst_int  : std_logic      ;
signal wb_trig_iface_ch0_ctl_rcv_count_rst_int_delay : std_logic      ;
signal wb_trig_iface_ch0_ctl_rcv_count_rst_sync0 : std_logic      ;
signal wb_trig_iface_ch0_ctl_rcv_count_rst_sync1 : std_logic      ;
signal wb_trig_iface_ch0_ctl_rcv_count_rst_sync2 : std_logic      ;
signal wb_trig_iface_ch0_ctl_transm_count_rst_int : std_logic      ;
signal wb_trig_iface_ch0_ctl_transm_count_rst_int_delay : std_logic      ;
signal wb_trig_iface_ch0_ctl_transm_count_rst_sync0 : std_logic      ;
signal wb_trig_iface_ch0_ctl_transm_count_rst_sync1 : std_logic      ;
signal wb_trig_iface_ch0_ctl_transm_count_rst_sync2 : std_logic      ;
signal wb_trig_iface_ch0_cfg_rcv_len_int        : std_logic_vector(7 downto 0);
signal wb_trig_iface_ch0_cfg_rcv_len_swb        : std_logic      ;
signal wb_trig_iface_ch0_cfg_rcv_len_swb_delay  : std_logic      ;
signal wb_trig_iface_ch0_cfg_rcv_len_swb_s0     : std_logic      ;
signal wb_trig_iface_ch0_cfg_rcv_len_swb_s1     : std_logic      ;
signal wb_trig_iface_ch0_cfg_rcv_len_swb_s2     : std_logic      ;
signal wb_trig_iface_ch0_cfg_transm_len_int     : std_logic_vector(7 downto 0);
signal wb_trig_iface_ch0_cfg_transm_len_swb     : std_logic      ;
signal wb_trig_iface_ch0_cfg_transm_len_swb_delay : std_logic      ;
signal wb_trig_iface_ch0_cfg_transm_len_swb_s0  : std_logic      ;
signal wb_trig_iface_ch0_cfg_transm_len_swb_s1  : std_logic      ;
signal wb_trig_iface_ch0_cfg_transm_len_swb_s2  : std_logic      ;
signal wb_trig_iface_ch0_count_rcv_int          : std_logic_vector(15 downto 0);
signal wb_trig_iface_ch0_count_rcv_lwb          : std_logic      ;
signal wb_trig_iface_ch0_count_rcv_lwb_delay    : std_logic      ;
signal wb_trig_iface_ch0_count_rcv_lwb_in_progress : std_logic      ;
signal wb_trig_iface_ch0_count_rcv_lwb_s0       : std_logic      ;
signal wb_trig_iface_ch0_count_rcv_lwb_s1       : std_logic      ;
signal wb_trig_iface_ch0_count_rcv_lwb_s2       : std_logic      ;
signal wb_trig_iface_ch0_count_transm_int       : std_logic_vector(15 downto 0);
signal wb_trig_iface_ch0_count_transm_lwb       : std_logic      ;
signal wb_trig_iface_ch0_count_transm_lwb_delay : std_logic      ;
signal wb_trig_iface_ch0_count_transm_lwb_in_progress : std_logic      ;
signal wb_trig_iface_ch0_count_transm_lwb_s0    : std_logic      ;
signal wb_trig_iface_ch0_count_transm_lwb_s1    : std_logic      ;
signal wb_trig_iface_ch0_count_transm_lwb_s2    : std_logic      ;
signal wb_trig_iface_ch1_ctl_dir_int            : std_logic      ;
signal wb_trig_iface_ch1_ctl_dir_pol_int        : std_logic      ;
signal wb_trig_iface_ch1_ctl_rcv_count_rst_int  : std_logic      ;
signal wb_trig_iface_ch1_ctl_rcv_count_rst_int_delay : std_logic      ;
signal wb_trig_iface_ch1_ctl_rcv_count_rst_sync0 : std_logic      ;
signal wb_trig_iface_ch1_ctl_rcv_count_rst_sync1 : std_logic      ;
signal wb_trig_iface_ch1_ctl_rcv_count_rst_sync2 : std_logic      ;
signal wb_trig_iface_ch1_ctl_transm_count_rst_int : std_logic      ;
signal wb_trig_iface_ch1_ctl_transm_count_rst_int_delay : std_logic      ;
signal wb_trig_iface_ch1_ctl_transm_count_rst_sync0 : std_logic      ;
signal wb_trig_iface_ch1_ctl_transm_count_rst_sync1 : std_logic      ;
signal wb_trig_iface_ch1_ctl_transm_count_rst_sync2 : std_logic      ;
signal wb_trig_iface_ch1_cfg_rcv_len_int        : std_logic_vector(7 downto 0);
signal wb_trig_iface_ch1_cfg_rcv_len_swb        : std_logic      ;
signal wb_trig_iface_ch1_cfg_rcv_len_swb_delay  : std_logic      ;
signal wb_trig_iface_ch1_cfg_rcv_len_swb_s0     : std_logic      ;
signal wb_trig_iface_ch1_cfg_rcv_len_swb_s1     : std_logic      ;
signal wb_trig_iface_ch1_cfg_rcv_len_swb_s2     : std_logic      ;
signal wb_trig_iface_ch1_cfg_transm_len_int     : std_logic_vector(7 downto 0);
signal wb_trig_iface_ch1_cfg_transm_len_swb     : std_logic      ;
signal wb_trig_iface_ch1_cfg_transm_len_swb_delay : std_logic      ;
signal wb_trig_iface_ch1_cfg_transm_len_swb_s0  : std_logic      ;
signal wb_trig_iface_ch1_cfg_transm_len_swb_s1  : std_logic      ;
signal wb_trig_iface_ch1_cfg_transm_len_swb_s2  : std_logic      ;
signal wb_trig_iface_ch1_count_rcv_int          : std_logic_vector(15 downto 0);
signal wb_trig_iface_ch1_count_rcv_lwb          : std_logic      ;
signal wb_trig_iface_ch1_count_rcv_lwb_delay    : std_logic      ;
signal wb_trig_iface_ch1_count_rcv_lwb_in_progress : std_logic      ;
signal wb_trig_iface_ch1_count_rcv_lwb_s0       : std_logic      ;
signal wb_trig_iface_ch1_count_rcv_lwb_s1       : std_logic      ;
signal wb_trig_iface_ch1_count_rcv_lwb_s2       : std_logic      ;
signal wb_trig_iface_ch1_count_transm_int       : std_logic_vector(15 downto 0);
signal wb_trig_iface_ch1_count_transm_lwb       : std_logic      ;
signal wb_trig_iface_ch1_count_transm_lwb_delay : std_logic      ;
signal wb_trig_iface_ch1_count_transm_lwb_in_progress : std_logic      ;
signal wb_trig_iface_ch1_count_transm_lwb_s0    : std_logic      ;
signal wb_trig_iface_ch1_count_transm_lwb_s1    : std_logic      ;
signal wb_trig_iface_ch1_count_transm_lwb_s2    : std_logic      ;
signal wb_trig_iface_ch2_ctl_dir_int            : std_logic      ;
signal wb_trig_iface_ch2_ctl_dir_pol_int        : std_logic      ;
signal wb_trig_iface_ch2_ctl_rcv_count_rst_int  : std_logic      ;
signal wb_trig_iface_ch2_ctl_rcv_count_rst_int_delay : std_logic      ;
signal wb_trig_iface_ch2_ctl_rcv_count_rst_sync0 : std_logic      ;
signal wb_trig_iface_ch2_ctl_rcv_count_rst_sync1 : std_logic      ;
signal wb_trig_iface_ch2_ctl_rcv_count_rst_sync2 : std_logic      ;
signal wb_trig_iface_ch2_ctl_transm_count_rst_int : std_logic      ;
signal wb_trig_iface_ch2_ctl_transm_count_rst_int_delay : std_logic      ;
signal wb_trig_iface_ch2_ctl_transm_count_rst_sync0 : std_logic      ;
signal wb_trig_iface_ch2_ctl_transm_count_rst_sync1 : std_logic      ;
signal wb_trig_iface_ch2_ctl_transm_count_rst_sync2 : std_logic      ;
signal wb_trig_iface_ch2_cfg_rcv_len_int        : std_logic_vector(7 downto 0);
signal wb_trig_iface_ch2_cfg_rcv_len_swb        : std_logic      ;
signal wb_trig_iface_ch2_cfg_rcv_len_swb_delay  : std_logic      ;
signal wb_trig_iface_ch2_cfg_rcv_len_swb_s0     : std_logic      ;
signal wb_trig_iface_ch2_cfg_rcv_len_swb_s1     : std_logic      ;
signal wb_trig_iface_ch2_cfg_rcv_len_swb_s2     : std_logic      ;
signal wb_trig_iface_ch2_cfg_transm_len_int     : std_logic_vector(7 downto 0);
signal wb_trig_iface_ch2_cfg_transm_len_swb     : std_logic      ;
signal wb_trig_iface_ch2_cfg_transm_len_swb_delay : std_logic      ;
signal wb_trig_iface_ch2_cfg_transm_len_swb_s0  : std_logic      ;
signal wb_trig_iface_ch2_cfg_transm_len_swb_s1  : std_logic      ;
signal wb_trig_iface_ch2_cfg_transm_len_swb_s2  : std_logic      ;
signal wb_trig_iface_ch2_count_rcv_int          : std_logic_vector(15 downto 0);
signal wb_trig_iface_ch2_count_rcv_lwb          : std_logic      ;
signal wb_trig_iface_ch2_count_rcv_lwb_delay    : std_logic      ;
signal wb_trig_iface_ch2_count_rcv_lwb_in_progress : std_logic      ;
signal wb_trig_iface_ch2_count_rcv_lwb_s0       : std_logic      ;
signal wb_trig_iface_ch2_count_rcv_lwb_s1       : std_logic      ;
signal wb_trig_iface_ch2_count_rcv_lwb_s2       : std_logic      ;
signal wb_trig_iface_ch2_count_transm_int       : std_logic_vector(15 downto 0);
signal wb_trig_iface_ch2_count_transm_lwb       : std_logic      ;
signal wb_trig_iface_ch2_count_transm_lwb_delay : std_logic      ;
signal wb_trig_iface_ch2_count_transm_lwb_in_progress : std_logic      ;
signal wb_trig_iface_ch2_count_transm_lwb_s0    : std_logic      ;
signal wb_trig_iface_ch2_count_transm_lwb_s1    : std_logic      ;
signal wb_trig_iface_ch2_count_transm_lwb_s2    : std_logic      ;
signal wb_trig_iface_ch3_ctl_dir_int            : std_logic      ;
signal wb_trig_iface_ch3_ctl_dir_pol_int        : std_logic      ;
signal wb_trig_iface_ch3_ctl_rcv_count_rst_int  : std_logic      ;
signal wb_trig_iface_ch3_ctl_rcv_count_rst_int_delay : std_logic      ;
signal wb_trig_iface_ch3_ctl_rcv_count_rst_sync0 : std_logic      ;
signal wb_trig_iface_ch3_ctl_rcv_count_rst_sync1 : std_logic      ;
signal wb_trig_iface_ch3_ctl_rcv_count_rst_sync2 : std_logic      ;
signal wb_trig_iface_ch3_ctl_transm_count_rst_int : std_logic      ;
signal wb_trig_iface_ch3_ctl_transm_count_rst_int_delay : std_logic      ;
signal wb_trig_iface_ch3_ctl_transm_count_rst_sync0 : std_logic      ;
signal wb_trig_iface_ch3_ctl_transm_count_rst_sync1 : std_logic      ;
signal wb_trig_iface_ch3_ctl_transm_count_rst_sync2 : std_logic      ;
signal wb_trig_iface_ch3_cfg_rcv_len_int        : std_logic_vector(7 downto 0);
signal wb_trig_iface_ch3_cfg_rcv_len_swb        : std_logic      ;
signal wb_trig_iface_ch3_cfg_rcv_len_swb_delay  : std_logic      ;
signal wb_trig_iface_ch3_cfg_rcv_len_swb_s0     : std_logic      ;
signal wb_trig_iface_ch3_cfg_rcv_len_swb_s1     : std_logic      ;
signal wb_trig_iface_ch3_cfg_rcv_len_swb_s2     : std_logic      ;
signal wb_trig_iface_ch3_cfg_transm_len_int     : std_logic_vector(7 downto 0);
signal wb_trig_iface_ch3_cfg_transm_len_swb     : std_logic      ;
signal wb_trig_iface_ch3_cfg_transm_len_swb_delay : std_logic      ;
signal wb_trig_iface_ch3_cfg_transm_len_swb_s0  : std_logic      ;
signal wb_trig_iface_ch3_cfg_transm_len_swb_s1  : std_logic      ;
signal wb_trig_iface_ch3_cfg_transm_len_swb_s2  : std_logic      ;
signal wb_trig_iface_ch3_count_rcv_int          : std_logic_vector(15 downto 0);
signal wb_trig_iface_ch3_count_rcv_lwb          : std_logic      ;
signal wb_trig_iface_ch3_count_rcv_lwb_delay    : std_logic      ;
signal wb_trig_iface_ch3_count_rcv_lwb_in_progress : std_logic      ;
signal wb_trig_iface_ch3_count_rcv_lwb_s0       : std_logic      ;
signal wb_trig_iface_ch3_count_rcv_lwb_s1       : std_logic      ;
signal wb_trig_iface_ch3_count_rcv_lwb_s2       : std_logic      ;
signal wb_trig_iface_ch3_count_transm_int       : std_logic_vector(15 downto 0);
signal wb_trig_iface_ch3_count_transm_lwb       : std_logic      ;
signal wb_trig_iface_ch3_count_transm_lwb_delay : std_logic      ;
signal wb_trig_iface_ch3_count_transm_lwb_in_progress : std_logic      ;
signal wb_trig_iface_ch3_count_transm_lwb_s0    : std_logic      ;
signal wb_trig_iface_ch3_count_transm_lwb_s1    : std_logic      ;
signal wb_trig_iface_ch3_count_transm_lwb_s2    : std_logic      ;
signal wb_trig_iface_ch4_ctl_dir_int            : std_logic      ;
signal wb_trig_iface_ch4_ctl_dir_pol_int        : std_logic      ;
signal wb_trig_iface_ch4_ctl_rcv_count_rst_int  : std_logic      ;
signal wb_trig_iface_ch4_ctl_rcv_count_rst_int_delay : std_logic      ;
signal wb_trig_iface_ch4_ctl_rcv_count_rst_sync0 : std_logic      ;
signal wb_trig_iface_ch4_ctl_rcv_count_rst_sync1 : std_logic      ;
signal wb_trig_iface_ch4_ctl_rcv_count_rst_sync2 : std_logic      ;
signal wb_trig_iface_ch4_ctl_transm_count_rst_int : std_logic      ;
signal wb_trig_iface_ch4_ctl_transm_count_rst_int_delay : std_logic      ;
signal wb_trig_iface_ch4_ctl_transm_count_rst_sync0 : std_logic      ;
signal wb_trig_iface_ch4_ctl_transm_count_rst_sync1 : std_logic      ;
signal wb_trig_iface_ch4_ctl_transm_count_rst_sync2 : std_logic      ;
signal wb_trig_iface_ch4_cfg_rcv_len_int        : std_logic_vector(7 downto 0);
signal wb_trig_iface_ch4_cfg_rcv_len_swb        : std_logic      ;
signal wb_trig_iface_ch4_cfg_rcv_len_swb_delay  : std_logic      ;
signal wb_trig_iface_ch4_cfg_rcv_len_swb_s0     : std_logic      ;
signal wb_trig_iface_ch4_cfg_rcv_len_swb_s1     : std_logic      ;
signal wb_trig_iface_ch4_cfg_rcv_len_swb_s2     : std_logic      ;
signal wb_trig_iface_ch4_cfg_transm_len_int     : std_logic_vector(7 downto 0);
signal wb_trig_iface_ch4_cfg_transm_len_swb     : std_logic      ;
signal wb_trig_iface_ch4_cfg_transm_len_swb_delay : std_logic      ;
signal wb_trig_iface_ch4_cfg_transm_len_swb_s0  : std_logic      ;
signal wb_trig_iface_ch4_cfg_transm_len_swb_s1  : std_logic      ;
signal wb_trig_iface_ch4_cfg_transm_len_swb_s2  : std_logic      ;
signal wb_trig_iface_ch4_count_rcv_int          : std_logic_vector(15 downto 0);
signal wb_trig_iface_ch4_count_rcv_lwb          : std_logic      ;
signal wb_trig_iface_ch4_count_rcv_lwb_delay    : std_logic      ;
signal wb_trig_iface_ch4_count_rcv_lwb_in_progress : std_logic      ;
signal wb_trig_iface_ch4_count_rcv_lwb_s0       : std_logic      ;
signal wb_trig_iface_ch4_count_rcv_lwb_s1       : std_logic      ;
signal wb_trig_iface_ch4_count_rcv_lwb_s2       : std_logic      ;
signal wb_trig_iface_ch4_count_transm_int       : std_logic_vector(15 downto 0);
signal wb_trig_iface_ch4_count_transm_lwb       : std_logic      ;
signal wb_trig_iface_ch4_count_transm_lwb_delay : std_logic      ;
signal wb_trig_iface_ch4_count_transm_lwb_in_progress : std_logic      ;
signal wb_trig_iface_ch4_count_transm_lwb_s0    : std_logic      ;
signal wb_trig_iface_ch4_count_transm_lwb_s1    : std_logic      ;
signal wb_trig_iface_ch4_count_transm_lwb_s2    : std_logic      ;
signal wb_trig_iface_ch5_ctl_dir_int            : std_logic      ;
signal wb_trig_iface_ch5_ctl_dir_pol_int        : std_logic      ;
signal wb_trig_iface_ch5_ctl_rcv_count_rst_int  : std_logic      ;
signal wb_trig_iface_ch5_ctl_rcv_count_rst_int_delay : std_logic      ;
signal wb_trig_iface_ch5_ctl_rcv_count_rst_sync0 : std_logic      ;
signal wb_trig_iface_ch5_ctl_rcv_count_rst_sync1 : std_logic      ;
signal wb_trig_iface_ch5_ctl_rcv_count_rst_sync2 : std_logic      ;
signal wb_trig_iface_ch5_ctl_transm_count_rst_int : std_logic      ;
signal wb_trig_iface_ch5_ctl_transm_count_rst_int_delay : std_logic      ;
signal wb_trig_iface_ch5_ctl_transm_count_rst_sync0 : std_logic      ;
signal wb_trig_iface_ch5_ctl_transm_count_rst_sync1 : std_logic      ;
signal wb_trig_iface_ch5_ctl_transm_count_rst_sync2 : std_logic      ;
signal wb_trig_iface_ch5_cfg_rcv_len_int        : std_logic_vector(7 downto 0);
signal wb_trig_iface_ch5_cfg_rcv_len_swb        : std_logic      ;
signal wb_trig_iface_ch5_cfg_rcv_len_swb_delay  : std_logic      ;
signal wb_trig_iface_ch5_cfg_rcv_len_swb_s0     : std_logic      ;
signal wb_trig_iface_ch5_cfg_rcv_len_swb_s1     : std_logic      ;
signal wb_trig_iface_ch5_cfg_rcv_len_swb_s2     : std_logic      ;
signal wb_trig_iface_ch5_cfg_transm_len_int     : std_logic_vector(7 downto 0);
signal wb_trig_iface_ch5_cfg_transm_len_swb     : std_logic      ;
signal wb_trig_iface_ch5_cfg_transm_len_swb_delay : std_logic      ;
signal wb_trig_iface_ch5_cfg_transm_len_swb_s0  : std_logic      ;
signal wb_trig_iface_ch5_cfg_transm_len_swb_s1  : std_logic      ;
signal wb_trig_iface_ch5_cfg_transm_len_swb_s2  : std_logic      ;
signal wb_trig_iface_ch5_count_rcv_int          : std_logic_vector(15 downto 0);
signal wb_trig_iface_ch5_count_rcv_lwb          : std_logic      ;
signal wb_trig_iface_ch5_count_rcv_lwb_delay    : std_logic      ;
signal wb_trig_iface_ch5_count_rcv_lwb_in_progress : std_logic      ;
signal wb_trig_iface_ch5_count_rcv_lwb_s0       : std_logic      ;
signal wb_trig_iface_ch5_count_rcv_lwb_s1       : std_logic      ;
signal wb_trig_iface_ch5_count_rcv_lwb_s2       : std_logic      ;
signal wb_trig_iface_ch5_count_transm_int       : std_logic_vector(15 downto 0);
signal wb_trig_iface_ch5_count_transm_lwb       : std_logic      ;
signal wb_trig_iface_ch5_count_transm_lwb_delay : std_logic      ;
signal wb_trig_iface_ch5_count_transm_lwb_in_progress : std_logic      ;
signal wb_trig_iface_ch5_count_transm_lwb_s0    : std_logic      ;
signal wb_trig_iface_ch5_count_transm_lwb_s1    : std_logic      ;
signal wb_trig_iface_ch5_count_transm_lwb_s2    : std_logic      ;
signal wb_trig_iface_ch6_ctl_dir_int            : std_logic      ;
signal wb_trig_iface_ch6_ctl_dir_pol_int        : std_logic      ;
signal wb_trig_iface_ch6_ctl_rcv_count_rst_int  : std_logic      ;
signal wb_trig_iface_ch6_ctl_rcv_count_rst_int_delay : std_logic      ;
signal wb_trig_iface_ch6_ctl_rcv_count_rst_sync0 : std_logic      ;
signal wb_trig_iface_ch6_ctl_rcv_count_rst_sync1 : std_logic      ;
signal wb_trig_iface_ch6_ctl_rcv_count_rst_sync2 : std_logic      ;
signal wb_trig_iface_ch6_ctl_transm_count_rst_int : std_logic      ;
signal wb_trig_iface_ch6_ctl_transm_count_rst_int_delay : std_logic      ;
signal wb_trig_iface_ch6_ctl_transm_count_rst_sync0 : std_logic      ;
signal wb_trig_iface_ch6_ctl_transm_count_rst_sync1 : std_logic      ;
signal wb_trig_iface_ch6_ctl_transm_count_rst_sync2 : std_logic      ;
signal wb_trig_iface_ch6_cfg_rcv_len_int        : std_logic_vector(7 downto 0);
signal wb_trig_iface_ch6_cfg_rcv_len_swb        : std_logic      ;
signal wb_trig_iface_ch6_cfg_rcv_len_swb_delay  : std_logic      ;
signal wb_trig_iface_ch6_cfg_rcv_len_swb_s0     : std_logic      ;
signal wb_trig_iface_ch6_cfg_rcv_len_swb_s1     : std_logic      ;
signal wb_trig_iface_ch6_cfg_rcv_len_swb_s2     : std_logic      ;
signal wb_trig_iface_ch6_cfg_transm_len_int     : std_logic_vector(7 downto 0);
signal wb_trig_iface_ch6_cfg_transm_len_swb     : std_logic      ;
signal wb_trig_iface_ch6_cfg_transm_len_swb_delay : std_logic      ;
signal wb_trig_iface_ch6_cfg_transm_len_swb_s0  : std_logic      ;
signal wb_trig_iface_ch6_cfg_transm_len_swb_s1  : std_logic      ;
signal wb_trig_iface_ch6_cfg_transm_len_swb_s2  : std_logic      ;
signal wb_trig_iface_ch6_count_rcv_int          : std_logic_vector(15 downto 0);
signal wb_trig_iface_ch6_count_rcv_lwb          : std_logic      ;
signal wb_trig_iface_ch6_count_rcv_lwb_delay    : std_logic      ;
signal wb_trig_iface_ch6_count_rcv_lwb_in_progress : std_logic      ;
signal wb_trig_iface_ch6_count_rcv_lwb_s0       : std_logic      ;
signal wb_trig_iface_ch6_count_rcv_lwb_s1       : std_logic      ;
signal wb_trig_iface_ch6_count_rcv_lwb_s2       : std_logic      ;
signal wb_trig_iface_ch6_count_transm_int       : std_logic_vector(15 downto 0);
signal wb_trig_iface_ch6_count_transm_lwb       : std_logic      ;
signal wb_trig_iface_ch6_count_transm_lwb_delay : std_logic      ;
signal wb_trig_iface_ch6_count_transm_lwb_in_progress : std_logic      ;
signal wb_trig_iface_ch6_count_transm_lwb_s0    : std_logic      ;
signal wb_trig_iface_ch6_count_transm_lwb_s1    : std_logic      ;
signal wb_trig_iface_ch6_count_transm_lwb_s2    : std_logic      ;
signal wb_trig_iface_ch7_ctl_dir_int            : std_logic      ;
signal wb_trig_iface_ch7_ctl_dir_pol_int        : std_logic      ;
signal wb_trig_iface_ch7_ctl_rcv_count_rst_int  : std_logic      ;
signal wb_trig_iface_ch7_ctl_rcv_count_rst_int_delay : std_logic      ;
signal wb_trig_iface_ch7_ctl_rcv_count_rst_sync0 : std_logic      ;
signal wb_trig_iface_ch7_ctl_rcv_count_rst_sync1 : std_logic      ;
signal wb_trig_iface_ch7_ctl_rcv_count_rst_sync2 : std_logic      ;
signal wb_trig_iface_ch7_ctl_transm_count_rst_int : std_logic      ;
signal wb_trig_iface_ch7_ctl_transm_count_rst_int_delay : std_logic      ;
signal wb_trig_iface_ch7_ctl_transm_count_rst_sync0 : std_logic      ;
signal wb_trig_iface_ch7_ctl_transm_count_rst_sync1 : std_logic      ;
signal wb_trig_iface_ch7_ctl_transm_count_rst_sync2 : std_logic      ;
signal wb_trig_iface_ch7_cfg_rcv_len_int        : std_logic_vector(7 downto 0);
signal wb_trig_iface_ch7_cfg_rcv_len_swb        : std_logic      ;
signal wb_trig_iface_ch7_cfg_rcv_len_swb_delay  : std_logic      ;
signal wb_trig_iface_ch7_cfg_rcv_len_swb_s0     : std_logic      ;
signal wb_trig_iface_ch7_cfg_rcv_len_swb_s1     : std_logic      ;
signal wb_trig_iface_ch7_cfg_rcv_len_swb_s2     : std_logic      ;
signal wb_trig_iface_ch7_cfg_transm_len_int     : std_logic_vector(7 downto 0);
signal wb_trig_iface_ch7_cfg_transm_len_swb     : std_logic      ;
signal wb_trig_iface_ch7_cfg_transm_len_swb_delay : std_logic      ;
signal wb_trig_iface_ch7_cfg_transm_len_swb_s0  : std_logic      ;
signal wb_trig_iface_ch7_cfg_transm_len_swb_s1  : std_logic      ;
signal wb_trig_iface_ch7_cfg_transm_len_swb_s2  : std_logic      ;
signal wb_trig_iface_ch7_count_rcv_int          : std_logic_vector(15 downto 0);
signal wb_trig_iface_ch7_count_rcv_lwb          : std_logic      ;
signal wb_trig_iface_ch7_count_rcv_lwb_delay    : std_logic      ;
signal wb_trig_iface_ch7_count_rcv_lwb_in_progress : std_logic      ;
signal wb_trig_iface_ch7_count_rcv_lwb_s0       : std_logic      ;
signal wb_trig_iface_ch7_count_rcv_lwb_s1       : std_logic      ;
signal wb_trig_iface_ch7_count_rcv_lwb_s2       : std_logic      ;
signal wb_trig_iface_ch7_count_transm_int       : std_logic_vector(15 downto 0);
signal wb_trig_iface_ch7_count_transm_lwb       : std_logic      ;
signal wb_trig_iface_ch7_count_transm_lwb_delay : std_logic      ;
signal wb_trig_iface_ch7_count_transm_lwb_in_progress : std_logic      ;
signal wb_trig_iface_ch7_count_transm_lwb_s0    : std_logic      ;
signal wb_trig_iface_ch7_count_transm_lwb_s1    : std_logic      ;
signal wb_trig_iface_ch7_count_transm_lwb_s2    : std_logic      ;
signal wb_trig_iface_ch8_ctl_dir_int            : std_logic      ;
signal wb_trig_iface_ch8_ctl_dir_pol_int        : std_logic      ;
signal wb_trig_iface_ch8_ctl_rcv_count_rst_int  : std_logic      ;
signal wb_trig_iface_ch8_ctl_rcv_count_rst_int_delay : std_logic      ;
signal wb_trig_iface_ch8_ctl_rcv_count_rst_sync0 : std_logic      ;
signal wb_trig_iface_ch8_ctl_rcv_count_rst_sync1 : std_logic      ;
signal wb_trig_iface_ch8_ctl_rcv_count_rst_sync2 : std_logic      ;
signal wb_trig_iface_ch8_ctl_transm_count_rst_int : std_logic      ;
signal wb_trig_iface_ch8_ctl_transm_count_rst_int_delay : std_logic      ;
signal wb_trig_iface_ch8_ctl_transm_count_rst_sync0 : std_logic      ;
signal wb_trig_iface_ch8_ctl_transm_count_rst_sync1 : std_logic      ;
signal wb_trig_iface_ch8_ctl_transm_count_rst_sync2 : std_logic      ;
signal wb_trig_iface_ch8_cfg_rcv_len_int        : std_logic_vector(7 downto 0);
signal wb_trig_iface_ch8_cfg_rcv_len_swb        : std_logic      ;
signal wb_trig_iface_ch8_cfg_rcv_len_swb_delay  : std_logic      ;
signal wb_trig_iface_ch8_cfg_rcv_len_swb_s0     : std_logic      ;
signal wb_trig_iface_ch8_cfg_rcv_len_swb_s1     : std_logic      ;
signal wb_trig_iface_ch8_cfg_rcv_len_swb_s2     : std_logic      ;
signal wb_trig_iface_ch8_cfg_transm_len_int     : std_logic_vector(7 downto 0);
signal wb_trig_iface_ch8_cfg_transm_len_swb     : std_logic      ;
signal wb_trig_iface_ch8_cfg_transm_len_swb_delay : std_logic      ;
signal wb_trig_iface_ch8_cfg_transm_len_swb_s0  : std_logic      ;
signal wb_trig_iface_ch8_cfg_transm_len_swb_s1  : std_logic      ;
signal wb_trig_iface_ch8_cfg_transm_len_swb_s2  : std_logic      ;
signal wb_trig_iface_ch8_count_rcv_int          : std_logic_vector(15 downto 0);
signal wb_trig_iface_ch8_count_rcv_lwb          : std_logic      ;
signal wb_trig_iface_ch8_count_rcv_lwb_delay    : std_logic      ;
signal wb_trig_iface_ch8_count_rcv_lwb_in_progress : std_logic      ;
signal wb_trig_iface_ch8_count_rcv_lwb_s0       : std_logic      ;
signal wb_trig_iface_ch8_count_rcv_lwb_s1       : std_logic      ;
signal wb_trig_iface_ch8_count_rcv_lwb_s2       : std_logic      ;
signal wb_trig_iface_ch8_count_transm_int       : std_logic_vector(15 downto 0);
signal wb_trig_iface_ch8_count_transm_lwb       : std_logic      ;
signal wb_trig_iface_ch8_count_transm_lwb_delay : std_logic      ;
signal wb_trig_iface_ch8_count_transm_lwb_in_progress : std_logic      ;
signal wb_trig_iface_ch8_count_transm_lwb_s0    : std_logic      ;
signal wb_trig_iface_ch8_count_transm_lwb_s1    : std_logic      ;
signal wb_trig_iface_ch8_count_transm_lwb_s2    : std_logic      ;
signal wb_trig_iface_ch9_ctl_dir_int            : std_logic      ;
signal wb_trig_iface_ch9_ctl_dir_pol_int        : std_logic      ;
signal wb_trig_iface_ch9_ctl_rcv_count_rst_int  : std_logic      ;
signal wb_trig_iface_ch9_ctl_rcv_count_rst_int_delay : std_logic      ;
signal wb_trig_iface_ch9_ctl_rcv_count_rst_sync0 : std_logic      ;
signal wb_trig_iface_ch9_ctl_rcv_count_rst_sync1 : std_logic      ;
signal wb_trig_iface_ch9_ctl_rcv_count_rst_sync2 : std_logic      ;
signal wb_trig_iface_ch9_ctl_transm_count_rst_int : std_logic      ;
signal wb_trig_iface_ch9_ctl_transm_count_rst_int_delay : std_logic      ;
signal wb_trig_iface_ch9_ctl_transm_count_rst_sync0 : std_logic      ;
signal wb_trig_iface_ch9_ctl_transm_count_rst_sync1 : std_logic      ;
signal wb_trig_iface_ch9_ctl_transm_count_rst_sync2 : std_logic      ;
signal wb_trig_iface_ch9_cfg_rcv_len_int        : std_logic_vector(7 downto 0);
signal wb_trig_iface_ch9_cfg_rcv_len_swb        : std_logic      ;
signal wb_trig_iface_ch9_cfg_rcv_len_swb_delay  : std_logic      ;
signal wb_trig_iface_ch9_cfg_rcv_len_swb_s0     : std_logic      ;
signal wb_trig_iface_ch9_cfg_rcv_len_swb_s1     : std_logic      ;
signal wb_trig_iface_ch9_cfg_rcv_len_swb_s2     : std_logic      ;
signal wb_trig_iface_ch9_cfg_transm_len_int     : std_logic_vector(7 downto 0);
signal wb_trig_iface_ch9_cfg_transm_len_swb     : std_logic      ;
signal wb_trig_iface_ch9_cfg_transm_len_swb_delay : std_logic      ;
signal wb_trig_iface_ch9_cfg_transm_len_swb_s0  : std_logic      ;
signal wb_trig_iface_ch9_cfg_transm_len_swb_s1  : std_logic      ;
signal wb_trig_iface_ch9_cfg_transm_len_swb_s2  : std_logic      ;
signal wb_trig_iface_ch9_count_rcv_int          : std_logic_vector(15 downto 0);
signal wb_trig_iface_ch9_count_rcv_lwb          : std_logic      ;
signal wb_trig_iface_ch9_count_rcv_lwb_delay    : std_logic      ;
signal wb_trig_iface_ch9_count_rcv_lwb_in_progress : std_logic      ;
signal wb_trig_iface_ch9_count_rcv_lwb_s0       : std_logic      ;
signal wb_trig_iface_ch9_count_rcv_lwb_s1       : std_logic      ;
signal wb_trig_iface_ch9_count_rcv_lwb_s2       : std_logic      ;
signal wb_trig_iface_ch9_count_transm_int       : std_logic_vector(15 downto 0);
signal wb_trig_iface_ch9_count_transm_lwb       : std_logic      ;
signal wb_trig_iface_ch9_count_transm_lwb_delay : std_logic      ;
signal wb_trig_iface_ch9_count_transm_lwb_in_progress : std_logic      ;
signal wb_trig_iface_ch9_count_transm_lwb_s0    : std_logic      ;
signal wb_trig_iface_ch9_count_transm_lwb_s1    : std_logic      ;
signal wb_trig_iface_ch9_count_transm_lwb_s2    : std_logic      ;
signal wb_trig_iface_ch10_ctl_dir_int           : std_logic      ;
signal wb_trig_iface_ch10_ctl_dir_pol_int       : std_logic      ;
signal wb_trig_iface_ch10_ctl_rcv_count_rst_int : std_logic      ;
signal wb_trig_iface_ch10_ctl_rcv_count_rst_int_delay : std_logic      ;
signal wb_trig_iface_ch10_ctl_rcv_count_rst_sync0 : std_logic      ;
signal wb_trig_iface_ch10_ctl_rcv_count_rst_sync1 : std_logic      ;
signal wb_trig_iface_ch10_ctl_rcv_count_rst_sync2 : std_logic      ;
signal wb_trig_iface_ch10_ctl_transm_count_rst_int : std_logic      ;
signal wb_trig_iface_ch10_ctl_transm_count_rst_int_delay : std_logic      ;
signal wb_trig_iface_ch10_ctl_transm_count_rst_sync0 : std_logic      ;
signal wb_trig_iface_ch10_ctl_transm_count_rst_sync1 : std_logic      ;
signal wb_trig_iface_ch10_ctl_transm_count_rst_sync2 : std_logic      ;
signal wb_trig_iface_ch10_cfg_rcv_len_int       : std_logic_vector(7 downto 0);
signal wb_trig_iface_ch10_cfg_rcv_len_swb       : std_logic      ;
signal wb_trig_iface_ch10_cfg_rcv_len_swb_delay : std_logic      ;
signal wb_trig_iface_ch10_cfg_rcv_len_swb_s0    : std_logic      ;
signal wb_trig_iface_ch10_cfg_rcv_len_swb_s1    : std_logic      ;
signal wb_trig_iface_ch10_cfg_rcv_len_swb_s2    : std_logic      ;
signal wb_trig_iface_ch10_cfg_transm_len_int    : std_logic_vector(7 downto 0);
signal wb_trig_iface_ch10_cfg_transm_len_swb    : std_logic      ;
signal wb_trig_iface_ch10_cfg_transm_len_swb_delay : std_logic      ;
signal wb_trig_iface_ch10_cfg_transm_len_swb_s0 : std_logic      ;
signal wb_trig_iface_ch10_cfg_transm_len_swb_s1 : std_logic      ;
signal wb_trig_iface_ch10_cfg_transm_len_swb_s2 : std_logic      ;
signal wb_trig_iface_ch10_count_rcv_int         : std_logic_vector(15 downto 0);
signal wb_trig_iface_ch10_count_rcv_lwb         : std_logic      ;
signal wb_trig_iface_ch10_count_rcv_lwb_delay   : std_logic      ;
signal wb_trig_iface_ch10_count_rcv_lwb_in_progress : std_logic      ;
signal wb_trig_iface_ch10_count_rcv_lwb_s0      : std_logic      ;
signal wb_trig_iface_ch10_count_rcv_lwb_s1      : std_logic      ;
signal wb_trig_iface_ch10_count_rcv_lwb_s2      : std_logic      ;
signal wb_trig_iface_ch10_count_transm_int      : std_logic_vector(15 downto 0);
signal wb_trig_iface_ch10_count_transm_lwb      : std_logic      ;
signal wb_trig_iface_ch10_count_transm_lwb_delay : std_logic      ;
signal wb_trig_iface_ch10_count_transm_lwb_in_progress : std_logic      ;
signal wb_trig_iface_ch10_count_transm_lwb_s0   : std_logic      ;
signal wb_trig_iface_ch10_count_transm_lwb_s1   : std_logic      ;
signal wb_trig_iface_ch10_count_transm_lwb_s2   : std_logic      ;
signal wb_trig_iface_ch11_ctl_dir_int           : std_logic      ;
signal wb_trig_iface_ch11_ctl_dir_pol_int       : std_logic      ;
signal wb_trig_iface_ch11_ctl_rcv_count_rst_int : std_logic      ;
signal wb_trig_iface_ch11_ctl_rcv_count_rst_int_delay : std_logic      ;
signal wb_trig_iface_ch11_ctl_rcv_count_rst_sync0 : std_logic      ;
signal wb_trig_iface_ch11_ctl_rcv_count_rst_sync1 : std_logic      ;
signal wb_trig_iface_ch11_ctl_rcv_count_rst_sync2 : std_logic      ;
signal wb_trig_iface_ch11_ctl_transm_count_rst_int : std_logic      ;
signal wb_trig_iface_ch11_ctl_transm_count_rst_int_delay : std_logic      ;
signal wb_trig_iface_ch11_ctl_transm_count_rst_sync0 : std_logic      ;
signal wb_trig_iface_ch11_ctl_transm_count_rst_sync1 : std_logic      ;
signal wb_trig_iface_ch11_ctl_transm_count_rst_sync2 : std_logic      ;
signal wb_trig_iface_ch11_cfg_rcv_len_int       : std_logic_vector(7 downto 0);
signal wb_trig_iface_ch11_cfg_rcv_len_swb       : std_logic      ;
signal wb_trig_iface_ch11_cfg_rcv_len_swb_delay : std_logic      ;
signal wb_trig_iface_ch11_cfg_rcv_len_swb_s0    : std_logic      ;
signal wb_trig_iface_ch11_cfg_rcv_len_swb_s1    : std_logic      ;
signal wb_trig_iface_ch11_cfg_rcv_len_swb_s2    : std_logic      ;
signal wb_trig_iface_ch11_cfg_transm_len_int    : std_logic_vector(7 downto 0);
signal wb_trig_iface_ch11_cfg_transm_len_swb    : std_logic      ;
signal wb_trig_iface_ch11_cfg_transm_len_swb_delay : std_logic      ;
signal wb_trig_iface_ch11_cfg_transm_len_swb_s0 : std_logic      ;
signal wb_trig_iface_ch11_cfg_transm_len_swb_s1 : std_logic      ;
signal wb_trig_iface_ch11_cfg_transm_len_swb_s2 : std_logic      ;
signal wb_trig_iface_ch11_count_rcv_int         : std_logic_vector(15 downto 0);
signal wb_trig_iface_ch11_count_rcv_lwb         : std_logic      ;
signal wb_trig_iface_ch11_count_rcv_lwb_delay   : std_logic      ;
signal wb_trig_iface_ch11_count_rcv_lwb_in_progress : std_logic      ;
signal wb_trig_iface_ch11_count_rcv_lwb_s0      : std_logic      ;
signal wb_trig_iface_ch11_count_rcv_lwb_s1      : std_logic      ;
signal wb_trig_iface_ch11_count_rcv_lwb_s2      : std_logic      ;
signal wb_trig_iface_ch11_count_transm_int      : std_logic_vector(15 downto 0);
signal wb_trig_iface_ch11_count_transm_lwb      : std_logic      ;
signal wb_trig_iface_ch11_count_transm_lwb_delay : std_logic      ;
signal wb_trig_iface_ch11_count_transm_lwb_in_progress : std_logic      ;
signal wb_trig_iface_ch11_count_transm_lwb_s0   : std_logic      ;
signal wb_trig_iface_ch11_count_transm_lwb_s1   : std_logic      ;
signal wb_trig_iface_ch11_count_transm_lwb_s2   : std_logic      ;
signal wb_trig_iface_ch12_ctl_dir_int           : std_logic      ;
signal wb_trig_iface_ch12_ctl_dir_pol_int       : std_logic      ;
signal wb_trig_iface_ch12_ctl_rcv_count_rst_int : std_logic      ;
signal wb_trig_iface_ch12_ctl_rcv_count_rst_int_delay : std_logic      ;
signal wb_trig_iface_ch12_ctl_rcv_count_rst_sync0 : std_logic      ;
signal wb_trig_iface_ch12_ctl_rcv_count_rst_sync1 : std_logic      ;
signal wb_trig_iface_ch12_ctl_rcv_count_rst_sync2 : std_logic      ;
signal wb_trig_iface_ch12_ctl_transm_count_rst_int : std_logic      ;
signal wb_trig_iface_ch12_ctl_transm_count_rst_int_delay : std_logic      ;
signal wb_trig_iface_ch12_ctl_transm_count_rst_sync0 : std_logic      ;
signal wb_trig_iface_ch12_ctl_transm_count_rst_sync1 : std_logic      ;
signal wb_trig_iface_ch12_ctl_transm_count_rst_sync2 : std_logic      ;
signal wb_trig_iface_ch12_cfg_rcv_len_int       : std_logic_vector(7 downto 0);
signal wb_trig_iface_ch12_cfg_rcv_len_swb       : std_logic      ;
signal wb_trig_iface_ch12_cfg_rcv_len_swb_delay : std_logic      ;
signal wb_trig_iface_ch12_cfg_rcv_len_swb_s0    : std_logic      ;
signal wb_trig_iface_ch12_cfg_rcv_len_swb_s1    : std_logic      ;
signal wb_trig_iface_ch12_cfg_rcv_len_swb_s2    : std_logic      ;
signal wb_trig_iface_ch12_cfg_transm_len_int    : std_logic_vector(7 downto 0);
signal wb_trig_iface_ch12_cfg_transm_len_swb    : std_logic      ;
signal wb_trig_iface_ch12_cfg_transm_len_swb_delay : std_logic      ;
signal wb_trig_iface_ch12_cfg_transm_len_swb_s0 : std_logic      ;
signal wb_trig_iface_ch12_cfg_transm_len_swb_s1 : std_logic      ;
signal wb_trig_iface_ch12_cfg_transm_len_swb_s2 : std_logic      ;
signal wb_trig_iface_ch12_count_rcv_int         : std_logic_vector(15 downto 0);
signal wb_trig_iface_ch12_count_rcv_lwb         : std_logic      ;
signal wb_trig_iface_ch12_count_rcv_lwb_delay   : std_logic      ;
signal wb_trig_iface_ch12_count_rcv_lwb_in_progress : std_logic      ;
signal wb_trig_iface_ch12_count_rcv_lwb_s0      : std_logic      ;
signal wb_trig_iface_ch12_count_rcv_lwb_s1      : std_logic      ;
signal wb_trig_iface_ch12_count_rcv_lwb_s2      : std_logic      ;
signal wb_trig_iface_ch12_count_transm_int      : std_logic_vector(15 downto 0);
signal wb_trig_iface_ch12_count_transm_lwb      : std_logic      ;
signal wb_trig_iface_ch12_count_transm_lwb_delay : std_logic      ;
signal wb_trig_iface_ch12_count_transm_lwb_in_progress : std_logic      ;
signal wb_trig_iface_ch12_count_transm_lwb_s0   : std_logic      ;
signal wb_trig_iface_ch12_count_transm_lwb_s1   : std_logic      ;
signal wb_trig_iface_ch12_count_transm_lwb_s2   : std_logic      ;
signal wb_trig_iface_ch13_ctl_dir_int           : std_logic      ;
signal wb_trig_iface_ch13_ctl_dir_pol_int       : std_logic      ;
signal wb_trig_iface_ch13_ctl_rcv_count_rst_int : std_logic      ;
signal wb_trig_iface_ch13_ctl_rcv_count_rst_int_delay : std_logic      ;
signal wb_trig_iface_ch13_ctl_rcv_count_rst_sync0 : std_logic      ;
signal wb_trig_iface_ch13_ctl_rcv_count_rst_sync1 : std_logic      ;
signal wb_trig_iface_ch13_ctl_rcv_count_rst_sync2 : std_logic      ;
signal wb_trig_iface_ch13_ctl_transm_count_rst_int : std_logic      ;
signal wb_trig_iface_ch13_ctl_transm_count_rst_int_delay : std_logic      ;
signal wb_trig_iface_ch13_ctl_transm_count_rst_sync0 : std_logic      ;
signal wb_trig_iface_ch13_ctl_transm_count_rst_sync1 : std_logic      ;
signal wb_trig_iface_ch13_ctl_transm_count_rst_sync2 : std_logic      ;
signal wb_trig_iface_ch13_cfg_rcv_len_int       : std_logic_vector(7 downto 0);
signal wb_trig_iface_ch13_cfg_rcv_len_swb       : std_logic      ;
signal wb_trig_iface_ch13_cfg_rcv_len_swb_delay : std_logic      ;
signal wb_trig_iface_ch13_cfg_rcv_len_swb_s0    : std_logic      ;
signal wb_trig_iface_ch13_cfg_rcv_len_swb_s1    : std_logic      ;
signal wb_trig_iface_ch13_cfg_rcv_len_swb_s2    : std_logic      ;
signal wb_trig_iface_ch13_cfg_transm_len_int    : std_logic_vector(7 downto 0);
signal wb_trig_iface_ch13_cfg_transm_len_swb    : std_logic      ;
signal wb_trig_iface_ch13_cfg_transm_len_swb_delay : std_logic      ;
signal wb_trig_iface_ch13_cfg_transm_len_swb_s0 : std_logic      ;
signal wb_trig_iface_ch13_cfg_transm_len_swb_s1 : std_logic      ;
signal wb_trig_iface_ch13_cfg_transm_len_swb_s2 : std_logic      ;
signal wb_trig_iface_ch13_count_rcv_int         : std_logic_vector(15 downto 0);
signal wb_trig_iface_ch13_count_rcv_lwb         : std_logic      ;
signal wb_trig_iface_ch13_count_rcv_lwb_delay   : std_logic      ;
signal wb_trig_iface_ch13_count_rcv_lwb_in_progress : std_logic      ;
signal wb_trig_iface_ch13_count_rcv_lwb_s0      : std_logic      ;
signal wb_trig_iface_ch13_count_rcv_lwb_s1      : std_logic      ;
signal wb_trig_iface_ch13_count_rcv_lwb_s2      : std_logic      ;
signal wb_trig_iface_ch13_count_transm_int      : std_logic_vector(15 downto 0);
signal wb_trig_iface_ch13_count_transm_lwb      : std_logic      ;
signal wb_trig_iface_ch13_count_transm_lwb_delay : std_logic      ;
signal wb_trig_iface_ch13_count_transm_lwb_in_progress : std_logic      ;
signal wb_trig_iface_ch13_count_transm_lwb_s0   : std_logic      ;
signal wb_trig_iface_ch13_count_transm_lwb_s1   : std_logic      ;
signal wb_trig_iface_ch13_count_transm_lwb_s2   : std_logic      ;
signal wb_trig_iface_ch14_ctl_dir_int           : std_logic      ;
signal wb_trig_iface_ch14_ctl_dir_pol_int       : std_logic      ;
signal wb_trig_iface_ch14_ctl_rcv_count_rst_int : std_logic      ;
signal wb_trig_iface_ch14_ctl_rcv_count_rst_int_delay : std_logic      ;
signal wb_trig_iface_ch14_ctl_rcv_count_rst_sync0 : std_logic      ;
signal wb_trig_iface_ch14_ctl_rcv_count_rst_sync1 : std_logic      ;
signal wb_trig_iface_ch14_ctl_rcv_count_rst_sync2 : std_logic      ;
signal wb_trig_iface_ch14_ctl_transm_count_rst_int : std_logic      ;
signal wb_trig_iface_ch14_ctl_transm_count_rst_int_delay : std_logic      ;
signal wb_trig_iface_ch14_ctl_transm_count_rst_sync0 : std_logic      ;
signal wb_trig_iface_ch14_ctl_transm_count_rst_sync1 : std_logic      ;
signal wb_trig_iface_ch14_ctl_transm_count_rst_sync2 : std_logic      ;
signal wb_trig_iface_ch14_cfg_rcv_len_int       : std_logic_vector(7 downto 0);
signal wb_trig_iface_ch14_cfg_rcv_len_swb       : std_logic      ;
signal wb_trig_iface_ch14_cfg_rcv_len_swb_delay : std_logic      ;
signal wb_trig_iface_ch14_cfg_rcv_len_swb_s0    : std_logic      ;
signal wb_trig_iface_ch14_cfg_rcv_len_swb_s1    : std_logic      ;
signal wb_trig_iface_ch14_cfg_rcv_len_swb_s2    : std_logic      ;
signal wb_trig_iface_ch14_cfg_transm_len_int    : std_logic_vector(7 downto 0);
signal wb_trig_iface_ch14_cfg_transm_len_swb    : std_logic      ;
signal wb_trig_iface_ch14_cfg_transm_len_swb_delay : std_logic      ;
signal wb_trig_iface_ch14_cfg_transm_len_swb_s0 : std_logic      ;
signal wb_trig_iface_ch14_cfg_transm_len_swb_s1 : std_logic      ;
signal wb_trig_iface_ch14_cfg_transm_len_swb_s2 : std_logic      ;
signal wb_trig_iface_ch14_count_rcv_int         : std_logic_vector(15 downto 0);
signal wb_trig_iface_ch14_count_rcv_lwb         : std_logic      ;
signal wb_trig_iface_ch14_count_rcv_lwb_delay   : std_logic      ;
signal wb_trig_iface_ch14_count_rcv_lwb_in_progress : std_logic      ;
signal wb_trig_iface_ch14_count_rcv_lwb_s0      : std_logic      ;
signal wb_trig_iface_ch14_count_rcv_lwb_s1      : std_logic      ;
signal wb_trig_iface_ch14_count_rcv_lwb_s2      : std_logic      ;
signal wb_trig_iface_ch14_count_transm_int      : std_logic_vector(15 downto 0);
signal wb_trig_iface_ch14_count_transm_lwb      : std_logic      ;
signal wb_trig_iface_ch14_count_transm_lwb_delay : std_logic      ;
signal wb_trig_iface_ch14_count_transm_lwb_in_progress : std_logic      ;
signal wb_trig_iface_ch14_count_transm_lwb_s0   : std_logic      ;
signal wb_trig_iface_ch14_count_transm_lwb_s1   : std_logic      ;
signal wb_trig_iface_ch14_count_transm_lwb_s2   : std_logic      ;
signal wb_trig_iface_ch15_ctl_dir_int           : std_logic      ;
signal wb_trig_iface_ch15_ctl_dir_pol_int       : std_logic      ;
signal wb_trig_iface_ch15_ctl_rcv_count_rst_int : std_logic      ;
signal wb_trig_iface_ch15_ctl_rcv_count_rst_int_delay : std_logic      ;
signal wb_trig_iface_ch15_ctl_rcv_count_rst_sync0 : std_logic      ;
signal wb_trig_iface_ch15_ctl_rcv_count_rst_sync1 : std_logic      ;
signal wb_trig_iface_ch15_ctl_rcv_count_rst_sync2 : std_logic      ;
signal wb_trig_iface_ch15_ctl_transm_count_rst_int : std_logic      ;
signal wb_trig_iface_ch15_ctl_transm_count_rst_int_delay : std_logic      ;
signal wb_trig_iface_ch15_ctl_transm_count_rst_sync0 : std_logic      ;
signal wb_trig_iface_ch15_ctl_transm_count_rst_sync1 : std_logic      ;
signal wb_trig_iface_ch15_ctl_transm_count_rst_sync2 : std_logic      ;
signal wb_trig_iface_ch15_cfg_rcv_len_int       : std_logic_vector(7 downto 0);
signal wb_trig_iface_ch15_cfg_rcv_len_swb       : std_logic      ;
signal wb_trig_iface_ch15_cfg_rcv_len_swb_delay : std_logic      ;
signal wb_trig_iface_ch15_cfg_rcv_len_swb_s0    : std_logic      ;
signal wb_trig_iface_ch15_cfg_rcv_len_swb_s1    : std_logic      ;
signal wb_trig_iface_ch15_cfg_rcv_len_swb_s2    : std_logic      ;
signal wb_trig_iface_ch15_cfg_transm_len_int    : std_logic_vector(7 downto 0);
signal wb_trig_iface_ch15_cfg_transm_len_swb    : std_logic      ;
signal wb_trig_iface_ch15_cfg_transm_len_swb_delay : std_logic      ;
signal wb_trig_iface_ch15_cfg_transm_len_swb_s0 : std_logic      ;
signal wb_trig_iface_ch15_cfg_transm_len_swb_s1 : std_logic      ;
signal wb_trig_iface_ch15_cfg_transm_len_swb_s2 : std_logic      ;
signal wb_trig_iface_ch15_count_rcv_int         : std_logic_vector(15 downto 0);
signal wb_trig_iface_ch15_count_rcv_lwb         : std_logic      ;
signal wb_trig_iface_ch15_count_rcv_lwb_delay   : std_logic      ;
signal wb_trig_iface_ch15_count_rcv_lwb_in_progress : std_logic      ;
signal wb_trig_iface_ch15_count_rcv_lwb_s0      : std_logic      ;
signal wb_trig_iface_ch15_count_rcv_lwb_s1      : std_logic      ;
signal wb_trig_iface_ch15_count_rcv_lwb_s2      : std_logic      ;
signal wb_trig_iface_ch15_count_transm_int      : std_logic_vector(15 downto 0);
signal wb_trig_iface_ch15_count_transm_lwb      : std_logic      ;
signal wb_trig_iface_ch15_count_transm_lwb_delay : std_logic      ;
signal wb_trig_iface_ch15_count_transm_lwb_in_progress : std_logic      ;
signal wb_trig_iface_ch15_count_transm_lwb_s0   : std_logic      ;
signal wb_trig_iface_ch15_count_transm_lwb_s1   : std_logic      ;
signal wb_trig_iface_ch15_count_transm_lwb_s2   : std_logic      ;
signal wb_trig_iface_ch16_ctl_dir_int           : std_logic      ;
signal wb_trig_iface_ch16_ctl_dir_pol_int       : std_logic      ;
signal wb_trig_iface_ch16_ctl_rcv_count_rst_int : std_logic      ;
signal wb_trig_iface_ch16_ctl_rcv_count_rst_int_delay : std_logic      ;
signal wb_trig_iface_ch16_ctl_rcv_count_rst_sync0 : std_logic      ;
signal wb_trig_iface_ch16_ctl_rcv_count_rst_sync1 : std_logic      ;
signal wb_trig_iface_ch16_ctl_rcv_count_rst_sync2 : std_logic      ;
signal wb_trig_iface_ch16_ctl_transm_count_rst_int : std_logic      ;
signal wb_trig_iface_ch16_ctl_transm_count_rst_int_delay : std_logic      ;
signal wb_trig_iface_ch16_ctl_transm_count_rst_sync0 : std_logic      ;
signal wb_trig_iface_ch16_ctl_transm_count_rst_sync1 : std_logic      ;
signal wb_trig_iface_ch16_ctl_transm_count_rst_sync2 : std_logic      ;
signal wb_trig_iface_ch16_cfg_rcv_len_int       : std_logic_vector(7 downto 0);
signal wb_trig_iface_ch16_cfg_rcv_len_swb       : std_logic      ;
signal wb_trig_iface_ch16_cfg_rcv_len_swb_delay : std_logic      ;
signal wb_trig_iface_ch16_cfg_rcv_len_swb_s0    : std_logic      ;
signal wb_trig_iface_ch16_cfg_rcv_len_swb_s1    : std_logic      ;
signal wb_trig_iface_ch16_cfg_rcv_len_swb_s2    : std_logic      ;
signal wb_trig_iface_ch16_cfg_transm_len_int    : std_logic_vector(7 downto 0);
signal wb_trig_iface_ch16_cfg_transm_len_swb    : std_logic      ;
signal wb_trig_iface_ch16_cfg_transm_len_swb_delay : std_logic      ;
signal wb_trig_iface_ch16_cfg_transm_len_swb_s0 : std_logic      ;
signal wb_trig_iface_ch16_cfg_transm_len_swb_s1 : std_logic      ;
signal wb_trig_iface_ch16_cfg_transm_len_swb_s2 : std_logic      ;
signal wb_trig_iface_ch16_count_rcv_int         : std_logic_vector(15 downto 0);
signal wb_trig_iface_ch16_count_rcv_lwb         : std_logic      ;
signal wb_trig_iface_ch16_count_rcv_lwb_delay   : std_logic      ;
signal wb_trig_iface_ch16_count_rcv_lwb_in_progress : std_logic      ;
signal wb_trig_iface_ch16_count_rcv_lwb_s0      : std_logic      ;
signal wb_trig_iface_ch16_count_rcv_lwb_s1      : std_logic      ;
signal wb_trig_iface_ch16_count_rcv_lwb_s2      : std_logic      ;
signal wb_trig_iface_ch16_count_transm_int      : std_logic_vector(15 downto 0);
signal wb_trig_iface_ch16_count_transm_lwb      : std_logic      ;
signal wb_trig_iface_ch16_count_transm_lwb_delay : std_logic      ;
signal wb_trig_iface_ch16_count_transm_lwb_in_progress : std_logic      ;
signal wb_trig_iface_ch16_count_transm_lwb_s0   : std_logic      ;
signal wb_trig_iface_ch16_count_transm_lwb_s1   : std_logic      ;
signal wb_trig_iface_ch16_count_transm_lwb_s2   : std_logic      ;
signal wb_trig_iface_ch17_ctl_dir_int           : std_logic      ;
signal wb_trig_iface_ch17_ctl_dir_pol_int       : std_logic      ;
signal wb_trig_iface_ch17_ctl_rcv_count_rst_int : std_logic      ;
signal wb_trig_iface_ch17_ctl_rcv_count_rst_int_delay : std_logic      ;
signal wb_trig_iface_ch17_ctl_rcv_count_rst_sync0 : std_logic      ;
signal wb_trig_iface_ch17_ctl_rcv_count_rst_sync1 : std_logic      ;
signal wb_trig_iface_ch17_ctl_rcv_count_rst_sync2 : std_logic      ;
signal wb_trig_iface_ch17_ctl_transm_count_rst_int : std_logic      ;
signal wb_trig_iface_ch17_ctl_transm_count_rst_int_delay : std_logic      ;
signal wb_trig_iface_ch17_ctl_transm_count_rst_sync0 : std_logic      ;
signal wb_trig_iface_ch17_ctl_transm_count_rst_sync1 : std_logic      ;
signal wb_trig_iface_ch17_ctl_transm_count_rst_sync2 : std_logic      ;
signal wb_trig_iface_ch17_cfg_rcv_len_int       : std_logic_vector(7 downto 0);
signal wb_trig_iface_ch17_cfg_rcv_len_swb       : std_logic      ;
signal wb_trig_iface_ch17_cfg_rcv_len_swb_delay : std_logic      ;
signal wb_trig_iface_ch17_cfg_rcv_len_swb_s0    : std_logic      ;
signal wb_trig_iface_ch17_cfg_rcv_len_swb_s1    : std_logic      ;
signal wb_trig_iface_ch17_cfg_rcv_len_swb_s2    : std_logic      ;
signal wb_trig_iface_ch17_cfg_transm_len_int    : std_logic_vector(7 downto 0);
signal wb_trig_iface_ch17_cfg_transm_len_swb    : std_logic      ;
signal wb_trig_iface_ch17_cfg_transm_len_swb_delay : std_logic      ;
signal wb_trig_iface_ch17_cfg_transm_len_swb_s0 : std_logic      ;
signal wb_trig_iface_ch17_cfg_transm_len_swb_s1 : std_logic      ;
signal wb_trig_iface_ch17_cfg_transm_len_swb_s2 : std_logic      ;
signal wb_trig_iface_ch17_count_rcv_int         : std_logic_vector(15 downto 0);
signal wb_trig_iface_ch17_count_rcv_lwb         : std_logic      ;
signal wb_trig_iface_ch17_count_rcv_lwb_delay   : std_logic      ;
signal wb_trig_iface_ch17_count_rcv_lwb_in_progress : std_logic      ;
signal wb_trig_iface_ch17_count_rcv_lwb_s0      : std_logic      ;
signal wb_trig_iface_ch17_count_rcv_lwb_s1      : std_logic      ;
signal wb_trig_iface_ch17_count_rcv_lwb_s2      : std_logic      ;
signal wb_trig_iface_ch17_count_transm_int      : std_logic_vector(15 downto 0);
signal wb_trig_iface_ch17_count_transm_lwb      : std_logic      ;
signal wb_trig_iface_ch17_count_transm_lwb_delay : std_logic      ;
signal wb_trig_iface_ch17_count_transm_lwb_in_progress : std_logic      ;
signal wb_trig_iface_ch17_count_transm_lwb_s0   : std_logic      ;
signal wb_trig_iface_ch17_count_transm_lwb_s1   : std_logic      ;
signal wb_trig_iface_ch17_count_transm_lwb_s2   : std_logic      ;
signal wb_trig_iface_ch18_ctl_dir_int           : std_logic      ;
signal wb_trig_iface_ch18_ctl_dir_pol_int       : std_logic      ;
signal wb_trig_iface_ch18_ctl_rcv_count_rst_int : std_logic      ;
signal wb_trig_iface_ch18_ctl_rcv_count_rst_int_delay : std_logic      ;
signal wb_trig_iface_ch18_ctl_rcv_count_rst_sync0 : std_logic      ;
signal wb_trig_iface_ch18_ctl_rcv_count_rst_sync1 : std_logic      ;
signal wb_trig_iface_ch18_ctl_rcv_count_rst_sync2 : std_logic      ;
signal wb_trig_iface_ch18_ctl_transm_count_rst_int : std_logic      ;
signal wb_trig_iface_ch18_ctl_transm_count_rst_int_delay : std_logic      ;
signal wb_trig_iface_ch18_ctl_transm_count_rst_sync0 : std_logic      ;
signal wb_trig_iface_ch18_ctl_transm_count_rst_sync1 : std_logic      ;
signal wb_trig_iface_ch18_ctl_transm_count_rst_sync2 : std_logic      ;
signal wb_trig_iface_ch18_cfg_rcv_len_int       : std_logic_vector(7 downto 0);
signal wb_trig_iface_ch18_cfg_rcv_len_swb       : std_logic      ;
signal wb_trig_iface_ch18_cfg_rcv_len_swb_delay : std_logic      ;
signal wb_trig_iface_ch18_cfg_rcv_len_swb_s0    : std_logic      ;
signal wb_trig_iface_ch18_cfg_rcv_len_swb_s1    : std_logic      ;
signal wb_trig_iface_ch18_cfg_rcv_len_swb_s2    : std_logic      ;
signal wb_trig_iface_ch18_cfg_transm_len_int    : std_logic_vector(7 downto 0);
signal wb_trig_iface_ch18_cfg_transm_len_swb    : std_logic      ;
signal wb_trig_iface_ch18_cfg_transm_len_swb_delay : std_logic      ;
signal wb_trig_iface_ch18_cfg_transm_len_swb_s0 : std_logic      ;
signal wb_trig_iface_ch18_cfg_transm_len_swb_s1 : std_logic      ;
signal wb_trig_iface_ch18_cfg_transm_len_swb_s2 : std_logic      ;
signal wb_trig_iface_ch18_count_rcv_int         : std_logic_vector(15 downto 0);
signal wb_trig_iface_ch18_count_rcv_lwb         : std_logic      ;
signal wb_trig_iface_ch18_count_rcv_lwb_delay   : std_logic      ;
signal wb_trig_iface_ch18_count_rcv_lwb_in_progress : std_logic      ;
signal wb_trig_iface_ch18_count_rcv_lwb_s0      : std_logic      ;
signal wb_trig_iface_ch18_count_rcv_lwb_s1      : std_logic      ;
signal wb_trig_iface_ch18_count_rcv_lwb_s2      : std_logic      ;
signal wb_trig_iface_ch18_count_transm_int      : std_logic_vector(15 downto 0);
signal wb_trig_iface_ch18_count_transm_lwb      : std_logic      ;
signal wb_trig_iface_ch18_count_transm_lwb_delay : std_logic      ;
signal wb_trig_iface_ch18_count_transm_lwb_in_progress : std_logic      ;
signal wb_trig_iface_ch18_count_transm_lwb_s0   : std_logic      ;
signal wb_trig_iface_ch18_count_transm_lwb_s1   : std_logic      ;
signal wb_trig_iface_ch18_count_transm_lwb_s2   : std_logic      ;
signal wb_trig_iface_ch19_ctl_dir_int           : std_logic      ;
signal wb_trig_iface_ch19_ctl_dir_pol_int       : std_logic      ;
signal wb_trig_iface_ch19_ctl_rcv_count_rst_int : std_logic      ;
signal wb_trig_iface_ch19_ctl_rcv_count_rst_int_delay : std_logic      ;
signal wb_trig_iface_ch19_ctl_rcv_count_rst_sync0 : std_logic      ;
signal wb_trig_iface_ch19_ctl_rcv_count_rst_sync1 : std_logic      ;
signal wb_trig_iface_ch19_ctl_rcv_count_rst_sync2 : std_logic      ;
signal wb_trig_iface_ch19_ctl_transm_count_rst_int : std_logic      ;
signal wb_trig_iface_ch19_ctl_transm_count_rst_int_delay : std_logic      ;
signal wb_trig_iface_ch19_ctl_transm_count_rst_sync0 : std_logic      ;
signal wb_trig_iface_ch19_ctl_transm_count_rst_sync1 : std_logic      ;
signal wb_trig_iface_ch19_ctl_transm_count_rst_sync2 : std_logic      ;
signal wb_trig_iface_ch19_cfg_rcv_len_int       : std_logic_vector(7 downto 0);
signal wb_trig_iface_ch19_cfg_rcv_len_swb       : std_logic      ;
signal wb_trig_iface_ch19_cfg_rcv_len_swb_delay : std_logic      ;
signal wb_trig_iface_ch19_cfg_rcv_len_swb_s0    : std_logic      ;
signal wb_trig_iface_ch19_cfg_rcv_len_swb_s1    : std_logic      ;
signal wb_trig_iface_ch19_cfg_rcv_len_swb_s2    : std_logic      ;
signal wb_trig_iface_ch19_cfg_transm_len_int    : std_logic_vector(7 downto 0);
signal wb_trig_iface_ch19_cfg_transm_len_swb    : std_logic      ;
signal wb_trig_iface_ch19_cfg_transm_len_swb_delay : std_logic      ;
signal wb_trig_iface_ch19_cfg_transm_len_swb_s0 : std_logic      ;
signal wb_trig_iface_ch19_cfg_transm_len_swb_s1 : std_logic      ;
signal wb_trig_iface_ch19_cfg_transm_len_swb_s2 : std_logic      ;
signal wb_trig_iface_ch19_count_rcv_int         : std_logic_vector(15 downto 0);
signal wb_trig_iface_ch19_count_rcv_lwb         : std_logic      ;
signal wb_trig_iface_ch19_count_rcv_lwb_delay   : std_logic      ;
signal wb_trig_iface_ch19_count_rcv_lwb_in_progress : std_logic      ;
signal wb_trig_iface_ch19_count_rcv_lwb_s0      : std_logic      ;
signal wb_trig_iface_ch19_count_rcv_lwb_s1      : std_logic      ;
signal wb_trig_iface_ch19_count_rcv_lwb_s2      : std_logic      ;
signal wb_trig_iface_ch19_count_transm_int      : std_logic_vector(15 downto 0);
signal wb_trig_iface_ch19_count_transm_lwb      : std_logic      ;
signal wb_trig_iface_ch19_count_transm_lwb_delay : std_logic      ;
signal wb_trig_iface_ch19_count_transm_lwb_in_progress : std_logic      ;
signal wb_trig_iface_ch19_count_transm_lwb_s0   : std_logic      ;
signal wb_trig_iface_ch19_count_transm_lwb_s1   : std_logic      ;
signal wb_trig_iface_ch19_count_transm_lwb_s2   : std_logic      ;
signal wb_trig_iface_ch20_ctl_dir_int           : std_logic      ;
signal wb_trig_iface_ch20_ctl_dir_pol_int       : std_logic      ;
signal wb_trig_iface_ch20_ctl_rcv_count_rst_int : std_logic      ;
signal wb_trig_iface_ch20_ctl_rcv_count_rst_int_delay : std_logic      ;
signal wb_trig_iface_ch20_ctl_rcv_count_rst_sync0 : std_logic      ;
signal wb_trig_iface_ch20_ctl_rcv_count_rst_sync1 : std_logic      ;
signal wb_trig_iface_ch20_ctl_rcv_count_rst_sync2 : std_logic      ;
signal wb_trig_iface_ch20_ctl_transm_count_rst_int : std_logic      ;
signal wb_trig_iface_ch20_ctl_transm_count_rst_int_delay : std_logic      ;
signal wb_trig_iface_ch20_ctl_transm_count_rst_sync0 : std_logic      ;
signal wb_trig_iface_ch20_ctl_transm_count_rst_sync1 : std_logic      ;
signal wb_trig_iface_ch20_ctl_transm_count_rst_sync2 : std_logic      ;
signal wb_trig_iface_ch20_cfg_rcv_len_int       : std_logic_vector(7 downto 0);
signal wb_trig_iface_ch20_cfg_rcv_len_swb       : std_logic      ;
signal wb_trig_iface_ch20_cfg_rcv_len_swb_delay : std_logic      ;
signal wb_trig_iface_ch20_cfg_rcv_len_swb_s0    : std_logic      ;
signal wb_trig_iface_ch20_cfg_rcv_len_swb_s1    : std_logic      ;
signal wb_trig_iface_ch20_cfg_rcv_len_swb_s2    : std_logic      ;
signal wb_trig_iface_ch20_cfg_transm_len_int    : std_logic_vector(7 downto 0);
signal wb_trig_iface_ch20_cfg_transm_len_swb    : std_logic      ;
signal wb_trig_iface_ch20_cfg_transm_len_swb_delay : std_logic      ;
signal wb_trig_iface_ch20_cfg_transm_len_swb_s0 : std_logic      ;
signal wb_trig_iface_ch20_cfg_transm_len_swb_s1 : std_logic      ;
signal wb_trig_iface_ch20_cfg_transm_len_swb_s2 : std_logic      ;
signal wb_trig_iface_ch20_count_rcv_int         : std_logic_vector(15 downto 0);
signal wb_trig_iface_ch20_count_rcv_lwb         : std_logic      ;
signal wb_trig_iface_ch20_count_rcv_lwb_delay   : std_logic      ;
signal wb_trig_iface_ch20_count_rcv_lwb_in_progress : std_logic      ;
signal wb_trig_iface_ch20_count_rcv_lwb_s0      : std_logic      ;
signal wb_trig_iface_ch20_count_rcv_lwb_s1      : std_logic      ;
signal wb_trig_iface_ch20_count_rcv_lwb_s2      : std_logic      ;
signal wb_trig_iface_ch20_count_transm_int      : std_logic_vector(15 downto 0);
signal wb_trig_iface_ch20_count_transm_lwb      : std_logic      ;
signal wb_trig_iface_ch20_count_transm_lwb_delay : std_logic      ;
signal wb_trig_iface_ch20_count_transm_lwb_in_progress : std_logic      ;
signal wb_trig_iface_ch20_count_transm_lwb_s0   : std_logic      ;
signal wb_trig_iface_ch20_count_transm_lwb_s1   : std_logic      ;
signal wb_trig_iface_ch20_count_transm_lwb_s2   : std_logic      ;
signal wb_trig_iface_ch21_ctl_dir_int           : std_logic      ;
signal wb_trig_iface_ch21_ctl_dir_pol_int       : std_logic      ;
signal wb_trig_iface_ch21_ctl_rcv_count_rst_int : std_logic      ;
signal wb_trig_iface_ch21_ctl_rcv_count_rst_int_delay : std_logic      ;
signal wb_trig_iface_ch21_ctl_rcv_count_rst_sync0 : std_logic      ;
signal wb_trig_iface_ch21_ctl_rcv_count_rst_sync1 : std_logic      ;
signal wb_trig_iface_ch21_ctl_rcv_count_rst_sync2 : std_logic      ;
signal wb_trig_iface_ch21_ctl_transm_count_rst_int : std_logic      ;
signal wb_trig_iface_ch21_ctl_transm_count_rst_int_delay : std_logic      ;
signal wb_trig_iface_ch21_ctl_transm_count_rst_sync0 : std_logic      ;
signal wb_trig_iface_ch21_ctl_transm_count_rst_sync1 : std_logic      ;
signal wb_trig_iface_ch21_ctl_transm_count_rst_sync2 : std_logic      ;
signal wb_trig_iface_ch21_cfg_rcv_len_int       : std_logic_vector(7 downto 0);
signal wb_trig_iface_ch21_cfg_rcv_len_swb       : std_logic      ;
signal wb_trig_iface_ch21_cfg_rcv_len_swb_delay : std_logic      ;
signal wb_trig_iface_ch21_cfg_rcv_len_swb_s0    : std_logic      ;
signal wb_trig_iface_ch21_cfg_rcv_len_swb_s1    : std_logic      ;
signal wb_trig_iface_ch21_cfg_rcv_len_swb_s2    : std_logic      ;
signal wb_trig_iface_ch21_cfg_transm_len_int    : std_logic_vector(7 downto 0);
signal wb_trig_iface_ch21_cfg_transm_len_swb    : std_logic      ;
signal wb_trig_iface_ch21_cfg_transm_len_swb_delay : std_logic      ;
signal wb_trig_iface_ch21_cfg_transm_len_swb_s0 : std_logic      ;
signal wb_trig_iface_ch21_cfg_transm_len_swb_s1 : std_logic      ;
signal wb_trig_iface_ch21_cfg_transm_len_swb_s2 : std_logic      ;
signal wb_trig_iface_ch21_count_rcv_int         : std_logic_vector(15 downto 0);
signal wb_trig_iface_ch21_count_rcv_lwb         : std_logic      ;
signal wb_trig_iface_ch21_count_rcv_lwb_delay   : std_logic      ;
signal wb_trig_iface_ch21_count_rcv_lwb_in_progress : std_logic      ;
signal wb_trig_iface_ch21_count_rcv_lwb_s0      : std_logic      ;
signal wb_trig_iface_ch21_count_rcv_lwb_s1      : std_logic      ;
signal wb_trig_iface_ch21_count_rcv_lwb_s2      : std_logic      ;
signal wb_trig_iface_ch21_count_transm_int      : std_logic_vector(15 downto 0);
signal wb_trig_iface_ch21_count_transm_lwb      : std_logic      ;
signal wb_trig_iface_ch21_count_transm_lwb_delay : std_logic      ;
signal wb_trig_iface_ch21_count_transm_lwb_in_progress : std_logic      ;
signal wb_trig_iface_ch21_count_transm_lwb_s0   : std_logic      ;
signal wb_trig_iface_ch21_count_transm_lwb_s1   : std_logic      ;
signal wb_trig_iface_ch21_count_transm_lwb_s2   : std_logic      ;
signal wb_trig_iface_ch22_ctl_dir_int           : std_logic      ;
signal wb_trig_iface_ch22_ctl_dir_pol_int       : std_logic      ;
signal wb_trig_iface_ch22_ctl_rcv_count_rst_int : std_logic      ;
signal wb_trig_iface_ch22_ctl_rcv_count_rst_int_delay : std_logic      ;
signal wb_trig_iface_ch22_ctl_rcv_count_rst_sync0 : std_logic      ;
signal wb_trig_iface_ch22_ctl_rcv_count_rst_sync1 : std_logic      ;
signal wb_trig_iface_ch22_ctl_rcv_count_rst_sync2 : std_logic      ;
signal wb_trig_iface_ch22_ctl_transm_count_rst_int : std_logic      ;
signal wb_trig_iface_ch22_ctl_transm_count_rst_int_delay : std_logic      ;
signal wb_trig_iface_ch22_ctl_transm_count_rst_sync0 : std_logic      ;
signal wb_trig_iface_ch22_ctl_transm_count_rst_sync1 : std_logic      ;
signal wb_trig_iface_ch22_ctl_transm_count_rst_sync2 : std_logic      ;
signal wb_trig_iface_ch22_cfg_rcv_len_int       : std_logic_vector(7 downto 0);
signal wb_trig_iface_ch22_cfg_rcv_len_swb       : std_logic      ;
signal wb_trig_iface_ch22_cfg_rcv_len_swb_delay : std_logic      ;
signal wb_trig_iface_ch22_cfg_rcv_len_swb_s0    : std_logic      ;
signal wb_trig_iface_ch22_cfg_rcv_len_swb_s1    : std_logic      ;
signal wb_trig_iface_ch22_cfg_rcv_len_swb_s2    : std_logic      ;
signal wb_trig_iface_ch22_cfg_transm_len_int    : std_logic_vector(7 downto 0);
signal wb_trig_iface_ch22_cfg_transm_len_swb    : std_logic      ;
signal wb_trig_iface_ch22_cfg_transm_len_swb_delay : std_logic      ;
signal wb_trig_iface_ch22_cfg_transm_len_swb_s0 : std_logic      ;
signal wb_trig_iface_ch22_cfg_transm_len_swb_s1 : std_logic      ;
signal wb_trig_iface_ch22_cfg_transm_len_swb_s2 : std_logic      ;
signal wb_trig_iface_ch22_count_rcv_int         : std_logic_vector(15 downto 0);
signal wb_trig_iface_ch22_count_rcv_lwb         : std_logic      ;
signal wb_trig_iface_ch22_count_rcv_lwb_delay   : std_logic      ;
signal wb_trig_iface_ch22_count_rcv_lwb_in_progress : std_logic      ;
signal wb_trig_iface_ch22_count_rcv_lwb_s0      : std_logic      ;
signal wb_trig_iface_ch22_count_rcv_lwb_s1      : std_logic      ;
signal wb_trig_iface_ch22_count_rcv_lwb_s2      : std_logic      ;
signal wb_trig_iface_ch22_count_transm_int      : std_logic_vector(15 downto 0);
signal wb_trig_iface_ch22_count_transm_lwb      : std_logic      ;
signal wb_trig_iface_ch22_count_transm_lwb_delay : std_logic      ;
signal wb_trig_iface_ch22_count_transm_lwb_in_progress : std_logic      ;
signal wb_trig_iface_ch22_count_transm_lwb_s0   : std_logic      ;
signal wb_trig_iface_ch22_count_transm_lwb_s1   : std_logic      ;
signal wb_trig_iface_ch22_count_transm_lwb_s2   : std_logic      ;
signal wb_trig_iface_ch23_ctl_dir_int           : std_logic      ;
signal wb_trig_iface_ch23_ctl_dir_pol_int       : std_logic      ;
signal wb_trig_iface_ch23_ctl_rcv_count_rst_int : std_logic      ;
signal wb_trig_iface_ch23_ctl_rcv_count_rst_int_delay : std_logic      ;
signal wb_trig_iface_ch23_ctl_rcv_count_rst_sync0 : std_logic      ;
signal wb_trig_iface_ch23_ctl_rcv_count_rst_sync1 : std_logic      ;
signal wb_trig_iface_ch23_ctl_rcv_count_rst_sync2 : std_logic      ;
signal wb_trig_iface_ch23_ctl_transm_count_rst_int : std_logic      ;
signal wb_trig_iface_ch23_ctl_transm_count_rst_int_delay : std_logic      ;
signal wb_trig_iface_ch23_ctl_transm_count_rst_sync0 : std_logic      ;
signal wb_trig_iface_ch23_ctl_transm_count_rst_sync1 : std_logic      ;
signal wb_trig_iface_ch23_ctl_transm_count_rst_sync2 : std_logic      ;
signal wb_trig_iface_ch23_cfg_rcv_len_int       : std_logic_vector(7 downto 0);
signal wb_trig_iface_ch23_cfg_rcv_len_swb       : std_logic      ;
signal wb_trig_iface_ch23_cfg_rcv_len_swb_delay : std_logic      ;
signal wb_trig_iface_ch23_cfg_rcv_len_swb_s0    : std_logic      ;
signal wb_trig_iface_ch23_cfg_rcv_len_swb_s1    : std_logic      ;
signal wb_trig_iface_ch23_cfg_rcv_len_swb_s2    : std_logic      ;
signal wb_trig_iface_ch23_cfg_transm_len_int    : std_logic_vector(7 downto 0);
signal wb_trig_iface_ch23_cfg_transm_len_swb    : std_logic      ;
signal wb_trig_iface_ch23_cfg_transm_len_swb_delay : std_logic      ;
signal wb_trig_iface_ch23_cfg_transm_len_swb_s0 : std_logic      ;
signal wb_trig_iface_ch23_cfg_transm_len_swb_s1 : std_logic      ;
signal wb_trig_iface_ch23_cfg_transm_len_swb_s2 : std_logic      ;
signal wb_trig_iface_ch23_count_rcv_int         : std_logic_vector(15 downto 0);
signal wb_trig_iface_ch23_count_rcv_lwb         : std_logic      ;
signal wb_trig_iface_ch23_count_rcv_lwb_delay   : std_logic      ;
signal wb_trig_iface_ch23_count_rcv_lwb_in_progress : std_logic      ;
signal wb_trig_iface_ch23_count_rcv_lwb_s0      : std_logic      ;
signal wb_trig_iface_ch23_count_rcv_lwb_s1      : std_logic      ;
signal wb_trig_iface_ch23_count_rcv_lwb_s2      : std_logic      ;
signal wb_trig_iface_ch23_count_transm_int      : std_logic_vector(15 downto 0);
signal wb_trig_iface_ch23_count_transm_lwb      : std_logic      ;
signal wb_trig_iface_ch23_count_transm_lwb_delay : std_logic      ;
signal wb_trig_iface_ch23_count_transm_lwb_in_progress : std_logic      ;
signal wb_trig_iface_ch23_count_transm_lwb_s0   : std_logic      ;
signal wb_trig_iface_ch23_count_transm_lwb_s1   : std_logic      ;
signal wb_trig_iface_ch23_count_transm_lwb_s2   : std_logic      ;
signal ack_sreg                                 : std_logic_vector(9 downto 0);
signal rddata_reg                               : std_logic_vector(31 downto 0);
signal wrdata_reg                               : std_logic_vector(31 downto 0);
signal bwsel_reg                                : std_logic_vector(3 downto 0);
signal rwaddr_reg                               : std_logic_vector(6 downto 0);
signal ack_in_progress                          : std_logic      ;
signal wr_int                                   : std_logic      ;
signal rd_int                                   : std_logic      ;
signal allones                                  : std_logic_vector(31 downto 0);
signal allzeros                                 : std_logic_vector(31 downto 0);

begin
-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
  wrdata_reg <= wb_dat_i;
  bwsel_reg <= wb_sel_i;
  rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
  wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
  allones <= (others => '1');
  allzeros <= (others => '0');
-- 
-- Main register bank access process.
  process (clk_sys_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      ack_sreg <= "0000000000";
      ack_in_progress <= '0';
      rddata_reg <= "00000000000000000000000000000000";
      wb_trig_iface_ch0_ctl_dir_int <= '0';
      wb_trig_iface_ch0_ctl_dir_pol_int <= '0';
      wb_trig_iface_ch0_ctl_rcv_count_rst_int <= '0';
      wb_trig_iface_ch0_ctl_rcv_count_rst_int_delay <= '0';
      wb_trig_iface_ch0_ctl_transm_count_rst_int <= '0';
      wb_trig_iface_ch0_ctl_transm_count_rst_int_delay <= '0';
      wb_trig_iface_ch0_cfg_rcv_len_int <= "00000000";
      wb_trig_iface_ch0_cfg_rcv_len_swb <= '0';
      wb_trig_iface_ch0_cfg_rcv_len_swb_delay <= '0';
      wb_trig_iface_ch0_cfg_transm_len_int <= "00000000";
      wb_trig_iface_ch0_cfg_transm_len_swb <= '0';
      wb_trig_iface_ch0_cfg_transm_len_swb_delay <= '0';
      wb_trig_iface_ch0_count_rcv_lwb <= '0';
      wb_trig_iface_ch0_count_rcv_lwb_delay <= '0';
      wb_trig_iface_ch0_count_rcv_lwb_in_progress <= '0';
      wb_trig_iface_ch0_count_transm_lwb <= '0';
      wb_trig_iface_ch0_count_transm_lwb_delay <= '0';
      wb_trig_iface_ch0_count_transm_lwb_in_progress <= '0';
      wb_trig_iface_ch1_ctl_dir_int <= '0';
      wb_trig_iface_ch1_ctl_dir_pol_int <= '0';
      wb_trig_iface_ch1_ctl_rcv_count_rst_int <= '0';
      wb_trig_iface_ch1_ctl_rcv_count_rst_int_delay <= '0';
      wb_trig_iface_ch1_ctl_transm_count_rst_int <= '0';
      wb_trig_iface_ch1_ctl_transm_count_rst_int_delay <= '0';
      wb_trig_iface_ch1_cfg_rcv_len_int <= "00000000";
      wb_trig_iface_ch1_cfg_rcv_len_swb <= '0';
      wb_trig_iface_ch1_cfg_rcv_len_swb_delay <= '0';
      wb_trig_iface_ch1_cfg_transm_len_int <= "00000000";
      wb_trig_iface_ch1_cfg_transm_len_swb <= '0';
      wb_trig_iface_ch1_cfg_transm_len_swb_delay <= '0';
      wb_trig_iface_ch1_count_rcv_lwb <= '0';
      wb_trig_iface_ch1_count_rcv_lwb_delay <= '0';
      wb_trig_iface_ch1_count_rcv_lwb_in_progress <= '0';
      wb_trig_iface_ch1_count_transm_lwb <= '0';
      wb_trig_iface_ch1_count_transm_lwb_delay <= '0';
      wb_trig_iface_ch1_count_transm_lwb_in_progress <= '0';
      wb_trig_iface_ch2_ctl_dir_int <= '0';
      wb_trig_iface_ch2_ctl_dir_pol_int <= '0';
      wb_trig_iface_ch2_ctl_rcv_count_rst_int <= '0';
      wb_trig_iface_ch2_ctl_rcv_count_rst_int_delay <= '0';
      wb_trig_iface_ch2_ctl_transm_count_rst_int <= '0';
      wb_trig_iface_ch2_ctl_transm_count_rst_int_delay <= '0';
      wb_trig_iface_ch2_cfg_rcv_len_int <= "00000000";
      wb_trig_iface_ch2_cfg_rcv_len_swb <= '0';
      wb_trig_iface_ch2_cfg_rcv_len_swb_delay <= '0';
      wb_trig_iface_ch2_cfg_transm_len_int <= "00000000";
      wb_trig_iface_ch2_cfg_transm_len_swb <= '0';
      wb_trig_iface_ch2_cfg_transm_len_swb_delay <= '0';
      wb_trig_iface_ch2_count_rcv_lwb <= '0';
      wb_trig_iface_ch2_count_rcv_lwb_delay <= '0';
      wb_trig_iface_ch2_count_rcv_lwb_in_progress <= '0';
      wb_trig_iface_ch2_count_transm_lwb <= '0';
      wb_trig_iface_ch2_count_transm_lwb_delay <= '0';
      wb_trig_iface_ch2_count_transm_lwb_in_progress <= '0';
      wb_trig_iface_ch3_ctl_dir_int <= '0';
      wb_trig_iface_ch3_ctl_dir_pol_int <= '0';
      wb_trig_iface_ch3_ctl_rcv_count_rst_int <= '0';
      wb_trig_iface_ch3_ctl_rcv_count_rst_int_delay <= '0';
      wb_trig_iface_ch3_ctl_transm_count_rst_int <= '0';
      wb_trig_iface_ch3_ctl_transm_count_rst_int_delay <= '0';
      wb_trig_iface_ch3_cfg_rcv_len_int <= "00000000";
      wb_trig_iface_ch3_cfg_rcv_len_swb <= '0';
      wb_trig_iface_ch3_cfg_rcv_len_swb_delay <= '0';
      wb_trig_iface_ch3_cfg_transm_len_int <= "00000000";
      wb_trig_iface_ch3_cfg_transm_len_swb <= '0';
      wb_trig_iface_ch3_cfg_transm_len_swb_delay <= '0';
      wb_trig_iface_ch3_count_rcv_lwb <= '0';
      wb_trig_iface_ch3_count_rcv_lwb_delay <= '0';
      wb_trig_iface_ch3_count_rcv_lwb_in_progress <= '0';
      wb_trig_iface_ch3_count_transm_lwb <= '0';
      wb_trig_iface_ch3_count_transm_lwb_delay <= '0';
      wb_trig_iface_ch3_count_transm_lwb_in_progress <= '0';
      wb_trig_iface_ch4_ctl_dir_int <= '0';
      wb_trig_iface_ch4_ctl_dir_pol_int <= '0';
      wb_trig_iface_ch4_ctl_rcv_count_rst_int <= '0';
      wb_trig_iface_ch4_ctl_rcv_count_rst_int_delay <= '0';
      wb_trig_iface_ch4_ctl_transm_count_rst_int <= '0';
      wb_trig_iface_ch4_ctl_transm_count_rst_int_delay <= '0';
      wb_trig_iface_ch4_cfg_rcv_len_int <= "00000000";
      wb_trig_iface_ch4_cfg_rcv_len_swb <= '0';
      wb_trig_iface_ch4_cfg_rcv_len_swb_delay <= '0';
      wb_trig_iface_ch4_cfg_transm_len_int <= "00000000";
      wb_trig_iface_ch4_cfg_transm_len_swb <= '0';
      wb_trig_iface_ch4_cfg_transm_len_swb_delay <= '0';
      wb_trig_iface_ch4_count_rcv_lwb <= '0';
      wb_trig_iface_ch4_count_rcv_lwb_delay <= '0';
      wb_trig_iface_ch4_count_rcv_lwb_in_progress <= '0';
      wb_trig_iface_ch4_count_transm_lwb <= '0';
      wb_trig_iface_ch4_count_transm_lwb_delay <= '0';
      wb_trig_iface_ch4_count_transm_lwb_in_progress <= '0';
      wb_trig_iface_ch5_ctl_dir_int <= '0';
      wb_trig_iface_ch5_ctl_dir_pol_int <= '0';
      wb_trig_iface_ch5_ctl_rcv_count_rst_int <= '0';
      wb_trig_iface_ch5_ctl_rcv_count_rst_int_delay <= '0';
      wb_trig_iface_ch5_ctl_transm_count_rst_int <= '0';
      wb_trig_iface_ch5_ctl_transm_count_rst_int_delay <= '0';
      wb_trig_iface_ch5_cfg_rcv_len_int <= "00000000";
      wb_trig_iface_ch5_cfg_rcv_len_swb <= '0';
      wb_trig_iface_ch5_cfg_rcv_len_swb_delay <= '0';
      wb_trig_iface_ch5_cfg_transm_len_int <= "00000000";
      wb_trig_iface_ch5_cfg_transm_len_swb <= '0';
      wb_trig_iface_ch5_cfg_transm_len_swb_delay <= '0';
      wb_trig_iface_ch5_count_rcv_lwb <= '0';
      wb_trig_iface_ch5_count_rcv_lwb_delay <= '0';
      wb_trig_iface_ch5_count_rcv_lwb_in_progress <= '0';
      wb_trig_iface_ch5_count_transm_lwb <= '0';
      wb_trig_iface_ch5_count_transm_lwb_delay <= '0';
      wb_trig_iface_ch5_count_transm_lwb_in_progress <= '0';
      wb_trig_iface_ch6_ctl_dir_int <= '0';
      wb_trig_iface_ch6_ctl_dir_pol_int <= '0';
      wb_trig_iface_ch6_ctl_rcv_count_rst_int <= '0';
      wb_trig_iface_ch6_ctl_rcv_count_rst_int_delay <= '0';
      wb_trig_iface_ch6_ctl_transm_count_rst_int <= '0';
      wb_trig_iface_ch6_ctl_transm_count_rst_int_delay <= '0';
      wb_trig_iface_ch6_cfg_rcv_len_int <= "00000000";
      wb_trig_iface_ch6_cfg_rcv_len_swb <= '0';
      wb_trig_iface_ch6_cfg_rcv_len_swb_delay <= '0';
      wb_trig_iface_ch6_cfg_transm_len_int <= "00000000";
      wb_trig_iface_ch6_cfg_transm_len_swb <= '0';
      wb_trig_iface_ch6_cfg_transm_len_swb_delay <= '0';
      wb_trig_iface_ch6_count_rcv_lwb <= '0';
      wb_trig_iface_ch6_count_rcv_lwb_delay <= '0';
      wb_trig_iface_ch6_count_rcv_lwb_in_progress <= '0';
      wb_trig_iface_ch6_count_transm_lwb <= '0';
      wb_trig_iface_ch6_count_transm_lwb_delay <= '0';
      wb_trig_iface_ch6_count_transm_lwb_in_progress <= '0';
      wb_trig_iface_ch7_ctl_dir_int <= '0';
      wb_trig_iface_ch7_ctl_dir_pol_int <= '0';
      wb_trig_iface_ch7_ctl_rcv_count_rst_int <= '0';
      wb_trig_iface_ch7_ctl_rcv_count_rst_int_delay <= '0';
      wb_trig_iface_ch7_ctl_transm_count_rst_int <= '0';
      wb_trig_iface_ch7_ctl_transm_count_rst_int_delay <= '0';
      wb_trig_iface_ch7_cfg_rcv_len_int <= "00000000";
      wb_trig_iface_ch7_cfg_rcv_len_swb <= '0';
      wb_trig_iface_ch7_cfg_rcv_len_swb_delay <= '0';
      wb_trig_iface_ch7_cfg_transm_len_int <= "00000000";
      wb_trig_iface_ch7_cfg_transm_len_swb <= '0';
      wb_trig_iface_ch7_cfg_transm_len_swb_delay <= '0';
      wb_trig_iface_ch7_count_rcv_lwb <= '0';
      wb_trig_iface_ch7_count_rcv_lwb_delay <= '0';
      wb_trig_iface_ch7_count_rcv_lwb_in_progress <= '0';
      wb_trig_iface_ch7_count_transm_lwb <= '0';
      wb_trig_iface_ch7_count_transm_lwb_delay <= '0';
      wb_trig_iface_ch7_count_transm_lwb_in_progress <= '0';
      wb_trig_iface_ch8_ctl_dir_int <= '0';
      wb_trig_iface_ch8_ctl_dir_pol_int <= '0';
      wb_trig_iface_ch8_ctl_rcv_count_rst_int <= '0';
      wb_trig_iface_ch8_ctl_rcv_count_rst_int_delay <= '0';
      wb_trig_iface_ch8_ctl_transm_count_rst_int <= '0';
      wb_trig_iface_ch8_ctl_transm_count_rst_int_delay <= '0';
      wb_trig_iface_ch8_cfg_rcv_len_int <= "00000000";
      wb_trig_iface_ch8_cfg_rcv_len_swb <= '0';
      wb_trig_iface_ch8_cfg_rcv_len_swb_delay <= '0';
      wb_trig_iface_ch8_cfg_transm_len_int <= "00000000";
      wb_trig_iface_ch8_cfg_transm_len_swb <= '0';
      wb_trig_iface_ch8_cfg_transm_len_swb_delay <= '0';
      wb_trig_iface_ch8_count_rcv_lwb <= '0';
      wb_trig_iface_ch8_count_rcv_lwb_delay <= '0';
      wb_trig_iface_ch8_count_rcv_lwb_in_progress <= '0';
      wb_trig_iface_ch8_count_transm_lwb <= '0';
      wb_trig_iface_ch8_count_transm_lwb_delay <= '0';
      wb_trig_iface_ch8_count_transm_lwb_in_progress <= '0';
      wb_trig_iface_ch9_ctl_dir_int <= '0';
      wb_trig_iface_ch9_ctl_dir_pol_int <= '0';
      wb_trig_iface_ch9_ctl_rcv_count_rst_int <= '0';
      wb_trig_iface_ch9_ctl_rcv_count_rst_int_delay <= '0';
      wb_trig_iface_ch9_ctl_transm_count_rst_int <= '0';
      wb_trig_iface_ch9_ctl_transm_count_rst_int_delay <= '0';
      wb_trig_iface_ch9_cfg_rcv_len_int <= "00000000";
      wb_trig_iface_ch9_cfg_rcv_len_swb <= '0';
      wb_trig_iface_ch9_cfg_rcv_len_swb_delay <= '0';
      wb_trig_iface_ch9_cfg_transm_len_int <= "00000000";
      wb_trig_iface_ch9_cfg_transm_len_swb <= '0';
      wb_trig_iface_ch9_cfg_transm_len_swb_delay <= '0';
      wb_trig_iface_ch9_count_rcv_lwb <= '0';
      wb_trig_iface_ch9_count_rcv_lwb_delay <= '0';
      wb_trig_iface_ch9_count_rcv_lwb_in_progress <= '0';
      wb_trig_iface_ch9_count_transm_lwb <= '0';
      wb_trig_iface_ch9_count_transm_lwb_delay <= '0';
      wb_trig_iface_ch9_count_transm_lwb_in_progress <= '0';
      wb_trig_iface_ch10_ctl_dir_int <= '0';
      wb_trig_iface_ch10_ctl_dir_pol_int <= '0';
      wb_trig_iface_ch10_ctl_rcv_count_rst_int <= '0';
      wb_trig_iface_ch10_ctl_rcv_count_rst_int_delay <= '0';
      wb_trig_iface_ch10_ctl_transm_count_rst_int <= '0';
      wb_trig_iface_ch10_ctl_transm_count_rst_int_delay <= '0';
      wb_trig_iface_ch10_cfg_rcv_len_int <= "00000000";
      wb_trig_iface_ch10_cfg_rcv_len_swb <= '0';
      wb_trig_iface_ch10_cfg_rcv_len_swb_delay <= '0';
      wb_trig_iface_ch10_cfg_transm_len_int <= "00000000";
      wb_trig_iface_ch10_cfg_transm_len_swb <= '0';
      wb_trig_iface_ch10_cfg_transm_len_swb_delay <= '0';
      wb_trig_iface_ch10_count_rcv_lwb <= '0';
      wb_trig_iface_ch10_count_rcv_lwb_delay <= '0';
      wb_trig_iface_ch10_count_rcv_lwb_in_progress <= '0';
      wb_trig_iface_ch10_count_transm_lwb <= '0';
      wb_trig_iface_ch10_count_transm_lwb_delay <= '0';
      wb_trig_iface_ch10_count_transm_lwb_in_progress <= '0';
      wb_trig_iface_ch11_ctl_dir_int <= '0';
      wb_trig_iface_ch11_ctl_dir_pol_int <= '0';
      wb_trig_iface_ch11_ctl_rcv_count_rst_int <= '0';
      wb_trig_iface_ch11_ctl_rcv_count_rst_int_delay <= '0';
      wb_trig_iface_ch11_ctl_transm_count_rst_int <= '0';
      wb_trig_iface_ch11_ctl_transm_count_rst_int_delay <= '0';
      wb_trig_iface_ch11_cfg_rcv_len_int <= "00000000";
      wb_trig_iface_ch11_cfg_rcv_len_swb <= '0';
      wb_trig_iface_ch11_cfg_rcv_len_swb_delay <= '0';
      wb_trig_iface_ch11_cfg_transm_len_int <= "00000000";
      wb_trig_iface_ch11_cfg_transm_len_swb <= '0';
      wb_trig_iface_ch11_cfg_transm_len_swb_delay <= '0';
      wb_trig_iface_ch11_count_rcv_lwb <= '0';
      wb_trig_iface_ch11_count_rcv_lwb_delay <= '0';
      wb_trig_iface_ch11_count_rcv_lwb_in_progress <= '0';
      wb_trig_iface_ch11_count_transm_lwb <= '0';
      wb_trig_iface_ch11_count_transm_lwb_delay <= '0';
      wb_trig_iface_ch11_count_transm_lwb_in_progress <= '0';
      wb_trig_iface_ch12_ctl_dir_int <= '0';
      wb_trig_iface_ch12_ctl_dir_pol_int <= '0';
      wb_trig_iface_ch12_ctl_rcv_count_rst_int <= '0';
      wb_trig_iface_ch12_ctl_rcv_count_rst_int_delay <= '0';
      wb_trig_iface_ch12_ctl_transm_count_rst_int <= '0';
      wb_trig_iface_ch12_ctl_transm_count_rst_int_delay <= '0';
      wb_trig_iface_ch12_cfg_rcv_len_int <= "00000000";
      wb_trig_iface_ch12_cfg_rcv_len_swb <= '0';
      wb_trig_iface_ch12_cfg_rcv_len_swb_delay <= '0';
      wb_trig_iface_ch12_cfg_transm_len_int <= "00000000";
      wb_trig_iface_ch12_cfg_transm_len_swb <= '0';
      wb_trig_iface_ch12_cfg_transm_len_swb_delay <= '0';
      wb_trig_iface_ch12_count_rcv_lwb <= '0';
      wb_trig_iface_ch12_count_rcv_lwb_delay <= '0';
      wb_trig_iface_ch12_count_rcv_lwb_in_progress <= '0';
      wb_trig_iface_ch12_count_transm_lwb <= '0';
      wb_trig_iface_ch12_count_transm_lwb_delay <= '0';
      wb_trig_iface_ch12_count_transm_lwb_in_progress <= '0';
      wb_trig_iface_ch13_ctl_dir_int <= '0';
      wb_trig_iface_ch13_ctl_dir_pol_int <= '0';
      wb_trig_iface_ch13_ctl_rcv_count_rst_int <= '0';
      wb_trig_iface_ch13_ctl_rcv_count_rst_int_delay <= '0';
      wb_trig_iface_ch13_ctl_transm_count_rst_int <= '0';
      wb_trig_iface_ch13_ctl_transm_count_rst_int_delay <= '0';
      wb_trig_iface_ch13_cfg_rcv_len_int <= "00000000";
      wb_trig_iface_ch13_cfg_rcv_len_swb <= '0';
      wb_trig_iface_ch13_cfg_rcv_len_swb_delay <= '0';
      wb_trig_iface_ch13_cfg_transm_len_int <= "00000000";
      wb_trig_iface_ch13_cfg_transm_len_swb <= '0';
      wb_trig_iface_ch13_cfg_transm_len_swb_delay <= '0';
      wb_trig_iface_ch13_count_rcv_lwb <= '0';
      wb_trig_iface_ch13_count_rcv_lwb_delay <= '0';
      wb_trig_iface_ch13_count_rcv_lwb_in_progress <= '0';
      wb_trig_iface_ch13_count_transm_lwb <= '0';
      wb_trig_iface_ch13_count_transm_lwb_delay <= '0';
      wb_trig_iface_ch13_count_transm_lwb_in_progress <= '0';
      wb_trig_iface_ch14_ctl_dir_int <= '0';
      wb_trig_iface_ch14_ctl_dir_pol_int <= '0';
      wb_trig_iface_ch14_ctl_rcv_count_rst_int <= '0';
      wb_trig_iface_ch14_ctl_rcv_count_rst_int_delay <= '0';
      wb_trig_iface_ch14_ctl_transm_count_rst_int <= '0';
      wb_trig_iface_ch14_ctl_transm_count_rst_int_delay <= '0';
      wb_trig_iface_ch14_cfg_rcv_len_int <= "00000000";
      wb_trig_iface_ch14_cfg_rcv_len_swb <= '0';
      wb_trig_iface_ch14_cfg_rcv_len_swb_delay <= '0';
      wb_trig_iface_ch14_cfg_transm_len_int <= "00000000";
      wb_trig_iface_ch14_cfg_transm_len_swb <= '0';
      wb_trig_iface_ch14_cfg_transm_len_swb_delay <= '0';
      wb_trig_iface_ch14_count_rcv_lwb <= '0';
      wb_trig_iface_ch14_count_rcv_lwb_delay <= '0';
      wb_trig_iface_ch14_count_rcv_lwb_in_progress <= '0';
      wb_trig_iface_ch14_count_transm_lwb <= '0';
      wb_trig_iface_ch14_count_transm_lwb_delay <= '0';
      wb_trig_iface_ch14_count_transm_lwb_in_progress <= '0';
      wb_trig_iface_ch15_ctl_dir_int <= '0';
      wb_trig_iface_ch15_ctl_dir_pol_int <= '0';
      wb_trig_iface_ch15_ctl_rcv_count_rst_int <= '0';
      wb_trig_iface_ch15_ctl_rcv_count_rst_int_delay <= '0';
      wb_trig_iface_ch15_ctl_transm_count_rst_int <= '0';
      wb_trig_iface_ch15_ctl_transm_count_rst_int_delay <= '0';
      wb_trig_iface_ch15_cfg_rcv_len_int <= "00000000";
      wb_trig_iface_ch15_cfg_rcv_len_swb <= '0';
      wb_trig_iface_ch15_cfg_rcv_len_swb_delay <= '0';
      wb_trig_iface_ch15_cfg_transm_len_int <= "00000000";
      wb_trig_iface_ch15_cfg_transm_len_swb <= '0';
      wb_trig_iface_ch15_cfg_transm_len_swb_delay <= '0';
      wb_trig_iface_ch15_count_rcv_lwb <= '0';
      wb_trig_iface_ch15_count_rcv_lwb_delay <= '0';
      wb_trig_iface_ch15_count_rcv_lwb_in_progress <= '0';
      wb_trig_iface_ch15_count_transm_lwb <= '0';
      wb_trig_iface_ch15_count_transm_lwb_delay <= '0';
      wb_trig_iface_ch15_count_transm_lwb_in_progress <= '0';
      wb_trig_iface_ch16_ctl_dir_int <= '0';
      wb_trig_iface_ch16_ctl_dir_pol_int <= '0';
      wb_trig_iface_ch16_ctl_rcv_count_rst_int <= '0';
      wb_trig_iface_ch16_ctl_rcv_count_rst_int_delay <= '0';
      wb_trig_iface_ch16_ctl_transm_count_rst_int <= '0';
      wb_trig_iface_ch16_ctl_transm_count_rst_int_delay <= '0';
      wb_trig_iface_ch16_cfg_rcv_len_int <= "00000000";
      wb_trig_iface_ch16_cfg_rcv_len_swb <= '0';
      wb_trig_iface_ch16_cfg_rcv_len_swb_delay <= '0';
      wb_trig_iface_ch16_cfg_transm_len_int <= "00000000";
      wb_trig_iface_ch16_cfg_transm_len_swb <= '0';
      wb_trig_iface_ch16_cfg_transm_len_swb_delay <= '0';
      wb_trig_iface_ch16_count_rcv_lwb <= '0';
      wb_trig_iface_ch16_count_rcv_lwb_delay <= '0';
      wb_trig_iface_ch16_count_rcv_lwb_in_progress <= '0';
      wb_trig_iface_ch16_count_transm_lwb <= '0';
      wb_trig_iface_ch16_count_transm_lwb_delay <= '0';
      wb_trig_iface_ch16_count_transm_lwb_in_progress <= '0';
      wb_trig_iface_ch17_ctl_dir_int <= '0';
      wb_trig_iface_ch17_ctl_dir_pol_int <= '0';
      wb_trig_iface_ch17_ctl_rcv_count_rst_int <= '0';
      wb_trig_iface_ch17_ctl_rcv_count_rst_int_delay <= '0';
      wb_trig_iface_ch17_ctl_transm_count_rst_int <= '0';
      wb_trig_iface_ch17_ctl_transm_count_rst_int_delay <= '0';
      wb_trig_iface_ch17_cfg_rcv_len_int <= "00000000";
      wb_trig_iface_ch17_cfg_rcv_len_swb <= '0';
      wb_trig_iface_ch17_cfg_rcv_len_swb_delay <= '0';
      wb_trig_iface_ch17_cfg_transm_len_int <= "00000000";
      wb_trig_iface_ch17_cfg_transm_len_swb <= '0';
      wb_trig_iface_ch17_cfg_transm_len_swb_delay <= '0';
      wb_trig_iface_ch17_count_rcv_lwb <= '0';
      wb_trig_iface_ch17_count_rcv_lwb_delay <= '0';
      wb_trig_iface_ch17_count_rcv_lwb_in_progress <= '0';
      wb_trig_iface_ch17_count_transm_lwb <= '0';
      wb_trig_iface_ch17_count_transm_lwb_delay <= '0';
      wb_trig_iface_ch17_count_transm_lwb_in_progress <= '0';
      wb_trig_iface_ch18_ctl_dir_int <= '0';
      wb_trig_iface_ch18_ctl_dir_pol_int <= '0';
      wb_trig_iface_ch18_ctl_rcv_count_rst_int <= '0';
      wb_trig_iface_ch18_ctl_rcv_count_rst_int_delay <= '0';
      wb_trig_iface_ch18_ctl_transm_count_rst_int <= '0';
      wb_trig_iface_ch18_ctl_transm_count_rst_int_delay <= '0';
      wb_trig_iface_ch18_cfg_rcv_len_int <= "00000000";
      wb_trig_iface_ch18_cfg_rcv_len_swb <= '0';
      wb_trig_iface_ch18_cfg_rcv_len_swb_delay <= '0';
      wb_trig_iface_ch18_cfg_transm_len_int <= "00000000";
      wb_trig_iface_ch18_cfg_transm_len_swb <= '0';
      wb_trig_iface_ch18_cfg_transm_len_swb_delay <= '0';
      wb_trig_iface_ch18_count_rcv_lwb <= '0';
      wb_trig_iface_ch18_count_rcv_lwb_delay <= '0';
      wb_trig_iface_ch18_count_rcv_lwb_in_progress <= '0';
      wb_trig_iface_ch18_count_transm_lwb <= '0';
      wb_trig_iface_ch18_count_transm_lwb_delay <= '0';
      wb_trig_iface_ch18_count_transm_lwb_in_progress <= '0';
      wb_trig_iface_ch19_ctl_dir_int <= '0';
      wb_trig_iface_ch19_ctl_dir_pol_int <= '0';
      wb_trig_iface_ch19_ctl_rcv_count_rst_int <= '0';
      wb_trig_iface_ch19_ctl_rcv_count_rst_int_delay <= '0';
      wb_trig_iface_ch19_ctl_transm_count_rst_int <= '0';
      wb_trig_iface_ch19_ctl_transm_count_rst_int_delay <= '0';
      wb_trig_iface_ch19_cfg_rcv_len_int <= "00000000";
      wb_trig_iface_ch19_cfg_rcv_len_swb <= '0';
      wb_trig_iface_ch19_cfg_rcv_len_swb_delay <= '0';
      wb_trig_iface_ch19_cfg_transm_len_int <= "00000000";
      wb_trig_iface_ch19_cfg_transm_len_swb <= '0';
      wb_trig_iface_ch19_cfg_transm_len_swb_delay <= '0';
      wb_trig_iface_ch19_count_rcv_lwb <= '0';
      wb_trig_iface_ch19_count_rcv_lwb_delay <= '0';
      wb_trig_iface_ch19_count_rcv_lwb_in_progress <= '0';
      wb_trig_iface_ch19_count_transm_lwb <= '0';
      wb_trig_iface_ch19_count_transm_lwb_delay <= '0';
      wb_trig_iface_ch19_count_transm_lwb_in_progress <= '0';
      wb_trig_iface_ch20_ctl_dir_int <= '0';
      wb_trig_iface_ch20_ctl_dir_pol_int <= '0';
      wb_trig_iface_ch20_ctl_rcv_count_rst_int <= '0';
      wb_trig_iface_ch20_ctl_rcv_count_rst_int_delay <= '0';
      wb_trig_iface_ch20_ctl_transm_count_rst_int <= '0';
      wb_trig_iface_ch20_ctl_transm_count_rst_int_delay <= '0';
      wb_trig_iface_ch20_cfg_rcv_len_int <= "00000000";
      wb_trig_iface_ch20_cfg_rcv_len_swb <= '0';
      wb_trig_iface_ch20_cfg_rcv_len_swb_delay <= '0';
      wb_trig_iface_ch20_cfg_transm_len_int <= "00000000";
      wb_trig_iface_ch20_cfg_transm_len_swb <= '0';
      wb_trig_iface_ch20_cfg_transm_len_swb_delay <= '0';
      wb_trig_iface_ch20_count_rcv_lwb <= '0';
      wb_trig_iface_ch20_count_rcv_lwb_delay <= '0';
      wb_trig_iface_ch20_count_rcv_lwb_in_progress <= '0';
      wb_trig_iface_ch20_count_transm_lwb <= '0';
      wb_trig_iface_ch20_count_transm_lwb_delay <= '0';
      wb_trig_iface_ch20_count_transm_lwb_in_progress <= '0';
      wb_trig_iface_ch21_ctl_dir_int <= '0';
      wb_trig_iface_ch21_ctl_dir_pol_int <= '0';
      wb_trig_iface_ch21_ctl_rcv_count_rst_int <= '0';
      wb_trig_iface_ch21_ctl_rcv_count_rst_int_delay <= '0';
      wb_trig_iface_ch21_ctl_transm_count_rst_int <= '0';
      wb_trig_iface_ch21_ctl_transm_count_rst_int_delay <= '0';
      wb_trig_iface_ch21_cfg_rcv_len_int <= "00000000";
      wb_trig_iface_ch21_cfg_rcv_len_swb <= '0';
      wb_trig_iface_ch21_cfg_rcv_len_swb_delay <= '0';
      wb_trig_iface_ch21_cfg_transm_len_int <= "00000000";
      wb_trig_iface_ch21_cfg_transm_len_swb <= '0';
      wb_trig_iface_ch21_cfg_transm_len_swb_delay <= '0';
      wb_trig_iface_ch21_count_rcv_lwb <= '0';
      wb_trig_iface_ch21_count_rcv_lwb_delay <= '0';
      wb_trig_iface_ch21_count_rcv_lwb_in_progress <= '0';
      wb_trig_iface_ch21_count_transm_lwb <= '0';
      wb_trig_iface_ch21_count_transm_lwb_delay <= '0';
      wb_trig_iface_ch21_count_transm_lwb_in_progress <= '0';
      wb_trig_iface_ch22_ctl_dir_int <= '0';
      wb_trig_iface_ch22_ctl_dir_pol_int <= '0';
      wb_trig_iface_ch22_ctl_rcv_count_rst_int <= '0';
      wb_trig_iface_ch22_ctl_rcv_count_rst_int_delay <= '0';
      wb_trig_iface_ch22_ctl_transm_count_rst_int <= '0';
      wb_trig_iface_ch22_ctl_transm_count_rst_int_delay <= '0';
      wb_trig_iface_ch22_cfg_rcv_len_int <= "00000000";
      wb_trig_iface_ch22_cfg_rcv_len_swb <= '0';
      wb_trig_iface_ch22_cfg_rcv_len_swb_delay <= '0';
      wb_trig_iface_ch22_cfg_transm_len_int <= "00000000";
      wb_trig_iface_ch22_cfg_transm_len_swb <= '0';
      wb_trig_iface_ch22_cfg_transm_len_swb_delay <= '0';
      wb_trig_iface_ch22_count_rcv_lwb <= '0';
      wb_trig_iface_ch22_count_rcv_lwb_delay <= '0';
      wb_trig_iface_ch22_count_rcv_lwb_in_progress <= '0';
      wb_trig_iface_ch22_count_transm_lwb <= '0';
      wb_trig_iface_ch22_count_transm_lwb_delay <= '0';
      wb_trig_iface_ch22_count_transm_lwb_in_progress <= '0';
      wb_trig_iface_ch23_ctl_dir_int <= '0';
      wb_trig_iface_ch23_ctl_dir_pol_int <= '0';
      wb_trig_iface_ch23_ctl_rcv_count_rst_int <= '0';
      wb_trig_iface_ch23_ctl_rcv_count_rst_int_delay <= '0';
      wb_trig_iface_ch23_ctl_transm_count_rst_int <= '0';
      wb_trig_iface_ch23_ctl_transm_count_rst_int_delay <= '0';
      wb_trig_iface_ch23_cfg_rcv_len_int <= "00000000";
      wb_trig_iface_ch23_cfg_rcv_len_swb <= '0';
      wb_trig_iface_ch23_cfg_rcv_len_swb_delay <= '0';
      wb_trig_iface_ch23_cfg_transm_len_int <= "00000000";
      wb_trig_iface_ch23_cfg_transm_len_swb <= '0';
      wb_trig_iface_ch23_cfg_transm_len_swb_delay <= '0';
      wb_trig_iface_ch23_count_rcv_lwb <= '0';
      wb_trig_iface_ch23_count_rcv_lwb_delay <= '0';
      wb_trig_iface_ch23_count_rcv_lwb_in_progress <= '0';
      wb_trig_iface_ch23_count_transm_lwb <= '0';
      wb_trig_iface_ch23_count_transm_lwb_delay <= '0';
      wb_trig_iface_ch23_count_transm_lwb_in_progress <= '0';
    elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
      ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
      ack_sreg(9) <= '0';
      if (ack_in_progress = '1') then
        if (ack_sreg(0) = '1') then
          ack_in_progress <= '0';
        else
          wb_trig_iface_ch0_ctl_rcv_count_rst_int <= wb_trig_iface_ch0_ctl_rcv_count_rst_int_delay;
          wb_trig_iface_ch0_ctl_rcv_count_rst_int_delay <= '0';
          wb_trig_iface_ch0_ctl_transm_count_rst_int <= wb_trig_iface_ch0_ctl_transm_count_rst_int_delay;
          wb_trig_iface_ch0_ctl_transm_count_rst_int_delay <= '0';
          wb_trig_iface_ch0_cfg_rcv_len_swb <= wb_trig_iface_ch0_cfg_rcv_len_swb_delay;
          wb_trig_iface_ch0_cfg_rcv_len_swb_delay <= '0';
          wb_trig_iface_ch0_cfg_transm_len_swb <= wb_trig_iface_ch0_cfg_transm_len_swb_delay;
          wb_trig_iface_ch0_cfg_transm_len_swb_delay <= '0';
          wb_trig_iface_ch0_count_rcv_lwb <= wb_trig_iface_ch0_count_rcv_lwb_delay;
          wb_trig_iface_ch0_count_rcv_lwb_delay <= '0';
          if ((ack_sreg(1) = '1') and (wb_trig_iface_ch0_count_rcv_lwb_in_progress = '1')) then
            rddata_reg(15 downto 0) <= wb_trig_iface_ch0_count_rcv_int;
            wb_trig_iface_ch0_count_rcv_lwb_in_progress <= '0';
          end if;
          wb_trig_iface_ch0_count_transm_lwb <= wb_trig_iface_ch0_count_transm_lwb_delay;
          wb_trig_iface_ch0_count_transm_lwb_delay <= '0';
          if ((ack_sreg(1) = '1') and (wb_trig_iface_ch0_count_transm_lwb_in_progress = '1')) then
            rddata_reg(31 downto 16) <= wb_trig_iface_ch0_count_transm_int;
            wb_trig_iface_ch0_count_transm_lwb_in_progress <= '0';
          end if;
          wb_trig_iface_ch1_ctl_rcv_count_rst_int <= wb_trig_iface_ch1_ctl_rcv_count_rst_int_delay;
          wb_trig_iface_ch1_ctl_rcv_count_rst_int_delay <= '0';
          wb_trig_iface_ch1_ctl_transm_count_rst_int <= wb_trig_iface_ch1_ctl_transm_count_rst_int_delay;
          wb_trig_iface_ch1_ctl_transm_count_rst_int_delay <= '0';
          wb_trig_iface_ch1_cfg_rcv_len_swb <= wb_trig_iface_ch1_cfg_rcv_len_swb_delay;
          wb_trig_iface_ch1_cfg_rcv_len_swb_delay <= '0';
          wb_trig_iface_ch1_cfg_transm_len_swb <= wb_trig_iface_ch1_cfg_transm_len_swb_delay;
          wb_trig_iface_ch1_cfg_transm_len_swb_delay <= '0';
          wb_trig_iface_ch1_count_rcv_lwb <= wb_trig_iface_ch1_count_rcv_lwb_delay;
          wb_trig_iface_ch1_count_rcv_lwb_delay <= '0';
          if ((ack_sreg(1) = '1') and (wb_trig_iface_ch1_count_rcv_lwb_in_progress = '1')) then
            rddata_reg(15 downto 0) <= wb_trig_iface_ch1_count_rcv_int;
            wb_trig_iface_ch1_count_rcv_lwb_in_progress <= '0';
          end if;
          wb_trig_iface_ch1_count_transm_lwb <= wb_trig_iface_ch1_count_transm_lwb_delay;
          wb_trig_iface_ch1_count_transm_lwb_delay <= '0';
          if ((ack_sreg(1) = '1') and (wb_trig_iface_ch1_count_transm_lwb_in_progress = '1')) then
            rddata_reg(31 downto 16) <= wb_trig_iface_ch1_count_transm_int;
            wb_trig_iface_ch1_count_transm_lwb_in_progress <= '0';
          end if;
          wb_trig_iface_ch2_ctl_rcv_count_rst_int <= wb_trig_iface_ch2_ctl_rcv_count_rst_int_delay;
          wb_trig_iface_ch2_ctl_rcv_count_rst_int_delay <= '0';
          wb_trig_iface_ch2_ctl_transm_count_rst_int <= wb_trig_iface_ch2_ctl_transm_count_rst_int_delay;
          wb_trig_iface_ch2_ctl_transm_count_rst_int_delay <= '0';
          wb_trig_iface_ch2_cfg_rcv_len_swb <= wb_trig_iface_ch2_cfg_rcv_len_swb_delay;
          wb_trig_iface_ch2_cfg_rcv_len_swb_delay <= '0';
          wb_trig_iface_ch2_cfg_transm_len_swb <= wb_trig_iface_ch2_cfg_transm_len_swb_delay;
          wb_trig_iface_ch2_cfg_transm_len_swb_delay <= '0';
          wb_trig_iface_ch2_count_rcv_lwb <= wb_trig_iface_ch2_count_rcv_lwb_delay;
          wb_trig_iface_ch2_count_rcv_lwb_delay <= '0';
          if ((ack_sreg(1) = '1') and (wb_trig_iface_ch2_count_rcv_lwb_in_progress = '1')) then
            rddata_reg(15 downto 0) <= wb_trig_iface_ch2_count_rcv_int;
            wb_trig_iface_ch2_count_rcv_lwb_in_progress <= '0';
          end if;
          wb_trig_iface_ch2_count_transm_lwb <= wb_trig_iface_ch2_count_transm_lwb_delay;
          wb_trig_iface_ch2_count_transm_lwb_delay <= '0';
          if ((ack_sreg(1) = '1') and (wb_trig_iface_ch2_count_transm_lwb_in_progress = '1')) then
            rddata_reg(31 downto 16) <= wb_trig_iface_ch2_count_transm_int;
            wb_trig_iface_ch2_count_transm_lwb_in_progress <= '0';
          end if;
          wb_trig_iface_ch3_ctl_rcv_count_rst_int <= wb_trig_iface_ch3_ctl_rcv_count_rst_int_delay;
          wb_trig_iface_ch3_ctl_rcv_count_rst_int_delay <= '0';
          wb_trig_iface_ch3_ctl_transm_count_rst_int <= wb_trig_iface_ch3_ctl_transm_count_rst_int_delay;
          wb_trig_iface_ch3_ctl_transm_count_rst_int_delay <= '0';
          wb_trig_iface_ch3_cfg_rcv_len_swb <= wb_trig_iface_ch3_cfg_rcv_len_swb_delay;
          wb_trig_iface_ch3_cfg_rcv_len_swb_delay <= '0';
          wb_trig_iface_ch3_cfg_transm_len_swb <= wb_trig_iface_ch3_cfg_transm_len_swb_delay;
          wb_trig_iface_ch3_cfg_transm_len_swb_delay <= '0';
          wb_trig_iface_ch3_count_rcv_lwb <= wb_trig_iface_ch3_count_rcv_lwb_delay;
          wb_trig_iface_ch3_count_rcv_lwb_delay <= '0';
          if ((ack_sreg(1) = '1') and (wb_trig_iface_ch3_count_rcv_lwb_in_progress = '1')) then
            rddata_reg(15 downto 0) <= wb_trig_iface_ch3_count_rcv_int;
            wb_trig_iface_ch3_count_rcv_lwb_in_progress <= '0';
          end if;
          wb_trig_iface_ch3_count_transm_lwb <= wb_trig_iface_ch3_count_transm_lwb_delay;
          wb_trig_iface_ch3_count_transm_lwb_delay <= '0';
          if ((ack_sreg(1) = '1') and (wb_trig_iface_ch3_count_transm_lwb_in_progress = '1')) then
            rddata_reg(31 downto 16) <= wb_trig_iface_ch3_count_transm_int;
            wb_trig_iface_ch3_count_transm_lwb_in_progress <= '0';
          end if;
          wb_trig_iface_ch4_ctl_rcv_count_rst_int <= wb_trig_iface_ch4_ctl_rcv_count_rst_int_delay;
          wb_trig_iface_ch4_ctl_rcv_count_rst_int_delay <= '0';
          wb_trig_iface_ch4_ctl_transm_count_rst_int <= wb_trig_iface_ch4_ctl_transm_count_rst_int_delay;
          wb_trig_iface_ch4_ctl_transm_count_rst_int_delay <= '0';
          wb_trig_iface_ch4_cfg_rcv_len_swb <= wb_trig_iface_ch4_cfg_rcv_len_swb_delay;
          wb_trig_iface_ch4_cfg_rcv_len_swb_delay <= '0';
          wb_trig_iface_ch4_cfg_transm_len_swb <= wb_trig_iface_ch4_cfg_transm_len_swb_delay;
          wb_trig_iface_ch4_cfg_transm_len_swb_delay <= '0';
          wb_trig_iface_ch4_count_rcv_lwb <= wb_trig_iface_ch4_count_rcv_lwb_delay;
          wb_trig_iface_ch4_count_rcv_lwb_delay <= '0';
          if ((ack_sreg(1) = '1') and (wb_trig_iface_ch4_count_rcv_lwb_in_progress = '1')) then
            rddata_reg(15 downto 0) <= wb_trig_iface_ch4_count_rcv_int;
            wb_trig_iface_ch4_count_rcv_lwb_in_progress <= '0';
          end if;
          wb_trig_iface_ch4_count_transm_lwb <= wb_trig_iface_ch4_count_transm_lwb_delay;
          wb_trig_iface_ch4_count_transm_lwb_delay <= '0';
          if ((ack_sreg(1) = '1') and (wb_trig_iface_ch4_count_transm_lwb_in_progress = '1')) then
            rddata_reg(31 downto 16) <= wb_trig_iface_ch4_count_transm_int;
            wb_trig_iface_ch4_count_transm_lwb_in_progress <= '0';
          end if;
          wb_trig_iface_ch5_ctl_rcv_count_rst_int <= wb_trig_iface_ch5_ctl_rcv_count_rst_int_delay;
          wb_trig_iface_ch5_ctl_rcv_count_rst_int_delay <= '0';
          wb_trig_iface_ch5_ctl_transm_count_rst_int <= wb_trig_iface_ch5_ctl_transm_count_rst_int_delay;
          wb_trig_iface_ch5_ctl_transm_count_rst_int_delay <= '0';
          wb_trig_iface_ch5_cfg_rcv_len_swb <= wb_trig_iface_ch5_cfg_rcv_len_swb_delay;
          wb_trig_iface_ch5_cfg_rcv_len_swb_delay <= '0';
          wb_trig_iface_ch5_cfg_transm_len_swb <= wb_trig_iface_ch5_cfg_transm_len_swb_delay;
          wb_trig_iface_ch5_cfg_transm_len_swb_delay <= '0';
          wb_trig_iface_ch5_count_rcv_lwb <= wb_trig_iface_ch5_count_rcv_lwb_delay;
          wb_trig_iface_ch5_count_rcv_lwb_delay <= '0';
          if ((ack_sreg(1) = '1') and (wb_trig_iface_ch5_count_rcv_lwb_in_progress = '1')) then
            rddata_reg(15 downto 0) <= wb_trig_iface_ch5_count_rcv_int;
            wb_trig_iface_ch5_count_rcv_lwb_in_progress <= '0';
          end if;
          wb_trig_iface_ch5_count_transm_lwb <= wb_trig_iface_ch5_count_transm_lwb_delay;
          wb_trig_iface_ch5_count_transm_lwb_delay <= '0';
          if ((ack_sreg(1) = '1') and (wb_trig_iface_ch5_count_transm_lwb_in_progress = '1')) then
            rddata_reg(31 downto 16) <= wb_trig_iface_ch5_count_transm_int;
            wb_trig_iface_ch5_count_transm_lwb_in_progress <= '0';
          end if;
          wb_trig_iface_ch6_ctl_rcv_count_rst_int <= wb_trig_iface_ch6_ctl_rcv_count_rst_int_delay;
          wb_trig_iface_ch6_ctl_rcv_count_rst_int_delay <= '0';
          wb_trig_iface_ch6_ctl_transm_count_rst_int <= wb_trig_iface_ch6_ctl_transm_count_rst_int_delay;
          wb_trig_iface_ch6_ctl_transm_count_rst_int_delay <= '0';
          wb_trig_iface_ch6_cfg_rcv_len_swb <= wb_trig_iface_ch6_cfg_rcv_len_swb_delay;
          wb_trig_iface_ch6_cfg_rcv_len_swb_delay <= '0';
          wb_trig_iface_ch6_cfg_transm_len_swb <= wb_trig_iface_ch6_cfg_transm_len_swb_delay;
          wb_trig_iface_ch6_cfg_transm_len_swb_delay <= '0';
          wb_trig_iface_ch6_count_rcv_lwb <= wb_trig_iface_ch6_count_rcv_lwb_delay;
          wb_trig_iface_ch6_count_rcv_lwb_delay <= '0';
          if ((ack_sreg(1) = '1') and (wb_trig_iface_ch6_count_rcv_lwb_in_progress = '1')) then
            rddata_reg(15 downto 0) <= wb_trig_iface_ch6_count_rcv_int;
            wb_trig_iface_ch6_count_rcv_lwb_in_progress <= '0';
          end if;
          wb_trig_iface_ch6_count_transm_lwb <= wb_trig_iface_ch6_count_transm_lwb_delay;
          wb_trig_iface_ch6_count_transm_lwb_delay <= '0';
          if ((ack_sreg(1) = '1') and (wb_trig_iface_ch6_count_transm_lwb_in_progress = '1')) then
            rddata_reg(31 downto 16) <= wb_trig_iface_ch6_count_transm_int;
            wb_trig_iface_ch6_count_transm_lwb_in_progress <= '0';
          end if;
          wb_trig_iface_ch7_ctl_rcv_count_rst_int <= wb_trig_iface_ch7_ctl_rcv_count_rst_int_delay;
          wb_trig_iface_ch7_ctl_rcv_count_rst_int_delay <= '0';
          wb_trig_iface_ch7_ctl_transm_count_rst_int <= wb_trig_iface_ch7_ctl_transm_count_rst_int_delay;
          wb_trig_iface_ch7_ctl_transm_count_rst_int_delay <= '0';
          wb_trig_iface_ch7_cfg_rcv_len_swb <= wb_trig_iface_ch7_cfg_rcv_len_swb_delay;
          wb_trig_iface_ch7_cfg_rcv_len_swb_delay <= '0';
          wb_trig_iface_ch7_cfg_transm_len_swb <= wb_trig_iface_ch7_cfg_transm_len_swb_delay;
          wb_trig_iface_ch7_cfg_transm_len_swb_delay <= '0';
          wb_trig_iface_ch7_count_rcv_lwb <= wb_trig_iface_ch7_count_rcv_lwb_delay;
          wb_trig_iface_ch7_count_rcv_lwb_delay <= '0';
          if ((ack_sreg(1) = '1') and (wb_trig_iface_ch7_count_rcv_lwb_in_progress = '1')) then
            rddata_reg(15 downto 0) <= wb_trig_iface_ch7_count_rcv_int;
            wb_trig_iface_ch7_count_rcv_lwb_in_progress <= '0';
          end if;
          wb_trig_iface_ch7_count_transm_lwb <= wb_trig_iface_ch7_count_transm_lwb_delay;
          wb_trig_iface_ch7_count_transm_lwb_delay <= '0';
          if ((ack_sreg(1) = '1') and (wb_trig_iface_ch7_count_transm_lwb_in_progress = '1')) then
            rddata_reg(31 downto 16) <= wb_trig_iface_ch7_count_transm_int;
            wb_trig_iface_ch7_count_transm_lwb_in_progress <= '0';
          end if;
          wb_trig_iface_ch8_ctl_rcv_count_rst_int <= wb_trig_iface_ch8_ctl_rcv_count_rst_int_delay;
          wb_trig_iface_ch8_ctl_rcv_count_rst_int_delay <= '0';
          wb_trig_iface_ch8_ctl_transm_count_rst_int <= wb_trig_iface_ch8_ctl_transm_count_rst_int_delay;
          wb_trig_iface_ch8_ctl_transm_count_rst_int_delay <= '0';
          wb_trig_iface_ch8_cfg_rcv_len_swb <= wb_trig_iface_ch8_cfg_rcv_len_swb_delay;
          wb_trig_iface_ch8_cfg_rcv_len_swb_delay <= '0';
          wb_trig_iface_ch8_cfg_transm_len_swb <= wb_trig_iface_ch8_cfg_transm_len_swb_delay;
          wb_trig_iface_ch8_cfg_transm_len_swb_delay <= '0';
          wb_trig_iface_ch8_count_rcv_lwb <= wb_trig_iface_ch8_count_rcv_lwb_delay;
          wb_trig_iface_ch8_count_rcv_lwb_delay <= '0';
          if ((ack_sreg(1) = '1') and (wb_trig_iface_ch8_count_rcv_lwb_in_progress = '1')) then
            rddata_reg(15 downto 0) <= wb_trig_iface_ch8_count_rcv_int;
            wb_trig_iface_ch8_count_rcv_lwb_in_progress <= '0';
          end if;
          wb_trig_iface_ch8_count_transm_lwb <= wb_trig_iface_ch8_count_transm_lwb_delay;
          wb_trig_iface_ch8_count_transm_lwb_delay <= '0';
          if ((ack_sreg(1) = '1') and (wb_trig_iface_ch8_count_transm_lwb_in_progress = '1')) then
            rddata_reg(31 downto 16) <= wb_trig_iface_ch8_count_transm_int;
            wb_trig_iface_ch8_count_transm_lwb_in_progress <= '0';
          end if;
          wb_trig_iface_ch9_ctl_rcv_count_rst_int <= wb_trig_iface_ch9_ctl_rcv_count_rst_int_delay;
          wb_trig_iface_ch9_ctl_rcv_count_rst_int_delay <= '0';
          wb_trig_iface_ch9_ctl_transm_count_rst_int <= wb_trig_iface_ch9_ctl_transm_count_rst_int_delay;
          wb_trig_iface_ch9_ctl_transm_count_rst_int_delay <= '0';
          wb_trig_iface_ch9_cfg_rcv_len_swb <= wb_trig_iface_ch9_cfg_rcv_len_swb_delay;
          wb_trig_iface_ch9_cfg_rcv_len_swb_delay <= '0';
          wb_trig_iface_ch9_cfg_transm_len_swb <= wb_trig_iface_ch9_cfg_transm_len_swb_delay;
          wb_trig_iface_ch9_cfg_transm_len_swb_delay <= '0';
          wb_trig_iface_ch9_count_rcv_lwb <= wb_trig_iface_ch9_count_rcv_lwb_delay;
          wb_trig_iface_ch9_count_rcv_lwb_delay <= '0';
          if ((ack_sreg(1) = '1') and (wb_trig_iface_ch9_count_rcv_lwb_in_progress = '1')) then
            rddata_reg(15 downto 0) <= wb_trig_iface_ch9_count_rcv_int;
            wb_trig_iface_ch9_count_rcv_lwb_in_progress <= '0';
          end if;
          wb_trig_iface_ch9_count_transm_lwb <= wb_trig_iface_ch9_count_transm_lwb_delay;
          wb_trig_iface_ch9_count_transm_lwb_delay <= '0';
          if ((ack_sreg(1) = '1') and (wb_trig_iface_ch9_count_transm_lwb_in_progress = '1')) then
            rddata_reg(31 downto 16) <= wb_trig_iface_ch9_count_transm_int;
            wb_trig_iface_ch9_count_transm_lwb_in_progress <= '0';
          end if;
          wb_trig_iface_ch10_ctl_rcv_count_rst_int <= wb_trig_iface_ch10_ctl_rcv_count_rst_int_delay;
          wb_trig_iface_ch10_ctl_rcv_count_rst_int_delay <= '0';
          wb_trig_iface_ch10_ctl_transm_count_rst_int <= wb_trig_iface_ch10_ctl_transm_count_rst_int_delay;
          wb_trig_iface_ch10_ctl_transm_count_rst_int_delay <= '0';
          wb_trig_iface_ch10_cfg_rcv_len_swb <= wb_trig_iface_ch10_cfg_rcv_len_swb_delay;
          wb_trig_iface_ch10_cfg_rcv_len_swb_delay <= '0';
          wb_trig_iface_ch10_cfg_transm_len_swb <= wb_trig_iface_ch10_cfg_transm_len_swb_delay;
          wb_trig_iface_ch10_cfg_transm_len_swb_delay <= '0';
          wb_trig_iface_ch10_count_rcv_lwb <= wb_trig_iface_ch10_count_rcv_lwb_delay;
          wb_trig_iface_ch10_count_rcv_lwb_delay <= '0';
          if ((ack_sreg(1) = '1') and (wb_trig_iface_ch10_count_rcv_lwb_in_progress = '1')) then
            rddata_reg(15 downto 0) <= wb_trig_iface_ch10_count_rcv_int;
            wb_trig_iface_ch10_count_rcv_lwb_in_progress <= '0';
          end if;
          wb_trig_iface_ch10_count_transm_lwb <= wb_trig_iface_ch10_count_transm_lwb_delay;
          wb_trig_iface_ch10_count_transm_lwb_delay <= '0';
          if ((ack_sreg(1) = '1') and (wb_trig_iface_ch10_count_transm_lwb_in_progress = '1')) then
            rddata_reg(31 downto 16) <= wb_trig_iface_ch10_count_transm_int;
            wb_trig_iface_ch10_count_transm_lwb_in_progress <= '0';
          end if;
          wb_trig_iface_ch11_ctl_rcv_count_rst_int <= wb_trig_iface_ch11_ctl_rcv_count_rst_int_delay;
          wb_trig_iface_ch11_ctl_rcv_count_rst_int_delay <= '0';
          wb_trig_iface_ch11_ctl_transm_count_rst_int <= wb_trig_iface_ch11_ctl_transm_count_rst_int_delay;
          wb_trig_iface_ch11_ctl_transm_count_rst_int_delay <= '0';
          wb_trig_iface_ch11_cfg_rcv_len_swb <= wb_trig_iface_ch11_cfg_rcv_len_swb_delay;
          wb_trig_iface_ch11_cfg_rcv_len_swb_delay <= '0';
          wb_trig_iface_ch11_cfg_transm_len_swb <= wb_trig_iface_ch11_cfg_transm_len_swb_delay;
          wb_trig_iface_ch11_cfg_transm_len_swb_delay <= '0';
          wb_trig_iface_ch11_count_rcv_lwb <= wb_trig_iface_ch11_count_rcv_lwb_delay;
          wb_trig_iface_ch11_count_rcv_lwb_delay <= '0';
          if ((ack_sreg(1) = '1') and (wb_trig_iface_ch11_count_rcv_lwb_in_progress = '1')) then
            rddata_reg(15 downto 0) <= wb_trig_iface_ch11_count_rcv_int;
            wb_trig_iface_ch11_count_rcv_lwb_in_progress <= '0';
          end if;
          wb_trig_iface_ch11_count_transm_lwb <= wb_trig_iface_ch11_count_transm_lwb_delay;
          wb_trig_iface_ch11_count_transm_lwb_delay <= '0';
          if ((ack_sreg(1) = '1') and (wb_trig_iface_ch11_count_transm_lwb_in_progress = '1')) then
            rddata_reg(31 downto 16) <= wb_trig_iface_ch11_count_transm_int;
            wb_trig_iface_ch11_count_transm_lwb_in_progress <= '0';
          end if;
          wb_trig_iface_ch12_ctl_rcv_count_rst_int <= wb_trig_iface_ch12_ctl_rcv_count_rst_int_delay;
          wb_trig_iface_ch12_ctl_rcv_count_rst_int_delay <= '0';
          wb_trig_iface_ch12_ctl_transm_count_rst_int <= wb_trig_iface_ch12_ctl_transm_count_rst_int_delay;
          wb_trig_iface_ch12_ctl_transm_count_rst_int_delay <= '0';
          wb_trig_iface_ch12_cfg_rcv_len_swb <= wb_trig_iface_ch12_cfg_rcv_len_swb_delay;
          wb_trig_iface_ch12_cfg_rcv_len_swb_delay <= '0';
          wb_trig_iface_ch12_cfg_transm_len_swb <= wb_trig_iface_ch12_cfg_transm_len_swb_delay;
          wb_trig_iface_ch12_cfg_transm_len_swb_delay <= '0';
          wb_trig_iface_ch12_count_rcv_lwb <= wb_trig_iface_ch12_count_rcv_lwb_delay;
          wb_trig_iface_ch12_count_rcv_lwb_delay <= '0';
          if ((ack_sreg(1) = '1') and (wb_trig_iface_ch12_count_rcv_lwb_in_progress = '1')) then
            rddata_reg(15 downto 0) <= wb_trig_iface_ch12_count_rcv_int;
            wb_trig_iface_ch12_count_rcv_lwb_in_progress <= '0';
          end if;
          wb_trig_iface_ch12_count_transm_lwb <= wb_trig_iface_ch12_count_transm_lwb_delay;
          wb_trig_iface_ch12_count_transm_lwb_delay <= '0';
          if ((ack_sreg(1) = '1') and (wb_trig_iface_ch12_count_transm_lwb_in_progress = '1')) then
            rddata_reg(31 downto 16) <= wb_trig_iface_ch12_count_transm_int;
            wb_trig_iface_ch12_count_transm_lwb_in_progress <= '0';
          end if;
          wb_trig_iface_ch13_ctl_rcv_count_rst_int <= wb_trig_iface_ch13_ctl_rcv_count_rst_int_delay;
          wb_trig_iface_ch13_ctl_rcv_count_rst_int_delay <= '0';
          wb_trig_iface_ch13_ctl_transm_count_rst_int <= wb_trig_iface_ch13_ctl_transm_count_rst_int_delay;
          wb_trig_iface_ch13_ctl_transm_count_rst_int_delay <= '0';
          wb_trig_iface_ch13_cfg_rcv_len_swb <= wb_trig_iface_ch13_cfg_rcv_len_swb_delay;
          wb_trig_iface_ch13_cfg_rcv_len_swb_delay <= '0';
          wb_trig_iface_ch13_cfg_transm_len_swb <= wb_trig_iface_ch13_cfg_transm_len_swb_delay;
          wb_trig_iface_ch13_cfg_transm_len_swb_delay <= '0';
          wb_trig_iface_ch13_count_rcv_lwb <= wb_trig_iface_ch13_count_rcv_lwb_delay;
          wb_trig_iface_ch13_count_rcv_lwb_delay <= '0';
          if ((ack_sreg(1) = '1') and (wb_trig_iface_ch13_count_rcv_lwb_in_progress = '1')) then
            rddata_reg(15 downto 0) <= wb_trig_iface_ch13_count_rcv_int;
            wb_trig_iface_ch13_count_rcv_lwb_in_progress <= '0';
          end if;
          wb_trig_iface_ch13_count_transm_lwb <= wb_trig_iface_ch13_count_transm_lwb_delay;
          wb_trig_iface_ch13_count_transm_lwb_delay <= '0';
          if ((ack_sreg(1) = '1') and (wb_trig_iface_ch13_count_transm_lwb_in_progress = '1')) then
            rddata_reg(31 downto 16) <= wb_trig_iface_ch13_count_transm_int;
            wb_trig_iface_ch13_count_transm_lwb_in_progress <= '0';
          end if;
          wb_trig_iface_ch14_ctl_rcv_count_rst_int <= wb_trig_iface_ch14_ctl_rcv_count_rst_int_delay;
          wb_trig_iface_ch14_ctl_rcv_count_rst_int_delay <= '0';
          wb_trig_iface_ch14_ctl_transm_count_rst_int <= wb_trig_iface_ch14_ctl_transm_count_rst_int_delay;
          wb_trig_iface_ch14_ctl_transm_count_rst_int_delay <= '0';
          wb_trig_iface_ch14_cfg_rcv_len_swb <= wb_trig_iface_ch14_cfg_rcv_len_swb_delay;
          wb_trig_iface_ch14_cfg_rcv_len_swb_delay <= '0';
          wb_trig_iface_ch14_cfg_transm_len_swb <= wb_trig_iface_ch14_cfg_transm_len_swb_delay;
          wb_trig_iface_ch14_cfg_transm_len_swb_delay <= '0';
          wb_trig_iface_ch14_count_rcv_lwb <= wb_trig_iface_ch14_count_rcv_lwb_delay;
          wb_trig_iface_ch14_count_rcv_lwb_delay <= '0';
          if ((ack_sreg(1) = '1') and (wb_trig_iface_ch14_count_rcv_lwb_in_progress = '1')) then
            rddata_reg(15 downto 0) <= wb_trig_iface_ch14_count_rcv_int;
            wb_trig_iface_ch14_count_rcv_lwb_in_progress <= '0';
          end if;
          wb_trig_iface_ch14_count_transm_lwb <= wb_trig_iface_ch14_count_transm_lwb_delay;
          wb_trig_iface_ch14_count_transm_lwb_delay <= '0';
          if ((ack_sreg(1) = '1') and (wb_trig_iface_ch14_count_transm_lwb_in_progress = '1')) then
            rddata_reg(31 downto 16) <= wb_trig_iface_ch14_count_transm_int;
            wb_trig_iface_ch14_count_transm_lwb_in_progress <= '0';
          end if;
          wb_trig_iface_ch15_ctl_rcv_count_rst_int <= wb_trig_iface_ch15_ctl_rcv_count_rst_int_delay;
          wb_trig_iface_ch15_ctl_rcv_count_rst_int_delay <= '0';
          wb_trig_iface_ch15_ctl_transm_count_rst_int <= wb_trig_iface_ch15_ctl_transm_count_rst_int_delay;
          wb_trig_iface_ch15_ctl_transm_count_rst_int_delay <= '0';
          wb_trig_iface_ch15_cfg_rcv_len_swb <= wb_trig_iface_ch15_cfg_rcv_len_swb_delay;
          wb_trig_iface_ch15_cfg_rcv_len_swb_delay <= '0';
          wb_trig_iface_ch15_cfg_transm_len_swb <= wb_trig_iface_ch15_cfg_transm_len_swb_delay;
          wb_trig_iface_ch15_cfg_transm_len_swb_delay <= '0';
          wb_trig_iface_ch15_count_rcv_lwb <= wb_trig_iface_ch15_count_rcv_lwb_delay;
          wb_trig_iface_ch15_count_rcv_lwb_delay <= '0';
          if ((ack_sreg(1) = '1') and (wb_trig_iface_ch15_count_rcv_lwb_in_progress = '1')) then
            rddata_reg(15 downto 0) <= wb_trig_iface_ch15_count_rcv_int;
            wb_trig_iface_ch15_count_rcv_lwb_in_progress <= '0';
          end if;
          wb_trig_iface_ch15_count_transm_lwb <= wb_trig_iface_ch15_count_transm_lwb_delay;
          wb_trig_iface_ch15_count_transm_lwb_delay <= '0';
          if ((ack_sreg(1) = '1') and (wb_trig_iface_ch15_count_transm_lwb_in_progress = '1')) then
            rddata_reg(31 downto 16) <= wb_trig_iface_ch15_count_transm_int;
            wb_trig_iface_ch15_count_transm_lwb_in_progress <= '0';
          end if;
          wb_trig_iface_ch16_ctl_rcv_count_rst_int <= wb_trig_iface_ch16_ctl_rcv_count_rst_int_delay;
          wb_trig_iface_ch16_ctl_rcv_count_rst_int_delay <= '0';
          wb_trig_iface_ch16_ctl_transm_count_rst_int <= wb_trig_iface_ch16_ctl_transm_count_rst_int_delay;
          wb_trig_iface_ch16_ctl_transm_count_rst_int_delay <= '0';
          wb_trig_iface_ch16_cfg_rcv_len_swb <= wb_trig_iface_ch16_cfg_rcv_len_swb_delay;
          wb_trig_iface_ch16_cfg_rcv_len_swb_delay <= '0';
          wb_trig_iface_ch16_cfg_transm_len_swb <= wb_trig_iface_ch16_cfg_transm_len_swb_delay;
          wb_trig_iface_ch16_cfg_transm_len_swb_delay <= '0';
          wb_trig_iface_ch16_count_rcv_lwb <= wb_trig_iface_ch16_count_rcv_lwb_delay;
          wb_trig_iface_ch16_count_rcv_lwb_delay <= '0';
          if ((ack_sreg(1) = '1') and (wb_trig_iface_ch16_count_rcv_lwb_in_progress = '1')) then
            rddata_reg(15 downto 0) <= wb_trig_iface_ch16_count_rcv_int;
            wb_trig_iface_ch16_count_rcv_lwb_in_progress <= '0';
          end if;
          wb_trig_iface_ch16_count_transm_lwb <= wb_trig_iface_ch16_count_transm_lwb_delay;
          wb_trig_iface_ch16_count_transm_lwb_delay <= '0';
          if ((ack_sreg(1) = '1') and (wb_trig_iface_ch16_count_transm_lwb_in_progress = '1')) then
            rddata_reg(31 downto 16) <= wb_trig_iface_ch16_count_transm_int;
            wb_trig_iface_ch16_count_transm_lwb_in_progress <= '0';
          end if;
          wb_trig_iface_ch17_ctl_rcv_count_rst_int <= wb_trig_iface_ch17_ctl_rcv_count_rst_int_delay;
          wb_trig_iface_ch17_ctl_rcv_count_rst_int_delay <= '0';
          wb_trig_iface_ch17_ctl_transm_count_rst_int <= wb_trig_iface_ch17_ctl_transm_count_rst_int_delay;
          wb_trig_iface_ch17_ctl_transm_count_rst_int_delay <= '0';
          wb_trig_iface_ch17_cfg_rcv_len_swb <= wb_trig_iface_ch17_cfg_rcv_len_swb_delay;
          wb_trig_iface_ch17_cfg_rcv_len_swb_delay <= '0';
          wb_trig_iface_ch17_cfg_transm_len_swb <= wb_trig_iface_ch17_cfg_transm_len_swb_delay;
          wb_trig_iface_ch17_cfg_transm_len_swb_delay <= '0';
          wb_trig_iface_ch17_count_rcv_lwb <= wb_trig_iface_ch17_count_rcv_lwb_delay;
          wb_trig_iface_ch17_count_rcv_lwb_delay <= '0';
          if ((ack_sreg(1) = '1') and (wb_trig_iface_ch17_count_rcv_lwb_in_progress = '1')) then
            rddata_reg(15 downto 0) <= wb_trig_iface_ch17_count_rcv_int;
            wb_trig_iface_ch17_count_rcv_lwb_in_progress <= '0';
          end if;
          wb_trig_iface_ch17_count_transm_lwb <= wb_trig_iface_ch17_count_transm_lwb_delay;
          wb_trig_iface_ch17_count_transm_lwb_delay <= '0';
          if ((ack_sreg(1) = '1') and (wb_trig_iface_ch17_count_transm_lwb_in_progress = '1')) then
            rddata_reg(31 downto 16) <= wb_trig_iface_ch17_count_transm_int;
            wb_trig_iface_ch17_count_transm_lwb_in_progress <= '0';
          end if;
          wb_trig_iface_ch18_ctl_rcv_count_rst_int <= wb_trig_iface_ch18_ctl_rcv_count_rst_int_delay;
          wb_trig_iface_ch18_ctl_rcv_count_rst_int_delay <= '0';
          wb_trig_iface_ch18_ctl_transm_count_rst_int <= wb_trig_iface_ch18_ctl_transm_count_rst_int_delay;
          wb_trig_iface_ch18_ctl_transm_count_rst_int_delay <= '0';
          wb_trig_iface_ch18_cfg_rcv_len_swb <= wb_trig_iface_ch18_cfg_rcv_len_swb_delay;
          wb_trig_iface_ch18_cfg_rcv_len_swb_delay <= '0';
          wb_trig_iface_ch18_cfg_transm_len_swb <= wb_trig_iface_ch18_cfg_transm_len_swb_delay;
          wb_trig_iface_ch18_cfg_transm_len_swb_delay <= '0';
          wb_trig_iface_ch18_count_rcv_lwb <= wb_trig_iface_ch18_count_rcv_lwb_delay;
          wb_trig_iface_ch18_count_rcv_lwb_delay <= '0';
          if ((ack_sreg(1) = '1') and (wb_trig_iface_ch18_count_rcv_lwb_in_progress = '1')) then
            rddata_reg(15 downto 0) <= wb_trig_iface_ch18_count_rcv_int;
            wb_trig_iface_ch18_count_rcv_lwb_in_progress <= '0';
          end if;
          wb_trig_iface_ch18_count_transm_lwb <= wb_trig_iface_ch18_count_transm_lwb_delay;
          wb_trig_iface_ch18_count_transm_lwb_delay <= '0';
          if ((ack_sreg(1) = '1') and (wb_trig_iface_ch18_count_transm_lwb_in_progress = '1')) then
            rddata_reg(31 downto 16) <= wb_trig_iface_ch18_count_transm_int;
            wb_trig_iface_ch18_count_transm_lwb_in_progress <= '0';
          end if;
          wb_trig_iface_ch19_ctl_rcv_count_rst_int <= wb_trig_iface_ch19_ctl_rcv_count_rst_int_delay;
          wb_trig_iface_ch19_ctl_rcv_count_rst_int_delay <= '0';
          wb_trig_iface_ch19_ctl_transm_count_rst_int <= wb_trig_iface_ch19_ctl_transm_count_rst_int_delay;
          wb_trig_iface_ch19_ctl_transm_count_rst_int_delay <= '0';
          wb_trig_iface_ch19_cfg_rcv_len_swb <= wb_trig_iface_ch19_cfg_rcv_len_swb_delay;
          wb_trig_iface_ch19_cfg_rcv_len_swb_delay <= '0';
          wb_trig_iface_ch19_cfg_transm_len_swb <= wb_trig_iface_ch19_cfg_transm_len_swb_delay;
          wb_trig_iface_ch19_cfg_transm_len_swb_delay <= '0';
          wb_trig_iface_ch19_count_rcv_lwb <= wb_trig_iface_ch19_count_rcv_lwb_delay;
          wb_trig_iface_ch19_count_rcv_lwb_delay <= '0';
          if ((ack_sreg(1) = '1') and (wb_trig_iface_ch19_count_rcv_lwb_in_progress = '1')) then
            rddata_reg(15 downto 0) <= wb_trig_iface_ch19_count_rcv_int;
            wb_trig_iface_ch19_count_rcv_lwb_in_progress <= '0';
          end if;
          wb_trig_iface_ch19_count_transm_lwb <= wb_trig_iface_ch19_count_transm_lwb_delay;
          wb_trig_iface_ch19_count_transm_lwb_delay <= '0';
          if ((ack_sreg(1) = '1') and (wb_trig_iface_ch19_count_transm_lwb_in_progress = '1')) then
            rddata_reg(31 downto 16) <= wb_trig_iface_ch19_count_transm_int;
            wb_trig_iface_ch19_count_transm_lwb_in_progress <= '0';
          end if;
          wb_trig_iface_ch20_ctl_rcv_count_rst_int <= wb_trig_iface_ch20_ctl_rcv_count_rst_int_delay;
          wb_trig_iface_ch20_ctl_rcv_count_rst_int_delay <= '0';
          wb_trig_iface_ch20_ctl_transm_count_rst_int <= wb_trig_iface_ch20_ctl_transm_count_rst_int_delay;
          wb_trig_iface_ch20_ctl_transm_count_rst_int_delay <= '0';
          wb_trig_iface_ch20_cfg_rcv_len_swb <= wb_trig_iface_ch20_cfg_rcv_len_swb_delay;
          wb_trig_iface_ch20_cfg_rcv_len_swb_delay <= '0';
          wb_trig_iface_ch20_cfg_transm_len_swb <= wb_trig_iface_ch20_cfg_transm_len_swb_delay;
          wb_trig_iface_ch20_cfg_transm_len_swb_delay <= '0';
          wb_trig_iface_ch20_count_rcv_lwb <= wb_trig_iface_ch20_count_rcv_lwb_delay;
          wb_trig_iface_ch20_count_rcv_lwb_delay <= '0';
          if ((ack_sreg(1) = '1') and (wb_trig_iface_ch20_count_rcv_lwb_in_progress = '1')) then
            rddata_reg(15 downto 0) <= wb_trig_iface_ch20_count_rcv_int;
            wb_trig_iface_ch20_count_rcv_lwb_in_progress <= '0';
          end if;
          wb_trig_iface_ch20_count_transm_lwb <= wb_trig_iface_ch20_count_transm_lwb_delay;
          wb_trig_iface_ch20_count_transm_lwb_delay <= '0';
          if ((ack_sreg(1) = '1') and (wb_trig_iface_ch20_count_transm_lwb_in_progress = '1')) then
            rddata_reg(31 downto 16) <= wb_trig_iface_ch20_count_transm_int;
            wb_trig_iface_ch20_count_transm_lwb_in_progress <= '0';
          end if;
          wb_trig_iface_ch21_ctl_rcv_count_rst_int <= wb_trig_iface_ch21_ctl_rcv_count_rst_int_delay;
          wb_trig_iface_ch21_ctl_rcv_count_rst_int_delay <= '0';
          wb_trig_iface_ch21_ctl_transm_count_rst_int <= wb_trig_iface_ch21_ctl_transm_count_rst_int_delay;
          wb_trig_iface_ch21_ctl_transm_count_rst_int_delay <= '0';
          wb_trig_iface_ch21_cfg_rcv_len_swb <= wb_trig_iface_ch21_cfg_rcv_len_swb_delay;
          wb_trig_iface_ch21_cfg_rcv_len_swb_delay <= '0';
          wb_trig_iface_ch21_cfg_transm_len_swb <= wb_trig_iface_ch21_cfg_transm_len_swb_delay;
          wb_trig_iface_ch21_cfg_transm_len_swb_delay <= '0';
          wb_trig_iface_ch21_count_rcv_lwb <= wb_trig_iface_ch21_count_rcv_lwb_delay;
          wb_trig_iface_ch21_count_rcv_lwb_delay <= '0';
          if ((ack_sreg(1) = '1') and (wb_trig_iface_ch21_count_rcv_lwb_in_progress = '1')) then
            rddata_reg(15 downto 0) <= wb_trig_iface_ch21_count_rcv_int;
            wb_trig_iface_ch21_count_rcv_lwb_in_progress <= '0';
          end if;
          wb_trig_iface_ch21_count_transm_lwb <= wb_trig_iface_ch21_count_transm_lwb_delay;
          wb_trig_iface_ch21_count_transm_lwb_delay <= '0';
          if ((ack_sreg(1) = '1') and (wb_trig_iface_ch21_count_transm_lwb_in_progress = '1')) then
            rddata_reg(31 downto 16) <= wb_trig_iface_ch21_count_transm_int;
            wb_trig_iface_ch21_count_transm_lwb_in_progress <= '0';
          end if;
          wb_trig_iface_ch22_ctl_rcv_count_rst_int <= wb_trig_iface_ch22_ctl_rcv_count_rst_int_delay;
          wb_trig_iface_ch22_ctl_rcv_count_rst_int_delay <= '0';
          wb_trig_iface_ch22_ctl_transm_count_rst_int <= wb_trig_iface_ch22_ctl_transm_count_rst_int_delay;
          wb_trig_iface_ch22_ctl_transm_count_rst_int_delay <= '0';
          wb_trig_iface_ch22_cfg_rcv_len_swb <= wb_trig_iface_ch22_cfg_rcv_len_swb_delay;
          wb_trig_iface_ch22_cfg_rcv_len_swb_delay <= '0';
          wb_trig_iface_ch22_cfg_transm_len_swb <= wb_trig_iface_ch22_cfg_transm_len_swb_delay;
          wb_trig_iface_ch22_cfg_transm_len_swb_delay <= '0';
          wb_trig_iface_ch22_count_rcv_lwb <= wb_trig_iface_ch22_count_rcv_lwb_delay;
          wb_trig_iface_ch22_count_rcv_lwb_delay <= '0';
          if ((ack_sreg(1) = '1') and (wb_trig_iface_ch22_count_rcv_lwb_in_progress = '1')) then
            rddata_reg(15 downto 0) <= wb_trig_iface_ch22_count_rcv_int;
            wb_trig_iface_ch22_count_rcv_lwb_in_progress <= '0';
          end if;
          wb_trig_iface_ch22_count_transm_lwb <= wb_trig_iface_ch22_count_transm_lwb_delay;
          wb_trig_iface_ch22_count_transm_lwb_delay <= '0';
          if ((ack_sreg(1) = '1') and (wb_trig_iface_ch22_count_transm_lwb_in_progress = '1')) then
            rddata_reg(31 downto 16) <= wb_trig_iface_ch22_count_transm_int;
            wb_trig_iface_ch22_count_transm_lwb_in_progress <= '0';
          end if;
          wb_trig_iface_ch23_ctl_rcv_count_rst_int <= wb_trig_iface_ch23_ctl_rcv_count_rst_int_delay;
          wb_trig_iface_ch23_ctl_rcv_count_rst_int_delay <= '0';
          wb_trig_iface_ch23_ctl_transm_count_rst_int <= wb_trig_iface_ch23_ctl_transm_count_rst_int_delay;
          wb_trig_iface_ch23_ctl_transm_count_rst_int_delay <= '0';
          wb_trig_iface_ch23_cfg_rcv_len_swb <= wb_trig_iface_ch23_cfg_rcv_len_swb_delay;
          wb_trig_iface_ch23_cfg_rcv_len_swb_delay <= '0';
          wb_trig_iface_ch23_cfg_transm_len_swb <= wb_trig_iface_ch23_cfg_transm_len_swb_delay;
          wb_trig_iface_ch23_cfg_transm_len_swb_delay <= '0';
          wb_trig_iface_ch23_count_rcv_lwb <= wb_trig_iface_ch23_count_rcv_lwb_delay;
          wb_trig_iface_ch23_count_rcv_lwb_delay <= '0';
          if ((ack_sreg(1) = '1') and (wb_trig_iface_ch23_count_rcv_lwb_in_progress = '1')) then
            rddata_reg(15 downto 0) <= wb_trig_iface_ch23_count_rcv_int;
            wb_trig_iface_ch23_count_rcv_lwb_in_progress <= '0';
          end if;
          wb_trig_iface_ch23_count_transm_lwb <= wb_trig_iface_ch23_count_transm_lwb_delay;
          wb_trig_iface_ch23_count_transm_lwb_delay <= '0';
          if ((ack_sreg(1) = '1') and (wb_trig_iface_ch23_count_transm_lwb_in_progress = '1')) then
            rddata_reg(31 downto 16) <= wb_trig_iface_ch23_count_transm_int;
            wb_trig_iface_ch23_count_transm_lwb_in_progress <= '0';
          end if;
        end if;
      else
        if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
          case rwaddr_reg(6 downto 0) is
          when "0000000" => 
            if (wb_we_i = '1') then
              wb_trig_iface_ch0_ctl_dir_int <= wrdata_reg(0);
              wb_trig_iface_ch0_ctl_dir_pol_int <= wrdata_reg(1);
              wb_trig_iface_ch0_ctl_rcv_count_rst_int <= wrdata_reg(2);
              wb_trig_iface_ch0_ctl_rcv_count_rst_int_delay <= wrdata_reg(2);
              wb_trig_iface_ch0_ctl_transm_count_rst_int <= wrdata_reg(3);
              wb_trig_iface_ch0_ctl_transm_count_rst_int_delay <= wrdata_reg(3);
            end if;
            rddata_reg(0) <= wb_trig_iface_ch0_ctl_dir_int;
            rddata_reg(1) <= wb_trig_iface_ch0_ctl_dir_pol_int;
            rddata_reg(2) <= '0';
            rddata_reg(3) <= '0';
            rddata_reg(4) <= 'X';
            rddata_reg(5) <= 'X';
            rddata_reg(6) <= 'X';
            rddata_reg(7) <= 'X';
            rddata_reg(8) <= 'X';
            rddata_reg(9) <= 'X';
            rddata_reg(10) <= 'X';
            rddata_reg(11) <= 'X';
            rddata_reg(12) <= 'X';
            rddata_reg(13) <= 'X';
            rddata_reg(14) <= 'X';
            rddata_reg(15) <= 'X';
            rddata_reg(16) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            rddata_reg(24) <= 'X';
            rddata_reg(25) <= 'X';
            rddata_reg(26) <= 'X';
            rddata_reg(27) <= 'X';
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(4) <= '1';
            ack_in_progress <= '1';
          when "0000001" => 
            if (wb_we_i = '1') then
              wb_trig_iface_ch0_cfg_rcv_len_int <= wrdata_reg(7 downto 0);
              wb_trig_iface_ch0_cfg_rcv_len_swb <= '1';
              wb_trig_iface_ch0_cfg_rcv_len_swb_delay <= '1';
              wb_trig_iface_ch0_cfg_transm_len_int <= wrdata_reg(15 downto 8);
              wb_trig_iface_ch0_cfg_transm_len_swb <= '1';
              wb_trig_iface_ch0_cfg_transm_len_swb_delay <= '1';
            end if;
            rddata_reg(7 downto 0) <= wb_trig_iface_ch0_cfg_rcv_len_int;
            rddata_reg(15 downto 8) <= wb_trig_iface_ch0_cfg_transm_len_int;
            rddata_reg(16) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            rddata_reg(24) <= 'X';
            rddata_reg(25) <= 'X';
            rddata_reg(26) <= 'X';
            rddata_reg(27) <= 'X';
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(3) <= '1';
            ack_in_progress <= '1';
          when "0000010" => 
            if (wb_we_i = '1') then
            end if;
            if (wb_we_i = '0') then
              wb_trig_iface_ch0_count_rcv_lwb <= '1';
              wb_trig_iface_ch0_count_rcv_lwb_delay <= '1';
              wb_trig_iface_ch0_count_rcv_lwb_in_progress <= '1';
            end if;
            if (wb_we_i = '0') then
              wb_trig_iface_ch0_count_transm_lwb <= '1';
              wb_trig_iface_ch0_count_transm_lwb_delay <= '1';
              wb_trig_iface_ch0_count_transm_lwb_in_progress <= '1';
            end if;
            ack_sreg(5) <= '1';
            ack_in_progress <= '1';
          when "0000011" => 
            if (wb_we_i = '1') then
              wb_trig_iface_ch1_ctl_dir_int <= wrdata_reg(0);
              wb_trig_iface_ch1_ctl_dir_pol_int <= wrdata_reg(1);
              wb_trig_iface_ch1_ctl_rcv_count_rst_int <= wrdata_reg(2);
              wb_trig_iface_ch1_ctl_rcv_count_rst_int_delay <= wrdata_reg(2);
              wb_trig_iface_ch1_ctl_transm_count_rst_int <= wrdata_reg(3);
              wb_trig_iface_ch1_ctl_transm_count_rst_int_delay <= wrdata_reg(3);
            end if;
            rddata_reg(0) <= wb_trig_iface_ch1_ctl_dir_int;
            rddata_reg(1) <= wb_trig_iface_ch1_ctl_dir_pol_int;
            rddata_reg(2) <= '0';
            rddata_reg(3) <= '0';
            rddata_reg(4) <= 'X';
            rddata_reg(5) <= 'X';
            rddata_reg(6) <= 'X';
            rddata_reg(7) <= 'X';
            rddata_reg(8) <= 'X';
            rddata_reg(9) <= 'X';
            rddata_reg(10) <= 'X';
            rddata_reg(11) <= 'X';
            rddata_reg(12) <= 'X';
            rddata_reg(13) <= 'X';
            rddata_reg(14) <= 'X';
            rddata_reg(15) <= 'X';
            rddata_reg(16) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            rddata_reg(24) <= 'X';
            rddata_reg(25) <= 'X';
            rddata_reg(26) <= 'X';
            rddata_reg(27) <= 'X';
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(4) <= '1';
            ack_in_progress <= '1';
          when "0000100" => 
            if (wb_we_i = '1') then
              wb_trig_iface_ch1_cfg_rcv_len_int <= wrdata_reg(7 downto 0);
              wb_trig_iface_ch1_cfg_rcv_len_swb <= '1';
              wb_trig_iface_ch1_cfg_rcv_len_swb_delay <= '1';
              wb_trig_iface_ch1_cfg_transm_len_int <= wrdata_reg(15 downto 8);
              wb_trig_iface_ch1_cfg_transm_len_swb <= '1';
              wb_trig_iface_ch1_cfg_transm_len_swb_delay <= '1';
            end if;
            rddata_reg(7 downto 0) <= wb_trig_iface_ch1_cfg_rcv_len_int;
            rddata_reg(15 downto 8) <= wb_trig_iface_ch1_cfg_transm_len_int;
            rddata_reg(16) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            rddata_reg(24) <= 'X';
            rddata_reg(25) <= 'X';
            rddata_reg(26) <= 'X';
            rddata_reg(27) <= 'X';
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(3) <= '1';
            ack_in_progress <= '1';
          when "0000101" => 
            if (wb_we_i = '1') then
            end if;
            if (wb_we_i = '0') then
              wb_trig_iface_ch1_count_rcv_lwb <= '1';
              wb_trig_iface_ch1_count_rcv_lwb_delay <= '1';
              wb_trig_iface_ch1_count_rcv_lwb_in_progress <= '1';
            end if;
            if (wb_we_i = '0') then
              wb_trig_iface_ch1_count_transm_lwb <= '1';
              wb_trig_iface_ch1_count_transm_lwb_delay <= '1';
              wb_trig_iface_ch1_count_transm_lwb_in_progress <= '1';
            end if;
            ack_sreg(5) <= '1';
            ack_in_progress <= '1';
          when "0000110" => 
            if (wb_we_i = '1') then
              wb_trig_iface_ch2_ctl_dir_int <= wrdata_reg(0);
              wb_trig_iface_ch2_ctl_dir_pol_int <= wrdata_reg(1);
              wb_trig_iface_ch2_ctl_rcv_count_rst_int <= wrdata_reg(2);
              wb_trig_iface_ch2_ctl_rcv_count_rst_int_delay <= wrdata_reg(2);
              wb_trig_iface_ch2_ctl_transm_count_rst_int <= wrdata_reg(3);
              wb_trig_iface_ch2_ctl_transm_count_rst_int_delay <= wrdata_reg(3);
            end if;
            rddata_reg(0) <= wb_trig_iface_ch2_ctl_dir_int;
            rddata_reg(1) <= wb_trig_iface_ch2_ctl_dir_pol_int;
            rddata_reg(2) <= '0';
            rddata_reg(3) <= '0';
            rddata_reg(4) <= 'X';
            rddata_reg(5) <= 'X';
            rddata_reg(6) <= 'X';
            rddata_reg(7) <= 'X';
            rddata_reg(8) <= 'X';
            rddata_reg(9) <= 'X';
            rddata_reg(10) <= 'X';
            rddata_reg(11) <= 'X';
            rddata_reg(12) <= 'X';
            rddata_reg(13) <= 'X';
            rddata_reg(14) <= 'X';
            rddata_reg(15) <= 'X';
            rddata_reg(16) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            rddata_reg(24) <= 'X';
            rddata_reg(25) <= 'X';
            rddata_reg(26) <= 'X';
            rddata_reg(27) <= 'X';
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(4) <= '1';
            ack_in_progress <= '1';
          when "0000111" => 
            if (wb_we_i = '1') then
              wb_trig_iface_ch2_cfg_rcv_len_int <= wrdata_reg(7 downto 0);
              wb_trig_iface_ch2_cfg_rcv_len_swb <= '1';
              wb_trig_iface_ch2_cfg_rcv_len_swb_delay <= '1';
              wb_trig_iface_ch2_cfg_transm_len_int <= wrdata_reg(15 downto 8);
              wb_trig_iface_ch2_cfg_transm_len_swb <= '1';
              wb_trig_iface_ch2_cfg_transm_len_swb_delay <= '1';
            end if;
            rddata_reg(7 downto 0) <= wb_trig_iface_ch2_cfg_rcv_len_int;
            rddata_reg(15 downto 8) <= wb_trig_iface_ch2_cfg_transm_len_int;
            rddata_reg(16) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            rddata_reg(24) <= 'X';
            rddata_reg(25) <= 'X';
            rddata_reg(26) <= 'X';
            rddata_reg(27) <= 'X';
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(3) <= '1';
            ack_in_progress <= '1';
          when "0001000" => 
            if (wb_we_i = '1') then
            end if;
            if (wb_we_i = '0') then
              wb_trig_iface_ch2_count_rcv_lwb <= '1';
              wb_trig_iface_ch2_count_rcv_lwb_delay <= '1';
              wb_trig_iface_ch2_count_rcv_lwb_in_progress <= '1';
            end if;
            if (wb_we_i = '0') then
              wb_trig_iface_ch2_count_transm_lwb <= '1';
              wb_trig_iface_ch2_count_transm_lwb_delay <= '1';
              wb_trig_iface_ch2_count_transm_lwb_in_progress <= '1';
            end if;
            ack_sreg(5) <= '1';
            ack_in_progress <= '1';
          when "0001001" => 
            if (wb_we_i = '1') then
              wb_trig_iface_ch3_ctl_dir_int <= wrdata_reg(0);
              wb_trig_iface_ch3_ctl_dir_pol_int <= wrdata_reg(1);
              wb_trig_iface_ch3_ctl_rcv_count_rst_int <= wrdata_reg(2);
              wb_trig_iface_ch3_ctl_rcv_count_rst_int_delay <= wrdata_reg(2);
              wb_trig_iface_ch3_ctl_transm_count_rst_int <= wrdata_reg(3);
              wb_trig_iface_ch3_ctl_transm_count_rst_int_delay <= wrdata_reg(3);
            end if;
            rddata_reg(0) <= wb_trig_iface_ch3_ctl_dir_int;
            rddata_reg(1) <= wb_trig_iface_ch3_ctl_dir_pol_int;
            rddata_reg(2) <= '0';
            rddata_reg(3) <= '0';
            rddata_reg(4) <= 'X';
            rddata_reg(5) <= 'X';
            rddata_reg(6) <= 'X';
            rddata_reg(7) <= 'X';
            rddata_reg(8) <= 'X';
            rddata_reg(9) <= 'X';
            rddata_reg(10) <= 'X';
            rddata_reg(11) <= 'X';
            rddata_reg(12) <= 'X';
            rddata_reg(13) <= 'X';
            rddata_reg(14) <= 'X';
            rddata_reg(15) <= 'X';
            rddata_reg(16) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            rddata_reg(24) <= 'X';
            rddata_reg(25) <= 'X';
            rddata_reg(26) <= 'X';
            rddata_reg(27) <= 'X';
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(4) <= '1';
            ack_in_progress <= '1';
          when "0001010" => 
            if (wb_we_i = '1') then
              wb_trig_iface_ch3_cfg_rcv_len_int <= wrdata_reg(7 downto 0);
              wb_trig_iface_ch3_cfg_rcv_len_swb <= '1';
              wb_trig_iface_ch3_cfg_rcv_len_swb_delay <= '1';
              wb_trig_iface_ch3_cfg_transm_len_int <= wrdata_reg(15 downto 8);
              wb_trig_iface_ch3_cfg_transm_len_swb <= '1';
              wb_trig_iface_ch3_cfg_transm_len_swb_delay <= '1';
            end if;
            rddata_reg(7 downto 0) <= wb_trig_iface_ch3_cfg_rcv_len_int;
            rddata_reg(15 downto 8) <= wb_trig_iface_ch3_cfg_transm_len_int;
            rddata_reg(16) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            rddata_reg(24) <= 'X';
            rddata_reg(25) <= 'X';
            rddata_reg(26) <= 'X';
            rddata_reg(27) <= 'X';
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(3) <= '1';
            ack_in_progress <= '1';
          when "0001011" => 
            if (wb_we_i = '1') then
            end if;
            if (wb_we_i = '0') then
              wb_trig_iface_ch3_count_rcv_lwb <= '1';
              wb_trig_iface_ch3_count_rcv_lwb_delay <= '1';
              wb_trig_iface_ch3_count_rcv_lwb_in_progress <= '1';
            end if;
            if (wb_we_i = '0') then
              wb_trig_iface_ch3_count_transm_lwb <= '1';
              wb_trig_iface_ch3_count_transm_lwb_delay <= '1';
              wb_trig_iface_ch3_count_transm_lwb_in_progress <= '1';
            end if;
            ack_sreg(5) <= '1';
            ack_in_progress <= '1';
          when "0001100" => 
            if (wb_we_i = '1') then
              wb_trig_iface_ch4_ctl_dir_int <= wrdata_reg(0);
              wb_trig_iface_ch4_ctl_dir_pol_int <= wrdata_reg(1);
              wb_trig_iface_ch4_ctl_rcv_count_rst_int <= wrdata_reg(2);
              wb_trig_iface_ch4_ctl_rcv_count_rst_int_delay <= wrdata_reg(2);
              wb_trig_iface_ch4_ctl_transm_count_rst_int <= wrdata_reg(3);
              wb_trig_iface_ch4_ctl_transm_count_rst_int_delay <= wrdata_reg(3);
            end if;
            rddata_reg(0) <= wb_trig_iface_ch4_ctl_dir_int;
            rddata_reg(1) <= wb_trig_iface_ch4_ctl_dir_pol_int;
            rddata_reg(2) <= '0';
            rddata_reg(3) <= '0';
            rddata_reg(4) <= 'X';
            rddata_reg(5) <= 'X';
            rddata_reg(6) <= 'X';
            rddata_reg(7) <= 'X';
            rddata_reg(8) <= 'X';
            rddata_reg(9) <= 'X';
            rddata_reg(10) <= 'X';
            rddata_reg(11) <= 'X';
            rddata_reg(12) <= 'X';
            rddata_reg(13) <= 'X';
            rddata_reg(14) <= 'X';
            rddata_reg(15) <= 'X';
            rddata_reg(16) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            rddata_reg(24) <= 'X';
            rddata_reg(25) <= 'X';
            rddata_reg(26) <= 'X';
            rddata_reg(27) <= 'X';
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(4) <= '1';
            ack_in_progress <= '1';
          when "0001101" => 
            if (wb_we_i = '1') then
              wb_trig_iface_ch4_cfg_rcv_len_int <= wrdata_reg(7 downto 0);
              wb_trig_iface_ch4_cfg_rcv_len_swb <= '1';
              wb_trig_iface_ch4_cfg_rcv_len_swb_delay <= '1';
              wb_trig_iface_ch4_cfg_transm_len_int <= wrdata_reg(15 downto 8);
              wb_trig_iface_ch4_cfg_transm_len_swb <= '1';
              wb_trig_iface_ch4_cfg_transm_len_swb_delay <= '1';
            end if;
            rddata_reg(7 downto 0) <= wb_trig_iface_ch4_cfg_rcv_len_int;
            rddata_reg(15 downto 8) <= wb_trig_iface_ch4_cfg_transm_len_int;
            rddata_reg(16) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            rddata_reg(24) <= 'X';
            rddata_reg(25) <= 'X';
            rddata_reg(26) <= 'X';
            rddata_reg(27) <= 'X';
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(3) <= '1';
            ack_in_progress <= '1';
          when "0001110" => 
            if (wb_we_i = '1') then
            end if;
            if (wb_we_i = '0') then
              wb_trig_iface_ch4_count_rcv_lwb <= '1';
              wb_trig_iface_ch4_count_rcv_lwb_delay <= '1';
              wb_trig_iface_ch4_count_rcv_lwb_in_progress <= '1';
            end if;
            if (wb_we_i = '0') then
              wb_trig_iface_ch4_count_transm_lwb <= '1';
              wb_trig_iface_ch4_count_transm_lwb_delay <= '1';
              wb_trig_iface_ch4_count_transm_lwb_in_progress <= '1';
            end if;
            ack_sreg(5) <= '1';
            ack_in_progress <= '1';
          when "0001111" => 
            if (wb_we_i = '1') then
              wb_trig_iface_ch5_ctl_dir_int <= wrdata_reg(0);
              wb_trig_iface_ch5_ctl_dir_pol_int <= wrdata_reg(1);
              wb_trig_iface_ch5_ctl_rcv_count_rst_int <= wrdata_reg(2);
              wb_trig_iface_ch5_ctl_rcv_count_rst_int_delay <= wrdata_reg(2);
              wb_trig_iface_ch5_ctl_transm_count_rst_int <= wrdata_reg(3);
              wb_trig_iface_ch5_ctl_transm_count_rst_int_delay <= wrdata_reg(3);
            end if;
            rddata_reg(0) <= wb_trig_iface_ch5_ctl_dir_int;
            rddata_reg(1) <= wb_trig_iface_ch5_ctl_dir_pol_int;
            rddata_reg(2) <= '0';
            rddata_reg(3) <= '0';
            rddata_reg(4) <= 'X';
            rddata_reg(5) <= 'X';
            rddata_reg(6) <= 'X';
            rddata_reg(7) <= 'X';
            rddata_reg(8) <= 'X';
            rddata_reg(9) <= 'X';
            rddata_reg(10) <= 'X';
            rddata_reg(11) <= 'X';
            rddata_reg(12) <= 'X';
            rddata_reg(13) <= 'X';
            rddata_reg(14) <= 'X';
            rddata_reg(15) <= 'X';
            rddata_reg(16) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            rddata_reg(24) <= 'X';
            rddata_reg(25) <= 'X';
            rddata_reg(26) <= 'X';
            rddata_reg(27) <= 'X';
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(4) <= '1';
            ack_in_progress <= '1';
          when "0010000" => 
            if (wb_we_i = '1') then
              wb_trig_iface_ch5_cfg_rcv_len_int <= wrdata_reg(7 downto 0);
              wb_trig_iface_ch5_cfg_rcv_len_swb <= '1';
              wb_trig_iface_ch5_cfg_rcv_len_swb_delay <= '1';
              wb_trig_iface_ch5_cfg_transm_len_int <= wrdata_reg(15 downto 8);
              wb_trig_iface_ch5_cfg_transm_len_swb <= '1';
              wb_trig_iface_ch5_cfg_transm_len_swb_delay <= '1';
            end if;
            rddata_reg(7 downto 0) <= wb_trig_iface_ch5_cfg_rcv_len_int;
            rddata_reg(15 downto 8) <= wb_trig_iface_ch5_cfg_transm_len_int;
            rddata_reg(16) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            rddata_reg(24) <= 'X';
            rddata_reg(25) <= 'X';
            rddata_reg(26) <= 'X';
            rddata_reg(27) <= 'X';
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(3) <= '1';
            ack_in_progress <= '1';
          when "0010001" => 
            if (wb_we_i = '1') then
            end if;
            if (wb_we_i = '0') then
              wb_trig_iface_ch5_count_rcv_lwb <= '1';
              wb_trig_iface_ch5_count_rcv_lwb_delay <= '1';
              wb_trig_iface_ch5_count_rcv_lwb_in_progress <= '1';
            end if;
            if (wb_we_i = '0') then
              wb_trig_iface_ch5_count_transm_lwb <= '1';
              wb_trig_iface_ch5_count_transm_lwb_delay <= '1';
              wb_trig_iface_ch5_count_transm_lwb_in_progress <= '1';
            end if;
            ack_sreg(5) <= '1';
            ack_in_progress <= '1';
          when "0010010" => 
            if (wb_we_i = '1') then
              wb_trig_iface_ch6_ctl_dir_int <= wrdata_reg(0);
              wb_trig_iface_ch6_ctl_dir_pol_int <= wrdata_reg(1);
              wb_trig_iface_ch6_ctl_rcv_count_rst_int <= wrdata_reg(2);
              wb_trig_iface_ch6_ctl_rcv_count_rst_int_delay <= wrdata_reg(2);
              wb_trig_iface_ch6_ctl_transm_count_rst_int <= wrdata_reg(3);
              wb_trig_iface_ch6_ctl_transm_count_rst_int_delay <= wrdata_reg(3);
            end if;
            rddata_reg(0) <= wb_trig_iface_ch6_ctl_dir_int;
            rddata_reg(1) <= wb_trig_iface_ch6_ctl_dir_pol_int;
            rddata_reg(2) <= '0';
            rddata_reg(3) <= '0';
            rddata_reg(4) <= 'X';
            rddata_reg(5) <= 'X';
            rddata_reg(6) <= 'X';
            rddata_reg(7) <= 'X';
            rddata_reg(8) <= 'X';
            rddata_reg(9) <= 'X';
            rddata_reg(10) <= 'X';
            rddata_reg(11) <= 'X';
            rddata_reg(12) <= 'X';
            rddata_reg(13) <= 'X';
            rddata_reg(14) <= 'X';
            rddata_reg(15) <= 'X';
            rddata_reg(16) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            rddata_reg(24) <= 'X';
            rddata_reg(25) <= 'X';
            rddata_reg(26) <= 'X';
            rddata_reg(27) <= 'X';
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(4) <= '1';
            ack_in_progress <= '1';
          when "0010011" => 
            if (wb_we_i = '1') then
              wb_trig_iface_ch6_cfg_rcv_len_int <= wrdata_reg(7 downto 0);
              wb_trig_iface_ch6_cfg_rcv_len_swb <= '1';
              wb_trig_iface_ch6_cfg_rcv_len_swb_delay <= '1';
              wb_trig_iface_ch6_cfg_transm_len_int <= wrdata_reg(15 downto 8);
              wb_trig_iface_ch6_cfg_transm_len_swb <= '1';
              wb_trig_iface_ch6_cfg_transm_len_swb_delay <= '1';
            end if;
            rddata_reg(7 downto 0) <= wb_trig_iface_ch6_cfg_rcv_len_int;
            rddata_reg(15 downto 8) <= wb_trig_iface_ch6_cfg_transm_len_int;
            rddata_reg(16) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            rddata_reg(24) <= 'X';
            rddata_reg(25) <= 'X';
            rddata_reg(26) <= 'X';
            rddata_reg(27) <= 'X';
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(3) <= '1';
            ack_in_progress <= '1';
          when "0010100" => 
            if (wb_we_i = '1') then
            end if;
            if (wb_we_i = '0') then
              wb_trig_iface_ch6_count_rcv_lwb <= '1';
              wb_trig_iface_ch6_count_rcv_lwb_delay <= '1';
              wb_trig_iface_ch6_count_rcv_lwb_in_progress <= '1';
            end if;
            if (wb_we_i = '0') then
              wb_trig_iface_ch6_count_transm_lwb <= '1';
              wb_trig_iface_ch6_count_transm_lwb_delay <= '1';
              wb_trig_iface_ch6_count_transm_lwb_in_progress <= '1';
            end if;
            ack_sreg(5) <= '1';
            ack_in_progress <= '1';
          when "0010101" => 
            if (wb_we_i = '1') then
              wb_trig_iface_ch7_ctl_dir_int <= wrdata_reg(0);
              wb_trig_iface_ch7_ctl_dir_pol_int <= wrdata_reg(1);
              wb_trig_iface_ch7_ctl_rcv_count_rst_int <= wrdata_reg(2);
              wb_trig_iface_ch7_ctl_rcv_count_rst_int_delay <= wrdata_reg(2);
              wb_trig_iface_ch7_ctl_transm_count_rst_int <= wrdata_reg(3);
              wb_trig_iface_ch7_ctl_transm_count_rst_int_delay <= wrdata_reg(3);
            end if;
            rddata_reg(0) <= wb_trig_iface_ch7_ctl_dir_int;
            rddata_reg(1) <= wb_trig_iface_ch7_ctl_dir_pol_int;
            rddata_reg(2) <= '0';
            rddata_reg(3) <= '0';
            rddata_reg(4) <= 'X';
            rddata_reg(5) <= 'X';
            rddata_reg(6) <= 'X';
            rddata_reg(7) <= 'X';
            rddata_reg(8) <= 'X';
            rddata_reg(9) <= 'X';
            rddata_reg(10) <= 'X';
            rddata_reg(11) <= 'X';
            rddata_reg(12) <= 'X';
            rddata_reg(13) <= 'X';
            rddata_reg(14) <= 'X';
            rddata_reg(15) <= 'X';
            rddata_reg(16) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            rddata_reg(24) <= 'X';
            rddata_reg(25) <= 'X';
            rddata_reg(26) <= 'X';
            rddata_reg(27) <= 'X';
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(4) <= '1';
            ack_in_progress <= '1';
          when "0010110" => 
            if (wb_we_i = '1') then
              wb_trig_iface_ch7_cfg_rcv_len_int <= wrdata_reg(7 downto 0);
              wb_trig_iface_ch7_cfg_rcv_len_swb <= '1';
              wb_trig_iface_ch7_cfg_rcv_len_swb_delay <= '1';
              wb_trig_iface_ch7_cfg_transm_len_int <= wrdata_reg(15 downto 8);
              wb_trig_iface_ch7_cfg_transm_len_swb <= '1';
              wb_trig_iface_ch7_cfg_transm_len_swb_delay <= '1';
            end if;
            rddata_reg(7 downto 0) <= wb_trig_iface_ch7_cfg_rcv_len_int;
            rddata_reg(15 downto 8) <= wb_trig_iface_ch7_cfg_transm_len_int;
            rddata_reg(16) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            rddata_reg(24) <= 'X';
            rddata_reg(25) <= 'X';
            rddata_reg(26) <= 'X';
            rddata_reg(27) <= 'X';
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(3) <= '1';
            ack_in_progress <= '1';
          when "0010111" => 
            if (wb_we_i = '1') then
            end if;
            if (wb_we_i = '0') then
              wb_trig_iface_ch7_count_rcv_lwb <= '1';
              wb_trig_iface_ch7_count_rcv_lwb_delay <= '1';
              wb_trig_iface_ch7_count_rcv_lwb_in_progress <= '1';
            end if;
            if (wb_we_i = '0') then
              wb_trig_iface_ch7_count_transm_lwb <= '1';
              wb_trig_iface_ch7_count_transm_lwb_delay <= '1';
              wb_trig_iface_ch7_count_transm_lwb_in_progress <= '1';
            end if;
            ack_sreg(5) <= '1';
            ack_in_progress <= '1';
          when "0011000" => 
            if (wb_we_i = '1') then
              wb_trig_iface_ch8_ctl_dir_int <= wrdata_reg(0);
              wb_trig_iface_ch8_ctl_dir_pol_int <= wrdata_reg(1);
              wb_trig_iface_ch8_ctl_rcv_count_rst_int <= wrdata_reg(2);
              wb_trig_iface_ch8_ctl_rcv_count_rst_int_delay <= wrdata_reg(2);
              wb_trig_iface_ch8_ctl_transm_count_rst_int <= wrdata_reg(3);
              wb_trig_iface_ch8_ctl_transm_count_rst_int_delay <= wrdata_reg(3);
            end if;
            rddata_reg(0) <= wb_trig_iface_ch8_ctl_dir_int;
            rddata_reg(1) <= wb_trig_iface_ch8_ctl_dir_pol_int;
            rddata_reg(2) <= '0';
            rddata_reg(3) <= '0';
            rddata_reg(4) <= 'X';
            rddata_reg(5) <= 'X';
            rddata_reg(6) <= 'X';
            rddata_reg(7) <= 'X';
            rddata_reg(8) <= 'X';
            rddata_reg(9) <= 'X';
            rddata_reg(10) <= 'X';
            rddata_reg(11) <= 'X';
            rddata_reg(12) <= 'X';
            rddata_reg(13) <= 'X';
            rddata_reg(14) <= 'X';
            rddata_reg(15) <= 'X';
            rddata_reg(16) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            rddata_reg(24) <= 'X';
            rddata_reg(25) <= 'X';
            rddata_reg(26) <= 'X';
            rddata_reg(27) <= 'X';
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(4) <= '1';
            ack_in_progress <= '1';
          when "0011001" => 
            if (wb_we_i = '1') then
              wb_trig_iface_ch8_cfg_rcv_len_int <= wrdata_reg(7 downto 0);
              wb_trig_iface_ch8_cfg_rcv_len_swb <= '1';
              wb_trig_iface_ch8_cfg_rcv_len_swb_delay <= '1';
              wb_trig_iface_ch8_cfg_transm_len_int <= wrdata_reg(15 downto 8);
              wb_trig_iface_ch8_cfg_transm_len_swb <= '1';
              wb_trig_iface_ch8_cfg_transm_len_swb_delay <= '1';
            end if;
            rddata_reg(7 downto 0) <= wb_trig_iface_ch8_cfg_rcv_len_int;
            rddata_reg(15 downto 8) <= wb_trig_iface_ch8_cfg_transm_len_int;
            rddata_reg(16) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            rddata_reg(24) <= 'X';
            rddata_reg(25) <= 'X';
            rddata_reg(26) <= 'X';
            rddata_reg(27) <= 'X';
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(3) <= '1';
            ack_in_progress <= '1';
          when "0011010" => 
            if (wb_we_i = '1') then
            end if;
            if (wb_we_i = '0') then
              wb_trig_iface_ch8_count_rcv_lwb <= '1';
              wb_trig_iface_ch8_count_rcv_lwb_delay <= '1';
              wb_trig_iface_ch8_count_rcv_lwb_in_progress <= '1';
            end if;
            if (wb_we_i = '0') then
              wb_trig_iface_ch8_count_transm_lwb <= '1';
              wb_trig_iface_ch8_count_transm_lwb_delay <= '1';
              wb_trig_iface_ch8_count_transm_lwb_in_progress <= '1';
            end if;
            ack_sreg(5) <= '1';
            ack_in_progress <= '1';
          when "0011011" => 
            if (wb_we_i = '1') then
              wb_trig_iface_ch9_ctl_dir_int <= wrdata_reg(0);
              wb_trig_iface_ch9_ctl_dir_pol_int <= wrdata_reg(1);
              wb_trig_iface_ch9_ctl_rcv_count_rst_int <= wrdata_reg(2);
              wb_trig_iface_ch9_ctl_rcv_count_rst_int_delay <= wrdata_reg(2);
              wb_trig_iface_ch9_ctl_transm_count_rst_int <= wrdata_reg(3);
              wb_trig_iface_ch9_ctl_transm_count_rst_int_delay <= wrdata_reg(3);
            end if;
            rddata_reg(0) <= wb_trig_iface_ch9_ctl_dir_int;
            rddata_reg(1) <= wb_trig_iface_ch9_ctl_dir_pol_int;
            rddata_reg(2) <= '0';
            rddata_reg(3) <= '0';
            rddata_reg(4) <= 'X';
            rddata_reg(5) <= 'X';
            rddata_reg(6) <= 'X';
            rddata_reg(7) <= 'X';
            rddata_reg(8) <= 'X';
            rddata_reg(9) <= 'X';
            rddata_reg(10) <= 'X';
            rddata_reg(11) <= 'X';
            rddata_reg(12) <= 'X';
            rddata_reg(13) <= 'X';
            rddata_reg(14) <= 'X';
            rddata_reg(15) <= 'X';
            rddata_reg(16) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            rddata_reg(24) <= 'X';
            rddata_reg(25) <= 'X';
            rddata_reg(26) <= 'X';
            rddata_reg(27) <= 'X';
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(4) <= '1';
            ack_in_progress <= '1';
          when "0011100" => 
            if (wb_we_i = '1') then
              wb_trig_iface_ch9_cfg_rcv_len_int <= wrdata_reg(7 downto 0);
              wb_trig_iface_ch9_cfg_rcv_len_swb <= '1';
              wb_trig_iface_ch9_cfg_rcv_len_swb_delay <= '1';
              wb_trig_iface_ch9_cfg_transm_len_int <= wrdata_reg(15 downto 8);
              wb_trig_iface_ch9_cfg_transm_len_swb <= '1';
              wb_trig_iface_ch9_cfg_transm_len_swb_delay <= '1';
            end if;
            rddata_reg(7 downto 0) <= wb_trig_iface_ch9_cfg_rcv_len_int;
            rddata_reg(15 downto 8) <= wb_trig_iface_ch9_cfg_transm_len_int;
            rddata_reg(16) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            rddata_reg(24) <= 'X';
            rddata_reg(25) <= 'X';
            rddata_reg(26) <= 'X';
            rddata_reg(27) <= 'X';
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(3) <= '1';
            ack_in_progress <= '1';
          when "0011101" => 
            if (wb_we_i = '1') then
            end if;
            if (wb_we_i = '0') then
              wb_trig_iface_ch9_count_rcv_lwb <= '1';
              wb_trig_iface_ch9_count_rcv_lwb_delay <= '1';
              wb_trig_iface_ch9_count_rcv_lwb_in_progress <= '1';
            end if;
            if (wb_we_i = '0') then
              wb_trig_iface_ch9_count_transm_lwb <= '1';
              wb_trig_iface_ch9_count_transm_lwb_delay <= '1';
              wb_trig_iface_ch9_count_transm_lwb_in_progress <= '1';
            end if;
            ack_sreg(5) <= '1';
            ack_in_progress <= '1';
          when "0011110" => 
            if (wb_we_i = '1') then
              wb_trig_iface_ch10_ctl_dir_int <= wrdata_reg(0);
              wb_trig_iface_ch10_ctl_dir_pol_int <= wrdata_reg(1);
              wb_trig_iface_ch10_ctl_rcv_count_rst_int <= wrdata_reg(2);
              wb_trig_iface_ch10_ctl_rcv_count_rst_int_delay <= wrdata_reg(2);
              wb_trig_iface_ch10_ctl_transm_count_rst_int <= wrdata_reg(3);
              wb_trig_iface_ch10_ctl_transm_count_rst_int_delay <= wrdata_reg(3);
            end if;
            rddata_reg(0) <= wb_trig_iface_ch10_ctl_dir_int;
            rddata_reg(1) <= wb_trig_iface_ch10_ctl_dir_pol_int;
            rddata_reg(2) <= '0';
            rddata_reg(3) <= '0';
            rddata_reg(4) <= 'X';
            rddata_reg(5) <= 'X';
            rddata_reg(6) <= 'X';
            rddata_reg(7) <= 'X';
            rddata_reg(8) <= 'X';
            rddata_reg(9) <= 'X';
            rddata_reg(10) <= 'X';
            rddata_reg(11) <= 'X';
            rddata_reg(12) <= 'X';
            rddata_reg(13) <= 'X';
            rddata_reg(14) <= 'X';
            rddata_reg(15) <= 'X';
            rddata_reg(16) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            rddata_reg(24) <= 'X';
            rddata_reg(25) <= 'X';
            rddata_reg(26) <= 'X';
            rddata_reg(27) <= 'X';
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(4) <= '1';
            ack_in_progress <= '1';
          when "0011111" => 
            if (wb_we_i = '1') then
              wb_trig_iface_ch10_cfg_rcv_len_int <= wrdata_reg(7 downto 0);
              wb_trig_iface_ch10_cfg_rcv_len_swb <= '1';
              wb_trig_iface_ch10_cfg_rcv_len_swb_delay <= '1';
              wb_trig_iface_ch10_cfg_transm_len_int <= wrdata_reg(15 downto 8);
              wb_trig_iface_ch10_cfg_transm_len_swb <= '1';
              wb_trig_iface_ch10_cfg_transm_len_swb_delay <= '1';
            end if;
            rddata_reg(7 downto 0) <= wb_trig_iface_ch10_cfg_rcv_len_int;
            rddata_reg(15 downto 8) <= wb_trig_iface_ch10_cfg_transm_len_int;
            rddata_reg(16) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            rddata_reg(24) <= 'X';
            rddata_reg(25) <= 'X';
            rddata_reg(26) <= 'X';
            rddata_reg(27) <= 'X';
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(3) <= '1';
            ack_in_progress <= '1';
          when "0100000" => 
            if (wb_we_i = '1') then
            end if;
            if (wb_we_i = '0') then
              wb_trig_iface_ch10_count_rcv_lwb <= '1';
              wb_trig_iface_ch10_count_rcv_lwb_delay <= '1';
              wb_trig_iface_ch10_count_rcv_lwb_in_progress <= '1';
            end if;
            if (wb_we_i = '0') then
              wb_trig_iface_ch10_count_transm_lwb <= '1';
              wb_trig_iface_ch10_count_transm_lwb_delay <= '1';
              wb_trig_iface_ch10_count_transm_lwb_in_progress <= '1';
            end if;
            ack_sreg(5) <= '1';
            ack_in_progress <= '1';
          when "0100001" => 
            if (wb_we_i = '1') then
              wb_trig_iface_ch11_ctl_dir_int <= wrdata_reg(0);
              wb_trig_iface_ch11_ctl_dir_pol_int <= wrdata_reg(1);
              wb_trig_iface_ch11_ctl_rcv_count_rst_int <= wrdata_reg(2);
              wb_trig_iface_ch11_ctl_rcv_count_rst_int_delay <= wrdata_reg(2);
              wb_trig_iface_ch11_ctl_transm_count_rst_int <= wrdata_reg(3);
              wb_trig_iface_ch11_ctl_transm_count_rst_int_delay <= wrdata_reg(3);
            end if;
            rddata_reg(0) <= wb_trig_iface_ch11_ctl_dir_int;
            rddata_reg(1) <= wb_trig_iface_ch11_ctl_dir_pol_int;
            rddata_reg(2) <= '0';
            rddata_reg(3) <= '0';
            rddata_reg(4) <= 'X';
            rddata_reg(5) <= 'X';
            rddata_reg(6) <= 'X';
            rddata_reg(7) <= 'X';
            rddata_reg(8) <= 'X';
            rddata_reg(9) <= 'X';
            rddata_reg(10) <= 'X';
            rddata_reg(11) <= 'X';
            rddata_reg(12) <= 'X';
            rddata_reg(13) <= 'X';
            rddata_reg(14) <= 'X';
            rddata_reg(15) <= 'X';
            rddata_reg(16) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            rddata_reg(24) <= 'X';
            rddata_reg(25) <= 'X';
            rddata_reg(26) <= 'X';
            rddata_reg(27) <= 'X';
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(4) <= '1';
            ack_in_progress <= '1';
          when "0100010" => 
            if (wb_we_i = '1') then
              wb_trig_iface_ch11_cfg_rcv_len_int <= wrdata_reg(7 downto 0);
              wb_trig_iface_ch11_cfg_rcv_len_swb <= '1';
              wb_trig_iface_ch11_cfg_rcv_len_swb_delay <= '1';
              wb_trig_iface_ch11_cfg_transm_len_int <= wrdata_reg(15 downto 8);
              wb_trig_iface_ch11_cfg_transm_len_swb <= '1';
              wb_trig_iface_ch11_cfg_transm_len_swb_delay <= '1';
            end if;
            rddata_reg(7 downto 0) <= wb_trig_iface_ch11_cfg_rcv_len_int;
            rddata_reg(15 downto 8) <= wb_trig_iface_ch11_cfg_transm_len_int;
            rddata_reg(16) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            rddata_reg(24) <= 'X';
            rddata_reg(25) <= 'X';
            rddata_reg(26) <= 'X';
            rddata_reg(27) <= 'X';
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(3) <= '1';
            ack_in_progress <= '1';
          when "0100011" => 
            if (wb_we_i = '1') then
            end if;
            if (wb_we_i = '0') then
              wb_trig_iface_ch11_count_rcv_lwb <= '1';
              wb_trig_iface_ch11_count_rcv_lwb_delay <= '1';
              wb_trig_iface_ch11_count_rcv_lwb_in_progress <= '1';
            end if;
            if (wb_we_i = '0') then
              wb_trig_iface_ch11_count_transm_lwb <= '1';
              wb_trig_iface_ch11_count_transm_lwb_delay <= '1';
              wb_trig_iface_ch11_count_transm_lwb_in_progress <= '1';
            end if;
            ack_sreg(5) <= '1';
            ack_in_progress <= '1';
          when "0100100" => 
            if (wb_we_i = '1') then
              wb_trig_iface_ch12_ctl_dir_int <= wrdata_reg(0);
              wb_trig_iface_ch12_ctl_dir_pol_int <= wrdata_reg(1);
              wb_trig_iface_ch12_ctl_rcv_count_rst_int <= wrdata_reg(2);
              wb_trig_iface_ch12_ctl_rcv_count_rst_int_delay <= wrdata_reg(2);
              wb_trig_iface_ch12_ctl_transm_count_rst_int <= wrdata_reg(3);
              wb_trig_iface_ch12_ctl_transm_count_rst_int_delay <= wrdata_reg(3);
            end if;
            rddata_reg(0) <= wb_trig_iface_ch12_ctl_dir_int;
            rddata_reg(1) <= wb_trig_iface_ch12_ctl_dir_pol_int;
            rddata_reg(2) <= '0';
            rddata_reg(3) <= '0';
            rddata_reg(4) <= 'X';
            rddata_reg(5) <= 'X';
            rddata_reg(6) <= 'X';
            rddata_reg(7) <= 'X';
            rddata_reg(8) <= 'X';
            rddata_reg(9) <= 'X';
            rddata_reg(10) <= 'X';
            rddata_reg(11) <= 'X';
            rddata_reg(12) <= 'X';
            rddata_reg(13) <= 'X';
            rddata_reg(14) <= 'X';
            rddata_reg(15) <= 'X';
            rddata_reg(16) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            rddata_reg(24) <= 'X';
            rddata_reg(25) <= 'X';
            rddata_reg(26) <= 'X';
            rddata_reg(27) <= 'X';
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(4) <= '1';
            ack_in_progress <= '1';
          when "0100101" => 
            if (wb_we_i = '1') then
              wb_trig_iface_ch12_cfg_rcv_len_int <= wrdata_reg(7 downto 0);
              wb_trig_iface_ch12_cfg_rcv_len_swb <= '1';
              wb_trig_iface_ch12_cfg_rcv_len_swb_delay <= '1';
              wb_trig_iface_ch12_cfg_transm_len_int <= wrdata_reg(15 downto 8);
              wb_trig_iface_ch12_cfg_transm_len_swb <= '1';
              wb_trig_iface_ch12_cfg_transm_len_swb_delay <= '1';
            end if;
            rddata_reg(7 downto 0) <= wb_trig_iface_ch12_cfg_rcv_len_int;
            rddata_reg(15 downto 8) <= wb_trig_iface_ch12_cfg_transm_len_int;
            rddata_reg(16) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            rddata_reg(24) <= 'X';
            rddata_reg(25) <= 'X';
            rddata_reg(26) <= 'X';
            rddata_reg(27) <= 'X';
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(3) <= '1';
            ack_in_progress <= '1';
          when "0100110" => 
            if (wb_we_i = '1') then
            end if;
            if (wb_we_i = '0') then
              wb_trig_iface_ch12_count_rcv_lwb <= '1';
              wb_trig_iface_ch12_count_rcv_lwb_delay <= '1';
              wb_trig_iface_ch12_count_rcv_lwb_in_progress <= '1';
            end if;
            if (wb_we_i = '0') then
              wb_trig_iface_ch12_count_transm_lwb <= '1';
              wb_trig_iface_ch12_count_transm_lwb_delay <= '1';
              wb_trig_iface_ch12_count_transm_lwb_in_progress <= '1';
            end if;
            ack_sreg(5) <= '1';
            ack_in_progress <= '1';
          when "0100111" => 
            if (wb_we_i = '1') then
              wb_trig_iface_ch13_ctl_dir_int <= wrdata_reg(0);
              wb_trig_iface_ch13_ctl_dir_pol_int <= wrdata_reg(1);
              wb_trig_iface_ch13_ctl_rcv_count_rst_int <= wrdata_reg(2);
              wb_trig_iface_ch13_ctl_rcv_count_rst_int_delay <= wrdata_reg(2);
              wb_trig_iface_ch13_ctl_transm_count_rst_int <= wrdata_reg(3);
              wb_trig_iface_ch13_ctl_transm_count_rst_int_delay <= wrdata_reg(3);
            end if;
            rddata_reg(0) <= wb_trig_iface_ch13_ctl_dir_int;
            rddata_reg(1) <= wb_trig_iface_ch13_ctl_dir_pol_int;
            rddata_reg(2) <= '0';
            rddata_reg(3) <= '0';
            rddata_reg(4) <= 'X';
            rddata_reg(5) <= 'X';
            rddata_reg(6) <= 'X';
            rddata_reg(7) <= 'X';
            rddata_reg(8) <= 'X';
            rddata_reg(9) <= 'X';
            rddata_reg(10) <= 'X';
            rddata_reg(11) <= 'X';
            rddata_reg(12) <= 'X';
            rddata_reg(13) <= 'X';
            rddata_reg(14) <= 'X';
            rddata_reg(15) <= 'X';
            rddata_reg(16) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            rddata_reg(24) <= 'X';
            rddata_reg(25) <= 'X';
            rddata_reg(26) <= 'X';
            rddata_reg(27) <= 'X';
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(4) <= '1';
            ack_in_progress <= '1';
          when "0101000" => 
            if (wb_we_i = '1') then
              wb_trig_iface_ch13_cfg_rcv_len_int <= wrdata_reg(7 downto 0);
              wb_trig_iface_ch13_cfg_rcv_len_swb <= '1';
              wb_trig_iface_ch13_cfg_rcv_len_swb_delay <= '1';
              wb_trig_iface_ch13_cfg_transm_len_int <= wrdata_reg(15 downto 8);
              wb_trig_iface_ch13_cfg_transm_len_swb <= '1';
              wb_trig_iface_ch13_cfg_transm_len_swb_delay <= '1';
            end if;
            rddata_reg(7 downto 0) <= wb_trig_iface_ch13_cfg_rcv_len_int;
            rddata_reg(15 downto 8) <= wb_trig_iface_ch13_cfg_transm_len_int;
            rddata_reg(16) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            rddata_reg(24) <= 'X';
            rddata_reg(25) <= 'X';
            rddata_reg(26) <= 'X';
            rddata_reg(27) <= 'X';
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(3) <= '1';
            ack_in_progress <= '1';
          when "0101001" => 
            if (wb_we_i = '1') then
            end if;
            if (wb_we_i = '0') then
              wb_trig_iface_ch13_count_rcv_lwb <= '1';
              wb_trig_iface_ch13_count_rcv_lwb_delay <= '1';
              wb_trig_iface_ch13_count_rcv_lwb_in_progress <= '1';
            end if;
            if (wb_we_i = '0') then
              wb_trig_iface_ch13_count_transm_lwb <= '1';
              wb_trig_iface_ch13_count_transm_lwb_delay <= '1';
              wb_trig_iface_ch13_count_transm_lwb_in_progress <= '1';
            end if;
            ack_sreg(5) <= '1';
            ack_in_progress <= '1';
          when "0101010" => 
            if (wb_we_i = '1') then
              wb_trig_iface_ch14_ctl_dir_int <= wrdata_reg(0);
              wb_trig_iface_ch14_ctl_dir_pol_int <= wrdata_reg(1);
              wb_trig_iface_ch14_ctl_rcv_count_rst_int <= wrdata_reg(2);
              wb_trig_iface_ch14_ctl_rcv_count_rst_int_delay <= wrdata_reg(2);
              wb_trig_iface_ch14_ctl_transm_count_rst_int <= wrdata_reg(3);
              wb_trig_iface_ch14_ctl_transm_count_rst_int_delay <= wrdata_reg(3);
            end if;
            rddata_reg(0) <= wb_trig_iface_ch14_ctl_dir_int;
            rddata_reg(1) <= wb_trig_iface_ch14_ctl_dir_pol_int;
            rddata_reg(2) <= '0';
            rddata_reg(3) <= '0';
            rddata_reg(4) <= 'X';
            rddata_reg(5) <= 'X';
            rddata_reg(6) <= 'X';
            rddata_reg(7) <= 'X';
            rddata_reg(8) <= 'X';
            rddata_reg(9) <= 'X';
            rddata_reg(10) <= 'X';
            rddata_reg(11) <= 'X';
            rddata_reg(12) <= 'X';
            rddata_reg(13) <= 'X';
            rddata_reg(14) <= 'X';
            rddata_reg(15) <= 'X';
            rddata_reg(16) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            rddata_reg(24) <= 'X';
            rddata_reg(25) <= 'X';
            rddata_reg(26) <= 'X';
            rddata_reg(27) <= 'X';
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(4) <= '1';
            ack_in_progress <= '1';
          when "0101011" => 
            if (wb_we_i = '1') then
              wb_trig_iface_ch14_cfg_rcv_len_int <= wrdata_reg(7 downto 0);
              wb_trig_iface_ch14_cfg_rcv_len_swb <= '1';
              wb_trig_iface_ch14_cfg_rcv_len_swb_delay <= '1';
              wb_trig_iface_ch14_cfg_transm_len_int <= wrdata_reg(15 downto 8);
              wb_trig_iface_ch14_cfg_transm_len_swb <= '1';
              wb_trig_iface_ch14_cfg_transm_len_swb_delay <= '1';
            end if;
            rddata_reg(7 downto 0) <= wb_trig_iface_ch14_cfg_rcv_len_int;
            rddata_reg(15 downto 8) <= wb_trig_iface_ch14_cfg_transm_len_int;
            rddata_reg(16) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            rddata_reg(24) <= 'X';
            rddata_reg(25) <= 'X';
            rddata_reg(26) <= 'X';
            rddata_reg(27) <= 'X';
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(3) <= '1';
            ack_in_progress <= '1';
          when "0101100" => 
            if (wb_we_i = '1') then
            end if;
            if (wb_we_i = '0') then
              wb_trig_iface_ch14_count_rcv_lwb <= '1';
              wb_trig_iface_ch14_count_rcv_lwb_delay <= '1';
              wb_trig_iface_ch14_count_rcv_lwb_in_progress <= '1';
            end if;
            if (wb_we_i = '0') then
              wb_trig_iface_ch14_count_transm_lwb <= '1';
              wb_trig_iface_ch14_count_transm_lwb_delay <= '1';
              wb_trig_iface_ch14_count_transm_lwb_in_progress <= '1';
            end if;
            ack_sreg(5) <= '1';
            ack_in_progress <= '1';
          when "0101101" => 
            if (wb_we_i = '1') then
              wb_trig_iface_ch15_ctl_dir_int <= wrdata_reg(0);
              wb_trig_iface_ch15_ctl_dir_pol_int <= wrdata_reg(1);
              wb_trig_iface_ch15_ctl_rcv_count_rst_int <= wrdata_reg(2);
              wb_trig_iface_ch15_ctl_rcv_count_rst_int_delay <= wrdata_reg(2);
              wb_trig_iface_ch15_ctl_transm_count_rst_int <= wrdata_reg(3);
              wb_trig_iface_ch15_ctl_transm_count_rst_int_delay <= wrdata_reg(3);
            end if;
            rddata_reg(0) <= wb_trig_iface_ch15_ctl_dir_int;
            rddata_reg(1) <= wb_trig_iface_ch15_ctl_dir_pol_int;
            rddata_reg(2) <= '0';
            rddata_reg(3) <= '0';
            rddata_reg(4) <= 'X';
            rddata_reg(5) <= 'X';
            rddata_reg(6) <= 'X';
            rddata_reg(7) <= 'X';
            rddata_reg(8) <= 'X';
            rddata_reg(9) <= 'X';
            rddata_reg(10) <= 'X';
            rddata_reg(11) <= 'X';
            rddata_reg(12) <= 'X';
            rddata_reg(13) <= 'X';
            rddata_reg(14) <= 'X';
            rddata_reg(15) <= 'X';
            rddata_reg(16) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            rddata_reg(24) <= 'X';
            rddata_reg(25) <= 'X';
            rddata_reg(26) <= 'X';
            rddata_reg(27) <= 'X';
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(4) <= '1';
            ack_in_progress <= '1';
          when "0101110" => 
            if (wb_we_i = '1') then
              wb_trig_iface_ch15_cfg_rcv_len_int <= wrdata_reg(7 downto 0);
              wb_trig_iface_ch15_cfg_rcv_len_swb <= '1';
              wb_trig_iface_ch15_cfg_rcv_len_swb_delay <= '1';
              wb_trig_iface_ch15_cfg_transm_len_int <= wrdata_reg(15 downto 8);
              wb_trig_iface_ch15_cfg_transm_len_swb <= '1';
              wb_trig_iface_ch15_cfg_transm_len_swb_delay <= '1';
            end if;
            rddata_reg(7 downto 0) <= wb_trig_iface_ch15_cfg_rcv_len_int;
            rddata_reg(15 downto 8) <= wb_trig_iface_ch15_cfg_transm_len_int;
            rddata_reg(16) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            rddata_reg(24) <= 'X';
            rddata_reg(25) <= 'X';
            rddata_reg(26) <= 'X';
            rddata_reg(27) <= 'X';
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(3) <= '1';
            ack_in_progress <= '1';
          when "0101111" => 
            if (wb_we_i = '1') then
            end if;
            if (wb_we_i = '0') then
              wb_trig_iface_ch15_count_rcv_lwb <= '1';
              wb_trig_iface_ch15_count_rcv_lwb_delay <= '1';
              wb_trig_iface_ch15_count_rcv_lwb_in_progress <= '1';
            end if;
            if (wb_we_i = '0') then
              wb_trig_iface_ch15_count_transm_lwb <= '1';
              wb_trig_iface_ch15_count_transm_lwb_delay <= '1';
              wb_trig_iface_ch15_count_transm_lwb_in_progress <= '1';
            end if;
            ack_sreg(5) <= '1';
            ack_in_progress <= '1';
          when "0110000" => 
            if (wb_we_i = '1') then
              wb_trig_iface_ch16_ctl_dir_int <= wrdata_reg(0);
              wb_trig_iface_ch16_ctl_dir_pol_int <= wrdata_reg(1);
              wb_trig_iface_ch16_ctl_rcv_count_rst_int <= wrdata_reg(2);
              wb_trig_iface_ch16_ctl_rcv_count_rst_int_delay <= wrdata_reg(2);
              wb_trig_iface_ch16_ctl_transm_count_rst_int <= wrdata_reg(3);
              wb_trig_iface_ch16_ctl_transm_count_rst_int_delay <= wrdata_reg(3);
            end if;
            rddata_reg(0) <= wb_trig_iface_ch16_ctl_dir_int;
            rddata_reg(1) <= wb_trig_iface_ch16_ctl_dir_pol_int;
            rddata_reg(2) <= '0';
            rddata_reg(3) <= '0';
            rddata_reg(4) <= 'X';
            rddata_reg(5) <= 'X';
            rddata_reg(6) <= 'X';
            rddata_reg(7) <= 'X';
            rddata_reg(8) <= 'X';
            rddata_reg(9) <= 'X';
            rddata_reg(10) <= 'X';
            rddata_reg(11) <= 'X';
            rddata_reg(12) <= 'X';
            rddata_reg(13) <= 'X';
            rddata_reg(14) <= 'X';
            rddata_reg(15) <= 'X';
            rddata_reg(16) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            rddata_reg(24) <= 'X';
            rddata_reg(25) <= 'X';
            rddata_reg(26) <= 'X';
            rddata_reg(27) <= 'X';
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(4) <= '1';
            ack_in_progress <= '1';
          when "0110001" => 
            if (wb_we_i = '1') then
              wb_trig_iface_ch16_cfg_rcv_len_int <= wrdata_reg(7 downto 0);
              wb_trig_iface_ch16_cfg_rcv_len_swb <= '1';
              wb_trig_iface_ch16_cfg_rcv_len_swb_delay <= '1';
              wb_trig_iface_ch16_cfg_transm_len_int <= wrdata_reg(15 downto 8);
              wb_trig_iface_ch16_cfg_transm_len_swb <= '1';
              wb_trig_iface_ch16_cfg_transm_len_swb_delay <= '1';
            end if;
            rddata_reg(7 downto 0) <= wb_trig_iface_ch16_cfg_rcv_len_int;
            rddata_reg(15 downto 8) <= wb_trig_iface_ch16_cfg_transm_len_int;
            rddata_reg(16) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            rddata_reg(24) <= 'X';
            rddata_reg(25) <= 'X';
            rddata_reg(26) <= 'X';
            rddata_reg(27) <= 'X';
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(3) <= '1';
            ack_in_progress <= '1';
          when "0110010" => 
            if (wb_we_i = '1') then
            end if;
            if (wb_we_i = '0') then
              wb_trig_iface_ch16_count_rcv_lwb <= '1';
              wb_trig_iface_ch16_count_rcv_lwb_delay <= '1';
              wb_trig_iface_ch16_count_rcv_lwb_in_progress <= '1';
            end if;
            if (wb_we_i = '0') then
              wb_trig_iface_ch16_count_transm_lwb <= '1';
              wb_trig_iface_ch16_count_transm_lwb_delay <= '1';
              wb_trig_iface_ch16_count_transm_lwb_in_progress <= '1';
            end if;
            ack_sreg(5) <= '1';
            ack_in_progress <= '1';
          when "0110011" => 
            if (wb_we_i = '1') then
              wb_trig_iface_ch17_ctl_dir_int <= wrdata_reg(0);
              wb_trig_iface_ch17_ctl_dir_pol_int <= wrdata_reg(1);
              wb_trig_iface_ch17_ctl_rcv_count_rst_int <= wrdata_reg(2);
              wb_trig_iface_ch17_ctl_rcv_count_rst_int_delay <= wrdata_reg(2);
              wb_trig_iface_ch17_ctl_transm_count_rst_int <= wrdata_reg(3);
              wb_trig_iface_ch17_ctl_transm_count_rst_int_delay <= wrdata_reg(3);
            end if;
            rddata_reg(0) <= wb_trig_iface_ch17_ctl_dir_int;
            rddata_reg(1) <= wb_trig_iface_ch17_ctl_dir_pol_int;
            rddata_reg(2) <= '0';
            rddata_reg(3) <= '0';
            rddata_reg(4) <= 'X';
            rddata_reg(5) <= 'X';
            rddata_reg(6) <= 'X';
            rddata_reg(7) <= 'X';
            rddata_reg(8) <= 'X';
            rddata_reg(9) <= 'X';
            rddata_reg(10) <= 'X';
            rddata_reg(11) <= 'X';
            rddata_reg(12) <= 'X';
            rddata_reg(13) <= 'X';
            rddata_reg(14) <= 'X';
            rddata_reg(15) <= 'X';
            rddata_reg(16) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            rddata_reg(24) <= 'X';
            rddata_reg(25) <= 'X';
            rddata_reg(26) <= 'X';
            rddata_reg(27) <= 'X';
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(4) <= '1';
            ack_in_progress <= '1';
          when "0110100" => 
            if (wb_we_i = '1') then
              wb_trig_iface_ch17_cfg_rcv_len_int <= wrdata_reg(7 downto 0);
              wb_trig_iface_ch17_cfg_rcv_len_swb <= '1';
              wb_trig_iface_ch17_cfg_rcv_len_swb_delay <= '1';
              wb_trig_iface_ch17_cfg_transm_len_int <= wrdata_reg(15 downto 8);
              wb_trig_iface_ch17_cfg_transm_len_swb <= '1';
              wb_trig_iface_ch17_cfg_transm_len_swb_delay <= '1';
            end if;
            rddata_reg(7 downto 0) <= wb_trig_iface_ch17_cfg_rcv_len_int;
            rddata_reg(15 downto 8) <= wb_trig_iface_ch17_cfg_transm_len_int;
            rddata_reg(16) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            rddata_reg(24) <= 'X';
            rddata_reg(25) <= 'X';
            rddata_reg(26) <= 'X';
            rddata_reg(27) <= 'X';
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(3) <= '1';
            ack_in_progress <= '1';
          when "0110101" => 
            if (wb_we_i = '1') then
            end if;
            if (wb_we_i = '0') then
              wb_trig_iface_ch17_count_rcv_lwb <= '1';
              wb_trig_iface_ch17_count_rcv_lwb_delay <= '1';
              wb_trig_iface_ch17_count_rcv_lwb_in_progress <= '1';
            end if;
            if (wb_we_i = '0') then
              wb_trig_iface_ch17_count_transm_lwb <= '1';
              wb_trig_iface_ch17_count_transm_lwb_delay <= '1';
              wb_trig_iface_ch17_count_transm_lwb_in_progress <= '1';
            end if;
            ack_sreg(5) <= '1';
            ack_in_progress <= '1';
          when "0110110" => 
            if (wb_we_i = '1') then
              wb_trig_iface_ch18_ctl_dir_int <= wrdata_reg(0);
              wb_trig_iface_ch18_ctl_dir_pol_int <= wrdata_reg(1);
              wb_trig_iface_ch18_ctl_rcv_count_rst_int <= wrdata_reg(2);
              wb_trig_iface_ch18_ctl_rcv_count_rst_int_delay <= wrdata_reg(2);
              wb_trig_iface_ch18_ctl_transm_count_rst_int <= wrdata_reg(3);
              wb_trig_iface_ch18_ctl_transm_count_rst_int_delay <= wrdata_reg(3);
            end if;
            rddata_reg(0) <= wb_trig_iface_ch18_ctl_dir_int;
            rddata_reg(1) <= wb_trig_iface_ch18_ctl_dir_pol_int;
            rddata_reg(2) <= '0';
            rddata_reg(3) <= '0';
            rddata_reg(4) <= 'X';
            rddata_reg(5) <= 'X';
            rddata_reg(6) <= 'X';
            rddata_reg(7) <= 'X';
            rddata_reg(8) <= 'X';
            rddata_reg(9) <= 'X';
            rddata_reg(10) <= 'X';
            rddata_reg(11) <= 'X';
            rddata_reg(12) <= 'X';
            rddata_reg(13) <= 'X';
            rddata_reg(14) <= 'X';
            rddata_reg(15) <= 'X';
            rddata_reg(16) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            rddata_reg(24) <= 'X';
            rddata_reg(25) <= 'X';
            rddata_reg(26) <= 'X';
            rddata_reg(27) <= 'X';
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(4) <= '1';
            ack_in_progress <= '1';
          when "0110111" => 
            if (wb_we_i = '1') then
              wb_trig_iface_ch18_cfg_rcv_len_int <= wrdata_reg(7 downto 0);
              wb_trig_iface_ch18_cfg_rcv_len_swb <= '1';
              wb_trig_iface_ch18_cfg_rcv_len_swb_delay <= '1';
              wb_trig_iface_ch18_cfg_transm_len_int <= wrdata_reg(15 downto 8);
              wb_trig_iface_ch18_cfg_transm_len_swb <= '1';
              wb_trig_iface_ch18_cfg_transm_len_swb_delay <= '1';
            end if;
            rddata_reg(7 downto 0) <= wb_trig_iface_ch18_cfg_rcv_len_int;
            rddata_reg(15 downto 8) <= wb_trig_iface_ch18_cfg_transm_len_int;
            rddata_reg(16) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            rddata_reg(24) <= 'X';
            rddata_reg(25) <= 'X';
            rddata_reg(26) <= 'X';
            rddata_reg(27) <= 'X';
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(3) <= '1';
            ack_in_progress <= '1';
          when "0111000" => 
            if (wb_we_i = '1') then
            end if;
            if (wb_we_i = '0') then
              wb_trig_iface_ch18_count_rcv_lwb <= '1';
              wb_trig_iface_ch18_count_rcv_lwb_delay <= '1';
              wb_trig_iface_ch18_count_rcv_lwb_in_progress <= '1';
            end if;
            if (wb_we_i = '0') then
              wb_trig_iface_ch18_count_transm_lwb <= '1';
              wb_trig_iface_ch18_count_transm_lwb_delay <= '1';
              wb_trig_iface_ch18_count_transm_lwb_in_progress <= '1';
            end if;
            ack_sreg(5) <= '1';
            ack_in_progress <= '1';
          when "0111001" => 
            if (wb_we_i = '1') then
              wb_trig_iface_ch19_ctl_dir_int <= wrdata_reg(0);
              wb_trig_iface_ch19_ctl_dir_pol_int <= wrdata_reg(1);
              wb_trig_iface_ch19_ctl_rcv_count_rst_int <= wrdata_reg(2);
              wb_trig_iface_ch19_ctl_rcv_count_rst_int_delay <= wrdata_reg(2);
              wb_trig_iface_ch19_ctl_transm_count_rst_int <= wrdata_reg(3);
              wb_trig_iface_ch19_ctl_transm_count_rst_int_delay <= wrdata_reg(3);
            end if;
            rddata_reg(0) <= wb_trig_iface_ch19_ctl_dir_int;
            rddata_reg(1) <= wb_trig_iface_ch19_ctl_dir_pol_int;
            rddata_reg(2) <= '0';
            rddata_reg(3) <= '0';
            rddata_reg(4) <= 'X';
            rddata_reg(5) <= 'X';
            rddata_reg(6) <= 'X';
            rddata_reg(7) <= 'X';
            rddata_reg(8) <= 'X';
            rddata_reg(9) <= 'X';
            rddata_reg(10) <= 'X';
            rddata_reg(11) <= 'X';
            rddata_reg(12) <= 'X';
            rddata_reg(13) <= 'X';
            rddata_reg(14) <= 'X';
            rddata_reg(15) <= 'X';
            rddata_reg(16) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            rddata_reg(24) <= 'X';
            rddata_reg(25) <= 'X';
            rddata_reg(26) <= 'X';
            rddata_reg(27) <= 'X';
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(4) <= '1';
            ack_in_progress <= '1';
          when "0111010" => 
            if (wb_we_i = '1') then
              wb_trig_iface_ch19_cfg_rcv_len_int <= wrdata_reg(7 downto 0);
              wb_trig_iface_ch19_cfg_rcv_len_swb <= '1';
              wb_trig_iface_ch19_cfg_rcv_len_swb_delay <= '1';
              wb_trig_iface_ch19_cfg_transm_len_int <= wrdata_reg(15 downto 8);
              wb_trig_iface_ch19_cfg_transm_len_swb <= '1';
              wb_trig_iface_ch19_cfg_transm_len_swb_delay <= '1';
            end if;
            rddata_reg(7 downto 0) <= wb_trig_iface_ch19_cfg_rcv_len_int;
            rddata_reg(15 downto 8) <= wb_trig_iface_ch19_cfg_transm_len_int;
            rddata_reg(16) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            rddata_reg(24) <= 'X';
            rddata_reg(25) <= 'X';
            rddata_reg(26) <= 'X';
            rddata_reg(27) <= 'X';
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(3) <= '1';
            ack_in_progress <= '1';
          when "0111011" => 
            if (wb_we_i = '1') then
            end if;
            if (wb_we_i = '0') then
              wb_trig_iface_ch19_count_rcv_lwb <= '1';
              wb_trig_iface_ch19_count_rcv_lwb_delay <= '1';
              wb_trig_iface_ch19_count_rcv_lwb_in_progress <= '1';
            end if;
            if (wb_we_i = '0') then
              wb_trig_iface_ch19_count_transm_lwb <= '1';
              wb_trig_iface_ch19_count_transm_lwb_delay <= '1';
              wb_trig_iface_ch19_count_transm_lwb_in_progress <= '1';
            end if;
            ack_sreg(5) <= '1';
            ack_in_progress <= '1';
          when "0111100" => 
            if (wb_we_i = '1') then
              wb_trig_iface_ch20_ctl_dir_int <= wrdata_reg(0);
              wb_trig_iface_ch20_ctl_dir_pol_int <= wrdata_reg(1);
              wb_trig_iface_ch20_ctl_rcv_count_rst_int <= wrdata_reg(2);
              wb_trig_iface_ch20_ctl_rcv_count_rst_int_delay <= wrdata_reg(2);
              wb_trig_iface_ch20_ctl_transm_count_rst_int <= wrdata_reg(3);
              wb_trig_iface_ch20_ctl_transm_count_rst_int_delay <= wrdata_reg(3);
            end if;
            rddata_reg(0) <= wb_trig_iface_ch20_ctl_dir_int;
            rddata_reg(1) <= wb_trig_iface_ch20_ctl_dir_pol_int;
            rddata_reg(2) <= '0';
            rddata_reg(3) <= '0';
            rddata_reg(4) <= 'X';
            rddata_reg(5) <= 'X';
            rddata_reg(6) <= 'X';
            rddata_reg(7) <= 'X';
            rddata_reg(8) <= 'X';
            rddata_reg(9) <= 'X';
            rddata_reg(10) <= 'X';
            rddata_reg(11) <= 'X';
            rddata_reg(12) <= 'X';
            rddata_reg(13) <= 'X';
            rddata_reg(14) <= 'X';
            rddata_reg(15) <= 'X';
            rddata_reg(16) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            rddata_reg(24) <= 'X';
            rddata_reg(25) <= 'X';
            rddata_reg(26) <= 'X';
            rddata_reg(27) <= 'X';
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(4) <= '1';
            ack_in_progress <= '1';
          when "0111101" => 
            if (wb_we_i = '1') then
              wb_trig_iface_ch20_cfg_rcv_len_int <= wrdata_reg(7 downto 0);
              wb_trig_iface_ch20_cfg_rcv_len_swb <= '1';
              wb_trig_iface_ch20_cfg_rcv_len_swb_delay <= '1';
              wb_trig_iface_ch20_cfg_transm_len_int <= wrdata_reg(15 downto 8);
              wb_trig_iface_ch20_cfg_transm_len_swb <= '1';
              wb_trig_iface_ch20_cfg_transm_len_swb_delay <= '1';
            end if;
            rddata_reg(7 downto 0) <= wb_trig_iface_ch20_cfg_rcv_len_int;
            rddata_reg(15 downto 8) <= wb_trig_iface_ch20_cfg_transm_len_int;
            rddata_reg(16) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            rddata_reg(24) <= 'X';
            rddata_reg(25) <= 'X';
            rddata_reg(26) <= 'X';
            rddata_reg(27) <= 'X';
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(3) <= '1';
            ack_in_progress <= '1';
          when "0111110" => 
            if (wb_we_i = '1') then
            end if;
            if (wb_we_i = '0') then
              wb_trig_iface_ch20_count_rcv_lwb <= '1';
              wb_trig_iface_ch20_count_rcv_lwb_delay <= '1';
              wb_trig_iface_ch20_count_rcv_lwb_in_progress <= '1';
            end if;
            if (wb_we_i = '0') then
              wb_trig_iface_ch20_count_transm_lwb <= '1';
              wb_trig_iface_ch20_count_transm_lwb_delay <= '1';
              wb_trig_iface_ch20_count_transm_lwb_in_progress <= '1';
            end if;
            ack_sreg(5) <= '1';
            ack_in_progress <= '1';
          when "0111111" => 
            if (wb_we_i = '1') then
              wb_trig_iface_ch21_ctl_dir_int <= wrdata_reg(0);
              wb_trig_iface_ch21_ctl_dir_pol_int <= wrdata_reg(1);
              wb_trig_iface_ch21_ctl_rcv_count_rst_int <= wrdata_reg(2);
              wb_trig_iface_ch21_ctl_rcv_count_rst_int_delay <= wrdata_reg(2);
              wb_trig_iface_ch21_ctl_transm_count_rst_int <= wrdata_reg(3);
              wb_trig_iface_ch21_ctl_transm_count_rst_int_delay <= wrdata_reg(3);
            end if;
            rddata_reg(0) <= wb_trig_iface_ch21_ctl_dir_int;
            rddata_reg(1) <= wb_trig_iface_ch21_ctl_dir_pol_int;
            rddata_reg(2) <= '0';
            rddata_reg(3) <= '0';
            rddata_reg(4) <= 'X';
            rddata_reg(5) <= 'X';
            rddata_reg(6) <= 'X';
            rddata_reg(7) <= 'X';
            rddata_reg(8) <= 'X';
            rddata_reg(9) <= 'X';
            rddata_reg(10) <= 'X';
            rddata_reg(11) <= 'X';
            rddata_reg(12) <= 'X';
            rddata_reg(13) <= 'X';
            rddata_reg(14) <= 'X';
            rddata_reg(15) <= 'X';
            rddata_reg(16) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            rddata_reg(24) <= 'X';
            rddata_reg(25) <= 'X';
            rddata_reg(26) <= 'X';
            rddata_reg(27) <= 'X';
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(4) <= '1';
            ack_in_progress <= '1';
          when "1000000" => 
            if (wb_we_i = '1') then
              wb_trig_iface_ch21_cfg_rcv_len_int <= wrdata_reg(7 downto 0);
              wb_trig_iface_ch21_cfg_rcv_len_swb <= '1';
              wb_trig_iface_ch21_cfg_rcv_len_swb_delay <= '1';
              wb_trig_iface_ch21_cfg_transm_len_int <= wrdata_reg(15 downto 8);
              wb_trig_iface_ch21_cfg_transm_len_swb <= '1';
              wb_trig_iface_ch21_cfg_transm_len_swb_delay <= '1';
            end if;
            rddata_reg(7 downto 0) <= wb_trig_iface_ch21_cfg_rcv_len_int;
            rddata_reg(15 downto 8) <= wb_trig_iface_ch21_cfg_transm_len_int;
            rddata_reg(16) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            rddata_reg(24) <= 'X';
            rddata_reg(25) <= 'X';
            rddata_reg(26) <= 'X';
            rddata_reg(27) <= 'X';
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(3) <= '1';
            ack_in_progress <= '1';
          when "1000001" => 
            if (wb_we_i = '1') then
            end if;
            if (wb_we_i = '0') then
              wb_trig_iface_ch21_count_rcv_lwb <= '1';
              wb_trig_iface_ch21_count_rcv_lwb_delay <= '1';
              wb_trig_iface_ch21_count_rcv_lwb_in_progress <= '1';
            end if;
            if (wb_we_i = '0') then
              wb_trig_iface_ch21_count_transm_lwb <= '1';
              wb_trig_iface_ch21_count_transm_lwb_delay <= '1';
              wb_trig_iface_ch21_count_transm_lwb_in_progress <= '1';
            end if;
            ack_sreg(5) <= '1';
            ack_in_progress <= '1';
          when "1000010" => 
            if (wb_we_i = '1') then
              wb_trig_iface_ch22_ctl_dir_int <= wrdata_reg(0);
              wb_trig_iface_ch22_ctl_dir_pol_int <= wrdata_reg(1);
              wb_trig_iface_ch22_ctl_rcv_count_rst_int <= wrdata_reg(2);
              wb_trig_iface_ch22_ctl_rcv_count_rst_int_delay <= wrdata_reg(2);
              wb_trig_iface_ch22_ctl_transm_count_rst_int <= wrdata_reg(3);
              wb_trig_iface_ch22_ctl_transm_count_rst_int_delay <= wrdata_reg(3);
            end if;
            rddata_reg(0) <= wb_trig_iface_ch22_ctl_dir_int;
            rddata_reg(1) <= wb_trig_iface_ch22_ctl_dir_pol_int;
            rddata_reg(2) <= '0';
            rddata_reg(3) <= '0';
            rddata_reg(4) <= 'X';
            rddata_reg(5) <= 'X';
            rddata_reg(6) <= 'X';
            rddata_reg(7) <= 'X';
            rddata_reg(8) <= 'X';
            rddata_reg(9) <= 'X';
            rddata_reg(10) <= 'X';
            rddata_reg(11) <= 'X';
            rddata_reg(12) <= 'X';
            rddata_reg(13) <= 'X';
            rddata_reg(14) <= 'X';
            rddata_reg(15) <= 'X';
            rddata_reg(16) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            rddata_reg(24) <= 'X';
            rddata_reg(25) <= 'X';
            rddata_reg(26) <= 'X';
            rddata_reg(27) <= 'X';
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(4) <= '1';
            ack_in_progress <= '1';
          when "1000011" => 
            if (wb_we_i = '1') then
              wb_trig_iface_ch22_cfg_rcv_len_int <= wrdata_reg(7 downto 0);
              wb_trig_iface_ch22_cfg_rcv_len_swb <= '1';
              wb_trig_iface_ch22_cfg_rcv_len_swb_delay <= '1';
              wb_trig_iface_ch22_cfg_transm_len_int <= wrdata_reg(15 downto 8);
              wb_trig_iface_ch22_cfg_transm_len_swb <= '1';
              wb_trig_iface_ch22_cfg_transm_len_swb_delay <= '1';
            end if;
            rddata_reg(7 downto 0) <= wb_trig_iface_ch22_cfg_rcv_len_int;
            rddata_reg(15 downto 8) <= wb_trig_iface_ch22_cfg_transm_len_int;
            rddata_reg(16) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            rddata_reg(24) <= 'X';
            rddata_reg(25) <= 'X';
            rddata_reg(26) <= 'X';
            rddata_reg(27) <= 'X';
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(3) <= '1';
            ack_in_progress <= '1';
          when "1000100" => 
            if (wb_we_i = '1') then
            end if;
            if (wb_we_i = '0') then
              wb_trig_iface_ch22_count_rcv_lwb <= '1';
              wb_trig_iface_ch22_count_rcv_lwb_delay <= '1';
              wb_trig_iface_ch22_count_rcv_lwb_in_progress <= '1';
            end if;
            if (wb_we_i = '0') then
              wb_trig_iface_ch22_count_transm_lwb <= '1';
              wb_trig_iface_ch22_count_transm_lwb_delay <= '1';
              wb_trig_iface_ch22_count_transm_lwb_in_progress <= '1';
            end if;
            ack_sreg(5) <= '1';
            ack_in_progress <= '1';
          when "1000101" => 
            if (wb_we_i = '1') then
              wb_trig_iface_ch23_ctl_dir_int <= wrdata_reg(0);
              wb_trig_iface_ch23_ctl_dir_pol_int <= wrdata_reg(1);
              wb_trig_iface_ch23_ctl_rcv_count_rst_int <= wrdata_reg(2);
              wb_trig_iface_ch23_ctl_rcv_count_rst_int_delay <= wrdata_reg(2);
              wb_trig_iface_ch23_ctl_transm_count_rst_int <= wrdata_reg(3);
              wb_trig_iface_ch23_ctl_transm_count_rst_int_delay <= wrdata_reg(3);
            end if;
            rddata_reg(0) <= wb_trig_iface_ch23_ctl_dir_int;
            rddata_reg(1) <= wb_trig_iface_ch23_ctl_dir_pol_int;
            rddata_reg(2) <= '0';
            rddata_reg(3) <= '0';
            rddata_reg(4) <= 'X';
            rddata_reg(5) <= 'X';
            rddata_reg(6) <= 'X';
            rddata_reg(7) <= 'X';
            rddata_reg(8) <= 'X';
            rddata_reg(9) <= 'X';
            rddata_reg(10) <= 'X';
            rddata_reg(11) <= 'X';
            rddata_reg(12) <= 'X';
            rddata_reg(13) <= 'X';
            rddata_reg(14) <= 'X';
            rddata_reg(15) <= 'X';
            rddata_reg(16) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            rddata_reg(24) <= 'X';
            rddata_reg(25) <= 'X';
            rddata_reg(26) <= 'X';
            rddata_reg(27) <= 'X';
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(4) <= '1';
            ack_in_progress <= '1';
          when "1000110" => 
            if (wb_we_i = '1') then
              wb_trig_iface_ch23_cfg_rcv_len_int <= wrdata_reg(7 downto 0);
              wb_trig_iface_ch23_cfg_rcv_len_swb <= '1';
              wb_trig_iface_ch23_cfg_rcv_len_swb_delay <= '1';
              wb_trig_iface_ch23_cfg_transm_len_int <= wrdata_reg(15 downto 8);
              wb_trig_iface_ch23_cfg_transm_len_swb <= '1';
              wb_trig_iface_ch23_cfg_transm_len_swb_delay <= '1';
            end if;
            rddata_reg(7 downto 0) <= wb_trig_iface_ch23_cfg_rcv_len_int;
            rddata_reg(15 downto 8) <= wb_trig_iface_ch23_cfg_transm_len_int;
            rddata_reg(16) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            rddata_reg(24) <= 'X';
            rddata_reg(25) <= 'X';
            rddata_reg(26) <= 'X';
            rddata_reg(27) <= 'X';
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(3) <= '1';
            ack_in_progress <= '1';
          when "1000111" => 
            if (wb_we_i = '1') then
            end if;
            if (wb_we_i = '0') then
              wb_trig_iface_ch23_count_rcv_lwb <= '1';
              wb_trig_iface_ch23_count_rcv_lwb_delay <= '1';
              wb_trig_iface_ch23_count_rcv_lwb_in_progress <= '1';
            end if;
            if (wb_we_i = '0') then
              wb_trig_iface_ch23_count_transm_lwb <= '1';
              wb_trig_iface_ch23_count_transm_lwb_delay <= '1';
              wb_trig_iface_ch23_count_transm_lwb_in_progress <= '1';
            end if;
            ack_sreg(5) <= '1';
            ack_in_progress <= '1';
          when others =>
-- prevent the slave from hanging the bus on invalid address
            ack_in_progress <= '1';
            ack_sreg(0) <= '1';
          end case;
        end if;
      end if;
    end if;
  end process;
  
  
-- Drive the data output bus
  wb_dat_o <= rddata_reg;
-- Trigger Direction
  regs_o.ch0_ctl_dir_o <= wb_trig_iface_ch0_ctl_dir_int;
-- Trigger Direction Polarity
  regs_o.ch0_ctl_dir_pol_o <= wb_trig_iface_ch0_ctl_dir_pol_int;
-- Receiver Pulse Counter Reset
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      regs_o.ch0_ctl_rcv_count_rst_o <= '0';
      wb_trig_iface_ch0_ctl_rcv_count_rst_sync0 <= '0';
      wb_trig_iface_ch0_ctl_rcv_count_rst_sync1 <= '0';
      wb_trig_iface_ch0_ctl_rcv_count_rst_sync2 <= '0';
    elsif rising_edge(fs_clk_i) then
      wb_trig_iface_ch0_ctl_rcv_count_rst_sync0 <= wb_trig_iface_ch0_ctl_rcv_count_rst_int;
      wb_trig_iface_ch0_ctl_rcv_count_rst_sync1 <= wb_trig_iface_ch0_ctl_rcv_count_rst_sync0;
      wb_trig_iface_ch0_ctl_rcv_count_rst_sync2 <= wb_trig_iface_ch0_ctl_rcv_count_rst_sync1;
      regs_o.ch0_ctl_rcv_count_rst_o <= wb_trig_iface_ch0_ctl_rcv_count_rst_sync2 and (not wb_trig_iface_ch0_ctl_rcv_count_rst_sync1);
    end if;
  end process;
  
  
-- Transmitter Pulse Counter Reset
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      regs_o.ch0_ctl_transm_count_rst_o <= '0';
      wb_trig_iface_ch0_ctl_transm_count_rst_sync0 <= '0';
      wb_trig_iface_ch0_ctl_transm_count_rst_sync1 <= '0';
      wb_trig_iface_ch0_ctl_transm_count_rst_sync2 <= '0';
    elsif rising_edge(fs_clk_i) then
      wb_trig_iface_ch0_ctl_transm_count_rst_sync0 <= wb_trig_iface_ch0_ctl_transm_count_rst_int;
      wb_trig_iface_ch0_ctl_transm_count_rst_sync1 <= wb_trig_iface_ch0_ctl_transm_count_rst_sync0;
      wb_trig_iface_ch0_ctl_transm_count_rst_sync2 <= wb_trig_iface_ch0_ctl_transm_count_rst_sync1;
      regs_o.ch0_ctl_transm_count_rst_o <= wb_trig_iface_ch0_ctl_transm_count_rst_sync2 and (not wb_trig_iface_ch0_ctl_transm_count_rst_sync1);
    end if;
  end process;
  
  
-- Receiver Pulse Length
-- asynchronous std_logic_vector register : Receiver Pulse Length (type RW/RO, fs_clk_i <-> clk_sys_i)
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_trig_iface_ch0_cfg_rcv_len_swb_s0 <= '0';
      wb_trig_iface_ch0_cfg_rcv_len_swb_s1 <= '0';
      wb_trig_iface_ch0_cfg_rcv_len_swb_s2 <= '0';
      regs_o.ch0_cfg_rcv_len_o <= "00000000";
    elsif rising_edge(fs_clk_i) then
      wb_trig_iface_ch0_cfg_rcv_len_swb_s0 <= wb_trig_iface_ch0_cfg_rcv_len_swb;
      wb_trig_iface_ch0_cfg_rcv_len_swb_s1 <= wb_trig_iface_ch0_cfg_rcv_len_swb_s0;
      wb_trig_iface_ch0_cfg_rcv_len_swb_s2 <= wb_trig_iface_ch0_cfg_rcv_len_swb_s1;
      if ((wb_trig_iface_ch0_cfg_rcv_len_swb_s2 = '0') and (wb_trig_iface_ch0_cfg_rcv_len_swb_s1 = '1')) then
        regs_o.ch0_cfg_rcv_len_o <= wb_trig_iface_ch0_cfg_rcv_len_int;
      end if;
    end if;
  end process;
  
  
-- Transmitter Pulse Length
-- asynchronous std_logic_vector register : Transmitter Pulse Length (type RW/RO, fs_clk_i <-> clk_sys_i)
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_trig_iface_ch0_cfg_transm_len_swb_s0 <= '0';
      wb_trig_iface_ch0_cfg_transm_len_swb_s1 <= '0';
      wb_trig_iface_ch0_cfg_transm_len_swb_s2 <= '0';
      regs_o.ch0_cfg_transm_len_o <= "00000000";
    elsif rising_edge(fs_clk_i) then
      wb_trig_iface_ch0_cfg_transm_len_swb_s0 <= wb_trig_iface_ch0_cfg_transm_len_swb;
      wb_trig_iface_ch0_cfg_transm_len_swb_s1 <= wb_trig_iface_ch0_cfg_transm_len_swb_s0;
      wb_trig_iface_ch0_cfg_transm_len_swb_s2 <= wb_trig_iface_ch0_cfg_transm_len_swb_s1;
      if ((wb_trig_iface_ch0_cfg_transm_len_swb_s2 = '0') and (wb_trig_iface_ch0_cfg_transm_len_swb_s1 = '1')) then
        regs_o.ch0_cfg_transm_len_o <= wb_trig_iface_ch0_cfg_transm_len_int;
      end if;
    end if;
  end process;
  
  
-- Receiver Counter
-- asynchronous std_logic_vector register : Receiver Counter (type RO/WO, wb_clk_i <-> clk_sys_i)
  process (wb_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_trig_iface_ch0_count_rcv_lwb_s0 <= '0';
      wb_trig_iface_ch0_count_rcv_lwb_s1 <= '0';
      wb_trig_iface_ch0_count_rcv_lwb_s2 <= '0';
      wb_trig_iface_ch0_count_rcv_int <= "0000000000000000";
    elsif rising_edge(wb_clk_i) then
      wb_trig_iface_ch0_count_rcv_lwb_s0 <= wb_trig_iface_ch0_count_rcv_lwb;
      wb_trig_iface_ch0_count_rcv_lwb_s1 <= wb_trig_iface_ch0_count_rcv_lwb_s0;
      wb_trig_iface_ch0_count_rcv_lwb_s2 <= wb_trig_iface_ch0_count_rcv_lwb_s1;
      if ((wb_trig_iface_ch0_count_rcv_lwb_s1 = '1') and (wb_trig_iface_ch0_count_rcv_lwb_s2 = '0')) then
        wb_trig_iface_ch0_count_rcv_int <= regs_i.ch0_count_rcv_i;
      end if;
    end if;
  end process;
  
  
-- Transmitter Counter
-- asynchronous std_logic_vector register : Transmitter Counter (type RO/WO, wb_clk_i <-> clk_sys_i)
  process (wb_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_trig_iface_ch0_count_transm_lwb_s0 <= '0';
      wb_trig_iface_ch0_count_transm_lwb_s1 <= '0';
      wb_trig_iface_ch0_count_transm_lwb_s2 <= '0';
      wb_trig_iface_ch0_count_transm_int <= "0000000000000000";
    elsif rising_edge(wb_clk_i) then
      wb_trig_iface_ch0_count_transm_lwb_s0 <= wb_trig_iface_ch0_count_transm_lwb;
      wb_trig_iface_ch0_count_transm_lwb_s1 <= wb_trig_iface_ch0_count_transm_lwb_s0;
      wb_trig_iface_ch0_count_transm_lwb_s2 <= wb_trig_iface_ch0_count_transm_lwb_s1;
      if ((wb_trig_iface_ch0_count_transm_lwb_s1 = '1') and (wb_trig_iface_ch0_count_transm_lwb_s2 = '0')) then
        wb_trig_iface_ch0_count_transm_int <= regs_i.ch0_count_transm_i;
      end if;
    end if;
  end process;
  
  
-- Trigger Direction
  regs_o.ch1_ctl_dir_o <= wb_trig_iface_ch1_ctl_dir_int;
-- Trigger Direction Polarity
  regs_o.ch1_ctl_dir_pol_o <= wb_trig_iface_ch1_ctl_dir_pol_int;
-- Receiver Pulse Counter Reset
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      regs_o.ch1_ctl_rcv_count_rst_o <= '0';
      wb_trig_iface_ch1_ctl_rcv_count_rst_sync0 <= '0';
      wb_trig_iface_ch1_ctl_rcv_count_rst_sync1 <= '0';
      wb_trig_iface_ch1_ctl_rcv_count_rst_sync2 <= '0';
    elsif rising_edge(fs_clk_i) then
      wb_trig_iface_ch1_ctl_rcv_count_rst_sync0 <= wb_trig_iface_ch1_ctl_rcv_count_rst_int;
      wb_trig_iface_ch1_ctl_rcv_count_rst_sync1 <= wb_trig_iface_ch1_ctl_rcv_count_rst_sync0;
      wb_trig_iface_ch1_ctl_rcv_count_rst_sync2 <= wb_trig_iface_ch1_ctl_rcv_count_rst_sync1;
      regs_o.ch1_ctl_rcv_count_rst_o <= wb_trig_iface_ch1_ctl_rcv_count_rst_sync2 and (not wb_trig_iface_ch1_ctl_rcv_count_rst_sync1);
    end if;
  end process;
  
  
-- Transmitter Pulse Counter Reset
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      regs_o.ch1_ctl_transm_count_rst_o <= '0';
      wb_trig_iface_ch1_ctl_transm_count_rst_sync0 <= '0';
      wb_trig_iface_ch1_ctl_transm_count_rst_sync1 <= '0';
      wb_trig_iface_ch1_ctl_transm_count_rst_sync2 <= '0';
    elsif rising_edge(fs_clk_i) then
      wb_trig_iface_ch1_ctl_transm_count_rst_sync0 <= wb_trig_iface_ch1_ctl_transm_count_rst_int;
      wb_trig_iface_ch1_ctl_transm_count_rst_sync1 <= wb_trig_iface_ch1_ctl_transm_count_rst_sync0;
      wb_trig_iface_ch1_ctl_transm_count_rst_sync2 <= wb_trig_iface_ch1_ctl_transm_count_rst_sync1;
      regs_o.ch1_ctl_transm_count_rst_o <= wb_trig_iface_ch1_ctl_transm_count_rst_sync2 and (not wb_trig_iface_ch1_ctl_transm_count_rst_sync1);
    end if;
  end process;
  
  
-- Receiver Pulse Length
-- asynchronous std_logic_vector register : Receiver Pulse Length (type RW/RO, fs_clk_i <-> clk_sys_i)
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_trig_iface_ch1_cfg_rcv_len_swb_s0 <= '0';
      wb_trig_iface_ch1_cfg_rcv_len_swb_s1 <= '0';
      wb_trig_iface_ch1_cfg_rcv_len_swb_s2 <= '0';
      regs_o.ch1_cfg_rcv_len_o <= "00000000";
    elsif rising_edge(fs_clk_i) then
      wb_trig_iface_ch1_cfg_rcv_len_swb_s0 <= wb_trig_iface_ch1_cfg_rcv_len_swb;
      wb_trig_iface_ch1_cfg_rcv_len_swb_s1 <= wb_trig_iface_ch1_cfg_rcv_len_swb_s0;
      wb_trig_iface_ch1_cfg_rcv_len_swb_s2 <= wb_trig_iface_ch1_cfg_rcv_len_swb_s1;
      if ((wb_trig_iface_ch1_cfg_rcv_len_swb_s2 = '0') and (wb_trig_iface_ch1_cfg_rcv_len_swb_s1 = '1')) then
        regs_o.ch1_cfg_rcv_len_o <= wb_trig_iface_ch1_cfg_rcv_len_int;
      end if;
    end if;
  end process;
  
  
-- Transmitter Pulse Length
-- asynchronous std_logic_vector register : Transmitter Pulse Length (type RW/RO, fs_clk_i <-> clk_sys_i)
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_trig_iface_ch1_cfg_transm_len_swb_s0 <= '0';
      wb_trig_iface_ch1_cfg_transm_len_swb_s1 <= '0';
      wb_trig_iface_ch1_cfg_transm_len_swb_s2 <= '0';
      regs_o.ch1_cfg_transm_len_o <= "00000000";
    elsif rising_edge(fs_clk_i) then
      wb_trig_iface_ch1_cfg_transm_len_swb_s0 <= wb_trig_iface_ch1_cfg_transm_len_swb;
      wb_trig_iface_ch1_cfg_transm_len_swb_s1 <= wb_trig_iface_ch1_cfg_transm_len_swb_s0;
      wb_trig_iface_ch1_cfg_transm_len_swb_s2 <= wb_trig_iface_ch1_cfg_transm_len_swb_s1;
      if ((wb_trig_iface_ch1_cfg_transm_len_swb_s2 = '0') and (wb_trig_iface_ch1_cfg_transm_len_swb_s1 = '1')) then
        regs_o.ch1_cfg_transm_len_o <= wb_trig_iface_ch1_cfg_transm_len_int;
      end if;
    end if;
  end process;
  
  
-- Receiver Counter
-- asynchronous std_logic_vector register : Receiver Counter (type RO/WO, wb_clk_i <-> clk_sys_i)
  process (wb_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_trig_iface_ch1_count_rcv_lwb_s0 <= '0';
      wb_trig_iface_ch1_count_rcv_lwb_s1 <= '0';
      wb_trig_iface_ch1_count_rcv_lwb_s2 <= '0';
      wb_trig_iface_ch1_count_rcv_int <= "0000000000000000";
    elsif rising_edge(wb_clk_i) then
      wb_trig_iface_ch1_count_rcv_lwb_s0 <= wb_trig_iface_ch1_count_rcv_lwb;
      wb_trig_iface_ch1_count_rcv_lwb_s1 <= wb_trig_iface_ch1_count_rcv_lwb_s0;
      wb_trig_iface_ch1_count_rcv_lwb_s2 <= wb_trig_iface_ch1_count_rcv_lwb_s1;
      if ((wb_trig_iface_ch1_count_rcv_lwb_s1 = '1') and (wb_trig_iface_ch1_count_rcv_lwb_s2 = '0')) then
        wb_trig_iface_ch1_count_rcv_int <= regs_i.ch1_count_rcv_i;
      end if;
    end if;
  end process;
  
  
-- Transmitter Counter
-- asynchronous std_logic_vector register : Transmitter Counter (type RO/WO, wb_clk_i <-> clk_sys_i)
  process (wb_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_trig_iface_ch1_count_transm_lwb_s0 <= '0';
      wb_trig_iface_ch1_count_transm_lwb_s1 <= '0';
      wb_trig_iface_ch1_count_transm_lwb_s2 <= '0';
      wb_trig_iface_ch1_count_transm_int <= "0000000000000000";
    elsif rising_edge(wb_clk_i) then
      wb_trig_iface_ch1_count_transm_lwb_s0 <= wb_trig_iface_ch1_count_transm_lwb;
      wb_trig_iface_ch1_count_transm_lwb_s1 <= wb_trig_iface_ch1_count_transm_lwb_s0;
      wb_trig_iface_ch1_count_transm_lwb_s2 <= wb_trig_iface_ch1_count_transm_lwb_s1;
      if ((wb_trig_iface_ch1_count_transm_lwb_s1 = '1') and (wb_trig_iface_ch1_count_transm_lwb_s2 = '0')) then
        wb_trig_iface_ch1_count_transm_int <= regs_i.ch1_count_transm_i;
      end if;
    end if;
  end process;
  
  
-- Trigger Direction
  regs_o.ch2_ctl_dir_o <= wb_trig_iface_ch2_ctl_dir_int;
-- Trigger Direction Polarity
  regs_o.ch2_ctl_dir_pol_o <= wb_trig_iface_ch2_ctl_dir_pol_int;
-- Receiver Pulse Counter Reset
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      regs_o.ch2_ctl_rcv_count_rst_o <= '0';
      wb_trig_iface_ch2_ctl_rcv_count_rst_sync0 <= '0';
      wb_trig_iface_ch2_ctl_rcv_count_rst_sync1 <= '0';
      wb_trig_iface_ch2_ctl_rcv_count_rst_sync2 <= '0';
    elsif rising_edge(fs_clk_i) then
      wb_trig_iface_ch2_ctl_rcv_count_rst_sync0 <= wb_trig_iface_ch2_ctl_rcv_count_rst_int;
      wb_trig_iface_ch2_ctl_rcv_count_rst_sync1 <= wb_trig_iface_ch2_ctl_rcv_count_rst_sync0;
      wb_trig_iface_ch2_ctl_rcv_count_rst_sync2 <= wb_trig_iface_ch2_ctl_rcv_count_rst_sync1;
      regs_o.ch2_ctl_rcv_count_rst_o <= wb_trig_iface_ch2_ctl_rcv_count_rst_sync2 and (not wb_trig_iface_ch2_ctl_rcv_count_rst_sync1);
    end if;
  end process;
  
  
-- Transmitter Pulse Counter Reset
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      regs_o.ch2_ctl_transm_count_rst_o <= '0';
      wb_trig_iface_ch2_ctl_transm_count_rst_sync0 <= '0';
      wb_trig_iface_ch2_ctl_transm_count_rst_sync1 <= '0';
      wb_trig_iface_ch2_ctl_transm_count_rst_sync2 <= '0';
    elsif rising_edge(fs_clk_i) then
      wb_trig_iface_ch2_ctl_transm_count_rst_sync0 <= wb_trig_iface_ch2_ctl_transm_count_rst_int;
      wb_trig_iface_ch2_ctl_transm_count_rst_sync1 <= wb_trig_iface_ch2_ctl_transm_count_rst_sync0;
      wb_trig_iface_ch2_ctl_transm_count_rst_sync2 <= wb_trig_iface_ch2_ctl_transm_count_rst_sync1;
      regs_o.ch2_ctl_transm_count_rst_o <= wb_trig_iface_ch2_ctl_transm_count_rst_sync2 and (not wb_trig_iface_ch2_ctl_transm_count_rst_sync1);
    end if;
  end process;
  
  
-- Receiver Pulse Length
-- asynchronous std_logic_vector register : Receiver Pulse Length (type RW/RO, fs_clk_i <-> clk_sys_i)
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_trig_iface_ch2_cfg_rcv_len_swb_s0 <= '0';
      wb_trig_iface_ch2_cfg_rcv_len_swb_s1 <= '0';
      wb_trig_iface_ch2_cfg_rcv_len_swb_s2 <= '0';
      regs_o.ch2_cfg_rcv_len_o <= "00000000";
    elsif rising_edge(fs_clk_i) then
      wb_trig_iface_ch2_cfg_rcv_len_swb_s0 <= wb_trig_iface_ch2_cfg_rcv_len_swb;
      wb_trig_iface_ch2_cfg_rcv_len_swb_s1 <= wb_trig_iface_ch2_cfg_rcv_len_swb_s0;
      wb_trig_iface_ch2_cfg_rcv_len_swb_s2 <= wb_trig_iface_ch2_cfg_rcv_len_swb_s1;
      if ((wb_trig_iface_ch2_cfg_rcv_len_swb_s2 = '0') and (wb_trig_iface_ch2_cfg_rcv_len_swb_s1 = '1')) then
        regs_o.ch2_cfg_rcv_len_o <= wb_trig_iface_ch2_cfg_rcv_len_int;
      end if;
    end if;
  end process;
  
  
-- Transmitter Pulse Length
-- asynchronous std_logic_vector register : Transmitter Pulse Length (type RW/RO, fs_clk_i <-> clk_sys_i)
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_trig_iface_ch2_cfg_transm_len_swb_s0 <= '0';
      wb_trig_iface_ch2_cfg_transm_len_swb_s1 <= '0';
      wb_trig_iface_ch2_cfg_transm_len_swb_s2 <= '0';
      regs_o.ch2_cfg_transm_len_o <= "00000000";
    elsif rising_edge(fs_clk_i) then
      wb_trig_iface_ch2_cfg_transm_len_swb_s0 <= wb_trig_iface_ch2_cfg_transm_len_swb;
      wb_trig_iface_ch2_cfg_transm_len_swb_s1 <= wb_trig_iface_ch2_cfg_transm_len_swb_s0;
      wb_trig_iface_ch2_cfg_transm_len_swb_s2 <= wb_trig_iface_ch2_cfg_transm_len_swb_s1;
      if ((wb_trig_iface_ch2_cfg_transm_len_swb_s2 = '0') and (wb_trig_iface_ch2_cfg_transm_len_swb_s1 = '1')) then
        regs_o.ch2_cfg_transm_len_o <= wb_trig_iface_ch2_cfg_transm_len_int;
      end if;
    end if;
  end process;
  
  
-- Receiver Counter
-- asynchronous std_logic_vector register : Receiver Counter (type RO/WO, wb_clk_i <-> clk_sys_i)
  process (wb_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_trig_iface_ch2_count_rcv_lwb_s0 <= '0';
      wb_trig_iface_ch2_count_rcv_lwb_s1 <= '0';
      wb_trig_iface_ch2_count_rcv_lwb_s2 <= '0';
      wb_trig_iface_ch2_count_rcv_int <= "0000000000000000";
    elsif rising_edge(wb_clk_i) then
      wb_trig_iface_ch2_count_rcv_lwb_s0 <= wb_trig_iface_ch2_count_rcv_lwb;
      wb_trig_iface_ch2_count_rcv_lwb_s1 <= wb_trig_iface_ch2_count_rcv_lwb_s0;
      wb_trig_iface_ch2_count_rcv_lwb_s2 <= wb_trig_iface_ch2_count_rcv_lwb_s1;
      if ((wb_trig_iface_ch2_count_rcv_lwb_s1 = '1') and (wb_trig_iface_ch2_count_rcv_lwb_s2 = '0')) then
        wb_trig_iface_ch2_count_rcv_int <= regs_i.ch2_count_rcv_i;
      end if;
    end if;
  end process;
  
  
-- Transmitter Counter
-- asynchronous std_logic_vector register : Transmitter Counter (type RO/WO, wb_clk_i <-> clk_sys_i)
  process (wb_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_trig_iface_ch2_count_transm_lwb_s0 <= '0';
      wb_trig_iface_ch2_count_transm_lwb_s1 <= '0';
      wb_trig_iface_ch2_count_transm_lwb_s2 <= '0';
      wb_trig_iface_ch2_count_transm_int <= "0000000000000000";
    elsif rising_edge(wb_clk_i) then
      wb_trig_iface_ch2_count_transm_lwb_s0 <= wb_trig_iface_ch2_count_transm_lwb;
      wb_trig_iface_ch2_count_transm_lwb_s1 <= wb_trig_iface_ch2_count_transm_lwb_s0;
      wb_trig_iface_ch2_count_transm_lwb_s2 <= wb_trig_iface_ch2_count_transm_lwb_s1;
      if ((wb_trig_iface_ch2_count_transm_lwb_s1 = '1') and (wb_trig_iface_ch2_count_transm_lwb_s2 = '0')) then
        wb_trig_iface_ch2_count_transm_int <= regs_i.ch2_count_transm_i;
      end if;
    end if;
  end process;
  
  
-- Trigger Direction
  regs_o.ch3_ctl_dir_o <= wb_trig_iface_ch3_ctl_dir_int;
-- Trigger Direction Polarity
  regs_o.ch3_ctl_dir_pol_o <= wb_trig_iface_ch3_ctl_dir_pol_int;
-- Receiver Pulse Counter Reset
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      regs_o.ch3_ctl_rcv_count_rst_o <= '0';
      wb_trig_iface_ch3_ctl_rcv_count_rst_sync0 <= '0';
      wb_trig_iface_ch3_ctl_rcv_count_rst_sync1 <= '0';
      wb_trig_iface_ch3_ctl_rcv_count_rst_sync2 <= '0';
    elsif rising_edge(fs_clk_i) then
      wb_trig_iface_ch3_ctl_rcv_count_rst_sync0 <= wb_trig_iface_ch3_ctl_rcv_count_rst_int;
      wb_trig_iface_ch3_ctl_rcv_count_rst_sync1 <= wb_trig_iface_ch3_ctl_rcv_count_rst_sync0;
      wb_trig_iface_ch3_ctl_rcv_count_rst_sync2 <= wb_trig_iface_ch3_ctl_rcv_count_rst_sync1;
      regs_o.ch3_ctl_rcv_count_rst_o <= wb_trig_iface_ch3_ctl_rcv_count_rst_sync2 and (not wb_trig_iface_ch3_ctl_rcv_count_rst_sync1);
    end if;
  end process;
  
  
-- Transmitter Pulse Counter Reset
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      regs_o.ch3_ctl_transm_count_rst_o <= '0';
      wb_trig_iface_ch3_ctl_transm_count_rst_sync0 <= '0';
      wb_trig_iface_ch3_ctl_transm_count_rst_sync1 <= '0';
      wb_trig_iface_ch3_ctl_transm_count_rst_sync2 <= '0';
    elsif rising_edge(fs_clk_i) then
      wb_trig_iface_ch3_ctl_transm_count_rst_sync0 <= wb_trig_iface_ch3_ctl_transm_count_rst_int;
      wb_trig_iface_ch3_ctl_transm_count_rst_sync1 <= wb_trig_iface_ch3_ctl_transm_count_rst_sync0;
      wb_trig_iface_ch3_ctl_transm_count_rst_sync2 <= wb_trig_iface_ch3_ctl_transm_count_rst_sync1;
      regs_o.ch3_ctl_transm_count_rst_o <= wb_trig_iface_ch3_ctl_transm_count_rst_sync2 and (not wb_trig_iface_ch3_ctl_transm_count_rst_sync1);
    end if;
  end process;
  
  
-- Receiver Pulse Length
-- asynchronous std_logic_vector register : Receiver Pulse Length (type RW/RO, fs_clk_i <-> clk_sys_i)
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_trig_iface_ch3_cfg_rcv_len_swb_s0 <= '0';
      wb_trig_iface_ch3_cfg_rcv_len_swb_s1 <= '0';
      wb_trig_iface_ch3_cfg_rcv_len_swb_s2 <= '0';
      regs_o.ch3_cfg_rcv_len_o <= "00000000";
    elsif rising_edge(fs_clk_i) then
      wb_trig_iface_ch3_cfg_rcv_len_swb_s0 <= wb_trig_iface_ch3_cfg_rcv_len_swb;
      wb_trig_iface_ch3_cfg_rcv_len_swb_s1 <= wb_trig_iface_ch3_cfg_rcv_len_swb_s0;
      wb_trig_iface_ch3_cfg_rcv_len_swb_s2 <= wb_trig_iface_ch3_cfg_rcv_len_swb_s1;
      if ((wb_trig_iface_ch3_cfg_rcv_len_swb_s2 = '0') and (wb_trig_iface_ch3_cfg_rcv_len_swb_s1 = '1')) then
        regs_o.ch3_cfg_rcv_len_o <= wb_trig_iface_ch3_cfg_rcv_len_int;
      end if;
    end if;
  end process;
  
  
-- Transmitter Pulse Length
-- asynchronous std_logic_vector register : Transmitter Pulse Length (type RW/RO, fs_clk_i <-> clk_sys_i)
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_trig_iface_ch3_cfg_transm_len_swb_s0 <= '0';
      wb_trig_iface_ch3_cfg_transm_len_swb_s1 <= '0';
      wb_trig_iface_ch3_cfg_transm_len_swb_s2 <= '0';
      regs_o.ch3_cfg_transm_len_o <= "00000000";
    elsif rising_edge(fs_clk_i) then
      wb_trig_iface_ch3_cfg_transm_len_swb_s0 <= wb_trig_iface_ch3_cfg_transm_len_swb;
      wb_trig_iface_ch3_cfg_transm_len_swb_s1 <= wb_trig_iface_ch3_cfg_transm_len_swb_s0;
      wb_trig_iface_ch3_cfg_transm_len_swb_s2 <= wb_trig_iface_ch3_cfg_transm_len_swb_s1;
      if ((wb_trig_iface_ch3_cfg_transm_len_swb_s2 = '0') and (wb_trig_iface_ch3_cfg_transm_len_swb_s1 = '1')) then
        regs_o.ch3_cfg_transm_len_o <= wb_trig_iface_ch3_cfg_transm_len_int;
      end if;
    end if;
  end process;
  
  
-- Receiver Counter
-- asynchronous std_logic_vector register : Receiver Counter (type RO/WO, wb_clk_i <-> clk_sys_i)
  process (wb_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_trig_iface_ch3_count_rcv_lwb_s0 <= '0';
      wb_trig_iface_ch3_count_rcv_lwb_s1 <= '0';
      wb_trig_iface_ch3_count_rcv_lwb_s2 <= '0';
      wb_trig_iface_ch3_count_rcv_int <= "0000000000000000";
    elsif rising_edge(wb_clk_i) then
      wb_trig_iface_ch3_count_rcv_lwb_s0 <= wb_trig_iface_ch3_count_rcv_lwb;
      wb_trig_iface_ch3_count_rcv_lwb_s1 <= wb_trig_iface_ch3_count_rcv_lwb_s0;
      wb_trig_iface_ch3_count_rcv_lwb_s2 <= wb_trig_iface_ch3_count_rcv_lwb_s1;
      if ((wb_trig_iface_ch3_count_rcv_lwb_s1 = '1') and (wb_trig_iface_ch3_count_rcv_lwb_s2 = '0')) then
        wb_trig_iface_ch3_count_rcv_int <= regs_i.ch3_count_rcv_i;
      end if;
    end if;
  end process;
  
  
-- Transmitter Counter
-- asynchronous std_logic_vector register : Transmitter Counter (type RO/WO, wb_clk_i <-> clk_sys_i)
  process (wb_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_trig_iface_ch3_count_transm_lwb_s0 <= '0';
      wb_trig_iface_ch3_count_transm_lwb_s1 <= '0';
      wb_trig_iface_ch3_count_transm_lwb_s2 <= '0';
      wb_trig_iface_ch3_count_transm_int <= "0000000000000000";
    elsif rising_edge(wb_clk_i) then
      wb_trig_iface_ch3_count_transm_lwb_s0 <= wb_trig_iface_ch3_count_transm_lwb;
      wb_trig_iface_ch3_count_transm_lwb_s1 <= wb_trig_iface_ch3_count_transm_lwb_s0;
      wb_trig_iface_ch3_count_transm_lwb_s2 <= wb_trig_iface_ch3_count_transm_lwb_s1;
      if ((wb_trig_iface_ch3_count_transm_lwb_s1 = '1') and (wb_trig_iface_ch3_count_transm_lwb_s2 = '0')) then
        wb_trig_iface_ch3_count_transm_int <= regs_i.ch3_count_transm_i;
      end if;
    end if;
  end process;
  
  
-- Trigger Direction
  regs_o.ch4_ctl_dir_o <= wb_trig_iface_ch4_ctl_dir_int;
-- Trigger Direction Polarity
  regs_o.ch4_ctl_dir_pol_o <= wb_trig_iface_ch4_ctl_dir_pol_int;
-- Receiver Pulse Counter Reset
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      regs_o.ch4_ctl_rcv_count_rst_o <= '0';
      wb_trig_iface_ch4_ctl_rcv_count_rst_sync0 <= '0';
      wb_trig_iface_ch4_ctl_rcv_count_rst_sync1 <= '0';
      wb_trig_iface_ch4_ctl_rcv_count_rst_sync2 <= '0';
    elsif rising_edge(fs_clk_i) then
      wb_trig_iface_ch4_ctl_rcv_count_rst_sync0 <= wb_trig_iface_ch4_ctl_rcv_count_rst_int;
      wb_trig_iface_ch4_ctl_rcv_count_rst_sync1 <= wb_trig_iface_ch4_ctl_rcv_count_rst_sync0;
      wb_trig_iface_ch4_ctl_rcv_count_rst_sync2 <= wb_trig_iface_ch4_ctl_rcv_count_rst_sync1;
      regs_o.ch4_ctl_rcv_count_rst_o <= wb_trig_iface_ch4_ctl_rcv_count_rst_sync2 and (not wb_trig_iface_ch4_ctl_rcv_count_rst_sync1);
    end if;
  end process;
  
  
-- Transmitter Pulse Counter Reset
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      regs_o.ch4_ctl_transm_count_rst_o <= '0';
      wb_trig_iface_ch4_ctl_transm_count_rst_sync0 <= '0';
      wb_trig_iface_ch4_ctl_transm_count_rst_sync1 <= '0';
      wb_trig_iface_ch4_ctl_transm_count_rst_sync2 <= '0';
    elsif rising_edge(fs_clk_i) then
      wb_trig_iface_ch4_ctl_transm_count_rst_sync0 <= wb_trig_iface_ch4_ctl_transm_count_rst_int;
      wb_trig_iface_ch4_ctl_transm_count_rst_sync1 <= wb_trig_iface_ch4_ctl_transm_count_rst_sync0;
      wb_trig_iface_ch4_ctl_transm_count_rst_sync2 <= wb_trig_iface_ch4_ctl_transm_count_rst_sync1;
      regs_o.ch4_ctl_transm_count_rst_o <= wb_trig_iface_ch4_ctl_transm_count_rst_sync2 and (not wb_trig_iface_ch4_ctl_transm_count_rst_sync1);
    end if;
  end process;
  
  
-- Receiver Pulse Length
-- asynchronous std_logic_vector register : Receiver Pulse Length (type RW/RO, fs_clk_i <-> clk_sys_i)
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_trig_iface_ch4_cfg_rcv_len_swb_s0 <= '0';
      wb_trig_iface_ch4_cfg_rcv_len_swb_s1 <= '0';
      wb_trig_iface_ch4_cfg_rcv_len_swb_s2 <= '0';
      regs_o.ch4_cfg_rcv_len_o <= "00000000";
    elsif rising_edge(fs_clk_i) then
      wb_trig_iface_ch4_cfg_rcv_len_swb_s0 <= wb_trig_iface_ch4_cfg_rcv_len_swb;
      wb_trig_iface_ch4_cfg_rcv_len_swb_s1 <= wb_trig_iface_ch4_cfg_rcv_len_swb_s0;
      wb_trig_iface_ch4_cfg_rcv_len_swb_s2 <= wb_trig_iface_ch4_cfg_rcv_len_swb_s1;
      if ((wb_trig_iface_ch4_cfg_rcv_len_swb_s2 = '0') and (wb_trig_iface_ch4_cfg_rcv_len_swb_s1 = '1')) then
        regs_o.ch4_cfg_rcv_len_o <= wb_trig_iface_ch4_cfg_rcv_len_int;
      end if;
    end if;
  end process;
  
  
-- Transmitter Pulse Length
-- asynchronous std_logic_vector register : Transmitter Pulse Length (type RW/RO, fs_clk_i <-> clk_sys_i)
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_trig_iface_ch4_cfg_transm_len_swb_s0 <= '0';
      wb_trig_iface_ch4_cfg_transm_len_swb_s1 <= '0';
      wb_trig_iface_ch4_cfg_transm_len_swb_s2 <= '0';
      regs_o.ch4_cfg_transm_len_o <= "00000000";
    elsif rising_edge(fs_clk_i) then
      wb_trig_iface_ch4_cfg_transm_len_swb_s0 <= wb_trig_iface_ch4_cfg_transm_len_swb;
      wb_trig_iface_ch4_cfg_transm_len_swb_s1 <= wb_trig_iface_ch4_cfg_transm_len_swb_s0;
      wb_trig_iface_ch4_cfg_transm_len_swb_s2 <= wb_trig_iface_ch4_cfg_transm_len_swb_s1;
      if ((wb_trig_iface_ch4_cfg_transm_len_swb_s2 = '0') and (wb_trig_iface_ch4_cfg_transm_len_swb_s1 = '1')) then
        regs_o.ch4_cfg_transm_len_o <= wb_trig_iface_ch4_cfg_transm_len_int;
      end if;
    end if;
  end process;
  
  
-- Receiver Counter
-- asynchronous std_logic_vector register : Receiver Counter (type RO/WO, wb_clk_i <-> clk_sys_i)
  process (wb_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_trig_iface_ch4_count_rcv_lwb_s0 <= '0';
      wb_trig_iface_ch4_count_rcv_lwb_s1 <= '0';
      wb_trig_iface_ch4_count_rcv_lwb_s2 <= '0';
      wb_trig_iface_ch4_count_rcv_int <= "0000000000000000";
    elsif rising_edge(wb_clk_i) then
      wb_trig_iface_ch4_count_rcv_lwb_s0 <= wb_trig_iface_ch4_count_rcv_lwb;
      wb_trig_iface_ch4_count_rcv_lwb_s1 <= wb_trig_iface_ch4_count_rcv_lwb_s0;
      wb_trig_iface_ch4_count_rcv_lwb_s2 <= wb_trig_iface_ch4_count_rcv_lwb_s1;
      if ((wb_trig_iface_ch4_count_rcv_lwb_s1 = '1') and (wb_trig_iface_ch4_count_rcv_lwb_s2 = '0')) then
        wb_trig_iface_ch4_count_rcv_int <= regs_i.ch4_count_rcv_i;
      end if;
    end if;
  end process;
  
  
-- Transmitter Counter
-- asynchronous std_logic_vector register : Transmitter Counter (type RO/WO, wb_clk_i <-> clk_sys_i)
  process (wb_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_trig_iface_ch4_count_transm_lwb_s0 <= '0';
      wb_trig_iface_ch4_count_transm_lwb_s1 <= '0';
      wb_trig_iface_ch4_count_transm_lwb_s2 <= '0';
      wb_trig_iface_ch4_count_transm_int <= "0000000000000000";
    elsif rising_edge(wb_clk_i) then
      wb_trig_iface_ch4_count_transm_lwb_s0 <= wb_trig_iface_ch4_count_transm_lwb;
      wb_trig_iface_ch4_count_transm_lwb_s1 <= wb_trig_iface_ch4_count_transm_lwb_s0;
      wb_trig_iface_ch4_count_transm_lwb_s2 <= wb_trig_iface_ch4_count_transm_lwb_s1;
      if ((wb_trig_iface_ch4_count_transm_lwb_s1 = '1') and (wb_trig_iface_ch4_count_transm_lwb_s2 = '0')) then
        wb_trig_iface_ch4_count_transm_int <= regs_i.ch4_count_transm_i;
      end if;
    end if;
  end process;
  
  
-- Trigger Direction
  regs_o.ch5_ctl_dir_o <= wb_trig_iface_ch5_ctl_dir_int;
-- Trigger Direction Polarity
  regs_o.ch5_ctl_dir_pol_o <= wb_trig_iface_ch5_ctl_dir_pol_int;
-- Receiver Pulse Counter Reset
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      regs_o.ch5_ctl_rcv_count_rst_o <= '0';
      wb_trig_iface_ch5_ctl_rcv_count_rst_sync0 <= '0';
      wb_trig_iface_ch5_ctl_rcv_count_rst_sync1 <= '0';
      wb_trig_iface_ch5_ctl_rcv_count_rst_sync2 <= '0';
    elsif rising_edge(fs_clk_i) then
      wb_trig_iface_ch5_ctl_rcv_count_rst_sync0 <= wb_trig_iface_ch5_ctl_rcv_count_rst_int;
      wb_trig_iface_ch5_ctl_rcv_count_rst_sync1 <= wb_trig_iface_ch5_ctl_rcv_count_rst_sync0;
      wb_trig_iface_ch5_ctl_rcv_count_rst_sync2 <= wb_trig_iface_ch5_ctl_rcv_count_rst_sync1;
      regs_o.ch5_ctl_rcv_count_rst_o <= wb_trig_iface_ch5_ctl_rcv_count_rst_sync2 and (not wb_trig_iface_ch5_ctl_rcv_count_rst_sync1);
    end if;
  end process;
  
  
-- Transmitter Pulse Counter Reset
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      regs_o.ch5_ctl_transm_count_rst_o <= '0';
      wb_trig_iface_ch5_ctl_transm_count_rst_sync0 <= '0';
      wb_trig_iface_ch5_ctl_transm_count_rst_sync1 <= '0';
      wb_trig_iface_ch5_ctl_transm_count_rst_sync2 <= '0';
    elsif rising_edge(fs_clk_i) then
      wb_trig_iface_ch5_ctl_transm_count_rst_sync0 <= wb_trig_iface_ch5_ctl_transm_count_rst_int;
      wb_trig_iface_ch5_ctl_transm_count_rst_sync1 <= wb_trig_iface_ch5_ctl_transm_count_rst_sync0;
      wb_trig_iface_ch5_ctl_transm_count_rst_sync2 <= wb_trig_iface_ch5_ctl_transm_count_rst_sync1;
      regs_o.ch5_ctl_transm_count_rst_o <= wb_trig_iface_ch5_ctl_transm_count_rst_sync2 and (not wb_trig_iface_ch5_ctl_transm_count_rst_sync1);
    end if;
  end process;
  
  
-- Receiver Pulse Length
-- asynchronous std_logic_vector register : Receiver Pulse Length (type RW/RO, fs_clk_i <-> clk_sys_i)
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_trig_iface_ch5_cfg_rcv_len_swb_s0 <= '0';
      wb_trig_iface_ch5_cfg_rcv_len_swb_s1 <= '0';
      wb_trig_iface_ch5_cfg_rcv_len_swb_s2 <= '0';
      regs_o.ch5_cfg_rcv_len_o <= "00000000";
    elsif rising_edge(fs_clk_i) then
      wb_trig_iface_ch5_cfg_rcv_len_swb_s0 <= wb_trig_iface_ch5_cfg_rcv_len_swb;
      wb_trig_iface_ch5_cfg_rcv_len_swb_s1 <= wb_trig_iface_ch5_cfg_rcv_len_swb_s0;
      wb_trig_iface_ch5_cfg_rcv_len_swb_s2 <= wb_trig_iface_ch5_cfg_rcv_len_swb_s1;
      if ((wb_trig_iface_ch5_cfg_rcv_len_swb_s2 = '0') and (wb_trig_iface_ch5_cfg_rcv_len_swb_s1 = '1')) then
        regs_o.ch5_cfg_rcv_len_o <= wb_trig_iface_ch5_cfg_rcv_len_int;
      end if;
    end if;
  end process;
  
  
-- Transmitter Pulse Length
-- asynchronous std_logic_vector register : Transmitter Pulse Length (type RW/RO, fs_clk_i <-> clk_sys_i)
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_trig_iface_ch5_cfg_transm_len_swb_s0 <= '0';
      wb_trig_iface_ch5_cfg_transm_len_swb_s1 <= '0';
      wb_trig_iface_ch5_cfg_transm_len_swb_s2 <= '0';
      regs_o.ch5_cfg_transm_len_o <= "00000000";
    elsif rising_edge(fs_clk_i) then
      wb_trig_iface_ch5_cfg_transm_len_swb_s0 <= wb_trig_iface_ch5_cfg_transm_len_swb;
      wb_trig_iface_ch5_cfg_transm_len_swb_s1 <= wb_trig_iface_ch5_cfg_transm_len_swb_s0;
      wb_trig_iface_ch5_cfg_transm_len_swb_s2 <= wb_trig_iface_ch5_cfg_transm_len_swb_s1;
      if ((wb_trig_iface_ch5_cfg_transm_len_swb_s2 = '0') and (wb_trig_iface_ch5_cfg_transm_len_swb_s1 = '1')) then
        regs_o.ch5_cfg_transm_len_o <= wb_trig_iface_ch5_cfg_transm_len_int;
      end if;
    end if;
  end process;
  
  
-- Receiver Counter
-- asynchronous std_logic_vector register : Receiver Counter (type RO/WO, wb_clk_i <-> clk_sys_i)
  process (wb_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_trig_iface_ch5_count_rcv_lwb_s0 <= '0';
      wb_trig_iface_ch5_count_rcv_lwb_s1 <= '0';
      wb_trig_iface_ch5_count_rcv_lwb_s2 <= '0';
      wb_trig_iface_ch5_count_rcv_int <= "0000000000000000";
    elsif rising_edge(wb_clk_i) then
      wb_trig_iface_ch5_count_rcv_lwb_s0 <= wb_trig_iface_ch5_count_rcv_lwb;
      wb_trig_iface_ch5_count_rcv_lwb_s1 <= wb_trig_iface_ch5_count_rcv_lwb_s0;
      wb_trig_iface_ch5_count_rcv_lwb_s2 <= wb_trig_iface_ch5_count_rcv_lwb_s1;
      if ((wb_trig_iface_ch5_count_rcv_lwb_s1 = '1') and (wb_trig_iface_ch5_count_rcv_lwb_s2 = '0')) then
        wb_trig_iface_ch5_count_rcv_int <= regs_i.ch5_count_rcv_i;
      end if;
    end if;
  end process;
  
  
-- Transmitter Counter
-- asynchronous std_logic_vector register : Transmitter Counter (type RO/WO, wb_clk_i <-> clk_sys_i)
  process (wb_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_trig_iface_ch5_count_transm_lwb_s0 <= '0';
      wb_trig_iface_ch5_count_transm_lwb_s1 <= '0';
      wb_trig_iface_ch5_count_transm_lwb_s2 <= '0';
      wb_trig_iface_ch5_count_transm_int <= "0000000000000000";
    elsif rising_edge(wb_clk_i) then
      wb_trig_iface_ch5_count_transm_lwb_s0 <= wb_trig_iface_ch5_count_transm_lwb;
      wb_trig_iface_ch5_count_transm_lwb_s1 <= wb_trig_iface_ch5_count_transm_lwb_s0;
      wb_trig_iface_ch5_count_transm_lwb_s2 <= wb_trig_iface_ch5_count_transm_lwb_s1;
      if ((wb_trig_iface_ch5_count_transm_lwb_s1 = '1') and (wb_trig_iface_ch5_count_transm_lwb_s2 = '0')) then
        wb_trig_iface_ch5_count_transm_int <= regs_i.ch5_count_transm_i;
      end if;
    end if;
  end process;
  
  
-- Trigger Direction
  regs_o.ch6_ctl_dir_o <= wb_trig_iface_ch6_ctl_dir_int;
-- Trigger Direction Polarity
  regs_o.ch6_ctl_dir_pol_o <= wb_trig_iface_ch6_ctl_dir_pol_int;
-- Receiver Pulse Counter Reset
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      regs_o.ch6_ctl_rcv_count_rst_o <= '0';
      wb_trig_iface_ch6_ctl_rcv_count_rst_sync0 <= '0';
      wb_trig_iface_ch6_ctl_rcv_count_rst_sync1 <= '0';
      wb_trig_iface_ch6_ctl_rcv_count_rst_sync2 <= '0';
    elsif rising_edge(fs_clk_i) then
      wb_trig_iface_ch6_ctl_rcv_count_rst_sync0 <= wb_trig_iface_ch6_ctl_rcv_count_rst_int;
      wb_trig_iface_ch6_ctl_rcv_count_rst_sync1 <= wb_trig_iface_ch6_ctl_rcv_count_rst_sync0;
      wb_trig_iface_ch6_ctl_rcv_count_rst_sync2 <= wb_trig_iface_ch6_ctl_rcv_count_rst_sync1;
      regs_o.ch6_ctl_rcv_count_rst_o <= wb_trig_iface_ch6_ctl_rcv_count_rst_sync2 and (not wb_trig_iface_ch6_ctl_rcv_count_rst_sync1);
    end if;
  end process;
  
  
-- Transmitter Pulse Counter Reset
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      regs_o.ch6_ctl_transm_count_rst_o <= '0';
      wb_trig_iface_ch6_ctl_transm_count_rst_sync0 <= '0';
      wb_trig_iface_ch6_ctl_transm_count_rst_sync1 <= '0';
      wb_trig_iface_ch6_ctl_transm_count_rst_sync2 <= '0';
    elsif rising_edge(fs_clk_i) then
      wb_trig_iface_ch6_ctl_transm_count_rst_sync0 <= wb_trig_iface_ch6_ctl_transm_count_rst_int;
      wb_trig_iface_ch6_ctl_transm_count_rst_sync1 <= wb_trig_iface_ch6_ctl_transm_count_rst_sync0;
      wb_trig_iface_ch6_ctl_transm_count_rst_sync2 <= wb_trig_iface_ch6_ctl_transm_count_rst_sync1;
      regs_o.ch6_ctl_transm_count_rst_o <= wb_trig_iface_ch6_ctl_transm_count_rst_sync2 and (not wb_trig_iface_ch6_ctl_transm_count_rst_sync1);
    end if;
  end process;
  
  
-- Receiver Pulse Length
-- asynchronous std_logic_vector register : Receiver Pulse Length (type RW/RO, fs_clk_i <-> clk_sys_i)
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_trig_iface_ch6_cfg_rcv_len_swb_s0 <= '0';
      wb_trig_iface_ch6_cfg_rcv_len_swb_s1 <= '0';
      wb_trig_iface_ch6_cfg_rcv_len_swb_s2 <= '0';
      regs_o.ch6_cfg_rcv_len_o <= "00000000";
    elsif rising_edge(fs_clk_i) then
      wb_trig_iface_ch6_cfg_rcv_len_swb_s0 <= wb_trig_iface_ch6_cfg_rcv_len_swb;
      wb_trig_iface_ch6_cfg_rcv_len_swb_s1 <= wb_trig_iface_ch6_cfg_rcv_len_swb_s0;
      wb_trig_iface_ch6_cfg_rcv_len_swb_s2 <= wb_trig_iface_ch6_cfg_rcv_len_swb_s1;
      if ((wb_trig_iface_ch6_cfg_rcv_len_swb_s2 = '0') and (wb_trig_iface_ch6_cfg_rcv_len_swb_s1 = '1')) then
        regs_o.ch6_cfg_rcv_len_o <= wb_trig_iface_ch6_cfg_rcv_len_int;
      end if;
    end if;
  end process;
  
  
-- Transmitter Pulse Length
-- asynchronous std_logic_vector register : Transmitter Pulse Length (type RW/RO, fs_clk_i <-> clk_sys_i)
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_trig_iface_ch6_cfg_transm_len_swb_s0 <= '0';
      wb_trig_iface_ch6_cfg_transm_len_swb_s1 <= '0';
      wb_trig_iface_ch6_cfg_transm_len_swb_s2 <= '0';
      regs_o.ch6_cfg_transm_len_o <= "00000000";
    elsif rising_edge(fs_clk_i) then
      wb_trig_iface_ch6_cfg_transm_len_swb_s0 <= wb_trig_iface_ch6_cfg_transm_len_swb;
      wb_trig_iface_ch6_cfg_transm_len_swb_s1 <= wb_trig_iface_ch6_cfg_transm_len_swb_s0;
      wb_trig_iface_ch6_cfg_transm_len_swb_s2 <= wb_trig_iface_ch6_cfg_transm_len_swb_s1;
      if ((wb_trig_iface_ch6_cfg_transm_len_swb_s2 = '0') and (wb_trig_iface_ch6_cfg_transm_len_swb_s1 = '1')) then
        regs_o.ch6_cfg_transm_len_o <= wb_trig_iface_ch6_cfg_transm_len_int;
      end if;
    end if;
  end process;
  
  
-- Receiver Counter
-- asynchronous std_logic_vector register : Receiver Counter (type RO/WO, wb_clk_i <-> clk_sys_i)
  process (wb_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_trig_iface_ch6_count_rcv_lwb_s0 <= '0';
      wb_trig_iface_ch6_count_rcv_lwb_s1 <= '0';
      wb_trig_iface_ch6_count_rcv_lwb_s2 <= '0';
      wb_trig_iface_ch6_count_rcv_int <= "0000000000000000";
    elsif rising_edge(wb_clk_i) then
      wb_trig_iface_ch6_count_rcv_lwb_s0 <= wb_trig_iface_ch6_count_rcv_lwb;
      wb_trig_iface_ch6_count_rcv_lwb_s1 <= wb_trig_iface_ch6_count_rcv_lwb_s0;
      wb_trig_iface_ch6_count_rcv_lwb_s2 <= wb_trig_iface_ch6_count_rcv_lwb_s1;
      if ((wb_trig_iface_ch6_count_rcv_lwb_s1 = '1') and (wb_trig_iface_ch6_count_rcv_lwb_s2 = '0')) then
        wb_trig_iface_ch6_count_rcv_int <= regs_i.ch6_count_rcv_i;
      end if;
    end if;
  end process;
  
  
-- Transmitter Counter
-- asynchronous std_logic_vector register : Transmitter Counter (type RO/WO, wb_clk_i <-> clk_sys_i)
  process (wb_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_trig_iface_ch6_count_transm_lwb_s0 <= '0';
      wb_trig_iface_ch6_count_transm_lwb_s1 <= '0';
      wb_trig_iface_ch6_count_transm_lwb_s2 <= '0';
      wb_trig_iface_ch6_count_transm_int <= "0000000000000000";
    elsif rising_edge(wb_clk_i) then
      wb_trig_iface_ch6_count_transm_lwb_s0 <= wb_trig_iface_ch6_count_transm_lwb;
      wb_trig_iface_ch6_count_transm_lwb_s1 <= wb_trig_iface_ch6_count_transm_lwb_s0;
      wb_trig_iface_ch6_count_transm_lwb_s2 <= wb_trig_iface_ch6_count_transm_lwb_s1;
      if ((wb_trig_iface_ch6_count_transm_lwb_s1 = '1') and (wb_trig_iface_ch6_count_transm_lwb_s2 = '0')) then
        wb_trig_iface_ch6_count_transm_int <= regs_i.ch6_count_transm_i;
      end if;
    end if;
  end process;
  
  
-- Trigger Direction
  regs_o.ch7_ctl_dir_o <= wb_trig_iface_ch7_ctl_dir_int;
-- Trigger Direction Polarity
  regs_o.ch7_ctl_dir_pol_o <= wb_trig_iface_ch7_ctl_dir_pol_int;
-- Receiver Pulse Counter Reset
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      regs_o.ch7_ctl_rcv_count_rst_o <= '0';
      wb_trig_iface_ch7_ctl_rcv_count_rst_sync0 <= '0';
      wb_trig_iface_ch7_ctl_rcv_count_rst_sync1 <= '0';
      wb_trig_iface_ch7_ctl_rcv_count_rst_sync2 <= '0';
    elsif rising_edge(fs_clk_i) then
      wb_trig_iface_ch7_ctl_rcv_count_rst_sync0 <= wb_trig_iface_ch7_ctl_rcv_count_rst_int;
      wb_trig_iface_ch7_ctl_rcv_count_rst_sync1 <= wb_trig_iface_ch7_ctl_rcv_count_rst_sync0;
      wb_trig_iface_ch7_ctl_rcv_count_rst_sync2 <= wb_trig_iface_ch7_ctl_rcv_count_rst_sync1;
      regs_o.ch7_ctl_rcv_count_rst_o <= wb_trig_iface_ch7_ctl_rcv_count_rst_sync2 and (not wb_trig_iface_ch7_ctl_rcv_count_rst_sync1);
    end if;
  end process;
  
  
-- Transmitter Pulse Counter Reset
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      regs_o.ch7_ctl_transm_count_rst_o <= '0';
      wb_trig_iface_ch7_ctl_transm_count_rst_sync0 <= '0';
      wb_trig_iface_ch7_ctl_transm_count_rst_sync1 <= '0';
      wb_trig_iface_ch7_ctl_transm_count_rst_sync2 <= '0';
    elsif rising_edge(fs_clk_i) then
      wb_trig_iface_ch7_ctl_transm_count_rst_sync0 <= wb_trig_iface_ch7_ctl_transm_count_rst_int;
      wb_trig_iface_ch7_ctl_transm_count_rst_sync1 <= wb_trig_iface_ch7_ctl_transm_count_rst_sync0;
      wb_trig_iface_ch7_ctl_transm_count_rst_sync2 <= wb_trig_iface_ch7_ctl_transm_count_rst_sync1;
      regs_o.ch7_ctl_transm_count_rst_o <= wb_trig_iface_ch7_ctl_transm_count_rst_sync2 and (not wb_trig_iface_ch7_ctl_transm_count_rst_sync1);
    end if;
  end process;
  
  
-- Receiver Pulse Length
-- asynchronous std_logic_vector register : Receiver Pulse Length (type RW/RO, fs_clk_i <-> clk_sys_i)
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_trig_iface_ch7_cfg_rcv_len_swb_s0 <= '0';
      wb_trig_iface_ch7_cfg_rcv_len_swb_s1 <= '0';
      wb_trig_iface_ch7_cfg_rcv_len_swb_s2 <= '0';
      regs_o.ch7_cfg_rcv_len_o <= "00000000";
    elsif rising_edge(fs_clk_i) then
      wb_trig_iface_ch7_cfg_rcv_len_swb_s0 <= wb_trig_iface_ch7_cfg_rcv_len_swb;
      wb_trig_iface_ch7_cfg_rcv_len_swb_s1 <= wb_trig_iface_ch7_cfg_rcv_len_swb_s0;
      wb_trig_iface_ch7_cfg_rcv_len_swb_s2 <= wb_trig_iface_ch7_cfg_rcv_len_swb_s1;
      if ((wb_trig_iface_ch7_cfg_rcv_len_swb_s2 = '0') and (wb_trig_iface_ch7_cfg_rcv_len_swb_s1 = '1')) then
        regs_o.ch7_cfg_rcv_len_o <= wb_trig_iface_ch7_cfg_rcv_len_int;
      end if;
    end if;
  end process;
  
  
-- Transmitter Pulse Length
-- asynchronous std_logic_vector register : Transmitter Pulse Length (type RW/RO, fs_clk_i <-> clk_sys_i)
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_trig_iface_ch7_cfg_transm_len_swb_s0 <= '0';
      wb_trig_iface_ch7_cfg_transm_len_swb_s1 <= '0';
      wb_trig_iface_ch7_cfg_transm_len_swb_s2 <= '0';
      regs_o.ch7_cfg_transm_len_o <= "00000000";
    elsif rising_edge(fs_clk_i) then
      wb_trig_iface_ch7_cfg_transm_len_swb_s0 <= wb_trig_iface_ch7_cfg_transm_len_swb;
      wb_trig_iface_ch7_cfg_transm_len_swb_s1 <= wb_trig_iface_ch7_cfg_transm_len_swb_s0;
      wb_trig_iface_ch7_cfg_transm_len_swb_s2 <= wb_trig_iface_ch7_cfg_transm_len_swb_s1;
      if ((wb_trig_iface_ch7_cfg_transm_len_swb_s2 = '0') and (wb_trig_iface_ch7_cfg_transm_len_swb_s1 = '1')) then
        regs_o.ch7_cfg_transm_len_o <= wb_trig_iface_ch7_cfg_transm_len_int;
      end if;
    end if;
  end process;
  
  
-- Receiver Counter
-- asynchronous std_logic_vector register : Receiver Counter (type RO/WO, wb_clk_i <-> clk_sys_i)
  process (wb_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_trig_iface_ch7_count_rcv_lwb_s0 <= '0';
      wb_trig_iface_ch7_count_rcv_lwb_s1 <= '0';
      wb_trig_iface_ch7_count_rcv_lwb_s2 <= '0';
      wb_trig_iface_ch7_count_rcv_int <= "0000000000000000";
    elsif rising_edge(wb_clk_i) then
      wb_trig_iface_ch7_count_rcv_lwb_s0 <= wb_trig_iface_ch7_count_rcv_lwb;
      wb_trig_iface_ch7_count_rcv_lwb_s1 <= wb_trig_iface_ch7_count_rcv_lwb_s0;
      wb_trig_iface_ch7_count_rcv_lwb_s2 <= wb_trig_iface_ch7_count_rcv_lwb_s1;
      if ((wb_trig_iface_ch7_count_rcv_lwb_s1 = '1') and (wb_trig_iface_ch7_count_rcv_lwb_s2 = '0')) then
        wb_trig_iface_ch7_count_rcv_int <= regs_i.ch7_count_rcv_i;
      end if;
    end if;
  end process;
  
  
-- Transmitter Counter
-- asynchronous std_logic_vector register : Transmitter Counter (type RO/WO, wb_clk_i <-> clk_sys_i)
  process (wb_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_trig_iface_ch7_count_transm_lwb_s0 <= '0';
      wb_trig_iface_ch7_count_transm_lwb_s1 <= '0';
      wb_trig_iface_ch7_count_transm_lwb_s2 <= '0';
      wb_trig_iface_ch7_count_transm_int <= "0000000000000000";
    elsif rising_edge(wb_clk_i) then
      wb_trig_iface_ch7_count_transm_lwb_s0 <= wb_trig_iface_ch7_count_transm_lwb;
      wb_trig_iface_ch7_count_transm_lwb_s1 <= wb_trig_iface_ch7_count_transm_lwb_s0;
      wb_trig_iface_ch7_count_transm_lwb_s2 <= wb_trig_iface_ch7_count_transm_lwb_s1;
      if ((wb_trig_iface_ch7_count_transm_lwb_s1 = '1') and (wb_trig_iface_ch7_count_transm_lwb_s2 = '0')) then
        wb_trig_iface_ch7_count_transm_int <= regs_i.ch7_count_transm_i;
      end if;
    end if;
  end process;
  
  
-- Trigger Direction
  regs_o.ch8_ctl_dir_o <= wb_trig_iface_ch8_ctl_dir_int;
-- Trigger Direction Polarity
  regs_o.ch8_ctl_dir_pol_o <= wb_trig_iface_ch8_ctl_dir_pol_int;
-- Receiver Pulse Counter Reset
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      regs_o.ch8_ctl_rcv_count_rst_o <= '0';
      wb_trig_iface_ch8_ctl_rcv_count_rst_sync0 <= '0';
      wb_trig_iface_ch8_ctl_rcv_count_rst_sync1 <= '0';
      wb_trig_iface_ch8_ctl_rcv_count_rst_sync2 <= '0';
    elsif rising_edge(fs_clk_i) then
      wb_trig_iface_ch8_ctl_rcv_count_rst_sync0 <= wb_trig_iface_ch8_ctl_rcv_count_rst_int;
      wb_trig_iface_ch8_ctl_rcv_count_rst_sync1 <= wb_trig_iface_ch8_ctl_rcv_count_rst_sync0;
      wb_trig_iface_ch8_ctl_rcv_count_rst_sync2 <= wb_trig_iface_ch8_ctl_rcv_count_rst_sync1;
      regs_o.ch8_ctl_rcv_count_rst_o <= wb_trig_iface_ch8_ctl_rcv_count_rst_sync2 and (not wb_trig_iface_ch8_ctl_rcv_count_rst_sync1);
    end if;
  end process;
  
  
-- Transmitter Pulse Counter Reset
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      regs_o.ch8_ctl_transm_count_rst_o <= '0';
      wb_trig_iface_ch8_ctl_transm_count_rst_sync0 <= '0';
      wb_trig_iface_ch8_ctl_transm_count_rst_sync1 <= '0';
      wb_trig_iface_ch8_ctl_transm_count_rst_sync2 <= '0';
    elsif rising_edge(fs_clk_i) then
      wb_trig_iface_ch8_ctl_transm_count_rst_sync0 <= wb_trig_iface_ch8_ctl_transm_count_rst_int;
      wb_trig_iface_ch8_ctl_transm_count_rst_sync1 <= wb_trig_iface_ch8_ctl_transm_count_rst_sync0;
      wb_trig_iface_ch8_ctl_transm_count_rst_sync2 <= wb_trig_iface_ch8_ctl_transm_count_rst_sync1;
      regs_o.ch8_ctl_transm_count_rst_o <= wb_trig_iface_ch8_ctl_transm_count_rst_sync2 and (not wb_trig_iface_ch8_ctl_transm_count_rst_sync1);
    end if;
  end process;
  
  
-- Receiver Pulse Length
-- asynchronous std_logic_vector register : Receiver Pulse Length (type RW/RO, fs_clk_i <-> clk_sys_i)
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_trig_iface_ch8_cfg_rcv_len_swb_s0 <= '0';
      wb_trig_iface_ch8_cfg_rcv_len_swb_s1 <= '0';
      wb_trig_iface_ch8_cfg_rcv_len_swb_s2 <= '0';
      regs_o.ch8_cfg_rcv_len_o <= "00000000";
    elsif rising_edge(fs_clk_i) then
      wb_trig_iface_ch8_cfg_rcv_len_swb_s0 <= wb_trig_iface_ch8_cfg_rcv_len_swb;
      wb_trig_iface_ch8_cfg_rcv_len_swb_s1 <= wb_trig_iface_ch8_cfg_rcv_len_swb_s0;
      wb_trig_iface_ch8_cfg_rcv_len_swb_s2 <= wb_trig_iface_ch8_cfg_rcv_len_swb_s1;
      if ((wb_trig_iface_ch8_cfg_rcv_len_swb_s2 = '0') and (wb_trig_iface_ch8_cfg_rcv_len_swb_s1 = '1')) then
        regs_o.ch8_cfg_rcv_len_o <= wb_trig_iface_ch8_cfg_rcv_len_int;
      end if;
    end if;
  end process;
  
  
-- Transmitter Pulse Length
-- asynchronous std_logic_vector register : Transmitter Pulse Length (type RW/RO, fs_clk_i <-> clk_sys_i)
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_trig_iface_ch8_cfg_transm_len_swb_s0 <= '0';
      wb_trig_iface_ch8_cfg_transm_len_swb_s1 <= '0';
      wb_trig_iface_ch8_cfg_transm_len_swb_s2 <= '0';
      regs_o.ch8_cfg_transm_len_o <= "00000000";
    elsif rising_edge(fs_clk_i) then
      wb_trig_iface_ch8_cfg_transm_len_swb_s0 <= wb_trig_iface_ch8_cfg_transm_len_swb;
      wb_trig_iface_ch8_cfg_transm_len_swb_s1 <= wb_trig_iface_ch8_cfg_transm_len_swb_s0;
      wb_trig_iface_ch8_cfg_transm_len_swb_s2 <= wb_trig_iface_ch8_cfg_transm_len_swb_s1;
      if ((wb_trig_iface_ch8_cfg_transm_len_swb_s2 = '0') and (wb_trig_iface_ch8_cfg_transm_len_swb_s1 = '1')) then
        regs_o.ch8_cfg_transm_len_o <= wb_trig_iface_ch8_cfg_transm_len_int;
      end if;
    end if;
  end process;
  
  
-- Receiver Counter
-- asynchronous std_logic_vector register : Receiver Counter (type RO/WO, wb_clk_i <-> clk_sys_i)
  process (wb_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_trig_iface_ch8_count_rcv_lwb_s0 <= '0';
      wb_trig_iface_ch8_count_rcv_lwb_s1 <= '0';
      wb_trig_iface_ch8_count_rcv_lwb_s2 <= '0';
      wb_trig_iface_ch8_count_rcv_int <= "0000000000000000";
    elsif rising_edge(wb_clk_i) then
      wb_trig_iface_ch8_count_rcv_lwb_s0 <= wb_trig_iface_ch8_count_rcv_lwb;
      wb_trig_iface_ch8_count_rcv_lwb_s1 <= wb_trig_iface_ch8_count_rcv_lwb_s0;
      wb_trig_iface_ch8_count_rcv_lwb_s2 <= wb_trig_iface_ch8_count_rcv_lwb_s1;
      if ((wb_trig_iface_ch8_count_rcv_lwb_s1 = '1') and (wb_trig_iface_ch8_count_rcv_lwb_s2 = '0')) then
        wb_trig_iface_ch8_count_rcv_int <= regs_i.ch8_count_rcv_i;
      end if;
    end if;
  end process;
  
  
-- Transmitter Counter
-- asynchronous std_logic_vector register : Transmitter Counter (type RO/WO, wb_clk_i <-> clk_sys_i)
  process (wb_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_trig_iface_ch8_count_transm_lwb_s0 <= '0';
      wb_trig_iface_ch8_count_transm_lwb_s1 <= '0';
      wb_trig_iface_ch8_count_transm_lwb_s2 <= '0';
      wb_trig_iface_ch8_count_transm_int <= "0000000000000000";
    elsif rising_edge(wb_clk_i) then
      wb_trig_iface_ch8_count_transm_lwb_s0 <= wb_trig_iface_ch8_count_transm_lwb;
      wb_trig_iface_ch8_count_transm_lwb_s1 <= wb_trig_iface_ch8_count_transm_lwb_s0;
      wb_trig_iface_ch8_count_transm_lwb_s2 <= wb_trig_iface_ch8_count_transm_lwb_s1;
      if ((wb_trig_iface_ch8_count_transm_lwb_s1 = '1') and (wb_trig_iface_ch8_count_transm_lwb_s2 = '0')) then
        wb_trig_iface_ch8_count_transm_int <= regs_i.ch8_count_transm_i;
      end if;
    end if;
  end process;
  
  
-- Trigger Direction
  regs_o.ch9_ctl_dir_o <= wb_trig_iface_ch9_ctl_dir_int;
-- Trigger Direction Polarity
  regs_o.ch9_ctl_dir_pol_o <= wb_trig_iface_ch9_ctl_dir_pol_int;
-- Receiver Pulse Counter Reset
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      regs_o.ch9_ctl_rcv_count_rst_o <= '0';
      wb_trig_iface_ch9_ctl_rcv_count_rst_sync0 <= '0';
      wb_trig_iface_ch9_ctl_rcv_count_rst_sync1 <= '0';
      wb_trig_iface_ch9_ctl_rcv_count_rst_sync2 <= '0';
    elsif rising_edge(fs_clk_i) then
      wb_trig_iface_ch9_ctl_rcv_count_rst_sync0 <= wb_trig_iface_ch9_ctl_rcv_count_rst_int;
      wb_trig_iface_ch9_ctl_rcv_count_rst_sync1 <= wb_trig_iface_ch9_ctl_rcv_count_rst_sync0;
      wb_trig_iface_ch9_ctl_rcv_count_rst_sync2 <= wb_trig_iface_ch9_ctl_rcv_count_rst_sync1;
      regs_o.ch9_ctl_rcv_count_rst_o <= wb_trig_iface_ch9_ctl_rcv_count_rst_sync2 and (not wb_trig_iface_ch9_ctl_rcv_count_rst_sync1);
    end if;
  end process;
  
  
-- Transmitter Pulse Counter Reset
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      regs_o.ch9_ctl_transm_count_rst_o <= '0';
      wb_trig_iface_ch9_ctl_transm_count_rst_sync0 <= '0';
      wb_trig_iface_ch9_ctl_transm_count_rst_sync1 <= '0';
      wb_trig_iface_ch9_ctl_transm_count_rst_sync2 <= '0';
    elsif rising_edge(fs_clk_i) then
      wb_trig_iface_ch9_ctl_transm_count_rst_sync0 <= wb_trig_iface_ch9_ctl_transm_count_rst_int;
      wb_trig_iface_ch9_ctl_transm_count_rst_sync1 <= wb_trig_iface_ch9_ctl_transm_count_rst_sync0;
      wb_trig_iface_ch9_ctl_transm_count_rst_sync2 <= wb_trig_iface_ch9_ctl_transm_count_rst_sync1;
      regs_o.ch9_ctl_transm_count_rst_o <= wb_trig_iface_ch9_ctl_transm_count_rst_sync2 and (not wb_trig_iface_ch9_ctl_transm_count_rst_sync1);
    end if;
  end process;
  
  
-- Receiver Pulse Length
-- asynchronous std_logic_vector register : Receiver Pulse Length (type RW/RO, fs_clk_i <-> clk_sys_i)
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_trig_iface_ch9_cfg_rcv_len_swb_s0 <= '0';
      wb_trig_iface_ch9_cfg_rcv_len_swb_s1 <= '0';
      wb_trig_iface_ch9_cfg_rcv_len_swb_s2 <= '0';
      regs_o.ch9_cfg_rcv_len_o <= "00000000";
    elsif rising_edge(fs_clk_i) then
      wb_trig_iface_ch9_cfg_rcv_len_swb_s0 <= wb_trig_iface_ch9_cfg_rcv_len_swb;
      wb_trig_iface_ch9_cfg_rcv_len_swb_s1 <= wb_trig_iface_ch9_cfg_rcv_len_swb_s0;
      wb_trig_iface_ch9_cfg_rcv_len_swb_s2 <= wb_trig_iface_ch9_cfg_rcv_len_swb_s1;
      if ((wb_trig_iface_ch9_cfg_rcv_len_swb_s2 = '0') and (wb_trig_iface_ch9_cfg_rcv_len_swb_s1 = '1')) then
        regs_o.ch9_cfg_rcv_len_o <= wb_trig_iface_ch9_cfg_rcv_len_int;
      end if;
    end if;
  end process;
  
  
-- Transmitter Pulse Length
-- asynchronous std_logic_vector register : Transmitter Pulse Length (type RW/RO, fs_clk_i <-> clk_sys_i)
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_trig_iface_ch9_cfg_transm_len_swb_s0 <= '0';
      wb_trig_iface_ch9_cfg_transm_len_swb_s1 <= '0';
      wb_trig_iface_ch9_cfg_transm_len_swb_s2 <= '0';
      regs_o.ch9_cfg_transm_len_o <= "00000000";
    elsif rising_edge(fs_clk_i) then
      wb_trig_iface_ch9_cfg_transm_len_swb_s0 <= wb_trig_iface_ch9_cfg_transm_len_swb;
      wb_trig_iface_ch9_cfg_transm_len_swb_s1 <= wb_trig_iface_ch9_cfg_transm_len_swb_s0;
      wb_trig_iface_ch9_cfg_transm_len_swb_s2 <= wb_trig_iface_ch9_cfg_transm_len_swb_s1;
      if ((wb_trig_iface_ch9_cfg_transm_len_swb_s2 = '0') and (wb_trig_iface_ch9_cfg_transm_len_swb_s1 = '1')) then
        regs_o.ch9_cfg_transm_len_o <= wb_trig_iface_ch9_cfg_transm_len_int;
      end if;
    end if;
  end process;
  
  
-- Receiver Counter
-- asynchronous std_logic_vector register : Receiver Counter (type RO/WO, wb_clk_i <-> clk_sys_i)
  process (wb_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_trig_iface_ch9_count_rcv_lwb_s0 <= '0';
      wb_trig_iface_ch9_count_rcv_lwb_s1 <= '0';
      wb_trig_iface_ch9_count_rcv_lwb_s2 <= '0';
      wb_trig_iface_ch9_count_rcv_int <= "0000000000000000";
    elsif rising_edge(wb_clk_i) then
      wb_trig_iface_ch9_count_rcv_lwb_s0 <= wb_trig_iface_ch9_count_rcv_lwb;
      wb_trig_iface_ch9_count_rcv_lwb_s1 <= wb_trig_iface_ch9_count_rcv_lwb_s0;
      wb_trig_iface_ch9_count_rcv_lwb_s2 <= wb_trig_iface_ch9_count_rcv_lwb_s1;
      if ((wb_trig_iface_ch9_count_rcv_lwb_s1 = '1') and (wb_trig_iface_ch9_count_rcv_lwb_s2 = '0')) then
        wb_trig_iface_ch9_count_rcv_int <= regs_i.ch9_count_rcv_i;
      end if;
    end if;
  end process;
  
  
-- Transmitter Counter
-- asynchronous std_logic_vector register : Transmitter Counter (type RO/WO, wb_clk_i <-> clk_sys_i)
  process (wb_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_trig_iface_ch9_count_transm_lwb_s0 <= '0';
      wb_trig_iface_ch9_count_transm_lwb_s1 <= '0';
      wb_trig_iface_ch9_count_transm_lwb_s2 <= '0';
      wb_trig_iface_ch9_count_transm_int <= "0000000000000000";
    elsif rising_edge(wb_clk_i) then
      wb_trig_iface_ch9_count_transm_lwb_s0 <= wb_trig_iface_ch9_count_transm_lwb;
      wb_trig_iface_ch9_count_transm_lwb_s1 <= wb_trig_iface_ch9_count_transm_lwb_s0;
      wb_trig_iface_ch9_count_transm_lwb_s2 <= wb_trig_iface_ch9_count_transm_lwb_s1;
      if ((wb_trig_iface_ch9_count_transm_lwb_s1 = '1') and (wb_trig_iface_ch9_count_transm_lwb_s2 = '0')) then
        wb_trig_iface_ch9_count_transm_int <= regs_i.ch9_count_transm_i;
      end if;
    end if;
  end process;
  
  
-- Trigger Direction
  regs_o.ch10_ctl_dir_o <= wb_trig_iface_ch10_ctl_dir_int;
-- Trigger Direction Polarity
  regs_o.ch10_ctl_dir_pol_o <= wb_trig_iface_ch10_ctl_dir_pol_int;
-- Receiver Pulse Counter Reset
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      regs_o.ch10_ctl_rcv_count_rst_o <= '0';
      wb_trig_iface_ch10_ctl_rcv_count_rst_sync0 <= '0';
      wb_trig_iface_ch10_ctl_rcv_count_rst_sync1 <= '0';
      wb_trig_iface_ch10_ctl_rcv_count_rst_sync2 <= '0';
    elsif rising_edge(fs_clk_i) then
      wb_trig_iface_ch10_ctl_rcv_count_rst_sync0 <= wb_trig_iface_ch10_ctl_rcv_count_rst_int;
      wb_trig_iface_ch10_ctl_rcv_count_rst_sync1 <= wb_trig_iface_ch10_ctl_rcv_count_rst_sync0;
      wb_trig_iface_ch10_ctl_rcv_count_rst_sync2 <= wb_trig_iface_ch10_ctl_rcv_count_rst_sync1;
      regs_o.ch10_ctl_rcv_count_rst_o <= wb_trig_iface_ch10_ctl_rcv_count_rst_sync2 and (not wb_trig_iface_ch10_ctl_rcv_count_rst_sync1);
    end if;
  end process;
  
  
-- Transmitter Pulse Counter Reset
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      regs_o.ch10_ctl_transm_count_rst_o <= '0';
      wb_trig_iface_ch10_ctl_transm_count_rst_sync0 <= '0';
      wb_trig_iface_ch10_ctl_transm_count_rst_sync1 <= '0';
      wb_trig_iface_ch10_ctl_transm_count_rst_sync2 <= '0';
    elsif rising_edge(fs_clk_i) then
      wb_trig_iface_ch10_ctl_transm_count_rst_sync0 <= wb_trig_iface_ch10_ctl_transm_count_rst_int;
      wb_trig_iface_ch10_ctl_transm_count_rst_sync1 <= wb_trig_iface_ch10_ctl_transm_count_rst_sync0;
      wb_trig_iface_ch10_ctl_transm_count_rst_sync2 <= wb_trig_iface_ch10_ctl_transm_count_rst_sync1;
      regs_o.ch10_ctl_transm_count_rst_o <= wb_trig_iface_ch10_ctl_transm_count_rst_sync2 and (not wb_trig_iface_ch10_ctl_transm_count_rst_sync1);
    end if;
  end process;
  
  
-- Receiver Pulse Length
-- asynchronous std_logic_vector register : Receiver Pulse Length (type RW/RO, fs_clk_i <-> clk_sys_i)
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_trig_iface_ch10_cfg_rcv_len_swb_s0 <= '0';
      wb_trig_iface_ch10_cfg_rcv_len_swb_s1 <= '0';
      wb_trig_iface_ch10_cfg_rcv_len_swb_s2 <= '0';
      regs_o.ch10_cfg_rcv_len_o <= "00000000";
    elsif rising_edge(fs_clk_i) then
      wb_trig_iface_ch10_cfg_rcv_len_swb_s0 <= wb_trig_iface_ch10_cfg_rcv_len_swb;
      wb_trig_iface_ch10_cfg_rcv_len_swb_s1 <= wb_trig_iface_ch10_cfg_rcv_len_swb_s0;
      wb_trig_iface_ch10_cfg_rcv_len_swb_s2 <= wb_trig_iface_ch10_cfg_rcv_len_swb_s1;
      if ((wb_trig_iface_ch10_cfg_rcv_len_swb_s2 = '0') and (wb_trig_iface_ch10_cfg_rcv_len_swb_s1 = '1')) then
        regs_o.ch10_cfg_rcv_len_o <= wb_trig_iface_ch10_cfg_rcv_len_int;
      end if;
    end if;
  end process;
  
  
-- Transmitter Pulse Length
-- asynchronous std_logic_vector register : Transmitter Pulse Length (type RW/RO, fs_clk_i <-> clk_sys_i)
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_trig_iface_ch10_cfg_transm_len_swb_s0 <= '0';
      wb_trig_iface_ch10_cfg_transm_len_swb_s1 <= '0';
      wb_trig_iface_ch10_cfg_transm_len_swb_s2 <= '0';
      regs_o.ch10_cfg_transm_len_o <= "00000000";
    elsif rising_edge(fs_clk_i) then
      wb_trig_iface_ch10_cfg_transm_len_swb_s0 <= wb_trig_iface_ch10_cfg_transm_len_swb;
      wb_trig_iface_ch10_cfg_transm_len_swb_s1 <= wb_trig_iface_ch10_cfg_transm_len_swb_s0;
      wb_trig_iface_ch10_cfg_transm_len_swb_s2 <= wb_trig_iface_ch10_cfg_transm_len_swb_s1;
      if ((wb_trig_iface_ch10_cfg_transm_len_swb_s2 = '0') and (wb_trig_iface_ch10_cfg_transm_len_swb_s1 = '1')) then
        regs_o.ch10_cfg_transm_len_o <= wb_trig_iface_ch10_cfg_transm_len_int;
      end if;
    end if;
  end process;
  
  
-- Receiver Counter
-- asynchronous std_logic_vector register : Receiver Counter (type RO/WO, wb_clk_i <-> clk_sys_i)
  process (wb_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_trig_iface_ch10_count_rcv_lwb_s0 <= '0';
      wb_trig_iface_ch10_count_rcv_lwb_s1 <= '0';
      wb_trig_iface_ch10_count_rcv_lwb_s2 <= '0';
      wb_trig_iface_ch10_count_rcv_int <= "0000000000000000";
    elsif rising_edge(wb_clk_i) then
      wb_trig_iface_ch10_count_rcv_lwb_s0 <= wb_trig_iface_ch10_count_rcv_lwb;
      wb_trig_iface_ch10_count_rcv_lwb_s1 <= wb_trig_iface_ch10_count_rcv_lwb_s0;
      wb_trig_iface_ch10_count_rcv_lwb_s2 <= wb_trig_iface_ch10_count_rcv_lwb_s1;
      if ((wb_trig_iface_ch10_count_rcv_lwb_s1 = '1') and (wb_trig_iface_ch10_count_rcv_lwb_s2 = '0')) then
        wb_trig_iface_ch10_count_rcv_int <= regs_i.ch10_count_rcv_i;
      end if;
    end if;
  end process;
  
  
-- Transmitter Counter
-- asynchronous std_logic_vector register : Transmitter Counter (type RO/WO, wb_clk_i <-> clk_sys_i)
  process (wb_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_trig_iface_ch10_count_transm_lwb_s0 <= '0';
      wb_trig_iface_ch10_count_transm_lwb_s1 <= '0';
      wb_trig_iface_ch10_count_transm_lwb_s2 <= '0';
      wb_trig_iface_ch10_count_transm_int <= "0000000000000000";
    elsif rising_edge(wb_clk_i) then
      wb_trig_iface_ch10_count_transm_lwb_s0 <= wb_trig_iface_ch10_count_transm_lwb;
      wb_trig_iface_ch10_count_transm_lwb_s1 <= wb_trig_iface_ch10_count_transm_lwb_s0;
      wb_trig_iface_ch10_count_transm_lwb_s2 <= wb_trig_iface_ch10_count_transm_lwb_s1;
      if ((wb_trig_iface_ch10_count_transm_lwb_s1 = '1') and (wb_trig_iface_ch10_count_transm_lwb_s2 = '0')) then
        wb_trig_iface_ch10_count_transm_int <= regs_i.ch10_count_transm_i;
      end if;
    end if;
  end process;
  
  
-- Trigger Direction
  regs_o.ch11_ctl_dir_o <= wb_trig_iface_ch11_ctl_dir_int;
-- Trigger Direction Polarity
  regs_o.ch11_ctl_dir_pol_o <= wb_trig_iface_ch11_ctl_dir_pol_int;
-- Receiver Pulse Counter Reset
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      regs_o.ch11_ctl_rcv_count_rst_o <= '0';
      wb_trig_iface_ch11_ctl_rcv_count_rst_sync0 <= '0';
      wb_trig_iface_ch11_ctl_rcv_count_rst_sync1 <= '0';
      wb_trig_iface_ch11_ctl_rcv_count_rst_sync2 <= '0';
    elsif rising_edge(fs_clk_i) then
      wb_trig_iface_ch11_ctl_rcv_count_rst_sync0 <= wb_trig_iface_ch11_ctl_rcv_count_rst_int;
      wb_trig_iface_ch11_ctl_rcv_count_rst_sync1 <= wb_trig_iface_ch11_ctl_rcv_count_rst_sync0;
      wb_trig_iface_ch11_ctl_rcv_count_rst_sync2 <= wb_trig_iface_ch11_ctl_rcv_count_rst_sync1;
      regs_o.ch11_ctl_rcv_count_rst_o <= wb_trig_iface_ch11_ctl_rcv_count_rst_sync2 and (not wb_trig_iface_ch11_ctl_rcv_count_rst_sync1);
    end if;
  end process;
  
  
-- Transmitter Pulse Counter Reset
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      regs_o.ch11_ctl_transm_count_rst_o <= '0';
      wb_trig_iface_ch11_ctl_transm_count_rst_sync0 <= '0';
      wb_trig_iface_ch11_ctl_transm_count_rst_sync1 <= '0';
      wb_trig_iface_ch11_ctl_transm_count_rst_sync2 <= '0';
    elsif rising_edge(fs_clk_i) then
      wb_trig_iface_ch11_ctl_transm_count_rst_sync0 <= wb_trig_iface_ch11_ctl_transm_count_rst_int;
      wb_trig_iface_ch11_ctl_transm_count_rst_sync1 <= wb_trig_iface_ch11_ctl_transm_count_rst_sync0;
      wb_trig_iface_ch11_ctl_transm_count_rst_sync2 <= wb_trig_iface_ch11_ctl_transm_count_rst_sync1;
      regs_o.ch11_ctl_transm_count_rst_o <= wb_trig_iface_ch11_ctl_transm_count_rst_sync2 and (not wb_trig_iface_ch11_ctl_transm_count_rst_sync1);
    end if;
  end process;
  
  
-- Receiver Pulse Length
-- asynchronous std_logic_vector register : Receiver Pulse Length (type RW/RO, fs_clk_i <-> clk_sys_i)
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_trig_iface_ch11_cfg_rcv_len_swb_s0 <= '0';
      wb_trig_iface_ch11_cfg_rcv_len_swb_s1 <= '0';
      wb_trig_iface_ch11_cfg_rcv_len_swb_s2 <= '0';
      regs_o.ch11_cfg_rcv_len_o <= "00000000";
    elsif rising_edge(fs_clk_i) then
      wb_trig_iface_ch11_cfg_rcv_len_swb_s0 <= wb_trig_iface_ch11_cfg_rcv_len_swb;
      wb_trig_iface_ch11_cfg_rcv_len_swb_s1 <= wb_trig_iface_ch11_cfg_rcv_len_swb_s0;
      wb_trig_iface_ch11_cfg_rcv_len_swb_s2 <= wb_trig_iface_ch11_cfg_rcv_len_swb_s1;
      if ((wb_trig_iface_ch11_cfg_rcv_len_swb_s2 = '0') and (wb_trig_iface_ch11_cfg_rcv_len_swb_s1 = '1')) then
        regs_o.ch11_cfg_rcv_len_o <= wb_trig_iface_ch11_cfg_rcv_len_int;
      end if;
    end if;
  end process;
  
  
-- Transmitter Pulse Length
-- asynchronous std_logic_vector register : Transmitter Pulse Length (type RW/RO, fs_clk_i <-> clk_sys_i)
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_trig_iface_ch11_cfg_transm_len_swb_s0 <= '0';
      wb_trig_iface_ch11_cfg_transm_len_swb_s1 <= '0';
      wb_trig_iface_ch11_cfg_transm_len_swb_s2 <= '0';
      regs_o.ch11_cfg_transm_len_o <= "00000000";
    elsif rising_edge(fs_clk_i) then
      wb_trig_iface_ch11_cfg_transm_len_swb_s0 <= wb_trig_iface_ch11_cfg_transm_len_swb;
      wb_trig_iface_ch11_cfg_transm_len_swb_s1 <= wb_trig_iface_ch11_cfg_transm_len_swb_s0;
      wb_trig_iface_ch11_cfg_transm_len_swb_s2 <= wb_trig_iface_ch11_cfg_transm_len_swb_s1;
      if ((wb_trig_iface_ch11_cfg_transm_len_swb_s2 = '0') and (wb_trig_iface_ch11_cfg_transm_len_swb_s1 = '1')) then
        regs_o.ch11_cfg_transm_len_o <= wb_trig_iface_ch11_cfg_transm_len_int;
      end if;
    end if;
  end process;
  
  
-- Receiver Counter
-- asynchronous std_logic_vector register : Receiver Counter (type RO/WO, wb_clk_i <-> clk_sys_i)
  process (wb_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_trig_iface_ch11_count_rcv_lwb_s0 <= '0';
      wb_trig_iface_ch11_count_rcv_lwb_s1 <= '0';
      wb_trig_iface_ch11_count_rcv_lwb_s2 <= '0';
      wb_trig_iface_ch11_count_rcv_int <= "0000000000000000";
    elsif rising_edge(wb_clk_i) then
      wb_trig_iface_ch11_count_rcv_lwb_s0 <= wb_trig_iface_ch11_count_rcv_lwb;
      wb_trig_iface_ch11_count_rcv_lwb_s1 <= wb_trig_iface_ch11_count_rcv_lwb_s0;
      wb_trig_iface_ch11_count_rcv_lwb_s2 <= wb_trig_iface_ch11_count_rcv_lwb_s1;
      if ((wb_trig_iface_ch11_count_rcv_lwb_s1 = '1') and (wb_trig_iface_ch11_count_rcv_lwb_s2 = '0')) then
        wb_trig_iface_ch11_count_rcv_int <= regs_i.ch11_count_rcv_i;
      end if;
    end if;
  end process;
  
  
-- Transmitter Counter
-- asynchronous std_logic_vector register : Transmitter Counter (type RO/WO, wb_clk_i <-> clk_sys_i)
  process (wb_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_trig_iface_ch11_count_transm_lwb_s0 <= '0';
      wb_trig_iface_ch11_count_transm_lwb_s1 <= '0';
      wb_trig_iface_ch11_count_transm_lwb_s2 <= '0';
      wb_trig_iface_ch11_count_transm_int <= "0000000000000000";
    elsif rising_edge(wb_clk_i) then
      wb_trig_iface_ch11_count_transm_lwb_s0 <= wb_trig_iface_ch11_count_transm_lwb;
      wb_trig_iface_ch11_count_transm_lwb_s1 <= wb_trig_iface_ch11_count_transm_lwb_s0;
      wb_trig_iface_ch11_count_transm_lwb_s2 <= wb_trig_iface_ch11_count_transm_lwb_s1;
      if ((wb_trig_iface_ch11_count_transm_lwb_s1 = '1') and (wb_trig_iface_ch11_count_transm_lwb_s2 = '0')) then
        wb_trig_iface_ch11_count_transm_int <= regs_i.ch11_count_transm_i;
      end if;
    end if;
  end process;
  
  
-- Trigger Direction
  regs_o.ch12_ctl_dir_o <= wb_trig_iface_ch12_ctl_dir_int;
-- Trigger Direction Polarity
  regs_o.ch12_ctl_dir_pol_o <= wb_trig_iface_ch12_ctl_dir_pol_int;
-- Receiver Pulse Counter Reset
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      regs_o.ch12_ctl_rcv_count_rst_o <= '0';
      wb_trig_iface_ch12_ctl_rcv_count_rst_sync0 <= '0';
      wb_trig_iface_ch12_ctl_rcv_count_rst_sync1 <= '0';
      wb_trig_iface_ch12_ctl_rcv_count_rst_sync2 <= '0';
    elsif rising_edge(fs_clk_i) then
      wb_trig_iface_ch12_ctl_rcv_count_rst_sync0 <= wb_trig_iface_ch12_ctl_rcv_count_rst_int;
      wb_trig_iface_ch12_ctl_rcv_count_rst_sync1 <= wb_trig_iface_ch12_ctl_rcv_count_rst_sync0;
      wb_trig_iface_ch12_ctl_rcv_count_rst_sync2 <= wb_trig_iface_ch12_ctl_rcv_count_rst_sync1;
      regs_o.ch12_ctl_rcv_count_rst_o <= wb_trig_iface_ch12_ctl_rcv_count_rst_sync2 and (not wb_trig_iface_ch12_ctl_rcv_count_rst_sync1);
    end if;
  end process;
  
  
-- Transmitter Pulse Counter Reset
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      regs_o.ch12_ctl_transm_count_rst_o <= '0';
      wb_trig_iface_ch12_ctl_transm_count_rst_sync0 <= '0';
      wb_trig_iface_ch12_ctl_transm_count_rst_sync1 <= '0';
      wb_trig_iface_ch12_ctl_transm_count_rst_sync2 <= '0';
    elsif rising_edge(fs_clk_i) then
      wb_trig_iface_ch12_ctl_transm_count_rst_sync0 <= wb_trig_iface_ch12_ctl_transm_count_rst_int;
      wb_trig_iface_ch12_ctl_transm_count_rst_sync1 <= wb_trig_iface_ch12_ctl_transm_count_rst_sync0;
      wb_trig_iface_ch12_ctl_transm_count_rst_sync2 <= wb_trig_iface_ch12_ctl_transm_count_rst_sync1;
      regs_o.ch12_ctl_transm_count_rst_o <= wb_trig_iface_ch12_ctl_transm_count_rst_sync2 and (not wb_trig_iface_ch12_ctl_transm_count_rst_sync1);
    end if;
  end process;
  
  
-- Receiver Pulse Length
-- asynchronous std_logic_vector register : Receiver Pulse Length (type RW/RO, fs_clk_i <-> clk_sys_i)
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_trig_iface_ch12_cfg_rcv_len_swb_s0 <= '0';
      wb_trig_iface_ch12_cfg_rcv_len_swb_s1 <= '0';
      wb_trig_iface_ch12_cfg_rcv_len_swb_s2 <= '0';
      regs_o.ch12_cfg_rcv_len_o <= "00000000";
    elsif rising_edge(fs_clk_i) then
      wb_trig_iface_ch12_cfg_rcv_len_swb_s0 <= wb_trig_iface_ch12_cfg_rcv_len_swb;
      wb_trig_iface_ch12_cfg_rcv_len_swb_s1 <= wb_trig_iface_ch12_cfg_rcv_len_swb_s0;
      wb_trig_iface_ch12_cfg_rcv_len_swb_s2 <= wb_trig_iface_ch12_cfg_rcv_len_swb_s1;
      if ((wb_trig_iface_ch12_cfg_rcv_len_swb_s2 = '0') and (wb_trig_iface_ch12_cfg_rcv_len_swb_s1 = '1')) then
        regs_o.ch12_cfg_rcv_len_o <= wb_trig_iface_ch12_cfg_rcv_len_int;
      end if;
    end if;
  end process;
  
  
-- Transmitter Pulse Length
-- asynchronous std_logic_vector register : Transmitter Pulse Length (type RW/RO, fs_clk_i <-> clk_sys_i)
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_trig_iface_ch12_cfg_transm_len_swb_s0 <= '0';
      wb_trig_iface_ch12_cfg_transm_len_swb_s1 <= '0';
      wb_trig_iface_ch12_cfg_transm_len_swb_s2 <= '0';
      regs_o.ch12_cfg_transm_len_o <= "00000000";
    elsif rising_edge(fs_clk_i) then
      wb_trig_iface_ch12_cfg_transm_len_swb_s0 <= wb_trig_iface_ch12_cfg_transm_len_swb;
      wb_trig_iface_ch12_cfg_transm_len_swb_s1 <= wb_trig_iface_ch12_cfg_transm_len_swb_s0;
      wb_trig_iface_ch12_cfg_transm_len_swb_s2 <= wb_trig_iface_ch12_cfg_transm_len_swb_s1;
      if ((wb_trig_iface_ch12_cfg_transm_len_swb_s2 = '0') and (wb_trig_iface_ch12_cfg_transm_len_swb_s1 = '1')) then
        regs_o.ch12_cfg_transm_len_o <= wb_trig_iface_ch12_cfg_transm_len_int;
      end if;
    end if;
  end process;
  
  
-- Receiver Counter
-- asynchronous std_logic_vector register : Receiver Counter (type RO/WO, wb_clk_i <-> clk_sys_i)
  process (wb_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_trig_iface_ch12_count_rcv_lwb_s0 <= '0';
      wb_trig_iface_ch12_count_rcv_lwb_s1 <= '0';
      wb_trig_iface_ch12_count_rcv_lwb_s2 <= '0';
      wb_trig_iface_ch12_count_rcv_int <= "0000000000000000";
    elsif rising_edge(wb_clk_i) then
      wb_trig_iface_ch12_count_rcv_lwb_s0 <= wb_trig_iface_ch12_count_rcv_lwb;
      wb_trig_iface_ch12_count_rcv_lwb_s1 <= wb_trig_iface_ch12_count_rcv_lwb_s0;
      wb_trig_iface_ch12_count_rcv_lwb_s2 <= wb_trig_iface_ch12_count_rcv_lwb_s1;
      if ((wb_trig_iface_ch12_count_rcv_lwb_s1 = '1') and (wb_trig_iface_ch12_count_rcv_lwb_s2 = '0')) then
        wb_trig_iface_ch12_count_rcv_int <= regs_i.ch12_count_rcv_i;
      end if;
    end if;
  end process;
  
  
-- Transmitter Counter
-- asynchronous std_logic_vector register : Transmitter Counter (type RO/WO, wb_clk_i <-> clk_sys_i)
  process (wb_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_trig_iface_ch12_count_transm_lwb_s0 <= '0';
      wb_trig_iface_ch12_count_transm_lwb_s1 <= '0';
      wb_trig_iface_ch12_count_transm_lwb_s2 <= '0';
      wb_trig_iface_ch12_count_transm_int <= "0000000000000000";
    elsif rising_edge(wb_clk_i) then
      wb_trig_iface_ch12_count_transm_lwb_s0 <= wb_trig_iface_ch12_count_transm_lwb;
      wb_trig_iface_ch12_count_transm_lwb_s1 <= wb_trig_iface_ch12_count_transm_lwb_s0;
      wb_trig_iface_ch12_count_transm_lwb_s2 <= wb_trig_iface_ch12_count_transm_lwb_s1;
      if ((wb_trig_iface_ch12_count_transm_lwb_s1 = '1') and (wb_trig_iface_ch12_count_transm_lwb_s2 = '0')) then
        wb_trig_iface_ch12_count_transm_int <= regs_i.ch12_count_transm_i;
      end if;
    end if;
  end process;
  
  
-- Trigger Direction
  regs_o.ch13_ctl_dir_o <= wb_trig_iface_ch13_ctl_dir_int;
-- Trigger Direction Polarity
  regs_o.ch13_ctl_dir_pol_o <= wb_trig_iface_ch13_ctl_dir_pol_int;
-- Receiver Pulse Counter Reset
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      regs_o.ch13_ctl_rcv_count_rst_o <= '0';
      wb_trig_iface_ch13_ctl_rcv_count_rst_sync0 <= '0';
      wb_trig_iface_ch13_ctl_rcv_count_rst_sync1 <= '0';
      wb_trig_iface_ch13_ctl_rcv_count_rst_sync2 <= '0';
    elsif rising_edge(fs_clk_i) then
      wb_trig_iface_ch13_ctl_rcv_count_rst_sync0 <= wb_trig_iface_ch13_ctl_rcv_count_rst_int;
      wb_trig_iface_ch13_ctl_rcv_count_rst_sync1 <= wb_trig_iface_ch13_ctl_rcv_count_rst_sync0;
      wb_trig_iface_ch13_ctl_rcv_count_rst_sync2 <= wb_trig_iface_ch13_ctl_rcv_count_rst_sync1;
      regs_o.ch13_ctl_rcv_count_rst_o <= wb_trig_iface_ch13_ctl_rcv_count_rst_sync2 and (not wb_trig_iface_ch13_ctl_rcv_count_rst_sync1);
    end if;
  end process;
  
  
-- Transmitter Pulse Counter Reset
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      regs_o.ch13_ctl_transm_count_rst_o <= '0';
      wb_trig_iface_ch13_ctl_transm_count_rst_sync0 <= '0';
      wb_trig_iface_ch13_ctl_transm_count_rst_sync1 <= '0';
      wb_trig_iface_ch13_ctl_transm_count_rst_sync2 <= '0';
    elsif rising_edge(fs_clk_i) then
      wb_trig_iface_ch13_ctl_transm_count_rst_sync0 <= wb_trig_iface_ch13_ctl_transm_count_rst_int;
      wb_trig_iface_ch13_ctl_transm_count_rst_sync1 <= wb_trig_iface_ch13_ctl_transm_count_rst_sync0;
      wb_trig_iface_ch13_ctl_transm_count_rst_sync2 <= wb_trig_iface_ch13_ctl_transm_count_rst_sync1;
      regs_o.ch13_ctl_transm_count_rst_o <= wb_trig_iface_ch13_ctl_transm_count_rst_sync2 and (not wb_trig_iface_ch13_ctl_transm_count_rst_sync1);
    end if;
  end process;
  
  
-- Receiver Pulse Length
-- asynchronous std_logic_vector register : Receiver Pulse Length (type RW/RO, fs_clk_i <-> clk_sys_i)
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_trig_iface_ch13_cfg_rcv_len_swb_s0 <= '0';
      wb_trig_iface_ch13_cfg_rcv_len_swb_s1 <= '0';
      wb_trig_iface_ch13_cfg_rcv_len_swb_s2 <= '0';
      regs_o.ch13_cfg_rcv_len_o <= "00000000";
    elsif rising_edge(fs_clk_i) then
      wb_trig_iface_ch13_cfg_rcv_len_swb_s0 <= wb_trig_iface_ch13_cfg_rcv_len_swb;
      wb_trig_iface_ch13_cfg_rcv_len_swb_s1 <= wb_trig_iface_ch13_cfg_rcv_len_swb_s0;
      wb_trig_iface_ch13_cfg_rcv_len_swb_s2 <= wb_trig_iface_ch13_cfg_rcv_len_swb_s1;
      if ((wb_trig_iface_ch13_cfg_rcv_len_swb_s2 = '0') and (wb_trig_iface_ch13_cfg_rcv_len_swb_s1 = '1')) then
        regs_o.ch13_cfg_rcv_len_o <= wb_trig_iface_ch13_cfg_rcv_len_int;
      end if;
    end if;
  end process;
  
  
-- Transmitter Pulse Length
-- asynchronous std_logic_vector register : Transmitter Pulse Length (type RW/RO, fs_clk_i <-> clk_sys_i)
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_trig_iface_ch13_cfg_transm_len_swb_s0 <= '0';
      wb_trig_iface_ch13_cfg_transm_len_swb_s1 <= '0';
      wb_trig_iface_ch13_cfg_transm_len_swb_s2 <= '0';
      regs_o.ch13_cfg_transm_len_o <= "00000000";
    elsif rising_edge(fs_clk_i) then
      wb_trig_iface_ch13_cfg_transm_len_swb_s0 <= wb_trig_iface_ch13_cfg_transm_len_swb;
      wb_trig_iface_ch13_cfg_transm_len_swb_s1 <= wb_trig_iface_ch13_cfg_transm_len_swb_s0;
      wb_trig_iface_ch13_cfg_transm_len_swb_s2 <= wb_trig_iface_ch13_cfg_transm_len_swb_s1;
      if ((wb_trig_iface_ch13_cfg_transm_len_swb_s2 = '0') and (wb_trig_iface_ch13_cfg_transm_len_swb_s1 = '1')) then
        regs_o.ch13_cfg_transm_len_o <= wb_trig_iface_ch13_cfg_transm_len_int;
      end if;
    end if;
  end process;
  
  
-- Receiver Counter
-- asynchronous std_logic_vector register : Receiver Counter (type RO/WO, wb_clk_i <-> clk_sys_i)
  process (wb_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_trig_iface_ch13_count_rcv_lwb_s0 <= '0';
      wb_trig_iface_ch13_count_rcv_lwb_s1 <= '0';
      wb_trig_iface_ch13_count_rcv_lwb_s2 <= '0';
      wb_trig_iface_ch13_count_rcv_int <= "0000000000000000";
    elsif rising_edge(wb_clk_i) then
      wb_trig_iface_ch13_count_rcv_lwb_s0 <= wb_trig_iface_ch13_count_rcv_lwb;
      wb_trig_iface_ch13_count_rcv_lwb_s1 <= wb_trig_iface_ch13_count_rcv_lwb_s0;
      wb_trig_iface_ch13_count_rcv_lwb_s2 <= wb_trig_iface_ch13_count_rcv_lwb_s1;
      if ((wb_trig_iface_ch13_count_rcv_lwb_s1 = '1') and (wb_trig_iface_ch13_count_rcv_lwb_s2 = '0')) then
        wb_trig_iface_ch13_count_rcv_int <= regs_i.ch13_count_rcv_i;
      end if;
    end if;
  end process;
  
  
-- Transmitter Counter
-- asynchronous std_logic_vector register : Transmitter Counter (type RO/WO, wb_clk_i <-> clk_sys_i)
  process (wb_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_trig_iface_ch13_count_transm_lwb_s0 <= '0';
      wb_trig_iface_ch13_count_transm_lwb_s1 <= '0';
      wb_trig_iface_ch13_count_transm_lwb_s2 <= '0';
      wb_trig_iface_ch13_count_transm_int <= "0000000000000000";
    elsif rising_edge(wb_clk_i) then
      wb_trig_iface_ch13_count_transm_lwb_s0 <= wb_trig_iface_ch13_count_transm_lwb;
      wb_trig_iface_ch13_count_transm_lwb_s1 <= wb_trig_iface_ch13_count_transm_lwb_s0;
      wb_trig_iface_ch13_count_transm_lwb_s2 <= wb_trig_iface_ch13_count_transm_lwb_s1;
      if ((wb_trig_iface_ch13_count_transm_lwb_s1 = '1') and (wb_trig_iface_ch13_count_transm_lwb_s2 = '0')) then
        wb_trig_iface_ch13_count_transm_int <= regs_i.ch13_count_transm_i;
      end if;
    end if;
  end process;
  
  
-- Trigger Direction
  regs_o.ch14_ctl_dir_o <= wb_trig_iface_ch14_ctl_dir_int;
-- Trigger Direction Polarity
  regs_o.ch14_ctl_dir_pol_o <= wb_trig_iface_ch14_ctl_dir_pol_int;
-- Receiver Pulse Counter Reset
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      regs_o.ch14_ctl_rcv_count_rst_o <= '0';
      wb_trig_iface_ch14_ctl_rcv_count_rst_sync0 <= '0';
      wb_trig_iface_ch14_ctl_rcv_count_rst_sync1 <= '0';
      wb_trig_iface_ch14_ctl_rcv_count_rst_sync2 <= '0';
    elsif rising_edge(fs_clk_i) then
      wb_trig_iface_ch14_ctl_rcv_count_rst_sync0 <= wb_trig_iface_ch14_ctl_rcv_count_rst_int;
      wb_trig_iface_ch14_ctl_rcv_count_rst_sync1 <= wb_trig_iface_ch14_ctl_rcv_count_rst_sync0;
      wb_trig_iface_ch14_ctl_rcv_count_rst_sync2 <= wb_trig_iface_ch14_ctl_rcv_count_rst_sync1;
      regs_o.ch14_ctl_rcv_count_rst_o <= wb_trig_iface_ch14_ctl_rcv_count_rst_sync2 and (not wb_trig_iface_ch14_ctl_rcv_count_rst_sync1);
    end if;
  end process;
  
  
-- Transmitter Pulse Counter Reset
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      regs_o.ch14_ctl_transm_count_rst_o <= '0';
      wb_trig_iface_ch14_ctl_transm_count_rst_sync0 <= '0';
      wb_trig_iface_ch14_ctl_transm_count_rst_sync1 <= '0';
      wb_trig_iface_ch14_ctl_transm_count_rst_sync2 <= '0';
    elsif rising_edge(fs_clk_i) then
      wb_trig_iface_ch14_ctl_transm_count_rst_sync0 <= wb_trig_iface_ch14_ctl_transm_count_rst_int;
      wb_trig_iface_ch14_ctl_transm_count_rst_sync1 <= wb_trig_iface_ch14_ctl_transm_count_rst_sync0;
      wb_trig_iface_ch14_ctl_transm_count_rst_sync2 <= wb_trig_iface_ch14_ctl_transm_count_rst_sync1;
      regs_o.ch14_ctl_transm_count_rst_o <= wb_trig_iface_ch14_ctl_transm_count_rst_sync2 and (not wb_trig_iface_ch14_ctl_transm_count_rst_sync1);
    end if;
  end process;
  
  
-- Receiver Pulse Length
-- asynchronous std_logic_vector register : Receiver Pulse Length (type RW/RO, fs_clk_i <-> clk_sys_i)
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_trig_iface_ch14_cfg_rcv_len_swb_s0 <= '0';
      wb_trig_iface_ch14_cfg_rcv_len_swb_s1 <= '0';
      wb_trig_iface_ch14_cfg_rcv_len_swb_s2 <= '0';
      regs_o.ch14_cfg_rcv_len_o <= "00000000";
    elsif rising_edge(fs_clk_i) then
      wb_trig_iface_ch14_cfg_rcv_len_swb_s0 <= wb_trig_iface_ch14_cfg_rcv_len_swb;
      wb_trig_iface_ch14_cfg_rcv_len_swb_s1 <= wb_trig_iface_ch14_cfg_rcv_len_swb_s0;
      wb_trig_iface_ch14_cfg_rcv_len_swb_s2 <= wb_trig_iface_ch14_cfg_rcv_len_swb_s1;
      if ((wb_trig_iface_ch14_cfg_rcv_len_swb_s2 = '0') and (wb_trig_iface_ch14_cfg_rcv_len_swb_s1 = '1')) then
        regs_o.ch14_cfg_rcv_len_o <= wb_trig_iface_ch14_cfg_rcv_len_int;
      end if;
    end if;
  end process;
  
  
-- Transmitter Pulse Length
-- asynchronous std_logic_vector register : Transmitter Pulse Length (type RW/RO, fs_clk_i <-> clk_sys_i)
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_trig_iface_ch14_cfg_transm_len_swb_s0 <= '0';
      wb_trig_iface_ch14_cfg_transm_len_swb_s1 <= '0';
      wb_trig_iface_ch14_cfg_transm_len_swb_s2 <= '0';
      regs_o.ch14_cfg_transm_len_o <= "00000000";
    elsif rising_edge(fs_clk_i) then
      wb_trig_iface_ch14_cfg_transm_len_swb_s0 <= wb_trig_iface_ch14_cfg_transm_len_swb;
      wb_trig_iface_ch14_cfg_transm_len_swb_s1 <= wb_trig_iface_ch14_cfg_transm_len_swb_s0;
      wb_trig_iface_ch14_cfg_transm_len_swb_s2 <= wb_trig_iface_ch14_cfg_transm_len_swb_s1;
      if ((wb_trig_iface_ch14_cfg_transm_len_swb_s2 = '0') and (wb_trig_iface_ch14_cfg_transm_len_swb_s1 = '1')) then
        regs_o.ch14_cfg_transm_len_o <= wb_trig_iface_ch14_cfg_transm_len_int;
      end if;
    end if;
  end process;
  
  
-- Receiver Counter
-- asynchronous std_logic_vector register : Receiver Counter (type RO/WO, wb_clk_i <-> clk_sys_i)
  process (wb_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_trig_iface_ch14_count_rcv_lwb_s0 <= '0';
      wb_trig_iface_ch14_count_rcv_lwb_s1 <= '0';
      wb_trig_iface_ch14_count_rcv_lwb_s2 <= '0';
      wb_trig_iface_ch14_count_rcv_int <= "0000000000000000";
    elsif rising_edge(wb_clk_i) then
      wb_trig_iface_ch14_count_rcv_lwb_s0 <= wb_trig_iface_ch14_count_rcv_lwb;
      wb_trig_iface_ch14_count_rcv_lwb_s1 <= wb_trig_iface_ch14_count_rcv_lwb_s0;
      wb_trig_iface_ch14_count_rcv_lwb_s2 <= wb_trig_iface_ch14_count_rcv_lwb_s1;
      if ((wb_trig_iface_ch14_count_rcv_lwb_s1 = '1') and (wb_trig_iface_ch14_count_rcv_lwb_s2 = '0')) then
        wb_trig_iface_ch14_count_rcv_int <= regs_i.ch14_count_rcv_i;
      end if;
    end if;
  end process;
  
  
-- Transmitter Counter
-- asynchronous std_logic_vector register : Transmitter Counter (type RO/WO, wb_clk_i <-> clk_sys_i)
  process (wb_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_trig_iface_ch14_count_transm_lwb_s0 <= '0';
      wb_trig_iface_ch14_count_transm_lwb_s1 <= '0';
      wb_trig_iface_ch14_count_transm_lwb_s2 <= '0';
      wb_trig_iface_ch14_count_transm_int <= "0000000000000000";
    elsif rising_edge(wb_clk_i) then
      wb_trig_iface_ch14_count_transm_lwb_s0 <= wb_trig_iface_ch14_count_transm_lwb;
      wb_trig_iface_ch14_count_transm_lwb_s1 <= wb_trig_iface_ch14_count_transm_lwb_s0;
      wb_trig_iface_ch14_count_transm_lwb_s2 <= wb_trig_iface_ch14_count_transm_lwb_s1;
      if ((wb_trig_iface_ch14_count_transm_lwb_s1 = '1') and (wb_trig_iface_ch14_count_transm_lwb_s2 = '0')) then
        wb_trig_iface_ch14_count_transm_int <= regs_i.ch14_count_transm_i;
      end if;
    end if;
  end process;
  
  
-- Trigger Direction
  regs_o.ch15_ctl_dir_o <= wb_trig_iface_ch15_ctl_dir_int;
-- Trigger Direction Polarity
  regs_o.ch15_ctl_dir_pol_o <= wb_trig_iface_ch15_ctl_dir_pol_int;
-- Receiver Pulse Counter Reset
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      regs_o.ch15_ctl_rcv_count_rst_o <= '0';
      wb_trig_iface_ch15_ctl_rcv_count_rst_sync0 <= '0';
      wb_trig_iface_ch15_ctl_rcv_count_rst_sync1 <= '0';
      wb_trig_iface_ch15_ctl_rcv_count_rst_sync2 <= '0';
    elsif rising_edge(fs_clk_i) then
      wb_trig_iface_ch15_ctl_rcv_count_rst_sync0 <= wb_trig_iface_ch15_ctl_rcv_count_rst_int;
      wb_trig_iface_ch15_ctl_rcv_count_rst_sync1 <= wb_trig_iface_ch15_ctl_rcv_count_rst_sync0;
      wb_trig_iface_ch15_ctl_rcv_count_rst_sync2 <= wb_trig_iface_ch15_ctl_rcv_count_rst_sync1;
      regs_o.ch15_ctl_rcv_count_rst_o <= wb_trig_iface_ch15_ctl_rcv_count_rst_sync2 and (not wb_trig_iface_ch15_ctl_rcv_count_rst_sync1);
    end if;
  end process;
  
  
-- Transmitter Pulse Counter Reset
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      regs_o.ch15_ctl_transm_count_rst_o <= '0';
      wb_trig_iface_ch15_ctl_transm_count_rst_sync0 <= '0';
      wb_trig_iface_ch15_ctl_transm_count_rst_sync1 <= '0';
      wb_trig_iface_ch15_ctl_transm_count_rst_sync2 <= '0';
    elsif rising_edge(fs_clk_i) then
      wb_trig_iface_ch15_ctl_transm_count_rst_sync0 <= wb_trig_iface_ch15_ctl_transm_count_rst_int;
      wb_trig_iface_ch15_ctl_transm_count_rst_sync1 <= wb_trig_iface_ch15_ctl_transm_count_rst_sync0;
      wb_trig_iface_ch15_ctl_transm_count_rst_sync2 <= wb_trig_iface_ch15_ctl_transm_count_rst_sync1;
      regs_o.ch15_ctl_transm_count_rst_o <= wb_trig_iface_ch15_ctl_transm_count_rst_sync2 and (not wb_trig_iface_ch15_ctl_transm_count_rst_sync1);
    end if;
  end process;
  
  
-- Receiver Pulse Length
-- asynchronous std_logic_vector register : Receiver Pulse Length (type RW/RO, fs_clk_i <-> clk_sys_i)
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_trig_iface_ch15_cfg_rcv_len_swb_s0 <= '0';
      wb_trig_iface_ch15_cfg_rcv_len_swb_s1 <= '0';
      wb_trig_iface_ch15_cfg_rcv_len_swb_s2 <= '0';
      regs_o.ch15_cfg_rcv_len_o <= "00000000";
    elsif rising_edge(fs_clk_i) then
      wb_trig_iface_ch15_cfg_rcv_len_swb_s0 <= wb_trig_iface_ch15_cfg_rcv_len_swb;
      wb_trig_iface_ch15_cfg_rcv_len_swb_s1 <= wb_trig_iface_ch15_cfg_rcv_len_swb_s0;
      wb_trig_iface_ch15_cfg_rcv_len_swb_s2 <= wb_trig_iface_ch15_cfg_rcv_len_swb_s1;
      if ((wb_trig_iface_ch15_cfg_rcv_len_swb_s2 = '0') and (wb_trig_iface_ch15_cfg_rcv_len_swb_s1 = '1')) then
        regs_o.ch15_cfg_rcv_len_o <= wb_trig_iface_ch15_cfg_rcv_len_int;
      end if;
    end if;
  end process;
  
  
-- Transmitter Pulse Length
-- asynchronous std_logic_vector register : Transmitter Pulse Length (type RW/RO, fs_clk_i <-> clk_sys_i)
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_trig_iface_ch15_cfg_transm_len_swb_s0 <= '0';
      wb_trig_iface_ch15_cfg_transm_len_swb_s1 <= '0';
      wb_trig_iface_ch15_cfg_transm_len_swb_s2 <= '0';
      regs_o.ch15_cfg_transm_len_o <= "00000000";
    elsif rising_edge(fs_clk_i) then
      wb_trig_iface_ch15_cfg_transm_len_swb_s0 <= wb_trig_iface_ch15_cfg_transm_len_swb;
      wb_trig_iface_ch15_cfg_transm_len_swb_s1 <= wb_trig_iface_ch15_cfg_transm_len_swb_s0;
      wb_trig_iface_ch15_cfg_transm_len_swb_s2 <= wb_trig_iface_ch15_cfg_transm_len_swb_s1;
      if ((wb_trig_iface_ch15_cfg_transm_len_swb_s2 = '0') and (wb_trig_iface_ch15_cfg_transm_len_swb_s1 = '1')) then
        regs_o.ch15_cfg_transm_len_o <= wb_trig_iface_ch15_cfg_transm_len_int;
      end if;
    end if;
  end process;
  
  
-- Receiver Counter
-- asynchronous std_logic_vector register : Receiver Counter (type RO/WO, wb_clk_i <-> clk_sys_i)
  process (wb_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_trig_iface_ch15_count_rcv_lwb_s0 <= '0';
      wb_trig_iface_ch15_count_rcv_lwb_s1 <= '0';
      wb_trig_iface_ch15_count_rcv_lwb_s2 <= '0';
      wb_trig_iface_ch15_count_rcv_int <= "0000000000000000";
    elsif rising_edge(wb_clk_i) then
      wb_trig_iface_ch15_count_rcv_lwb_s0 <= wb_trig_iface_ch15_count_rcv_lwb;
      wb_trig_iface_ch15_count_rcv_lwb_s1 <= wb_trig_iface_ch15_count_rcv_lwb_s0;
      wb_trig_iface_ch15_count_rcv_lwb_s2 <= wb_trig_iface_ch15_count_rcv_lwb_s1;
      if ((wb_trig_iface_ch15_count_rcv_lwb_s1 = '1') and (wb_trig_iface_ch15_count_rcv_lwb_s2 = '0')) then
        wb_trig_iface_ch15_count_rcv_int <= regs_i.ch15_count_rcv_i;
      end if;
    end if;
  end process;
  
  
-- Transmitter Counter
-- asynchronous std_logic_vector register : Transmitter Counter (type RO/WO, wb_clk_i <-> clk_sys_i)
  process (wb_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_trig_iface_ch15_count_transm_lwb_s0 <= '0';
      wb_trig_iface_ch15_count_transm_lwb_s1 <= '0';
      wb_trig_iface_ch15_count_transm_lwb_s2 <= '0';
      wb_trig_iface_ch15_count_transm_int <= "0000000000000000";
    elsif rising_edge(wb_clk_i) then
      wb_trig_iface_ch15_count_transm_lwb_s0 <= wb_trig_iface_ch15_count_transm_lwb;
      wb_trig_iface_ch15_count_transm_lwb_s1 <= wb_trig_iface_ch15_count_transm_lwb_s0;
      wb_trig_iface_ch15_count_transm_lwb_s2 <= wb_trig_iface_ch15_count_transm_lwb_s1;
      if ((wb_trig_iface_ch15_count_transm_lwb_s1 = '1') and (wb_trig_iface_ch15_count_transm_lwb_s2 = '0')) then
        wb_trig_iface_ch15_count_transm_int <= regs_i.ch15_count_transm_i;
      end if;
    end if;
  end process;
  
  
-- Trigger Direction
  regs_o.ch16_ctl_dir_o <= wb_trig_iface_ch16_ctl_dir_int;
-- Trigger Direction Polarity
  regs_o.ch16_ctl_dir_pol_o <= wb_trig_iface_ch16_ctl_dir_pol_int;
-- Receiver Pulse Counter Reset
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      regs_o.ch16_ctl_rcv_count_rst_o <= '0';
      wb_trig_iface_ch16_ctl_rcv_count_rst_sync0 <= '0';
      wb_trig_iface_ch16_ctl_rcv_count_rst_sync1 <= '0';
      wb_trig_iface_ch16_ctl_rcv_count_rst_sync2 <= '0';
    elsif rising_edge(fs_clk_i) then
      wb_trig_iface_ch16_ctl_rcv_count_rst_sync0 <= wb_trig_iface_ch16_ctl_rcv_count_rst_int;
      wb_trig_iface_ch16_ctl_rcv_count_rst_sync1 <= wb_trig_iface_ch16_ctl_rcv_count_rst_sync0;
      wb_trig_iface_ch16_ctl_rcv_count_rst_sync2 <= wb_trig_iface_ch16_ctl_rcv_count_rst_sync1;
      regs_o.ch16_ctl_rcv_count_rst_o <= wb_trig_iface_ch16_ctl_rcv_count_rst_sync2 and (not wb_trig_iface_ch16_ctl_rcv_count_rst_sync1);
    end if;
  end process;
  
  
-- Transmitter Pulse Counter Reset
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      regs_o.ch16_ctl_transm_count_rst_o <= '0';
      wb_trig_iface_ch16_ctl_transm_count_rst_sync0 <= '0';
      wb_trig_iface_ch16_ctl_transm_count_rst_sync1 <= '0';
      wb_trig_iface_ch16_ctl_transm_count_rst_sync2 <= '0';
    elsif rising_edge(fs_clk_i) then
      wb_trig_iface_ch16_ctl_transm_count_rst_sync0 <= wb_trig_iface_ch16_ctl_transm_count_rst_int;
      wb_trig_iface_ch16_ctl_transm_count_rst_sync1 <= wb_trig_iface_ch16_ctl_transm_count_rst_sync0;
      wb_trig_iface_ch16_ctl_transm_count_rst_sync2 <= wb_trig_iface_ch16_ctl_transm_count_rst_sync1;
      regs_o.ch16_ctl_transm_count_rst_o <= wb_trig_iface_ch16_ctl_transm_count_rst_sync2 and (not wb_trig_iface_ch16_ctl_transm_count_rst_sync1);
    end if;
  end process;
  
  
-- Receiver Pulse Length
-- asynchronous std_logic_vector register : Receiver Pulse Length (type RW/RO, fs_clk_i <-> clk_sys_i)
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_trig_iface_ch16_cfg_rcv_len_swb_s0 <= '0';
      wb_trig_iface_ch16_cfg_rcv_len_swb_s1 <= '0';
      wb_trig_iface_ch16_cfg_rcv_len_swb_s2 <= '0';
      regs_o.ch16_cfg_rcv_len_o <= "00000000";
    elsif rising_edge(fs_clk_i) then
      wb_trig_iface_ch16_cfg_rcv_len_swb_s0 <= wb_trig_iface_ch16_cfg_rcv_len_swb;
      wb_trig_iface_ch16_cfg_rcv_len_swb_s1 <= wb_trig_iface_ch16_cfg_rcv_len_swb_s0;
      wb_trig_iface_ch16_cfg_rcv_len_swb_s2 <= wb_trig_iface_ch16_cfg_rcv_len_swb_s1;
      if ((wb_trig_iface_ch16_cfg_rcv_len_swb_s2 = '0') and (wb_trig_iface_ch16_cfg_rcv_len_swb_s1 = '1')) then
        regs_o.ch16_cfg_rcv_len_o <= wb_trig_iface_ch16_cfg_rcv_len_int;
      end if;
    end if;
  end process;
  
  
-- Transmitter Pulse Length
-- asynchronous std_logic_vector register : Transmitter Pulse Length (type RW/RO, fs_clk_i <-> clk_sys_i)
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_trig_iface_ch16_cfg_transm_len_swb_s0 <= '0';
      wb_trig_iface_ch16_cfg_transm_len_swb_s1 <= '0';
      wb_trig_iface_ch16_cfg_transm_len_swb_s2 <= '0';
      regs_o.ch16_cfg_transm_len_o <= "00000000";
    elsif rising_edge(fs_clk_i) then
      wb_trig_iface_ch16_cfg_transm_len_swb_s0 <= wb_trig_iface_ch16_cfg_transm_len_swb;
      wb_trig_iface_ch16_cfg_transm_len_swb_s1 <= wb_trig_iface_ch16_cfg_transm_len_swb_s0;
      wb_trig_iface_ch16_cfg_transm_len_swb_s2 <= wb_trig_iface_ch16_cfg_transm_len_swb_s1;
      if ((wb_trig_iface_ch16_cfg_transm_len_swb_s2 = '0') and (wb_trig_iface_ch16_cfg_transm_len_swb_s1 = '1')) then
        regs_o.ch16_cfg_transm_len_o <= wb_trig_iface_ch16_cfg_transm_len_int;
      end if;
    end if;
  end process;
  
  
-- Receiver Counter
-- asynchronous std_logic_vector register : Receiver Counter (type RO/WO, wb_clk_i <-> clk_sys_i)
  process (wb_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_trig_iface_ch16_count_rcv_lwb_s0 <= '0';
      wb_trig_iface_ch16_count_rcv_lwb_s1 <= '0';
      wb_trig_iface_ch16_count_rcv_lwb_s2 <= '0';
      wb_trig_iface_ch16_count_rcv_int <= "0000000000000000";
    elsif rising_edge(wb_clk_i) then
      wb_trig_iface_ch16_count_rcv_lwb_s0 <= wb_trig_iface_ch16_count_rcv_lwb;
      wb_trig_iface_ch16_count_rcv_lwb_s1 <= wb_trig_iface_ch16_count_rcv_lwb_s0;
      wb_trig_iface_ch16_count_rcv_lwb_s2 <= wb_trig_iface_ch16_count_rcv_lwb_s1;
      if ((wb_trig_iface_ch16_count_rcv_lwb_s1 = '1') and (wb_trig_iface_ch16_count_rcv_lwb_s2 = '0')) then
        wb_trig_iface_ch16_count_rcv_int <= regs_i.ch16_count_rcv_i;
      end if;
    end if;
  end process;
  
  
-- Transmitter Counter
-- asynchronous std_logic_vector register : Transmitter Counter (type RO/WO, wb_clk_i <-> clk_sys_i)
  process (wb_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_trig_iface_ch16_count_transm_lwb_s0 <= '0';
      wb_trig_iface_ch16_count_transm_lwb_s1 <= '0';
      wb_trig_iface_ch16_count_transm_lwb_s2 <= '0';
      wb_trig_iface_ch16_count_transm_int <= "0000000000000000";
    elsif rising_edge(wb_clk_i) then
      wb_trig_iface_ch16_count_transm_lwb_s0 <= wb_trig_iface_ch16_count_transm_lwb;
      wb_trig_iface_ch16_count_transm_lwb_s1 <= wb_trig_iface_ch16_count_transm_lwb_s0;
      wb_trig_iface_ch16_count_transm_lwb_s2 <= wb_trig_iface_ch16_count_transm_lwb_s1;
      if ((wb_trig_iface_ch16_count_transm_lwb_s1 = '1') and (wb_trig_iface_ch16_count_transm_lwb_s2 = '0')) then
        wb_trig_iface_ch16_count_transm_int <= regs_i.ch16_count_transm_i;
      end if;
    end if;
  end process;
  
  
-- Trigger Direction
  regs_o.ch17_ctl_dir_o <= wb_trig_iface_ch17_ctl_dir_int;
-- Trigger Direction Polarity
  regs_o.ch17_ctl_dir_pol_o <= wb_trig_iface_ch17_ctl_dir_pol_int;
-- Receiver Pulse Counter Reset
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      regs_o.ch17_ctl_rcv_count_rst_o <= '0';
      wb_trig_iface_ch17_ctl_rcv_count_rst_sync0 <= '0';
      wb_trig_iface_ch17_ctl_rcv_count_rst_sync1 <= '0';
      wb_trig_iface_ch17_ctl_rcv_count_rst_sync2 <= '0';
    elsif rising_edge(fs_clk_i) then
      wb_trig_iface_ch17_ctl_rcv_count_rst_sync0 <= wb_trig_iface_ch17_ctl_rcv_count_rst_int;
      wb_trig_iface_ch17_ctl_rcv_count_rst_sync1 <= wb_trig_iface_ch17_ctl_rcv_count_rst_sync0;
      wb_trig_iface_ch17_ctl_rcv_count_rst_sync2 <= wb_trig_iface_ch17_ctl_rcv_count_rst_sync1;
      regs_o.ch17_ctl_rcv_count_rst_o <= wb_trig_iface_ch17_ctl_rcv_count_rst_sync2 and (not wb_trig_iface_ch17_ctl_rcv_count_rst_sync1);
    end if;
  end process;
  
  
-- Transmitter Pulse Counter Reset
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      regs_o.ch17_ctl_transm_count_rst_o <= '0';
      wb_trig_iface_ch17_ctl_transm_count_rst_sync0 <= '0';
      wb_trig_iface_ch17_ctl_transm_count_rst_sync1 <= '0';
      wb_trig_iface_ch17_ctl_transm_count_rst_sync2 <= '0';
    elsif rising_edge(fs_clk_i) then
      wb_trig_iface_ch17_ctl_transm_count_rst_sync0 <= wb_trig_iface_ch17_ctl_transm_count_rst_int;
      wb_trig_iface_ch17_ctl_transm_count_rst_sync1 <= wb_trig_iface_ch17_ctl_transm_count_rst_sync0;
      wb_trig_iface_ch17_ctl_transm_count_rst_sync2 <= wb_trig_iface_ch17_ctl_transm_count_rst_sync1;
      regs_o.ch17_ctl_transm_count_rst_o <= wb_trig_iface_ch17_ctl_transm_count_rst_sync2 and (not wb_trig_iface_ch17_ctl_transm_count_rst_sync1);
    end if;
  end process;
  
  
-- Receiver Pulse Length
-- asynchronous std_logic_vector register : Receiver Pulse Length (type RW/RO, fs_clk_i <-> clk_sys_i)
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_trig_iface_ch17_cfg_rcv_len_swb_s0 <= '0';
      wb_trig_iface_ch17_cfg_rcv_len_swb_s1 <= '0';
      wb_trig_iface_ch17_cfg_rcv_len_swb_s2 <= '0';
      regs_o.ch17_cfg_rcv_len_o <= "00000000";
    elsif rising_edge(fs_clk_i) then
      wb_trig_iface_ch17_cfg_rcv_len_swb_s0 <= wb_trig_iface_ch17_cfg_rcv_len_swb;
      wb_trig_iface_ch17_cfg_rcv_len_swb_s1 <= wb_trig_iface_ch17_cfg_rcv_len_swb_s0;
      wb_trig_iface_ch17_cfg_rcv_len_swb_s2 <= wb_trig_iface_ch17_cfg_rcv_len_swb_s1;
      if ((wb_trig_iface_ch17_cfg_rcv_len_swb_s2 = '0') and (wb_trig_iface_ch17_cfg_rcv_len_swb_s1 = '1')) then
        regs_o.ch17_cfg_rcv_len_o <= wb_trig_iface_ch17_cfg_rcv_len_int;
      end if;
    end if;
  end process;
  
  
-- Transmitter Pulse Length
-- asynchronous std_logic_vector register : Transmitter Pulse Length (type RW/RO, fs_clk_i <-> clk_sys_i)
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_trig_iface_ch17_cfg_transm_len_swb_s0 <= '0';
      wb_trig_iface_ch17_cfg_transm_len_swb_s1 <= '0';
      wb_trig_iface_ch17_cfg_transm_len_swb_s2 <= '0';
      regs_o.ch17_cfg_transm_len_o <= "00000000";
    elsif rising_edge(fs_clk_i) then
      wb_trig_iface_ch17_cfg_transm_len_swb_s0 <= wb_trig_iface_ch17_cfg_transm_len_swb;
      wb_trig_iface_ch17_cfg_transm_len_swb_s1 <= wb_trig_iface_ch17_cfg_transm_len_swb_s0;
      wb_trig_iface_ch17_cfg_transm_len_swb_s2 <= wb_trig_iface_ch17_cfg_transm_len_swb_s1;
      if ((wb_trig_iface_ch17_cfg_transm_len_swb_s2 = '0') and (wb_trig_iface_ch17_cfg_transm_len_swb_s1 = '1')) then
        regs_o.ch17_cfg_transm_len_o <= wb_trig_iface_ch17_cfg_transm_len_int;
      end if;
    end if;
  end process;
  
  
-- Receiver Counter
-- asynchronous std_logic_vector register : Receiver Counter (type RO/WO, wb_clk_i <-> clk_sys_i)
  process (wb_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_trig_iface_ch17_count_rcv_lwb_s0 <= '0';
      wb_trig_iface_ch17_count_rcv_lwb_s1 <= '0';
      wb_trig_iface_ch17_count_rcv_lwb_s2 <= '0';
      wb_trig_iface_ch17_count_rcv_int <= "0000000000000000";
    elsif rising_edge(wb_clk_i) then
      wb_trig_iface_ch17_count_rcv_lwb_s0 <= wb_trig_iface_ch17_count_rcv_lwb;
      wb_trig_iface_ch17_count_rcv_lwb_s1 <= wb_trig_iface_ch17_count_rcv_lwb_s0;
      wb_trig_iface_ch17_count_rcv_lwb_s2 <= wb_trig_iface_ch17_count_rcv_lwb_s1;
      if ((wb_trig_iface_ch17_count_rcv_lwb_s1 = '1') and (wb_trig_iface_ch17_count_rcv_lwb_s2 = '0')) then
        wb_trig_iface_ch17_count_rcv_int <= regs_i.ch17_count_rcv_i;
      end if;
    end if;
  end process;
  
  
-- Transmitter Counter
-- asynchronous std_logic_vector register : Transmitter Counter (type RO/WO, wb_clk_i <-> clk_sys_i)
  process (wb_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_trig_iface_ch17_count_transm_lwb_s0 <= '0';
      wb_trig_iface_ch17_count_transm_lwb_s1 <= '0';
      wb_trig_iface_ch17_count_transm_lwb_s2 <= '0';
      wb_trig_iface_ch17_count_transm_int <= "0000000000000000";
    elsif rising_edge(wb_clk_i) then
      wb_trig_iface_ch17_count_transm_lwb_s0 <= wb_trig_iface_ch17_count_transm_lwb;
      wb_trig_iface_ch17_count_transm_lwb_s1 <= wb_trig_iface_ch17_count_transm_lwb_s0;
      wb_trig_iface_ch17_count_transm_lwb_s2 <= wb_trig_iface_ch17_count_transm_lwb_s1;
      if ((wb_trig_iface_ch17_count_transm_lwb_s1 = '1') and (wb_trig_iface_ch17_count_transm_lwb_s2 = '0')) then
        wb_trig_iface_ch17_count_transm_int <= regs_i.ch17_count_transm_i;
      end if;
    end if;
  end process;
  
  
-- Trigger Direction
  regs_o.ch18_ctl_dir_o <= wb_trig_iface_ch18_ctl_dir_int;
-- Trigger Direction Polarity
  regs_o.ch18_ctl_dir_pol_o <= wb_trig_iface_ch18_ctl_dir_pol_int;
-- Receiver Pulse Counter Reset
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      regs_o.ch18_ctl_rcv_count_rst_o <= '0';
      wb_trig_iface_ch18_ctl_rcv_count_rst_sync0 <= '0';
      wb_trig_iface_ch18_ctl_rcv_count_rst_sync1 <= '0';
      wb_trig_iface_ch18_ctl_rcv_count_rst_sync2 <= '0';
    elsif rising_edge(fs_clk_i) then
      wb_trig_iface_ch18_ctl_rcv_count_rst_sync0 <= wb_trig_iface_ch18_ctl_rcv_count_rst_int;
      wb_trig_iface_ch18_ctl_rcv_count_rst_sync1 <= wb_trig_iface_ch18_ctl_rcv_count_rst_sync0;
      wb_trig_iface_ch18_ctl_rcv_count_rst_sync2 <= wb_trig_iface_ch18_ctl_rcv_count_rst_sync1;
      regs_o.ch18_ctl_rcv_count_rst_o <= wb_trig_iface_ch18_ctl_rcv_count_rst_sync2 and (not wb_trig_iface_ch18_ctl_rcv_count_rst_sync1);
    end if;
  end process;
  
  
-- Transmitter Pulse Counter Reset
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      regs_o.ch18_ctl_transm_count_rst_o <= '0';
      wb_trig_iface_ch18_ctl_transm_count_rst_sync0 <= '0';
      wb_trig_iface_ch18_ctl_transm_count_rst_sync1 <= '0';
      wb_trig_iface_ch18_ctl_transm_count_rst_sync2 <= '0';
    elsif rising_edge(fs_clk_i) then
      wb_trig_iface_ch18_ctl_transm_count_rst_sync0 <= wb_trig_iface_ch18_ctl_transm_count_rst_int;
      wb_trig_iface_ch18_ctl_transm_count_rst_sync1 <= wb_trig_iface_ch18_ctl_transm_count_rst_sync0;
      wb_trig_iface_ch18_ctl_transm_count_rst_sync2 <= wb_trig_iface_ch18_ctl_transm_count_rst_sync1;
      regs_o.ch18_ctl_transm_count_rst_o <= wb_trig_iface_ch18_ctl_transm_count_rst_sync2 and (not wb_trig_iface_ch18_ctl_transm_count_rst_sync1);
    end if;
  end process;
  
  
-- Receiver Pulse Length
-- asynchronous std_logic_vector register : Receiver Pulse Length (type RW/RO, fs_clk_i <-> clk_sys_i)
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_trig_iface_ch18_cfg_rcv_len_swb_s0 <= '0';
      wb_trig_iface_ch18_cfg_rcv_len_swb_s1 <= '0';
      wb_trig_iface_ch18_cfg_rcv_len_swb_s2 <= '0';
      regs_o.ch18_cfg_rcv_len_o <= "00000000";
    elsif rising_edge(fs_clk_i) then
      wb_trig_iface_ch18_cfg_rcv_len_swb_s0 <= wb_trig_iface_ch18_cfg_rcv_len_swb;
      wb_trig_iface_ch18_cfg_rcv_len_swb_s1 <= wb_trig_iface_ch18_cfg_rcv_len_swb_s0;
      wb_trig_iface_ch18_cfg_rcv_len_swb_s2 <= wb_trig_iface_ch18_cfg_rcv_len_swb_s1;
      if ((wb_trig_iface_ch18_cfg_rcv_len_swb_s2 = '0') and (wb_trig_iface_ch18_cfg_rcv_len_swb_s1 = '1')) then
        regs_o.ch18_cfg_rcv_len_o <= wb_trig_iface_ch18_cfg_rcv_len_int;
      end if;
    end if;
  end process;
  
  
-- Transmitter Pulse Length
-- asynchronous std_logic_vector register : Transmitter Pulse Length (type RW/RO, fs_clk_i <-> clk_sys_i)
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_trig_iface_ch18_cfg_transm_len_swb_s0 <= '0';
      wb_trig_iface_ch18_cfg_transm_len_swb_s1 <= '0';
      wb_trig_iface_ch18_cfg_transm_len_swb_s2 <= '0';
      regs_o.ch18_cfg_transm_len_o <= "00000000";
    elsif rising_edge(fs_clk_i) then
      wb_trig_iface_ch18_cfg_transm_len_swb_s0 <= wb_trig_iface_ch18_cfg_transm_len_swb;
      wb_trig_iface_ch18_cfg_transm_len_swb_s1 <= wb_trig_iface_ch18_cfg_transm_len_swb_s0;
      wb_trig_iface_ch18_cfg_transm_len_swb_s2 <= wb_trig_iface_ch18_cfg_transm_len_swb_s1;
      if ((wb_trig_iface_ch18_cfg_transm_len_swb_s2 = '0') and (wb_trig_iface_ch18_cfg_transm_len_swb_s1 = '1')) then
        regs_o.ch18_cfg_transm_len_o <= wb_trig_iface_ch18_cfg_transm_len_int;
      end if;
    end if;
  end process;
  
  
-- Receiver Counter
-- asynchronous std_logic_vector register : Receiver Counter (type RO/WO, wb_clk_i <-> clk_sys_i)
  process (wb_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_trig_iface_ch18_count_rcv_lwb_s0 <= '0';
      wb_trig_iface_ch18_count_rcv_lwb_s1 <= '0';
      wb_trig_iface_ch18_count_rcv_lwb_s2 <= '0';
      wb_trig_iface_ch18_count_rcv_int <= "0000000000000000";
    elsif rising_edge(wb_clk_i) then
      wb_trig_iface_ch18_count_rcv_lwb_s0 <= wb_trig_iface_ch18_count_rcv_lwb;
      wb_trig_iface_ch18_count_rcv_lwb_s1 <= wb_trig_iface_ch18_count_rcv_lwb_s0;
      wb_trig_iface_ch18_count_rcv_lwb_s2 <= wb_trig_iface_ch18_count_rcv_lwb_s1;
      if ((wb_trig_iface_ch18_count_rcv_lwb_s1 = '1') and (wb_trig_iface_ch18_count_rcv_lwb_s2 = '0')) then
        wb_trig_iface_ch18_count_rcv_int <= regs_i.ch18_count_rcv_i;
      end if;
    end if;
  end process;
  
  
-- Transmitter Counter
-- asynchronous std_logic_vector register : Transmitter Counter (type RO/WO, wb_clk_i <-> clk_sys_i)
  process (wb_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_trig_iface_ch18_count_transm_lwb_s0 <= '0';
      wb_trig_iface_ch18_count_transm_lwb_s1 <= '0';
      wb_trig_iface_ch18_count_transm_lwb_s2 <= '0';
      wb_trig_iface_ch18_count_transm_int <= "0000000000000000";
    elsif rising_edge(wb_clk_i) then
      wb_trig_iface_ch18_count_transm_lwb_s0 <= wb_trig_iface_ch18_count_transm_lwb;
      wb_trig_iface_ch18_count_transm_lwb_s1 <= wb_trig_iface_ch18_count_transm_lwb_s0;
      wb_trig_iface_ch18_count_transm_lwb_s2 <= wb_trig_iface_ch18_count_transm_lwb_s1;
      if ((wb_trig_iface_ch18_count_transm_lwb_s1 = '1') and (wb_trig_iface_ch18_count_transm_lwb_s2 = '0')) then
        wb_trig_iface_ch18_count_transm_int <= regs_i.ch18_count_transm_i;
      end if;
    end if;
  end process;
  
  
-- Trigger Direction
  regs_o.ch19_ctl_dir_o <= wb_trig_iface_ch19_ctl_dir_int;
-- Trigger Direction Polarity
  regs_o.ch19_ctl_dir_pol_o <= wb_trig_iface_ch19_ctl_dir_pol_int;
-- Receiver Pulse Counter Reset
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      regs_o.ch19_ctl_rcv_count_rst_o <= '0';
      wb_trig_iface_ch19_ctl_rcv_count_rst_sync0 <= '0';
      wb_trig_iface_ch19_ctl_rcv_count_rst_sync1 <= '0';
      wb_trig_iface_ch19_ctl_rcv_count_rst_sync2 <= '0';
    elsif rising_edge(fs_clk_i) then
      wb_trig_iface_ch19_ctl_rcv_count_rst_sync0 <= wb_trig_iface_ch19_ctl_rcv_count_rst_int;
      wb_trig_iface_ch19_ctl_rcv_count_rst_sync1 <= wb_trig_iface_ch19_ctl_rcv_count_rst_sync0;
      wb_trig_iface_ch19_ctl_rcv_count_rst_sync2 <= wb_trig_iface_ch19_ctl_rcv_count_rst_sync1;
      regs_o.ch19_ctl_rcv_count_rst_o <= wb_trig_iface_ch19_ctl_rcv_count_rst_sync2 and (not wb_trig_iface_ch19_ctl_rcv_count_rst_sync1);
    end if;
  end process;
  
  
-- Transmitter Pulse Counter Reset
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      regs_o.ch19_ctl_transm_count_rst_o <= '0';
      wb_trig_iface_ch19_ctl_transm_count_rst_sync0 <= '0';
      wb_trig_iface_ch19_ctl_transm_count_rst_sync1 <= '0';
      wb_trig_iface_ch19_ctl_transm_count_rst_sync2 <= '0';
    elsif rising_edge(fs_clk_i) then
      wb_trig_iface_ch19_ctl_transm_count_rst_sync0 <= wb_trig_iface_ch19_ctl_transm_count_rst_int;
      wb_trig_iface_ch19_ctl_transm_count_rst_sync1 <= wb_trig_iface_ch19_ctl_transm_count_rst_sync0;
      wb_trig_iface_ch19_ctl_transm_count_rst_sync2 <= wb_trig_iface_ch19_ctl_transm_count_rst_sync1;
      regs_o.ch19_ctl_transm_count_rst_o <= wb_trig_iface_ch19_ctl_transm_count_rst_sync2 and (not wb_trig_iface_ch19_ctl_transm_count_rst_sync1);
    end if;
  end process;
  
  
-- Receiver Pulse Length
-- asynchronous std_logic_vector register : Receiver Pulse Length (type RW/RO, fs_clk_i <-> clk_sys_i)
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_trig_iface_ch19_cfg_rcv_len_swb_s0 <= '0';
      wb_trig_iface_ch19_cfg_rcv_len_swb_s1 <= '0';
      wb_trig_iface_ch19_cfg_rcv_len_swb_s2 <= '0';
      regs_o.ch19_cfg_rcv_len_o <= "00000000";
    elsif rising_edge(fs_clk_i) then
      wb_trig_iface_ch19_cfg_rcv_len_swb_s0 <= wb_trig_iface_ch19_cfg_rcv_len_swb;
      wb_trig_iface_ch19_cfg_rcv_len_swb_s1 <= wb_trig_iface_ch19_cfg_rcv_len_swb_s0;
      wb_trig_iface_ch19_cfg_rcv_len_swb_s2 <= wb_trig_iface_ch19_cfg_rcv_len_swb_s1;
      if ((wb_trig_iface_ch19_cfg_rcv_len_swb_s2 = '0') and (wb_trig_iface_ch19_cfg_rcv_len_swb_s1 = '1')) then
        regs_o.ch19_cfg_rcv_len_o <= wb_trig_iface_ch19_cfg_rcv_len_int;
      end if;
    end if;
  end process;
  
  
-- Transmitter Pulse Length
-- asynchronous std_logic_vector register : Transmitter Pulse Length (type RW/RO, fs_clk_i <-> clk_sys_i)
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_trig_iface_ch19_cfg_transm_len_swb_s0 <= '0';
      wb_trig_iface_ch19_cfg_transm_len_swb_s1 <= '0';
      wb_trig_iface_ch19_cfg_transm_len_swb_s2 <= '0';
      regs_o.ch19_cfg_transm_len_o <= "00000000";
    elsif rising_edge(fs_clk_i) then
      wb_trig_iface_ch19_cfg_transm_len_swb_s0 <= wb_trig_iface_ch19_cfg_transm_len_swb;
      wb_trig_iface_ch19_cfg_transm_len_swb_s1 <= wb_trig_iface_ch19_cfg_transm_len_swb_s0;
      wb_trig_iface_ch19_cfg_transm_len_swb_s2 <= wb_trig_iface_ch19_cfg_transm_len_swb_s1;
      if ((wb_trig_iface_ch19_cfg_transm_len_swb_s2 = '0') and (wb_trig_iface_ch19_cfg_transm_len_swb_s1 = '1')) then
        regs_o.ch19_cfg_transm_len_o <= wb_trig_iface_ch19_cfg_transm_len_int;
      end if;
    end if;
  end process;
  
  
-- Receiver Counter
-- asynchronous std_logic_vector register : Receiver Counter (type RO/WO, wb_clk_i <-> clk_sys_i)
  process (wb_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_trig_iface_ch19_count_rcv_lwb_s0 <= '0';
      wb_trig_iface_ch19_count_rcv_lwb_s1 <= '0';
      wb_trig_iface_ch19_count_rcv_lwb_s2 <= '0';
      wb_trig_iface_ch19_count_rcv_int <= "0000000000000000";
    elsif rising_edge(wb_clk_i) then
      wb_trig_iface_ch19_count_rcv_lwb_s0 <= wb_trig_iface_ch19_count_rcv_lwb;
      wb_trig_iface_ch19_count_rcv_lwb_s1 <= wb_trig_iface_ch19_count_rcv_lwb_s0;
      wb_trig_iface_ch19_count_rcv_lwb_s2 <= wb_trig_iface_ch19_count_rcv_lwb_s1;
      if ((wb_trig_iface_ch19_count_rcv_lwb_s1 = '1') and (wb_trig_iface_ch19_count_rcv_lwb_s2 = '0')) then
        wb_trig_iface_ch19_count_rcv_int <= regs_i.ch19_count_rcv_i;
      end if;
    end if;
  end process;
  
  
-- Transmitter Counter
-- asynchronous std_logic_vector register : Transmitter Counter (type RO/WO, wb_clk_i <-> clk_sys_i)
  process (wb_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_trig_iface_ch19_count_transm_lwb_s0 <= '0';
      wb_trig_iface_ch19_count_transm_lwb_s1 <= '0';
      wb_trig_iface_ch19_count_transm_lwb_s2 <= '0';
      wb_trig_iface_ch19_count_transm_int <= "0000000000000000";
    elsif rising_edge(wb_clk_i) then
      wb_trig_iface_ch19_count_transm_lwb_s0 <= wb_trig_iface_ch19_count_transm_lwb;
      wb_trig_iface_ch19_count_transm_lwb_s1 <= wb_trig_iface_ch19_count_transm_lwb_s0;
      wb_trig_iface_ch19_count_transm_lwb_s2 <= wb_trig_iface_ch19_count_transm_lwb_s1;
      if ((wb_trig_iface_ch19_count_transm_lwb_s1 = '1') and (wb_trig_iface_ch19_count_transm_lwb_s2 = '0')) then
        wb_trig_iface_ch19_count_transm_int <= regs_i.ch19_count_transm_i;
      end if;
    end if;
  end process;
  
  
-- Trigger Direction
  regs_o.ch20_ctl_dir_o <= wb_trig_iface_ch20_ctl_dir_int;
-- Trigger Direction Polarity
  regs_o.ch20_ctl_dir_pol_o <= wb_trig_iface_ch20_ctl_dir_pol_int;
-- Receiver Pulse Counter Reset
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      regs_o.ch20_ctl_rcv_count_rst_o <= '0';
      wb_trig_iface_ch20_ctl_rcv_count_rst_sync0 <= '0';
      wb_trig_iface_ch20_ctl_rcv_count_rst_sync1 <= '0';
      wb_trig_iface_ch20_ctl_rcv_count_rst_sync2 <= '0';
    elsif rising_edge(fs_clk_i) then
      wb_trig_iface_ch20_ctl_rcv_count_rst_sync0 <= wb_trig_iface_ch20_ctl_rcv_count_rst_int;
      wb_trig_iface_ch20_ctl_rcv_count_rst_sync1 <= wb_trig_iface_ch20_ctl_rcv_count_rst_sync0;
      wb_trig_iface_ch20_ctl_rcv_count_rst_sync2 <= wb_trig_iface_ch20_ctl_rcv_count_rst_sync1;
      regs_o.ch20_ctl_rcv_count_rst_o <= wb_trig_iface_ch20_ctl_rcv_count_rst_sync2 and (not wb_trig_iface_ch20_ctl_rcv_count_rst_sync1);
    end if;
  end process;
  
  
-- Transmitter Pulse Counter Reset
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      regs_o.ch20_ctl_transm_count_rst_o <= '0';
      wb_trig_iface_ch20_ctl_transm_count_rst_sync0 <= '0';
      wb_trig_iface_ch20_ctl_transm_count_rst_sync1 <= '0';
      wb_trig_iface_ch20_ctl_transm_count_rst_sync2 <= '0';
    elsif rising_edge(fs_clk_i) then
      wb_trig_iface_ch20_ctl_transm_count_rst_sync0 <= wb_trig_iface_ch20_ctl_transm_count_rst_int;
      wb_trig_iface_ch20_ctl_transm_count_rst_sync1 <= wb_trig_iface_ch20_ctl_transm_count_rst_sync0;
      wb_trig_iface_ch20_ctl_transm_count_rst_sync2 <= wb_trig_iface_ch20_ctl_transm_count_rst_sync1;
      regs_o.ch20_ctl_transm_count_rst_o <= wb_trig_iface_ch20_ctl_transm_count_rst_sync2 and (not wb_trig_iface_ch20_ctl_transm_count_rst_sync1);
    end if;
  end process;
  
  
-- Receiver Pulse Length
-- asynchronous std_logic_vector register : Receiver Pulse Length (type RW/RO, fs_clk_i <-> clk_sys_i)
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_trig_iface_ch20_cfg_rcv_len_swb_s0 <= '0';
      wb_trig_iface_ch20_cfg_rcv_len_swb_s1 <= '0';
      wb_trig_iface_ch20_cfg_rcv_len_swb_s2 <= '0';
      regs_o.ch20_cfg_rcv_len_o <= "00000000";
    elsif rising_edge(fs_clk_i) then
      wb_trig_iface_ch20_cfg_rcv_len_swb_s0 <= wb_trig_iface_ch20_cfg_rcv_len_swb;
      wb_trig_iface_ch20_cfg_rcv_len_swb_s1 <= wb_trig_iface_ch20_cfg_rcv_len_swb_s0;
      wb_trig_iface_ch20_cfg_rcv_len_swb_s2 <= wb_trig_iface_ch20_cfg_rcv_len_swb_s1;
      if ((wb_trig_iface_ch20_cfg_rcv_len_swb_s2 = '0') and (wb_trig_iface_ch20_cfg_rcv_len_swb_s1 = '1')) then
        regs_o.ch20_cfg_rcv_len_o <= wb_trig_iface_ch20_cfg_rcv_len_int;
      end if;
    end if;
  end process;
  
  
-- Transmitter Pulse Length
-- asynchronous std_logic_vector register : Transmitter Pulse Length (type RW/RO, fs_clk_i <-> clk_sys_i)
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_trig_iface_ch20_cfg_transm_len_swb_s0 <= '0';
      wb_trig_iface_ch20_cfg_transm_len_swb_s1 <= '0';
      wb_trig_iface_ch20_cfg_transm_len_swb_s2 <= '0';
      regs_o.ch20_cfg_transm_len_o <= "00000000";
    elsif rising_edge(fs_clk_i) then
      wb_trig_iface_ch20_cfg_transm_len_swb_s0 <= wb_trig_iface_ch20_cfg_transm_len_swb;
      wb_trig_iface_ch20_cfg_transm_len_swb_s1 <= wb_trig_iface_ch20_cfg_transm_len_swb_s0;
      wb_trig_iface_ch20_cfg_transm_len_swb_s2 <= wb_trig_iface_ch20_cfg_transm_len_swb_s1;
      if ((wb_trig_iface_ch20_cfg_transm_len_swb_s2 = '0') and (wb_trig_iface_ch20_cfg_transm_len_swb_s1 = '1')) then
        regs_o.ch20_cfg_transm_len_o <= wb_trig_iface_ch20_cfg_transm_len_int;
      end if;
    end if;
  end process;
  
  
-- Receiver Counter
-- asynchronous std_logic_vector register : Receiver Counter (type RO/WO, wb_clk_i <-> clk_sys_i)
  process (wb_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_trig_iface_ch20_count_rcv_lwb_s0 <= '0';
      wb_trig_iface_ch20_count_rcv_lwb_s1 <= '0';
      wb_trig_iface_ch20_count_rcv_lwb_s2 <= '0';
      wb_trig_iface_ch20_count_rcv_int <= "0000000000000000";
    elsif rising_edge(wb_clk_i) then
      wb_trig_iface_ch20_count_rcv_lwb_s0 <= wb_trig_iface_ch20_count_rcv_lwb;
      wb_trig_iface_ch20_count_rcv_lwb_s1 <= wb_trig_iface_ch20_count_rcv_lwb_s0;
      wb_trig_iface_ch20_count_rcv_lwb_s2 <= wb_trig_iface_ch20_count_rcv_lwb_s1;
      if ((wb_trig_iface_ch20_count_rcv_lwb_s1 = '1') and (wb_trig_iface_ch20_count_rcv_lwb_s2 = '0')) then
        wb_trig_iface_ch20_count_rcv_int <= regs_i.ch20_count_rcv_i;
      end if;
    end if;
  end process;
  
  
-- Transmitter Counter
-- asynchronous std_logic_vector register : Transmitter Counter (type RO/WO, wb_clk_i <-> clk_sys_i)
  process (wb_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_trig_iface_ch20_count_transm_lwb_s0 <= '0';
      wb_trig_iface_ch20_count_transm_lwb_s1 <= '0';
      wb_trig_iface_ch20_count_transm_lwb_s2 <= '0';
      wb_trig_iface_ch20_count_transm_int <= "0000000000000000";
    elsif rising_edge(wb_clk_i) then
      wb_trig_iface_ch20_count_transm_lwb_s0 <= wb_trig_iface_ch20_count_transm_lwb;
      wb_trig_iface_ch20_count_transm_lwb_s1 <= wb_trig_iface_ch20_count_transm_lwb_s0;
      wb_trig_iface_ch20_count_transm_lwb_s2 <= wb_trig_iface_ch20_count_transm_lwb_s1;
      if ((wb_trig_iface_ch20_count_transm_lwb_s1 = '1') and (wb_trig_iface_ch20_count_transm_lwb_s2 = '0')) then
        wb_trig_iface_ch20_count_transm_int <= regs_i.ch20_count_transm_i;
      end if;
    end if;
  end process;
  
  
-- Trigger Direction
  regs_o.ch21_ctl_dir_o <= wb_trig_iface_ch21_ctl_dir_int;
-- Trigger Direction Polarity
  regs_o.ch21_ctl_dir_pol_o <= wb_trig_iface_ch21_ctl_dir_pol_int;
-- Receiver Pulse Counter Reset
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      regs_o.ch21_ctl_rcv_count_rst_o <= '0';
      wb_trig_iface_ch21_ctl_rcv_count_rst_sync0 <= '0';
      wb_trig_iface_ch21_ctl_rcv_count_rst_sync1 <= '0';
      wb_trig_iface_ch21_ctl_rcv_count_rst_sync2 <= '0';
    elsif rising_edge(fs_clk_i) then
      wb_trig_iface_ch21_ctl_rcv_count_rst_sync0 <= wb_trig_iface_ch21_ctl_rcv_count_rst_int;
      wb_trig_iface_ch21_ctl_rcv_count_rst_sync1 <= wb_trig_iface_ch21_ctl_rcv_count_rst_sync0;
      wb_trig_iface_ch21_ctl_rcv_count_rst_sync2 <= wb_trig_iface_ch21_ctl_rcv_count_rst_sync1;
      regs_o.ch21_ctl_rcv_count_rst_o <= wb_trig_iface_ch21_ctl_rcv_count_rst_sync2 and (not wb_trig_iface_ch21_ctl_rcv_count_rst_sync1);
    end if;
  end process;
  
  
-- Transmitter Pulse Counter Reset
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      regs_o.ch21_ctl_transm_count_rst_o <= '0';
      wb_trig_iface_ch21_ctl_transm_count_rst_sync0 <= '0';
      wb_trig_iface_ch21_ctl_transm_count_rst_sync1 <= '0';
      wb_trig_iface_ch21_ctl_transm_count_rst_sync2 <= '0';
    elsif rising_edge(fs_clk_i) then
      wb_trig_iface_ch21_ctl_transm_count_rst_sync0 <= wb_trig_iface_ch21_ctl_transm_count_rst_int;
      wb_trig_iface_ch21_ctl_transm_count_rst_sync1 <= wb_trig_iface_ch21_ctl_transm_count_rst_sync0;
      wb_trig_iface_ch21_ctl_transm_count_rst_sync2 <= wb_trig_iface_ch21_ctl_transm_count_rst_sync1;
      regs_o.ch21_ctl_transm_count_rst_o <= wb_trig_iface_ch21_ctl_transm_count_rst_sync2 and (not wb_trig_iface_ch21_ctl_transm_count_rst_sync1);
    end if;
  end process;
  
  
-- Receiver Pulse Length
-- asynchronous std_logic_vector register : Receiver Pulse Length (type RW/RO, fs_clk_i <-> clk_sys_i)
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_trig_iface_ch21_cfg_rcv_len_swb_s0 <= '0';
      wb_trig_iface_ch21_cfg_rcv_len_swb_s1 <= '0';
      wb_trig_iface_ch21_cfg_rcv_len_swb_s2 <= '0';
      regs_o.ch21_cfg_rcv_len_o <= "00000000";
    elsif rising_edge(fs_clk_i) then
      wb_trig_iface_ch21_cfg_rcv_len_swb_s0 <= wb_trig_iface_ch21_cfg_rcv_len_swb;
      wb_trig_iface_ch21_cfg_rcv_len_swb_s1 <= wb_trig_iface_ch21_cfg_rcv_len_swb_s0;
      wb_trig_iface_ch21_cfg_rcv_len_swb_s2 <= wb_trig_iface_ch21_cfg_rcv_len_swb_s1;
      if ((wb_trig_iface_ch21_cfg_rcv_len_swb_s2 = '0') and (wb_trig_iface_ch21_cfg_rcv_len_swb_s1 = '1')) then
        regs_o.ch21_cfg_rcv_len_o <= wb_trig_iface_ch21_cfg_rcv_len_int;
      end if;
    end if;
  end process;
  
  
-- Transmitter Pulse Length
-- asynchronous std_logic_vector register : Transmitter Pulse Length (type RW/RO, fs_clk_i <-> clk_sys_i)
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_trig_iface_ch21_cfg_transm_len_swb_s0 <= '0';
      wb_trig_iface_ch21_cfg_transm_len_swb_s1 <= '0';
      wb_trig_iface_ch21_cfg_transm_len_swb_s2 <= '0';
      regs_o.ch21_cfg_transm_len_o <= "00000000";
    elsif rising_edge(fs_clk_i) then
      wb_trig_iface_ch21_cfg_transm_len_swb_s0 <= wb_trig_iface_ch21_cfg_transm_len_swb;
      wb_trig_iface_ch21_cfg_transm_len_swb_s1 <= wb_trig_iface_ch21_cfg_transm_len_swb_s0;
      wb_trig_iface_ch21_cfg_transm_len_swb_s2 <= wb_trig_iface_ch21_cfg_transm_len_swb_s1;
      if ((wb_trig_iface_ch21_cfg_transm_len_swb_s2 = '0') and (wb_trig_iface_ch21_cfg_transm_len_swb_s1 = '1')) then
        regs_o.ch21_cfg_transm_len_o <= wb_trig_iface_ch21_cfg_transm_len_int;
      end if;
    end if;
  end process;
  
  
-- Receiver Counter
-- asynchronous std_logic_vector register : Receiver Counter (type RO/WO, wb_clk_i <-> clk_sys_i)
  process (wb_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_trig_iface_ch21_count_rcv_lwb_s0 <= '0';
      wb_trig_iface_ch21_count_rcv_lwb_s1 <= '0';
      wb_trig_iface_ch21_count_rcv_lwb_s2 <= '0';
      wb_trig_iface_ch21_count_rcv_int <= "0000000000000000";
    elsif rising_edge(wb_clk_i) then
      wb_trig_iface_ch21_count_rcv_lwb_s0 <= wb_trig_iface_ch21_count_rcv_lwb;
      wb_trig_iface_ch21_count_rcv_lwb_s1 <= wb_trig_iface_ch21_count_rcv_lwb_s0;
      wb_trig_iface_ch21_count_rcv_lwb_s2 <= wb_trig_iface_ch21_count_rcv_lwb_s1;
      if ((wb_trig_iface_ch21_count_rcv_lwb_s1 = '1') and (wb_trig_iface_ch21_count_rcv_lwb_s2 = '0')) then
        wb_trig_iface_ch21_count_rcv_int <= regs_i.ch21_count_rcv_i;
      end if;
    end if;
  end process;
  
  
-- Transmitter Counter
-- asynchronous std_logic_vector register : Transmitter Counter (type RO/WO, wb_clk_i <-> clk_sys_i)
  process (wb_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_trig_iface_ch21_count_transm_lwb_s0 <= '0';
      wb_trig_iface_ch21_count_transm_lwb_s1 <= '0';
      wb_trig_iface_ch21_count_transm_lwb_s2 <= '0';
      wb_trig_iface_ch21_count_transm_int <= "0000000000000000";
    elsif rising_edge(wb_clk_i) then
      wb_trig_iface_ch21_count_transm_lwb_s0 <= wb_trig_iface_ch21_count_transm_lwb;
      wb_trig_iface_ch21_count_transm_lwb_s1 <= wb_trig_iface_ch21_count_transm_lwb_s0;
      wb_trig_iface_ch21_count_transm_lwb_s2 <= wb_trig_iface_ch21_count_transm_lwb_s1;
      if ((wb_trig_iface_ch21_count_transm_lwb_s1 = '1') and (wb_trig_iface_ch21_count_transm_lwb_s2 = '0')) then
        wb_trig_iface_ch21_count_transm_int <= regs_i.ch21_count_transm_i;
      end if;
    end if;
  end process;
  
  
-- Trigger Direction
  regs_o.ch22_ctl_dir_o <= wb_trig_iface_ch22_ctl_dir_int;
-- Trigger Direction Polarity
  regs_o.ch22_ctl_dir_pol_o <= wb_trig_iface_ch22_ctl_dir_pol_int;
-- Receiver Pulse Counter Reset
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      regs_o.ch22_ctl_rcv_count_rst_o <= '0';
      wb_trig_iface_ch22_ctl_rcv_count_rst_sync0 <= '0';
      wb_trig_iface_ch22_ctl_rcv_count_rst_sync1 <= '0';
      wb_trig_iface_ch22_ctl_rcv_count_rst_sync2 <= '0';
    elsif rising_edge(fs_clk_i) then
      wb_trig_iface_ch22_ctl_rcv_count_rst_sync0 <= wb_trig_iface_ch22_ctl_rcv_count_rst_int;
      wb_trig_iface_ch22_ctl_rcv_count_rst_sync1 <= wb_trig_iface_ch22_ctl_rcv_count_rst_sync0;
      wb_trig_iface_ch22_ctl_rcv_count_rst_sync2 <= wb_trig_iface_ch22_ctl_rcv_count_rst_sync1;
      regs_o.ch22_ctl_rcv_count_rst_o <= wb_trig_iface_ch22_ctl_rcv_count_rst_sync2 and (not wb_trig_iface_ch22_ctl_rcv_count_rst_sync1);
    end if;
  end process;
  
  
-- Transmitter Pulse Counter Reset
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      regs_o.ch22_ctl_transm_count_rst_o <= '0';
      wb_trig_iface_ch22_ctl_transm_count_rst_sync0 <= '0';
      wb_trig_iface_ch22_ctl_transm_count_rst_sync1 <= '0';
      wb_trig_iface_ch22_ctl_transm_count_rst_sync2 <= '0';
    elsif rising_edge(fs_clk_i) then
      wb_trig_iface_ch22_ctl_transm_count_rst_sync0 <= wb_trig_iface_ch22_ctl_transm_count_rst_int;
      wb_trig_iface_ch22_ctl_transm_count_rst_sync1 <= wb_trig_iface_ch22_ctl_transm_count_rst_sync0;
      wb_trig_iface_ch22_ctl_transm_count_rst_sync2 <= wb_trig_iface_ch22_ctl_transm_count_rst_sync1;
      regs_o.ch22_ctl_transm_count_rst_o <= wb_trig_iface_ch22_ctl_transm_count_rst_sync2 and (not wb_trig_iface_ch22_ctl_transm_count_rst_sync1);
    end if;
  end process;
  
  
-- Receiver Pulse Length
-- asynchronous std_logic_vector register : Receiver Pulse Length (type RW/RO, fs_clk_i <-> clk_sys_i)
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_trig_iface_ch22_cfg_rcv_len_swb_s0 <= '0';
      wb_trig_iface_ch22_cfg_rcv_len_swb_s1 <= '0';
      wb_trig_iface_ch22_cfg_rcv_len_swb_s2 <= '0';
      regs_o.ch22_cfg_rcv_len_o <= "00000000";
    elsif rising_edge(fs_clk_i) then
      wb_trig_iface_ch22_cfg_rcv_len_swb_s0 <= wb_trig_iface_ch22_cfg_rcv_len_swb;
      wb_trig_iface_ch22_cfg_rcv_len_swb_s1 <= wb_trig_iface_ch22_cfg_rcv_len_swb_s0;
      wb_trig_iface_ch22_cfg_rcv_len_swb_s2 <= wb_trig_iface_ch22_cfg_rcv_len_swb_s1;
      if ((wb_trig_iface_ch22_cfg_rcv_len_swb_s2 = '0') and (wb_trig_iface_ch22_cfg_rcv_len_swb_s1 = '1')) then
        regs_o.ch22_cfg_rcv_len_o <= wb_trig_iface_ch22_cfg_rcv_len_int;
      end if;
    end if;
  end process;
  
  
-- Transmitter Pulse Length
-- asynchronous std_logic_vector register : Transmitter Pulse Length (type RW/RO, fs_clk_i <-> clk_sys_i)
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_trig_iface_ch22_cfg_transm_len_swb_s0 <= '0';
      wb_trig_iface_ch22_cfg_transm_len_swb_s1 <= '0';
      wb_trig_iface_ch22_cfg_transm_len_swb_s2 <= '0';
      regs_o.ch22_cfg_transm_len_o <= "00000000";
    elsif rising_edge(fs_clk_i) then
      wb_trig_iface_ch22_cfg_transm_len_swb_s0 <= wb_trig_iface_ch22_cfg_transm_len_swb;
      wb_trig_iface_ch22_cfg_transm_len_swb_s1 <= wb_trig_iface_ch22_cfg_transm_len_swb_s0;
      wb_trig_iface_ch22_cfg_transm_len_swb_s2 <= wb_trig_iface_ch22_cfg_transm_len_swb_s1;
      if ((wb_trig_iface_ch22_cfg_transm_len_swb_s2 = '0') and (wb_trig_iface_ch22_cfg_transm_len_swb_s1 = '1')) then
        regs_o.ch22_cfg_transm_len_o <= wb_trig_iface_ch22_cfg_transm_len_int;
      end if;
    end if;
  end process;
  
  
-- Receiver Counter
-- asynchronous std_logic_vector register : Receiver Counter (type RO/WO, wb_clk_i <-> clk_sys_i)
  process (wb_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_trig_iface_ch22_count_rcv_lwb_s0 <= '0';
      wb_trig_iface_ch22_count_rcv_lwb_s1 <= '0';
      wb_trig_iface_ch22_count_rcv_lwb_s2 <= '0';
      wb_trig_iface_ch22_count_rcv_int <= "0000000000000000";
    elsif rising_edge(wb_clk_i) then
      wb_trig_iface_ch22_count_rcv_lwb_s0 <= wb_trig_iface_ch22_count_rcv_lwb;
      wb_trig_iface_ch22_count_rcv_lwb_s1 <= wb_trig_iface_ch22_count_rcv_lwb_s0;
      wb_trig_iface_ch22_count_rcv_lwb_s2 <= wb_trig_iface_ch22_count_rcv_lwb_s1;
      if ((wb_trig_iface_ch22_count_rcv_lwb_s1 = '1') and (wb_trig_iface_ch22_count_rcv_lwb_s2 = '0')) then
        wb_trig_iface_ch22_count_rcv_int <= regs_i.ch22_count_rcv_i;
      end if;
    end if;
  end process;
  
  
-- Transmitter Counter
-- asynchronous std_logic_vector register : Transmitter Counter (type RO/WO, wb_clk_i <-> clk_sys_i)
  process (wb_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_trig_iface_ch22_count_transm_lwb_s0 <= '0';
      wb_trig_iface_ch22_count_transm_lwb_s1 <= '0';
      wb_trig_iface_ch22_count_transm_lwb_s2 <= '0';
      wb_trig_iface_ch22_count_transm_int <= "0000000000000000";
    elsif rising_edge(wb_clk_i) then
      wb_trig_iface_ch22_count_transm_lwb_s0 <= wb_trig_iface_ch22_count_transm_lwb;
      wb_trig_iface_ch22_count_transm_lwb_s1 <= wb_trig_iface_ch22_count_transm_lwb_s0;
      wb_trig_iface_ch22_count_transm_lwb_s2 <= wb_trig_iface_ch22_count_transm_lwb_s1;
      if ((wb_trig_iface_ch22_count_transm_lwb_s1 = '1') and (wb_trig_iface_ch22_count_transm_lwb_s2 = '0')) then
        wb_trig_iface_ch22_count_transm_int <= regs_i.ch22_count_transm_i;
      end if;
    end if;
  end process;
  
  
-- Trigger Direction
  regs_o.ch23_ctl_dir_o <= wb_trig_iface_ch23_ctl_dir_int;
-- Trigger Direction Polarity
  regs_o.ch23_ctl_dir_pol_o <= wb_trig_iface_ch23_ctl_dir_pol_int;
-- Receiver Pulse Counter Reset
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      regs_o.ch23_ctl_rcv_count_rst_o <= '0';
      wb_trig_iface_ch23_ctl_rcv_count_rst_sync0 <= '0';
      wb_trig_iface_ch23_ctl_rcv_count_rst_sync1 <= '0';
      wb_trig_iface_ch23_ctl_rcv_count_rst_sync2 <= '0';
    elsif rising_edge(fs_clk_i) then
      wb_trig_iface_ch23_ctl_rcv_count_rst_sync0 <= wb_trig_iface_ch23_ctl_rcv_count_rst_int;
      wb_trig_iface_ch23_ctl_rcv_count_rst_sync1 <= wb_trig_iface_ch23_ctl_rcv_count_rst_sync0;
      wb_trig_iface_ch23_ctl_rcv_count_rst_sync2 <= wb_trig_iface_ch23_ctl_rcv_count_rst_sync1;
      regs_o.ch23_ctl_rcv_count_rst_o <= wb_trig_iface_ch23_ctl_rcv_count_rst_sync2 and (not wb_trig_iface_ch23_ctl_rcv_count_rst_sync1);
    end if;
  end process;
  
  
-- Transmitter Pulse Counter Reset
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      regs_o.ch23_ctl_transm_count_rst_o <= '0';
      wb_trig_iface_ch23_ctl_transm_count_rst_sync0 <= '0';
      wb_trig_iface_ch23_ctl_transm_count_rst_sync1 <= '0';
      wb_trig_iface_ch23_ctl_transm_count_rst_sync2 <= '0';
    elsif rising_edge(fs_clk_i) then
      wb_trig_iface_ch23_ctl_transm_count_rst_sync0 <= wb_trig_iface_ch23_ctl_transm_count_rst_int;
      wb_trig_iface_ch23_ctl_transm_count_rst_sync1 <= wb_trig_iface_ch23_ctl_transm_count_rst_sync0;
      wb_trig_iface_ch23_ctl_transm_count_rst_sync2 <= wb_trig_iface_ch23_ctl_transm_count_rst_sync1;
      regs_o.ch23_ctl_transm_count_rst_o <= wb_trig_iface_ch23_ctl_transm_count_rst_sync2 and (not wb_trig_iface_ch23_ctl_transm_count_rst_sync1);
    end if;
  end process;
  
  
-- Receiver Pulse Length
-- asynchronous std_logic_vector register : Receiver Pulse Length (type RW/RO, fs_clk_i <-> clk_sys_i)
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_trig_iface_ch23_cfg_rcv_len_swb_s0 <= '0';
      wb_trig_iface_ch23_cfg_rcv_len_swb_s1 <= '0';
      wb_trig_iface_ch23_cfg_rcv_len_swb_s2 <= '0';
      regs_o.ch23_cfg_rcv_len_o <= "00000000";
    elsif rising_edge(fs_clk_i) then
      wb_trig_iface_ch23_cfg_rcv_len_swb_s0 <= wb_trig_iface_ch23_cfg_rcv_len_swb;
      wb_trig_iface_ch23_cfg_rcv_len_swb_s1 <= wb_trig_iface_ch23_cfg_rcv_len_swb_s0;
      wb_trig_iface_ch23_cfg_rcv_len_swb_s2 <= wb_trig_iface_ch23_cfg_rcv_len_swb_s1;
      if ((wb_trig_iface_ch23_cfg_rcv_len_swb_s2 = '0') and (wb_trig_iface_ch23_cfg_rcv_len_swb_s1 = '1')) then
        regs_o.ch23_cfg_rcv_len_o <= wb_trig_iface_ch23_cfg_rcv_len_int;
      end if;
    end if;
  end process;
  
  
-- Transmitter Pulse Length
-- asynchronous std_logic_vector register : Transmitter Pulse Length (type RW/RO, fs_clk_i <-> clk_sys_i)
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_trig_iface_ch23_cfg_transm_len_swb_s0 <= '0';
      wb_trig_iface_ch23_cfg_transm_len_swb_s1 <= '0';
      wb_trig_iface_ch23_cfg_transm_len_swb_s2 <= '0';
      regs_o.ch23_cfg_transm_len_o <= "00000000";
    elsif rising_edge(fs_clk_i) then
      wb_trig_iface_ch23_cfg_transm_len_swb_s0 <= wb_trig_iface_ch23_cfg_transm_len_swb;
      wb_trig_iface_ch23_cfg_transm_len_swb_s1 <= wb_trig_iface_ch23_cfg_transm_len_swb_s0;
      wb_trig_iface_ch23_cfg_transm_len_swb_s2 <= wb_trig_iface_ch23_cfg_transm_len_swb_s1;
      if ((wb_trig_iface_ch23_cfg_transm_len_swb_s2 = '0') and (wb_trig_iface_ch23_cfg_transm_len_swb_s1 = '1')) then
        regs_o.ch23_cfg_transm_len_o <= wb_trig_iface_ch23_cfg_transm_len_int;
      end if;
    end if;
  end process;
  
  
-- Receiver Counter
-- asynchronous std_logic_vector register : Receiver Counter (type RO/WO, wb_clk_i <-> clk_sys_i)
  process (wb_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_trig_iface_ch23_count_rcv_lwb_s0 <= '0';
      wb_trig_iface_ch23_count_rcv_lwb_s1 <= '0';
      wb_trig_iface_ch23_count_rcv_lwb_s2 <= '0';
      wb_trig_iface_ch23_count_rcv_int <= "0000000000000000";
    elsif rising_edge(wb_clk_i) then
      wb_trig_iface_ch23_count_rcv_lwb_s0 <= wb_trig_iface_ch23_count_rcv_lwb;
      wb_trig_iface_ch23_count_rcv_lwb_s1 <= wb_trig_iface_ch23_count_rcv_lwb_s0;
      wb_trig_iface_ch23_count_rcv_lwb_s2 <= wb_trig_iface_ch23_count_rcv_lwb_s1;
      if ((wb_trig_iface_ch23_count_rcv_lwb_s1 = '1') and (wb_trig_iface_ch23_count_rcv_lwb_s2 = '0')) then
        wb_trig_iface_ch23_count_rcv_int <= regs_i.ch23_count_rcv_i;
      end if;
    end if;
  end process;
  
  
-- Transmitter Counter
-- asynchronous std_logic_vector register : Transmitter Counter (type RO/WO, wb_clk_i <-> clk_sys_i)
  process (wb_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_trig_iface_ch23_count_transm_lwb_s0 <= '0';
      wb_trig_iface_ch23_count_transm_lwb_s1 <= '0';
      wb_trig_iface_ch23_count_transm_lwb_s2 <= '0';
      wb_trig_iface_ch23_count_transm_int <= "0000000000000000";
    elsif rising_edge(wb_clk_i) then
      wb_trig_iface_ch23_count_transm_lwb_s0 <= wb_trig_iface_ch23_count_transm_lwb;
      wb_trig_iface_ch23_count_transm_lwb_s1 <= wb_trig_iface_ch23_count_transm_lwb_s0;
      wb_trig_iface_ch23_count_transm_lwb_s2 <= wb_trig_iface_ch23_count_transm_lwb_s1;
      if ((wb_trig_iface_ch23_count_transm_lwb_s1 = '1') and (wb_trig_iface_ch23_count_transm_lwb_s2 = '0')) then
        wb_trig_iface_ch23_count_transm_int <= regs_i.ch23_count_transm_i;
      end if;
    end if;
  end process;
  
  
  rwaddr_reg <= wb_adr_i;
  wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
-- ACK signal generation. Just pass the LSB of ACK counter.
  wb_ack_o <= ack_sreg(0);
end syn;
