######################################################################
#
# Base version generated by Vivado for 'behavioral' simulation
# Modified by Adrian Byszuk
#
######################################################################
vlib work
vlib msim

vlib msim/xil_defaultlib
vlib msim/fifo_generator_v12_0
vlib msim/axi_interconnect_v1_7
vlib msim/lib_pkg_v1_0
vlib msim/lib_fifo_v1_0
vlib msim/lib_srl_fifo_v1_0
vlib msim/lib_cdc_v1_0
vlib msim/axi_datamover_v5_1

vmap xil_defaultlib msim/xil_defaultlib
vmap fifo_generator_v12_0 msim/fifo_generator_v12_0
vmap axi_interconnect_v1_7 msim/axi_interconnect_v1_7
vmap lib_pkg_v1_0 msim/lib_pkg_v1_0
vmap lib_fifo_v1_0 msim/lib_fifo_v1_0
vmap lib_srl_fifo_v1_0 msim/lib_srl_fifo_v1_0
vmap lib_cdc_v1_0 msim/lib_cdc_v1_0
vmap axi_datamover_v5_1 msim/axi_datamover_v5_1

#### Compile DDR IP core ####
vlog -64 -incr -work xil_defaultlib  \
"../../platform/kintex7/kc705/ddr_core/ddr_core/user_design/rtl/ip_top/*.v" \
"../../platform/kintex7/kc705/ddr_core/ddr_core/user_design/rtl/ui/*.v" \
"../../platform/kintex7/kc705/ddr_core/ddr_core/user_design/rtl/clocking/*.v" \
"../../platform/kintex7/kc705/ddr_core/ddr_core/user_design/rtl/phy/*.v" \
"../../platform/kintex7/kc705/ddr_core/ddr_core/user_design/rtl/ecc/*.v" \
"../../platform/kintex7/kc705/ddr_core/ddr_core/user_design/rtl/controller/*.v" \
"../../platform/kintex7/kc705/ddr_core/ddr_core/user_design/rtl/axi/*.v" \
"../../platform/kintex7/kc705/ddr_core/ddr_core/user_design/rtl/ddr_core_mig_sim.v" \
"../../platform/kintex7/kc705/ddr_core/ddr_core/user_design/rtl/ddr_core.v"

#pass paremeters to memory model
vlog -64 -incr +define+x1Gb +define+sg125 +define+x8 -sv -work xil_defaultlib +incdir+../../sim/ddr_model/kintex7 \
"../../sim/ddr_model/kintex7/ddr3_model.sv"

vlog -64 -incr -work xil_defaultlib \
"../../sim/ddr_model/wiredly.v" \

#### Compile AXI Interconnect IP core ####
vlog -64 -incr -work fifo_generator_v12_0 \
"../../platform/kintex7/kc705/axi_interconnect/fifo_generator_v12_0/simulation/fifo_generator_vlog_beh.v"

vcom -64 -93 -work fifo_generator_v12_0  \
"../../platform/kintex7/kc705/axi_interconnect/fifo_generator_v12_0/hdl/fifo_generator_v12_0_rfs.vhd"

vlog -64 -incr -work fifo_generator_v12_0 \
"../../platform/kintex7/kc705/axi_interconnect/fifo_generator_v12_0/hdl/fifo_generator_v12_0_rfs.v"

vlog -64 -incr -work axi_interconnect_v1_7 \
"../../platform/kintex7/kc705/axi_interconnect/axi_interconnect_v1_7/hdl/verilog/*.v"

vlog -64 -incr -work xil_defaultlib \
"../../platform/kintex7/kc705/axi_interconnect/sim/axi_interconnect.v"

vcom -64 -93 -work lib_pkg_v1_0  \
"../../platform/kintex7/kc705/axi_datamover_0/lib_pkg_v1_0/hdl/src/vhdl/lib_pkg.vhd"

vcom -64 -93 -work lib_fifo_v1_0 \
"../../platform/kintex7/kc705/axi_datamover_0/lib_fifo_v1_0/hdl/src/vhdl/*.vhd"

vcom -64 -93 -work lib_srl_fifo_v1_0 \
"../../platform/kintex7/kc705/axi_datamover_0/lib_srl_fifo_v1_0/hdl/src/vhdl/cntr_incr_decr_addn_f.vhd" \
"../../platform/kintex7/kc705/axi_datamover_0/lib_srl_fifo_v1_0/hdl/src/vhdl/dynshreg_f.vhd" \
"../../platform/kintex7/kc705/axi_datamover_0/lib_srl_fifo_v1_0/hdl/src/vhdl/srl_fifo_rbu_f.vhd" \
"../../platform/kintex7/kc705/axi_datamover_0/lib_srl_fifo_v1_0/hdl/src/vhdl/srl_fifo_f.vhd"

vcom -64 -93 -work lib_cdc_v1_0  \
"../../platform/kintex7/kc705/axi_datamover_0/lib_cdc_v1_0/hdl/src/vhdl/cdc_sync.vhd"

vcom -64 -93 -work axi_datamover_v5_1 \
"../../platform/kintex7/kc705/axi_datamover_0/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_reset.vhd" \
"../../platform/kintex7/kc705/axi_datamover_0/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_afifo_autord.vhd" \
"../../platform/kintex7/kc705/axi_datamover_0/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_sfifo_autord.vhd" \
"../../platform/kintex7/kc705/axi_datamover_0/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_fifo.vhd" \
"../../platform/kintex7/kc705/axi_datamover_0/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_cmd_status.vhd" \
"../../platform/kintex7/kc705/axi_datamover_0/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_scc.vhd" \
"../../platform/kintex7/kc705/axi_datamover_0/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_strb_gen2.vhd" \
"../../platform/kintex7/kc705/axi_datamover_0/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_pcc.vhd" \
"../../platform/kintex7/kc705/axi_datamover_0/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_addr_cntl.vhd" \
"../../platform/kintex7/kc705/axi_datamover_0/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_rdmux.vhd" \
"../../platform/kintex7/kc705/axi_datamover_0/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_rddata_cntl.vhd" \
"../../platform/kintex7/kc705/axi_datamover_0/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_rd_status_cntl.vhd" \
"../../platform/kintex7/kc705/axi_datamover_0/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_wr_demux.vhd" \
"../../platform/kintex7/kc705/axi_datamover_0/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_wrdata_cntl.vhd" \
"../../platform/kintex7/kc705/axi_datamover_0/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_wr_status_cntl.vhd" \
"../../platform/kintex7/kc705/axi_datamover_0/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_skid2mm_buf.vhd" \
"../../platform/kintex7/kc705/axi_datamover_0/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_skid_buf.vhd" \
"../../platform/kintex7/kc705/axi_datamover_0/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_rd_sf.vhd" \
"../../platform/kintex7/kc705/axi_datamover_0/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_wr_sf.vhd" \
"../../platform/kintex7/kc705/axi_datamover_0/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_stbs_set.vhd" \
"../../platform/kintex7/kc705/axi_datamover_0/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_stbs_set_nodre.vhd" \
"../../platform/kintex7/kc705/axi_datamover_0/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_ibttcc.vhd" \
"../../platform/kintex7/kc705/axi_datamover_0/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_indet_btt.vhd" \
"../../platform/kintex7/kc705/axi_datamover_0/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_dre_mux2_1_x_n.vhd" \
"../../platform/kintex7/kc705/axi_datamover_0/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_dre_mux4_1_x_n.vhd" \
"../../platform/kintex7/kc705/axi_datamover_0/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_dre_mux8_1_x_n.vhd" \
"../../platform/kintex7/kc705/axi_datamover_0/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_mm2s_dre.vhd" \
"../../platform/kintex7/kc705/axi_datamover_0/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_s2mm_dre.vhd" \
"../../platform/kintex7/kc705/axi_datamover_0/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_ms_strb_set.vhd" \
"../../platform/kintex7/kc705/axi_datamover_0/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_mssai_skid_buf.vhd" \
"../../platform/kintex7/kc705/axi_datamover_0/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_slice.vhd" \
"../../platform/kintex7/kc705/axi_datamover_0/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_s2mm_scatter.vhd" \
"../../platform/kintex7/kc705/axi_datamover_0/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_s2mm_realign.vhd" \
"../../platform/kintex7/kc705/axi_datamover_0/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_s2mm_basic_wrap.vhd" \
"../../platform/kintex7/kc705/axi_datamover_0/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_s2mm_omit_wrap.vhd" \
"../../platform/kintex7/kc705/axi_datamover_0/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_s2mm_full_wrap.vhd" \
"../../platform/kintex7/kc705/axi_datamover_0/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_mm2s_basic_wrap.vhd" \
"../../platform/kintex7/kc705/axi_datamover_0/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_mm2s_omit_wrap.vhd" \
"../../platform/kintex7/kc705/axi_datamover_0/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_mm2s_full_wrap.vhd" \
"../../platform/kintex7/kc705/axi_datamover_0/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover.vhd"

vcom -64 -93 -work xil_defaultlib  \
"../../platform/kintex7/kc705/axi_datamover_0/sim/axi_datamover_0.vhd"

#### Compile PCIe IP core ####
vlog -64 -incr -work xil_defaultlib \
"../../platform/kintex7/kc705/pcie_core/source/*.v" \
"../../platform/kintex7/kc705/pcie_core/sim/pcie_core.v"

vlog -64 -incr -work xil_defaultlib  +incdir+../../sim/pcie +incdir+./../../../../../testbench/pcie \
"../../sim/pcie/sys_clk_gen.v" \
"../../sim/pcie/sys_clk_gen_ds.v" \
"../../sim/pcie/pci_exp_usrapp_tx.v" \
"../../sim/pcie/pci_exp_usrapp_rx.v" \
"../../sim/pcie/pci_exp_usrapp_pl.v" \
"../../sim/pcie/pci_exp_usrapp_com.v" \
"../../sim/pcie/pci_exp_usrapp_cfg.v" \
"../../sim/pcie/pcie_axi_trn_bridge.v" \
"../../sim/pcie/pcie_2_1_rport_7x.v" \
"../../sim/pcie/xilinx_pcie_2_1_rport_7x.v"

#### Compile general cores ####
vcom -64 -93 -work xil_defaultlib  \
"../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd" \
"../../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd" \
"../../ip_cores/general-cores/modules/genrams/xilinx/*.vhd" \
"../../ip_cores/general-cores/modules/genrams/xilinx/series7/s7_fifo_pkg.vhd" \
"../../ip_cores/general-cores/modules/genrams/xilinx/series7/s7_hwfifo_wrapper.vhd" \
"../../ip_cores/general-cores/modules/genrams/xilinx/series7/generic_sync_fifo.vhd" \
"../../ip_cores/general-cores/modules/genrams/xilinx/series7/generic_async_fifo.vhd" \
"../../ip_cores/general-cores/modules/genrams/inferred_async_fifo.vhd" \
"../../ip_cores/general-cores/modules/genrams/inferred_sync_fifo.vhd"

#### Compile PCIe project modules ####
#Compile packages
vcom -64 -93 -work xil_defaultlib  \
"../../platform/kintex7/kc705/ipcores_pkg.vhd" \
"../../modules/pcie/pkgs/*.vhd"

#Compile RTL design
vcom -64 -93 -work xil_defaultlib  \
"../../modules/pcie/common/DMA_FSM.vhd" \
"../../modules/pcie/common/DMA_Calculate.vhd" \
"../../modules/pcie/common/rx_CplD_Channel.vhd" \
"../../modules/pcie/common/Tx_Output_Arbitor.vhd" \
"../../modules/pcie/common/tx_Mem_Reader.vhd" \
"../../modules/pcie/common/rx_usDMA_Channel.vhd" \
"../../modules/pcie/common/rx_MWr_Channel.vhd" \
"../../modules/pcie/common/rx_MRd_Channel.vhd" \
"../../modules/pcie/common/rx_dsDMA_Channel.vhd" \
"../../modules/pcie/common/RxIn_Delays.vhd" \
"../../modules/pcie/common/Interrupts.vhd" \
"../../modules/pcie/common/tx_Transact.vhd" \
"../../modules/pcie/common/rx_Transact.vhd" \
"../../modules/pcie/common/Registers.vhd" \
"../../modules/pcie/common/tlpControl.vhd" \
"../../modules/pcie/common/ddr_Transact.vhd" \
"../../modules/pcie/common/wb_transact.vhd" \
"../../modules/pcie/common/wb_mem.vhd" \
"../../modules/pcie/bpm_pcie.vhd" \
"../../top/pcie/top_kc705.vhd"

vlog -64 -incr -work xil_defaultlib \
"../../testbench/pcie/board.v"

#### compile glbl module ####
eval vlog -incr -work xil_defaultlib $XILINX_VIVADO/data/verilog/src/glbl.v

