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-- Title          : Wishbone slave core for FMC ADC 250MS/s core registers
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-- File           : wb_fmc250m_4ch_regs_pkg.vhd
-- Author         : auto-generated by wbgen2 from wb_fmc250m_4ch_regs.wb
-- Created        : Thu Oct  6 16:55:33 2016
-- Standard       : VHDL'87
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-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wb_fmc250m_4ch_regs.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

package wb_fmc_250m_4ch_csr_wbgen2_pkg is
  
  
  -- Input registers (user design -> WB slave)
  
  type t_wb_fmc_250m_4ch_csr_in_registers is record
    adc_sta_clk_chains_i                     : std_logic_vector(3 downto 0);
    adc_sta_reserved_clk_chains_i            : std_logic_vector(3 downto 0);
    adc_sta_data_chains_i                    : std_logic_vector(3 downto 0);
    adc_sta_reserved_data_chains_i           : std_logic_vector(3 downto 0);
    adc_sta_adc_pkt_size_i                   : std_logic_vector(15 downto 0);
    adc_ctl_reserved_i                       : std_logic_vector(26 downto 0);
    ch0_sta_val_i                            : std_logic_vector(15 downto 0);
    ch0_sta_reserved_i                       : std_logic_vector(15 downto 0);
    ch0_fn_dly_clk_chain_dly_i               : std_logic_vector(4 downto 0);
    ch0_fn_dly_reserved_clk_chain_dly_i      : std_logic_vector(2 downto 0);
    ch0_fn_dly_data_chain_dly_i              : std_logic_vector(4 downto 0);
    ch0_fn_dly_reserved_data_chain_dly_i     : std_logic_vector(2 downto 0);
    ch0_fn_sel_reserved_i                    : std_logic_vector(14 downto 0);
    ch1_sta_val_i                            : std_logic_vector(15 downto 0);
    ch1_sta_reserved_i                       : std_logic_vector(15 downto 0);
    ch1_fn_dly_clk_chain_dly_i               : std_logic_vector(4 downto 0);
    ch1_fn_dly_reserved_clk_chain_dly_i      : std_logic_vector(2 downto 0);
    ch1_fn_dly_data_chain_dly_i              : std_logic_vector(4 downto 0);
    ch1_fn_dly_reserved_data_chain_dly_i     : std_logic_vector(2 downto 0);
    ch1_fn_sel_reserved_i                    : std_logic_vector(14 downto 0);
    ch2_sta_val_i                            : std_logic_vector(15 downto 0);
    ch2_sta_reserved_i                       : std_logic_vector(15 downto 0);
    ch2_fn_dly_clk_chain_dly_i               : std_logic_vector(4 downto 0);
    ch2_fn_dly_reserved_clk_chain_dly_i      : std_logic_vector(2 downto 0);
    ch2_fn_dly_data_chain_dly_i              : std_logic_vector(4 downto 0);
    ch2_fn_dly_reserved_data_chain_dly_i     : std_logic_vector(2 downto 0);
    ch2_fn_sel_reserved_i                    : std_logic_vector(14 downto 0);
    ch3_sta_val_i                            : std_logic_vector(15 downto 0);
    ch3_sta_reserved_i                       : std_logic_vector(15 downto 0);
    ch3_fn_dly_clk_chain_dly_i               : std_logic_vector(4 downto 0);
    ch3_fn_dly_reserved_clk_chain_dly_i      : std_logic_vector(2 downto 0);
    ch3_fn_dly_data_chain_dly_i              : std_logic_vector(4 downto 0);
    ch3_fn_dly_reserved_data_chain_dly_i     : std_logic_vector(2 downto 0);
    ch3_fn_sel_reserved_i                    : std_logic_vector(14 downto 0);
    temp_mon_dev_i                           : std_logic;
    end record;
  
  constant c_wb_fmc_250m_4ch_csr_in_registers_init_value: t_wb_fmc_250m_4ch_csr_in_registers := (
    adc_sta_clk_chains_i => (others => '0'),
    adc_sta_reserved_clk_chains_i => (others => '0'),
    adc_sta_data_chains_i => (others => '0'),
    adc_sta_reserved_data_chains_i => (others => '0'),
    adc_sta_adc_pkt_size_i => (others => '0'),
    adc_ctl_reserved_i => (others => '0'),
    ch0_sta_val_i => (others => '0'),
    ch0_sta_reserved_i => (others => '0'),
    ch0_fn_dly_clk_chain_dly_i => (others => '0'),
    ch0_fn_dly_reserved_clk_chain_dly_i => (others => '0'),
    ch0_fn_dly_data_chain_dly_i => (others => '0'),
    ch0_fn_dly_reserved_data_chain_dly_i => (others => '0'),
    ch0_fn_sel_reserved_i => (others => '0'),
    ch1_sta_val_i => (others => '0'),
    ch1_sta_reserved_i => (others => '0'),
    ch1_fn_dly_clk_chain_dly_i => (others => '0'),
    ch1_fn_dly_reserved_clk_chain_dly_i => (others => '0'),
    ch1_fn_dly_data_chain_dly_i => (others => '0'),
    ch1_fn_dly_reserved_data_chain_dly_i => (others => '0'),
    ch1_fn_sel_reserved_i => (others => '0'),
    ch2_sta_val_i => (others => '0'),
    ch2_sta_reserved_i => (others => '0'),
    ch2_fn_dly_clk_chain_dly_i => (others => '0'),
    ch2_fn_dly_reserved_clk_chain_dly_i => (others => '0'),
    ch2_fn_dly_data_chain_dly_i => (others => '0'),
    ch2_fn_dly_reserved_data_chain_dly_i => (others => '0'),
    ch2_fn_sel_reserved_i => (others => '0'),
    ch3_sta_val_i => (others => '0'),
    ch3_sta_reserved_i => (others => '0'),
    ch3_fn_dly_clk_chain_dly_i => (others => '0'),
    ch3_fn_dly_reserved_clk_chain_dly_i => (others => '0'),
    ch3_fn_dly_data_chain_dly_i => (others => '0'),
    ch3_fn_dly_reserved_data_chain_dly_i => (others => '0'),
    ch3_fn_sel_reserved_i => (others => '0'),
    temp_mon_dev_i => '0'
    );
    
    -- Output registers (WB slave -> user design)
    
    type t_wb_fmc_250m_4ch_csr_out_registers is record
      adc_ctl_update_clk_dly_o                 : std_logic;
      adc_ctl_update_data_dly_o                : std_logic;
      adc_ctl_rst_adcs_o                       : std_logic;
      adc_ctl_rst_div_adcs_o                   : std_logic;
      adc_ctl_sleep_adcs_o                     : std_logic;
      ch0_fn_dly_clk_chain_dly_o               : std_logic_vector(4 downto 0);
      ch0_fn_dly_clk_chain_dly_load_o          : std_logic;
      ch0_fn_dly_data_chain_dly_o              : std_logic_vector(4 downto 0);
      ch0_fn_dly_data_chain_dly_load_o         : std_logic;
      ch0_fn_dly_inc_clk_chain_dly_o           : std_logic;
      ch0_fn_dly_dec_clk_chain_dly_o           : std_logic;
      ch0_fn_dly_reserved_clk_incdec_dly_o     : std_logic_vector(5 downto 0);
      ch0_fn_dly_inc_data_chain_dly_o          : std_logic;
      ch0_fn_dly_dec_data_chain_dly_o          : std_logic;
      ch0_fn_dly_reserved_data_incdec_dly_o    : std_logic_vector(5 downto 0);
      ch0_fn_sel_line_o                        : std_logic_vector(16 downto 0);
      ch0_cs_dly_fe_dly_o                      : std_logic_vector(1 downto 0);
      ch0_cs_dly_reserved_fe_dly_o             : std_logic_vector(5 downto 0);
      ch0_cs_dly_rg_dly_o                      : std_logic_vector(1 downto 0);
      ch0_cs_dly_reserved_rg_dly_o             : std_logic_vector(21 downto 0);
      ch1_fn_dly_clk_chain_dly_o               : std_logic_vector(4 downto 0);
      ch1_fn_dly_clk_chain_dly_load_o          : std_logic;
      ch1_fn_dly_data_chain_dly_o              : std_logic_vector(4 downto 0);
      ch1_fn_dly_data_chain_dly_load_o         : std_logic;
      ch1_fn_dly_inc_clk_chain_dly_o           : std_logic;
      ch1_fn_dly_dec_clk_chain_dly_o           : std_logic;
      ch1_fn_dly_reserved_clk_incdec_dly_o     : std_logic_vector(5 downto 0);
      ch1_fn_dly_inc_data_chain_dly_o          : std_logic;
      ch1_fn_dly_dec_data_chain_dly_o          : std_logic;
      ch1_fn_dly_reserved_data_incdec_dly_o    : std_logic_vector(5 downto 0);
      ch1_fn_sel_line_o                        : std_logic_vector(16 downto 0);
      ch1_cs_dly_fe_dly_o                      : std_logic_vector(1 downto 0);
      ch1_cs_dly_reserved_fe_dly_o             : std_logic_vector(5 downto 0);
      ch1_cs_dly_rg_dly_o                      : std_logic_vector(1 downto 0);
      ch1_cs_dly_reserved_rg_dly_o             : std_logic_vector(21 downto 0);
      ch2_fn_dly_clk_chain_dly_o               : std_logic_vector(4 downto 0);
      ch2_fn_dly_clk_chain_dly_load_o          : std_logic;
      ch2_fn_dly_data_chain_dly_o              : std_logic_vector(4 downto 0);
      ch2_fn_dly_data_chain_dly_load_o         : std_logic;
      ch2_fn_dly_inc_clk_chain_dly_o           : std_logic;
      ch2_fn_dly_dec_clk_chain_dly_o           : std_logic;
      ch2_fn_dly_reserved_clk_incdec_dly_o     : std_logic_vector(5 downto 0);
      ch2_fn_dly_inc_data_chain_dly_o          : std_logic;
      ch2_fn_dly_dec_data_chain_dly_o          : std_logic;
      ch2_fn_dly_reserved_data_incdec_dly_o    : std_logic_vector(5 downto 0);
      ch2_fn_sel_line_o                        : std_logic_vector(16 downto 0);
      ch2_cs_dly_fe_dly_o                      : std_logic_vector(1 downto 0);
      ch2_cs_dly_reserved_fe_dly_o             : std_logic_vector(5 downto 0);
      ch2_cs_dly_rg_dly_o                      : std_logic_vector(1 downto 0);
      ch2_cs_dly_reserved_rg_dly_o             : std_logic_vector(21 downto 0);
      ch3_fn_dly_clk_chain_dly_o               : std_logic_vector(4 downto 0);
      ch3_fn_dly_clk_chain_dly_load_o          : std_logic;
      ch3_fn_dly_data_chain_dly_o              : std_logic_vector(4 downto 0);
      ch3_fn_dly_data_chain_dly_load_o         : std_logic;
      ch3_fn_dly_inc_clk_chain_dly_o           : std_logic;
      ch3_fn_dly_dec_clk_chain_dly_o           : std_logic;
      ch3_fn_dly_reserved_clk_incdec_dly_o     : std_logic_vector(5 downto 0);
      ch3_fn_dly_inc_data_chain_dly_o          : std_logic;
      ch3_fn_dly_dec_data_chain_dly_o          : std_logic;
      ch3_fn_dly_reserved_data_incdec_dly_o    : std_logic_vector(5 downto 0);
      ch3_fn_sel_line_o                        : std_logic_vector(16 downto 0);
      ch3_cs_dly_fe_dly_o                      : std_logic_vector(1 downto 0);
      ch3_cs_dly_reserved_fe_dly_o             : std_logic_vector(5 downto 0);
      ch3_cs_dly_rg_dly_o                      : std_logic_vector(1 downto 0);
      ch3_cs_dly_reserved_rg_dly_o             : std_logic_vector(21 downto 0);
      end record;
    
    constant c_wb_fmc_250m_4ch_csr_out_registers_init_value: t_wb_fmc_250m_4ch_csr_out_registers := (
      adc_ctl_update_clk_dly_o => '0',
      adc_ctl_update_data_dly_o => '0',
      adc_ctl_rst_adcs_o => '0',
      adc_ctl_rst_div_adcs_o => '0',
      adc_ctl_sleep_adcs_o => '0',
      ch0_fn_dly_clk_chain_dly_o => (others => '0'),
      ch0_fn_dly_clk_chain_dly_load_o => '0',
      ch0_fn_dly_data_chain_dly_o => (others => '0'),
      ch0_fn_dly_data_chain_dly_load_o => '0',
      ch0_fn_dly_inc_clk_chain_dly_o => '0',
      ch0_fn_dly_dec_clk_chain_dly_o => '0',
      ch0_fn_dly_reserved_clk_incdec_dly_o => (others => '0'),
      ch0_fn_dly_inc_data_chain_dly_o => '0',
      ch0_fn_dly_dec_data_chain_dly_o => '0',
      ch0_fn_dly_reserved_data_incdec_dly_o => (others => '0'),
      ch0_fn_sel_line_o => (others => '0'),
      ch0_cs_dly_fe_dly_o => (others => '0'),
      ch0_cs_dly_reserved_fe_dly_o => (others => '0'),
      ch0_cs_dly_rg_dly_o => (others => '0'),
      ch0_cs_dly_reserved_rg_dly_o => (others => '0'),
      ch1_fn_dly_clk_chain_dly_o => (others => '0'),
      ch1_fn_dly_clk_chain_dly_load_o => '0',
      ch1_fn_dly_data_chain_dly_o => (others => '0'),
      ch1_fn_dly_data_chain_dly_load_o => '0',
      ch1_fn_dly_inc_clk_chain_dly_o => '0',
      ch1_fn_dly_dec_clk_chain_dly_o => '0',
      ch1_fn_dly_reserved_clk_incdec_dly_o => (others => '0'),
      ch1_fn_dly_inc_data_chain_dly_o => '0',
      ch1_fn_dly_dec_data_chain_dly_o => '0',
      ch1_fn_dly_reserved_data_incdec_dly_o => (others => '0'),
      ch1_fn_sel_line_o => (others => '0'),
      ch1_cs_dly_fe_dly_o => (others => '0'),
      ch1_cs_dly_reserved_fe_dly_o => (others => '0'),
      ch1_cs_dly_rg_dly_o => (others => '0'),
      ch1_cs_dly_reserved_rg_dly_o => (others => '0'),
      ch2_fn_dly_clk_chain_dly_o => (others => '0'),
      ch2_fn_dly_clk_chain_dly_load_o => '0',
      ch2_fn_dly_data_chain_dly_o => (others => '0'),
      ch2_fn_dly_data_chain_dly_load_o => '0',
      ch2_fn_dly_inc_clk_chain_dly_o => '0',
      ch2_fn_dly_dec_clk_chain_dly_o => '0',
      ch2_fn_dly_reserved_clk_incdec_dly_o => (others => '0'),
      ch2_fn_dly_inc_data_chain_dly_o => '0',
      ch2_fn_dly_dec_data_chain_dly_o => '0',
      ch2_fn_dly_reserved_data_incdec_dly_o => (others => '0'),
      ch2_fn_sel_line_o => (others => '0'),
      ch2_cs_dly_fe_dly_o => (others => '0'),
      ch2_cs_dly_reserved_fe_dly_o => (others => '0'),
      ch2_cs_dly_rg_dly_o => (others => '0'),
      ch2_cs_dly_reserved_rg_dly_o => (others => '0'),
      ch3_fn_dly_clk_chain_dly_o => (others => '0'),
      ch3_fn_dly_clk_chain_dly_load_o => '0',
      ch3_fn_dly_data_chain_dly_o => (others => '0'),
      ch3_fn_dly_data_chain_dly_load_o => '0',
      ch3_fn_dly_inc_clk_chain_dly_o => '0',
      ch3_fn_dly_dec_clk_chain_dly_o => '0',
      ch3_fn_dly_reserved_clk_incdec_dly_o => (others => '0'),
      ch3_fn_dly_inc_data_chain_dly_o => '0',
      ch3_fn_dly_dec_data_chain_dly_o => '0',
      ch3_fn_dly_reserved_data_incdec_dly_o => (others => '0'),
      ch3_fn_sel_line_o => (others => '0'),
      ch3_cs_dly_fe_dly_o => (others => '0'),
      ch3_cs_dly_reserved_fe_dly_o => (others => '0'),
      ch3_cs_dly_rg_dly_o => (others => '0'),
      ch3_cs_dly_reserved_rg_dly_o => (others => '0')
      );
    function "or" (left, right: t_wb_fmc_250m_4ch_csr_in_registers) return t_wb_fmc_250m_4ch_csr_in_registers;
    function f_x_to_zero (x:std_logic) return std_logic;
    function f_x_to_zero (x:std_logic_vector) return std_logic_vector;
end package;

package body wb_fmc_250m_4ch_csr_wbgen2_pkg is
function f_x_to_zero (x:std_logic) return std_logic is
begin
if x = '1' then
return '1';
else
return '0';
end if;
end function;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector is
variable tmp: std_logic_vector(x'length-1 downto 0);
begin
for i in 0 to x'length-1 loop
if(x(i) = 'X' or x(i) = 'U') then
tmp(i):= '0';
else
tmp(i):=x(i);
end if; 
end loop; 
return tmp;
end function;
function "or" (left, right: t_wb_fmc_250m_4ch_csr_in_registers) return t_wb_fmc_250m_4ch_csr_in_registers is
variable tmp: t_wb_fmc_250m_4ch_csr_in_registers;
begin
tmp.adc_sta_clk_chains_i := f_x_to_zero(left.adc_sta_clk_chains_i) or f_x_to_zero(right.adc_sta_clk_chains_i);
tmp.adc_sta_reserved_clk_chains_i := f_x_to_zero(left.adc_sta_reserved_clk_chains_i) or f_x_to_zero(right.adc_sta_reserved_clk_chains_i);
tmp.adc_sta_data_chains_i := f_x_to_zero(left.adc_sta_data_chains_i) or f_x_to_zero(right.adc_sta_data_chains_i);
tmp.adc_sta_reserved_data_chains_i := f_x_to_zero(left.adc_sta_reserved_data_chains_i) or f_x_to_zero(right.adc_sta_reserved_data_chains_i);
tmp.adc_sta_adc_pkt_size_i := f_x_to_zero(left.adc_sta_adc_pkt_size_i) or f_x_to_zero(right.adc_sta_adc_pkt_size_i);
tmp.adc_ctl_reserved_i := f_x_to_zero(left.adc_ctl_reserved_i) or f_x_to_zero(right.adc_ctl_reserved_i);
tmp.ch0_sta_val_i := f_x_to_zero(left.ch0_sta_val_i) or f_x_to_zero(right.ch0_sta_val_i);
tmp.ch0_sta_reserved_i := f_x_to_zero(left.ch0_sta_reserved_i) or f_x_to_zero(right.ch0_sta_reserved_i);
tmp.ch0_fn_dly_clk_chain_dly_i := f_x_to_zero(left.ch0_fn_dly_clk_chain_dly_i) or f_x_to_zero(right.ch0_fn_dly_clk_chain_dly_i);
tmp.ch0_fn_dly_reserved_clk_chain_dly_i := f_x_to_zero(left.ch0_fn_dly_reserved_clk_chain_dly_i) or f_x_to_zero(right.ch0_fn_dly_reserved_clk_chain_dly_i);
tmp.ch0_fn_dly_data_chain_dly_i := f_x_to_zero(left.ch0_fn_dly_data_chain_dly_i) or f_x_to_zero(right.ch0_fn_dly_data_chain_dly_i);
tmp.ch0_fn_dly_reserved_data_chain_dly_i := f_x_to_zero(left.ch0_fn_dly_reserved_data_chain_dly_i) or f_x_to_zero(right.ch0_fn_dly_reserved_data_chain_dly_i);
tmp.ch0_fn_sel_reserved_i := f_x_to_zero(left.ch0_fn_sel_reserved_i) or f_x_to_zero(right.ch0_fn_sel_reserved_i);
tmp.ch1_sta_val_i := f_x_to_zero(left.ch1_sta_val_i) or f_x_to_zero(right.ch1_sta_val_i);
tmp.ch1_sta_reserved_i := f_x_to_zero(left.ch1_sta_reserved_i) or f_x_to_zero(right.ch1_sta_reserved_i);
tmp.ch1_fn_dly_clk_chain_dly_i := f_x_to_zero(left.ch1_fn_dly_clk_chain_dly_i) or f_x_to_zero(right.ch1_fn_dly_clk_chain_dly_i);
tmp.ch1_fn_dly_reserved_clk_chain_dly_i := f_x_to_zero(left.ch1_fn_dly_reserved_clk_chain_dly_i) or f_x_to_zero(right.ch1_fn_dly_reserved_clk_chain_dly_i);
tmp.ch1_fn_dly_data_chain_dly_i := f_x_to_zero(left.ch1_fn_dly_data_chain_dly_i) or f_x_to_zero(right.ch1_fn_dly_data_chain_dly_i);
tmp.ch1_fn_dly_reserved_data_chain_dly_i := f_x_to_zero(left.ch1_fn_dly_reserved_data_chain_dly_i) or f_x_to_zero(right.ch1_fn_dly_reserved_data_chain_dly_i);
tmp.ch1_fn_sel_reserved_i := f_x_to_zero(left.ch1_fn_sel_reserved_i) or f_x_to_zero(right.ch1_fn_sel_reserved_i);
tmp.ch2_sta_val_i := f_x_to_zero(left.ch2_sta_val_i) or f_x_to_zero(right.ch2_sta_val_i);
tmp.ch2_sta_reserved_i := f_x_to_zero(left.ch2_sta_reserved_i) or f_x_to_zero(right.ch2_sta_reserved_i);
tmp.ch2_fn_dly_clk_chain_dly_i := f_x_to_zero(left.ch2_fn_dly_clk_chain_dly_i) or f_x_to_zero(right.ch2_fn_dly_clk_chain_dly_i);
tmp.ch2_fn_dly_reserved_clk_chain_dly_i := f_x_to_zero(left.ch2_fn_dly_reserved_clk_chain_dly_i) or f_x_to_zero(right.ch2_fn_dly_reserved_clk_chain_dly_i);
tmp.ch2_fn_dly_data_chain_dly_i := f_x_to_zero(left.ch2_fn_dly_data_chain_dly_i) or f_x_to_zero(right.ch2_fn_dly_data_chain_dly_i);
tmp.ch2_fn_dly_reserved_data_chain_dly_i := f_x_to_zero(left.ch2_fn_dly_reserved_data_chain_dly_i) or f_x_to_zero(right.ch2_fn_dly_reserved_data_chain_dly_i);
tmp.ch2_fn_sel_reserved_i := f_x_to_zero(left.ch2_fn_sel_reserved_i) or f_x_to_zero(right.ch2_fn_sel_reserved_i);
tmp.ch3_sta_val_i := f_x_to_zero(left.ch3_sta_val_i) or f_x_to_zero(right.ch3_sta_val_i);
tmp.ch3_sta_reserved_i := f_x_to_zero(left.ch3_sta_reserved_i) or f_x_to_zero(right.ch3_sta_reserved_i);
tmp.ch3_fn_dly_clk_chain_dly_i := f_x_to_zero(left.ch3_fn_dly_clk_chain_dly_i) or f_x_to_zero(right.ch3_fn_dly_clk_chain_dly_i);
tmp.ch3_fn_dly_reserved_clk_chain_dly_i := f_x_to_zero(left.ch3_fn_dly_reserved_clk_chain_dly_i) or f_x_to_zero(right.ch3_fn_dly_reserved_clk_chain_dly_i);
tmp.ch3_fn_dly_data_chain_dly_i := f_x_to_zero(left.ch3_fn_dly_data_chain_dly_i) or f_x_to_zero(right.ch3_fn_dly_data_chain_dly_i);
tmp.ch3_fn_dly_reserved_data_chain_dly_i := f_x_to_zero(left.ch3_fn_dly_reserved_data_chain_dly_i) or f_x_to_zero(right.ch3_fn_dly_reserved_data_chain_dly_i);
tmp.ch3_fn_sel_reserved_i := f_x_to_zero(left.ch3_fn_sel_reserved_i) or f_x_to_zero(right.ch3_fn_sel_reserved_i);
tmp.temp_mon_dev_i := f_x_to_zero(left.temp_mon_dev_i) or f_x_to_zero(right.temp_mon_dev_i);
return tmp;
end function;
end package body;
