/*
  Register definitions for slave core: Control and status registers for FMC PICO 1M 4CH

  * File           : wb_fmcpico1m_4ch_regs.h
  * Author         : auto-generated by wbgen2 from wb_fmcpico1m_4ch_regs.wb
  * Created        : Mon Mar 20 18:26:54 2017
  * Standard       : ANSI C

    THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wb_fmcpico1m_4ch_regs.wb
    DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!

*/

#ifndef __WBGEN2_REGDEFS_WB_FMCPICO1M_4CH_REGS_WB
#define __WBGEN2_REGDEFS_WB_FMCPICO1M_4CH_REGS_WB

#include <inttypes.h>

#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
#else
#error "Unsupported compiler?"
#endif

#ifndef __WBGEN2_MACROS_DEFINED__
#define __WBGEN2_MACROS_DEFINED__
#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
#endif


/* definitions for register: FMC Status */

/* definitions for field: FMC Present in reg: FMC Status */
#define WB_FMCPICO1M_4CH_CSR_FMC_STATUS_PRSNT WBGEN2_GEN_MASK(0, 1)

/* definitions for field: Power Good from mezzanine in reg: FMC Status */
#define WB_FMCPICO1M_4CH_CSR_FMC_STATUS_PG_M2C WBGEN2_GEN_MASK(1, 1)

/* definitions for register: FMC Control */

/* definitions for field: LED 1 Control in reg: FMC Control */
#define WB_FMCPICO1M_4CH_CSR_FMC_CTL_LED1     WBGEN2_GEN_MASK(0, 1)

/* definitions for field: LED 2 Control in reg: FMC Control */
#define WB_FMCPICO1M_4CH_CSR_FMC_CTL_LED2     WBGEN2_GEN_MASK(1, 1)

/* definitions for register: Input Range Control */

/* definitions for field: R0 in reg: Input Range Control */
#define WB_FMCPICO1M_4CH_CSR_RNG_CTL_R0       WBGEN2_GEN_MASK(0, 1)

/* definitions for field: R1 in reg: Input Range Control */
#define WB_FMCPICO1M_4CH_CSR_RNG_CTL_R1       WBGEN2_GEN_MASK(8, 1)

/* definitions for field: R2 in reg: Input Range Control */
#define WB_FMCPICO1M_4CH_CSR_RNG_CTL_R2       WBGEN2_GEN_MASK(16, 1)

/* definitions for field: R3 in reg: Input Range Control */
#define WB_FMCPICO1M_4CH_CSR_RNG_CTL_R3       WBGEN2_GEN_MASK(24, 1)

/* definitions for register: ADC Data Channel 0 */

/* definitions for register: ADC Data Channel 1 */

/* definitions for register: ADC Data Channel 2 */

/* definitions for register: ADC Data Channel 3 */
/* [0x0]: REG FMC Status */
#define WB_FMCPICO1M_4CH_CSR_REG_FMC_STATUS 0x00000000
/* [0x4]: REG FMC Control */
#define WB_FMCPICO1M_4CH_CSR_REG_FMC_CTL 0x00000004
/* [0x8]: REG Input Range Control */
#define WB_FMCPICO1M_4CH_CSR_REG_RNG_CTL 0x00000008
/* [0xc]: REG ADC Data Channel 0 */
#define WB_FMCPICO1M_4CH_CSR_REG_DATA0 0x0000000c
/* [0x10]: REG ADC Data Channel 1 */
#define WB_FMCPICO1M_4CH_CSR_REG_DATA1 0x00000010
/* [0x14]: REG ADC Data Channel 2 */
#define WB_FMCPICO1M_4CH_CSR_REG_DATA2 0x00000014
/* [0x18]: REG ADC Data Channel 3 */
#define WB_FMCPICO1M_4CH_CSR_REG_DATA3 0x00000018
#endif
