/*
  Register definitions for slave core: FMC Active Clock registers

  * File           : wb_fmc_active_clk_regs.h
  * Author         : auto-generated by wbgen2 from wb_fmc_active_clk_regs.wb
  * Created        : Mon Apr 18 10:20:28 2016
  * Standard       : ANSI C

    THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wb_fmc_active_clk_regs.wb
    DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!

*/

#ifndef __WBGEN2_REGDEFS_WB_FMC_ACTIVE_CLK_REGS_WB
#define __WBGEN2_REGDEFS_WB_FMC_ACTIVE_CLK_REGS_WB

#include <inttypes.h>

#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
#else
#error "Unsupported compiler?"
#endif

#ifndef __WBGEN2_MACROS_DEFINED__
#define __WBGEN2_MACROS_DEFINED__
#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
#endif


/* definitions for register: Clock distribution control register */

/* definitions for field: Si 571 Output Enable in reg: Clock distribution control register */
#define WB_FMC_ACTIVE_CLK_CSR_CLK_DISTRIB_SI571_OE WBGEN2_GEN_MASK(0, 1)

/* definitions for field: AD9510 PLL function in reg: Clock distribution control register */
#define WB_FMC_ACTIVE_CLK_CSR_CLK_DISTRIB_PLL_FUNCTION WBGEN2_GEN_MASK(1, 1)

/* definitions for field: AD9510 PLL Status in reg: Clock distribution control register */
#define WB_FMC_ACTIVE_CLK_CSR_CLK_DISTRIB_PLL_STATUS WBGEN2_GEN_MASK(2, 1)

/* definitions for field: Reference Clock Selection in reg: Clock distribution control register */
#define WB_FMC_ACTIVE_CLK_CSR_CLK_DISTRIB_CLK_SEL WBGEN2_GEN_MASK(3, 1)

/* definitions for field: Reserved in reg: Clock distribution control register */
#define WB_FMC_ACTIVE_CLK_CSR_CLK_DISTRIB_RESERVED_MASK WBGEN2_GEN_MASK(4, 28)
#define WB_FMC_ACTIVE_CLK_CSR_CLK_DISTRIB_RESERVED_SHIFT 4
#define WB_FMC_ACTIVE_CLK_CSR_CLK_DISTRIB_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 4, 28)
#define WB_FMC_ACTIVE_CLK_CSR_CLK_DISTRIB_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 4, 28)

/* definitions for register: Dummy */

/* definitions for field: Reserved in reg: Dummy */
#define WB_FMC_ACTIVE_CLK_CSR_DUMMY_RESERVED_MASK WBGEN2_GEN_MASK(0, 32)
#define WB_FMC_ACTIVE_CLK_CSR_DUMMY_RESERVED_SHIFT 0
#define WB_FMC_ACTIVE_CLK_CSR_DUMMY_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 0, 32)
#define WB_FMC_ACTIVE_CLK_CSR_DUMMY_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 0, 32)
/* [0x0]: REG Clock distribution control register */
#define WB_FMC_ACTIVE_CLK_CSR_REG_CLK_DISTRIB 0x00000000
/* [0x4]: REG Dummy */
#define WB_FMC_ACTIVE_CLK_CSR_REG_DUMMY 0x00000004
#endif
