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-- Title          : Wishbone slave core for FMC ADC/DAC interface registers
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-- File           : xfmc150_regs_pkg.vhd
-- Author         : auto-generated by wbgen2 from xfmc150.wb
-- Created        : Thu Oct 11 10:21:39 2012
-- Standard       : VHDL'87
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-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE xfmc150.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

package fmc150_wbgen2_pkg is
  
  
  -- Input registers (user design -> WB slave)
  
  type t_fmc150_in_registers is record
    data_out_i                               : std_logic_vector(31 downto 0);
    flgs_out_spi_busy_i                      : std_logic;
    flgs_out_pll_status_i                    : std_logic;
    flgs_out_adc_clk_locked_i                : std_logic;
    flgs_out_fmc_prst_i                      : std_logic;
    end record;
  
  constant c_fmc150_in_registers_init_value: t_fmc150_in_registers := (
    data_out_i => (others => '0'),
    flgs_out_spi_busy_i => '0',
    flgs_out_pll_status_i => '0',
    flgs_out_adc_clk_locked_i => '0',
    flgs_out_fmc_prst_i => '0'
    );
    
    -- Output registers (WB slave -> user design)
    
    type t_fmc150_out_registers is record
      flgs_pulse_o                             : std_logic;
      flgs_in_spi_rw_o                         : std_logic;
      flgs_in_ext_clk_o                        : std_logic;
      addr_o                                   : std_logic_vector(15 downto 0);
      data_in_o                                : std_logic_vector(31 downto 0);
      cs_cdce72010_o                           : std_logic;
      cs_ads62p49_o                            : std_logic;
      cs_dac3283_o                             : std_logic;
      cs_amc7823_o                             : std_logic;
      adc_dly_str_o                            : std_logic_vector(4 downto 0);
      adc_dly_cha_o                            : std_logic_vector(4 downto 0);
      adc_dly_chb_o                            : std_logic_vector(4 downto 0);
      end record;
    
    constant c_fmc150_out_registers_init_value: t_fmc150_out_registers := (
      flgs_pulse_o => '0',
      flgs_in_spi_rw_o => '0',
      flgs_in_ext_clk_o => '0',
      addr_o => (others => '0'),
      data_in_o => (others => '0'),
      cs_cdce72010_o => '0',
      cs_ads62p49_o => '0',
      cs_dac3283_o => '0',
      cs_amc7823_o => '0',
      adc_dly_str_o => (others => '0'),
      adc_dly_cha_o => (others => '0'),
      adc_dly_chb_o => (others => '0')
      );
    function "or" (left, right: t_fmc150_in_registers) return t_fmc150_in_registers;
    function f_x_to_zero (x:std_logic) return std_logic;
    function f_x_to_zero (x:std_logic_vector) return std_logic_vector;
end package;

package body fmc150_wbgen2_pkg is
function f_x_to_zero (x:std_logic) return std_logic is
begin
if(x = 'X' or x = 'U') then
return '0';
else
return x;
end if; 
end function;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector is
variable tmp: std_logic_vector(x'length-1 downto 0);
begin
for i in 0 to x'length-1 loop
if(x(i) = 'X' or x(i) = 'U') then
tmp(i):= '0';
else
tmp(i):=x(i);
end if; 
end loop; 
return tmp;
end function;
function "or" (left, right: t_fmc150_in_registers) return t_fmc150_in_registers is
variable tmp: t_fmc150_in_registers;
begin
tmp.data_out_i := f_x_to_zero(left.data_out_i) or f_x_to_zero(right.data_out_i);
tmp.flgs_out_spi_busy_i := f_x_to_zero(left.flgs_out_spi_busy_i) or f_x_to_zero(right.flgs_out_spi_busy_i);
tmp.flgs_out_pll_status_i := f_x_to_zero(left.flgs_out_pll_status_i) or f_x_to_zero(right.flgs_out_pll_status_i);
tmp.flgs_out_adc_clk_locked_i := f_x_to_zero(left.flgs_out_adc_clk_locked_i) or f_x_to_zero(right.flgs_out_adc_clk_locked_i);
tmp.flgs_out_fmc_prst_i := f_x_to_zero(left.flgs_out_fmc_prst_i) or f_x_to_zero(right.flgs_out_fmc_prst_i);
return tmp;
end function;
end package body;
