# acq_core_regs

### BPM FSM Acquisition registers

Wishbone slave for BPM Core Acquisition

### Contents:

1. Memory map summary
2. HDL symbol
3. Register description
3.1. Control register
3.2. Status register
3.3. Trigger configuration
3.4. Trigger data config threshold
3.5. Trigger data threshold
3.6. Trigger delay
3.7. Software trigger
3.8. Number of shots
3.9. Trigger address register
3.10. Pre-trigger samples
3.11. Post-trigger samples
3.12. Samples counter
3.13. DDR3 Start Address
3.14. DDR3 End Address
3.15. Acquisition channel control
3.16. Channel 0 Description
3.17. Channel 0 Atom Description
3.18. Channel 1 Description
3.19. Channel 1 Atom Description
3.20. Channel 2 Description
3.21. Channel 2 Atom Description
3.22. Channel 3 Description
3.23. Channel 3 Atom Description
3.24. Channel 4 Description
3.25. Channel 4 Atom Description
3.26. Channel 5 Description
3.27. Channel 5 Atom Description
3.28. Channel 6 Description
3.29. Channel 6 Atom Description
3.30. Channel 7 Description
3.31. Channel 7 Atom Description
3.32. Channel 8 Description
3.33. Channel 8 Atom Description
3.34. Channel 9 Description
3.35. Channel 9 Atom Description
3.36. Channel 10 Description
3.37. Channel 10 Atom Description
3.38. Channel 11 Description
3.39. Channel 11 Atom Description
3.40. Channel 12 Description
3.41. Channel 12 Atom Description
3.42. Channel 13 Description
3.43. Channel 13 Atom Description
3.44. Channel 14 Description
3.45. Channel 14 Atom Description
3.46. Channel 15 Description
3.47. Channel 15 Atom Description
3.48. Channel 16 Description
3.49. Channel 16 Atom Description
3.50. Channel 17 Description
3.51. Channel 17 Atom Description
3.52. Channel 18 Description
3.53. Channel 18 Atom Description
3.54. Channel 19 Description
3.55. Channel 19 Atom Description
3.56. Channel 20 Description
3.57. Channel 20 Atom Description
3.58. Channel 21 Description
3.59. Channel 21 Atom Description
3.60. Channel 22 Description
3.61. Channel 22 Atom Description
3.62. Channel 23 Description
3.63. Channel 23 Atom Description

### 1. Memory map summary

H/W Address | Type | Name | VHDL/Verilog prefix | C prefix
--- | --- | --- | --- | ---
0x0 | REG | Control register | acq_core_ctl | CTL
0x1 | REG | Status register | acq_core_sta | STA
0x2 | REG | Trigger configuration | acq_core_trig_cfg | TRIG_CFG
0x3 | REG | Trigger data config threshold | acq_core_trig_data_cfg | TRIG_DATA_CFG
0x4 | REG | Trigger data threshold | acq_core_trig_data_thres | TRIG_DATA_THRES
0x5 | REG | Trigger delay | acq_core_trig_dly | TRIG_DLY
0x6 | REG | Software trigger | acq_core_sw_trig | SW_TRIG
0x7 | REG | Number of shots | acq_core_shots | SHOTS
0x8 | REG | Trigger address register | acq_core_trig_pos | TRIG_POS
0x9 | REG | Pre-trigger samples | acq_core_pre_samples | PRE_SAMPLES
0xa | REG | Post-trigger samples | acq_core_post_samples | POST_SAMPLES
0xb | REG | Samples counter | acq_core_samples_cnt | SAMPLES_CNT
0xc | REG | DDR3 Start Address | acq_core_ddr3_start_addr | DDR3_START_ADDR
0xd | REG | DDR3 End Address | acq_core_ddr3_end_addr | DDR3_END_ADDR
0xe | REG | Acquisition channel control | acq_core_acq_chan_ctl | ACQ_CHAN_CTL
0xf | REG | Channel 0 Description | acq_core_ch0_desc | CH0_DESC
0x10 | REG | Channel 0 Atom Description | acq_core_ch0_atom_desc | CH0_ATOM_DESC
0x11 | REG | Channel 1 Description | acq_core_ch1_desc | CH1_DESC
0x12 | REG | Channel 1 Atom Description | acq_core_ch1_atom_desc | CH1_ATOM_DESC
0x13 | REG | Channel 2 Description | acq_core_ch2_desc | CH2_DESC
0x14 | REG | Channel 2 Atom Description | acq_core_ch2_atom_desc | CH2_ATOM_DESC
0x15 | REG | Channel 3 Description | acq_core_ch3_desc | CH3_DESC
0x16 | REG | Channel 3 Atom Description | acq_core_ch3_atom_desc | CH3_ATOM_DESC
0x17 | REG | Channel 4 Description | acq_core_ch4_desc | CH4_DESC
0x18 | REG | Channel 4 Atom Description | acq_core_ch4_atom_desc | CH4_ATOM_DESC
0x19 | REG | Channel 5 Description | acq_core_ch5_desc | CH5_DESC
0x1a | REG | Channel 5 Atom Description | acq_core_ch5_atom_desc | CH5_ATOM_DESC
0x1b | REG | Channel 6 Description | acq_core_ch6_desc | CH6_DESC
0x1c | REG | Channel 6 Atom Description | acq_core_ch6_atom_desc | CH6_ATOM_DESC
0x1d | REG | Channel 7 Description | acq_core_ch7_desc | CH7_DESC
0x1e | REG | Channel 7 Atom Description | acq_core_ch7_atom_desc | CH7_ATOM_DESC
0x1f | REG | Channel 8 Description | acq_core_ch8_desc | CH8_DESC
0x20 | REG | Channel 8 Atom Description | acq_core_ch8_atom_desc | CH8_ATOM_DESC
0x21 | REG | Channel 9 Description | acq_core_ch9_desc | CH9_DESC
0x22 | REG | Channel 9 Atom Description | acq_core_ch9_atom_desc | CH9_ATOM_DESC
0x23 | REG | Channel 10 Description | acq_core_ch10_desc | CH10_DESC
0x24 | REG | Channel 10 Atom Description | acq_core_ch10_atom_desc | CH10_ATOM_DESC
0x25 | REG | Channel 11 Description | acq_core_ch11_desc | CH11_DESC
0x26 | REG | Channel 11 Atom Description | acq_core_ch11_atom_desc | CH11_ATOM_DESC
0x27 | REG | Channel 12 Description | acq_core_ch12_desc | CH12_DESC
0x28 | REG | Channel 12 Atom Description | acq_core_ch12_atom_desc | CH12_ATOM_DESC
0x29 | REG | Channel 13 Description | acq_core_ch13_desc | CH13_DESC
0x2a | REG | Channel 13 Atom Description | acq_core_ch13_atom_desc | CH13_ATOM_DESC
0x2b | REG | Channel 14 Description | acq_core_ch14_desc | CH14_DESC
0x2c | REG | Channel 14 Atom Description | acq_core_ch14_atom_desc | CH14_ATOM_DESC
0x2d | REG | Channel 15 Description | acq_core_ch15_desc | CH15_DESC
0x2e | REG | Channel 15 Atom Description | acq_core_ch15_atom_desc | CH15_ATOM_DESC
0x2f | REG | Channel 16 Description | acq_core_ch16_desc | CH16_DESC
0x30 | REG | Channel 16 Atom Description | acq_core_ch16_atom_desc | CH16_ATOM_DESC
0x31 | REG | Channel 17 Description | acq_core_ch17_desc | CH17_DESC
0x32 | REG | Channel 17 Atom Description | acq_core_ch17_atom_desc | CH17_ATOM_DESC
0x33 | REG | Channel 18 Description | acq_core_ch18_desc | CH18_DESC
0x34 | REG | Channel 18 Atom Description | acq_core_ch18_atom_desc | CH18_ATOM_DESC
0x35 | REG | Channel 19 Description | acq_core_ch19_desc | CH19_DESC
0x36 | REG | Channel 19 Atom Description | acq_core_ch19_atom_desc | CH19_ATOM_DESC
0x37 | REG | Channel 20 Description | acq_core_ch20_desc | CH20_DESC
0x38 | REG | Channel 20 Atom Description | acq_core_ch20_atom_desc | CH20_ATOM_DESC
0x39 | REG | Channel 21 Description | acq_core_ch21_desc | CH21_DESC
0x3a | REG | Channel 21 Atom Description | acq_core_ch21_atom_desc | CH21_ATOM_DESC
0x3b | REG | Channel 22 Description | acq_core_ch22_desc | CH22_DESC
0x3c | REG | Channel 22 Atom Description | acq_core_ch22_atom_desc | CH22_ATOM_DESC
0x3d | REG | Channel 23 Description | acq_core_ch23_desc | CH23_DESC
0x3e | REG | Channel 23 Atom Description | acq_core_ch23_atom_desc | CH23_ATOM_DESC

### 2. HDL symbol

→ | rst_n_i |  | Control register: |
→ | clk_sys_i |  | acq_core_ctl_fsm_start_acq_o | →
⇒ | wb_adr_i[5:0] |  | acq_core_ctl_fsm_stop_acq_o | →
⇒ | wb_dat_i[31:0] |  | acq_core_ctl_reserved1_o[13:0] | ⇒
⇐ | wb_dat_o[31:0] |  | acq_core_ctl_fsm_acq_now_o | →
→ | wb_cyc_i |  | acq_core_ctl_reserved2_o[14:0] | ⇒
⇒ | wb_sel_i[3:0] |  |  |
→ | wb_stb_i |  | Status register: |
→ | wb_we_i |  | acq_core_sta_fsm_state_i[2:0] | ⇐
← | wb_ack_o |  | acq_core_sta_fsm_acq_done_i | ←
← | wb_stall_o |  | acq_core_sta_reserved1_i[3:0] | ⇐
|  |  | acq_core_sta_fc_trans_done_i | ←
|  |  | acq_core_sta_fc_full_i | ←
|  |  | acq_core_sta_reserved2_i[5:0] | ⇐
|  |  | acq_core_sta_ddr3_trans_done_i | ←
|  |  | acq_core_sta_reserved3_i[14:0] | ⇐
|  |  | Trigger configuration: |
|  |  | acq_core_trig_cfg_hw_trig_sel_o | →
|  |  | acq_core_trig_cfg_hw_trig_pol_o | →
|  |  | acq_core_trig_cfg_hw_trig_en_o | →
|  |  | acq_core_trig_cfg_sw_trig_en_o | →
|  |  | acq_core_trig_cfg_int_trig_sel_o[4:0] | ⇒
|  |  | acq_core_trig_cfg_reserved_o[22:0] | ⇒
|  |  | Trigger data config threshold: |
|  |  | acq_core_trig_data_cfg_thres_filt_o[7:0] | ⇒
|  |  | acq_core_trig_data_cfg_reserved_o[23:0] | ⇒
|  |  | Trigger data threshold: |
|  |  | acq_core_trig_data_thres_o[31:0] | ⇒
|  |  | Trigger delay: |
|  |  | acq_core_trig_dly_o[31:0] | ⇒
|  |  | Software trigger: |
|  |  | acq_core_sw_trig_o[31:0] | ⇒
|  |  | acq_core_sw_trig_wr_o | →
|  |  | Number of shots: |
|  |  | acq_core_shots_nb_o[15:0] | ⇒
|  |  | acq_core_shots_reserved_o[15:0] | ⇒
|  |  | Trigger address register: |
|  |  | acq_core_trig_pos_i[31:0] | ⇐
|  |  | Pre-trigger samples: |
|  |  | acq_core_pre_samples_o[31:0] | ⇒
|  |  | Post-trigger samples: |
|  |  | acq_core_post_samples_o[31:0] | ⇒
|  |  | Samples counter: |
|  |  | acq_core_samples_cnt_i[31:0] | ⇐
|  |  | DDR3 Start Address: |
|  |  | acq_core_ddr3_start_addr_o[31:0] | ⇒
|  |  | DDR3 End Address: |
|  |  | acq_core_ddr3_end_addr_o[31:0] | ⇒
|  |  | Acquisition channel control: |
|  |  | acq_core_acq_chan_ctl_which_o[4:0] | ⇒
|  |  | acq_core_acq_chan_ctl_reserved_o[2:0] | ⇒
|  |  | acq_core_acq_chan_ctl_dtrig_which_o[4:0] | ⇒
|  |  | acq_core_acq_chan_ctl_reserved1_o[18:0] | ⇒
|  |  | Channel 0 Description: |
|  |  | acq_core_ch0_desc_int_width_i[15:0] | ⇐
|  |  | acq_core_ch0_desc_num_coalesce_i[15:0] | ⇐
|  |  | Channel 0 Atom Description: |
|  |  | acq_core_ch0_atom_desc_num_atoms_i[15:0] | ⇐
|  |  | acq_core_ch0_atom_desc_atom_width_i[15:0] | ⇐
|  |  | Channel 1 Description: |
|  |  | acq_core_ch1_desc_int_width_i[15:0] | ⇐
|  |  | acq_core_ch1_desc_num_coalesce_i[15:0] | ⇐
|  |  | Channel 1 Atom Description: |
|  |  | acq_core_ch1_atom_desc_num_atoms_i[15:0] | ⇐
|  |  | acq_core_ch1_atom_desc_atom_width_i[15:0] | ⇐
|  |  | Channel 2 Description: |
|  |  | acq_core_ch2_desc_int_width_i[15:0] | ⇐
|  |  | acq_core_ch2_desc_num_coalesce_i[15:0] | ⇐
|  |  | Channel 2 Atom Description: |
|  |  | acq_core_ch2_atom_desc_num_atoms_i[15:0] | ⇐
|  |  | acq_core_ch2_atom_desc_atom_width_i[15:0] | ⇐
|  |  | Channel 3 Description: |
|  |  | acq_core_ch3_desc_int_width_i[15:0] | ⇐
|  |  | acq_core_ch3_desc_num_coalesce_i[15:0] | ⇐
|  |  | Channel 3 Atom Description: |
|  |  | acq_core_ch3_atom_desc_num_atoms_i[15:0] | ⇐
|  |  | acq_core_ch3_atom_desc_atom_width_i[15:0] | ⇐
|  |  | Channel 4 Description: |
|  |  | acq_core_ch4_desc_int_width_i[15:0] | ⇐
|  |  | acq_core_ch4_desc_num_coalesce_i[15:0] | ⇐
|  |  | Channel 4 Atom Description: |
|  |  | acq_core_ch4_atom_desc_num_atoms_i[15:0] | ⇐
|  |  | acq_core_ch4_atom_desc_atom_width_i[15:0] | ⇐
|  |  | Channel 5 Description: |
|  |  | acq_core_ch5_desc_int_width_i[15:0] | ⇐
|  |  | acq_core_ch5_desc_num_coalesce_i[15:0] | ⇐
|  |  | Channel 5 Atom Description: |
|  |  | acq_core_ch5_atom_desc_num_atoms_i[15:0] | ⇐
|  |  | acq_core_ch5_atom_desc_atom_width_i[15:0] | ⇐
|  |  | Channel 6 Description: |
|  |  | acq_core_ch6_desc_int_width_i[15:0] | ⇐
|  |  | acq_core_ch6_desc_num_coalesce_i[15:0] | ⇐
|  |  | Channel 6 Atom Description: |
|  |  | acq_core_ch6_atom_desc_num_atoms_i[15:0] | ⇐
|  |  | acq_core_ch6_atom_desc_atom_width_i[15:0] | ⇐
|  |  | Channel 7 Description: |
|  |  | acq_core_ch7_desc_int_width_i[15:0] | ⇐
|  |  | acq_core_ch7_desc_num_coalesce_i[15:0] | ⇐
|  |  | Channel 7 Atom Description: |
|  |  | acq_core_ch7_atom_desc_num_atoms_i[15:0] | ⇐
|  |  | acq_core_ch7_atom_desc_atom_width_i[15:0] | ⇐
|  |  | Channel 8 Description: |
|  |  | acq_core_ch8_desc_int_width_i[15:0] | ⇐
|  |  | acq_core_ch8_desc_num_coalesce_i[15:0] | ⇐
|  |  | Channel 8 Atom Description: |
|  |  | acq_core_ch8_atom_desc_num_atoms_i[15:0] | ⇐
|  |  | acq_core_ch8_atom_desc_atom_width_i[15:0] | ⇐
|  |  | Channel 9 Description: |
|  |  | acq_core_ch9_desc_int_width_i[15:0] | ⇐
|  |  | acq_core_ch9_desc_num_coalesce_i[15:0] | ⇐
|  |  | Channel 9 Atom Description: |
|  |  | acq_core_ch9_atom_desc_num_atoms_i[15:0] | ⇐
|  |  | acq_core_ch9_atom_desc_atom_width_i[15:0] | ⇐
|  |  | Channel 10 Description: |
|  |  | acq_core_ch10_desc_int_width_i[15:0] | ⇐
|  |  | acq_core_ch10_desc_num_coalesce_i[15:0] | ⇐
|  |  | Channel 10 Atom Description: |
|  |  | acq_core_ch10_atom_desc_num_atoms_i[15:0] | ⇐
|  |  | acq_core_ch10_atom_desc_atom_width_i[15:0] | ⇐
|  |  | Channel 11 Description: |
|  |  | acq_core_ch11_desc_int_width_i[15:0] | ⇐
|  |  | acq_core_ch11_desc_num_coalesce_i[15:0] | ⇐
|  |  | Channel 11 Atom Description: |
|  |  | acq_core_ch11_atom_desc_num_atoms_i[15:0] | ⇐
|  |  | acq_core_ch11_atom_desc_atom_width_i[15:0] | ⇐
|  |  | Channel 12 Description: |
|  |  | acq_core_ch12_desc_int_width_i[15:0] | ⇐
|  |  | acq_core_ch12_desc_num_coalesce_i[15:0] | ⇐
|  |  | Channel 12 Atom Description: |
|  |  | acq_core_ch12_atom_desc_num_atoms_i[15:0] | ⇐
|  |  | acq_core_ch12_atom_desc_atom_width_i[15:0] | ⇐
|  |  | Channel 13 Description: |
|  |  | acq_core_ch13_desc_int_width_i[15:0] | ⇐
|  |  | acq_core_ch13_desc_num_coalesce_i[15:0] | ⇐
|  |  | Channel 13 Atom Description: |
|  |  | acq_core_ch13_atom_desc_num_atoms_i[15:0] | ⇐
|  |  | acq_core_ch13_atom_desc_atom_width_i[15:0] | ⇐
|  |  | Channel 14 Description: |
|  |  | acq_core_ch14_desc_int_width_i[15:0] | ⇐
|  |  | acq_core_ch14_desc_num_coalesce_i[15:0] | ⇐
|  |  | Channel 14 Atom Description: |
|  |  | acq_core_ch14_atom_desc_num_atoms_i[15:0] | ⇐
|  |  | acq_core_ch14_atom_desc_atom_width_i[15:0] | ⇐
|  |  | Channel 15 Description: |
|  |  | acq_core_ch15_desc_int_width_i[15:0] | ⇐
|  |  | acq_core_ch15_desc_num_coalesce_i[15:0] | ⇐
|  |  | Channel 15 Atom Description: |
|  |  | acq_core_ch15_atom_desc_num_atoms_i[15:0] | ⇐
|  |  | acq_core_ch15_atom_desc_atom_width_i[15:0] | ⇐
|  |  | Channel 16 Description: |
|  |  | acq_core_ch16_desc_int_width_i[15:0] | ⇐
|  |  | acq_core_ch16_desc_num_coalesce_i[15:0] | ⇐
|  |  | Channel 16 Atom Description: |
|  |  | acq_core_ch16_atom_desc_num_atoms_i[15:0] | ⇐
|  |  | acq_core_ch16_atom_desc_atom_width_i[15:0] | ⇐
|  |  | Channel 17 Description: |
|  |  | acq_core_ch17_desc_int_width_i[15:0] | ⇐
|  |  | acq_core_ch17_desc_num_coalesce_i[15:0] | ⇐
|  |  | Channel 17 Atom Description: |
|  |  | acq_core_ch17_atom_desc_num_atoms_i[15:0] | ⇐
|  |  | acq_core_ch17_atom_desc_atom_width_i[15:0] | ⇐
|  |  | Channel 18 Description: |
|  |  | acq_core_ch18_desc_int_width_i[15:0] | ⇐
|  |  | acq_core_ch18_desc_num_coalesce_i[15:0] | ⇐
|  |  | Channel 18 Atom Description: |
|  |  | acq_core_ch18_atom_desc_num_atoms_i[15:0] | ⇐
|  |  | acq_core_ch18_atom_desc_atom_width_i[15:0] | ⇐
|  |  | Channel 19 Description: |
|  |  | acq_core_ch19_desc_int_width_i[15:0] | ⇐
|  |  | acq_core_ch19_desc_num_coalesce_i[15:0] | ⇐
|  |  | Channel 19 Atom Description: |
|  |  | acq_core_ch19_atom_desc_num_atoms_i[15:0] | ⇐
|  |  | acq_core_ch19_atom_desc_atom_width_i[15:0] | ⇐
|  |  | Channel 20 Description: |
|  |  | acq_core_ch20_desc_int_width_i[15:0] | ⇐
|  |  | acq_core_ch20_desc_num_coalesce_i[15:0] | ⇐
|  |  | Channel 20 Atom Description: |
|  |  | acq_core_ch20_atom_desc_num_atoms_i[15:0] | ⇐
|  |  | acq_core_ch20_atom_desc_atom_width_i[15:0] | ⇐
|  |  | Channel 21 Description: |
|  |  | acq_core_ch21_desc_int_width_i[15:0] | ⇐
|  |  | acq_core_ch21_desc_num_coalesce_i[15:0] | ⇐
|  |  | Channel 21 Atom Description: |
|  |  | acq_core_ch21_atom_desc_num_atoms_i[15:0] | ⇐
|  |  | acq_core_ch21_atom_desc_atom_width_i[15:0] | ⇐
|  |  | Channel 22 Description: |
|  |  | acq_core_ch22_desc_int_width_i[15:0] | ⇐
|  |  | acq_core_ch22_desc_num_coalesce_i[15:0] | ⇐
|  |  | Channel 22 Atom Description: |
|  |  | acq_core_ch22_atom_desc_num_atoms_i[15:0] | ⇐
|  |  | acq_core_ch22_atom_desc_atom_width_i[15:0] | ⇐
|  |  | Channel 23 Description: |
|  |  | acq_core_ch23_desc_int_width_i[15:0] | ⇐
|  |  | acq_core_ch23_desc_num_coalesce_i[15:0] | ⇐
|  |  | Channel 23 Atom Description: |
|  |  | acq_core_ch23_atom_desc_num_atoms_i[15:0] | ⇐
|  |  | acq_core_ch23_atom_desc_atom_width_i[15:0] | ⇐

### 3. Register description

### 3.1. Control register

HW prefix: | acq_core_ctl
HW address: | 0x0
C prefix: | CTL
C offset: | 0x0

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
RESERVED2[14:7] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
RESERVED2[6:0] | FSM_ACQ_NOW |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
RESERVED1[13:6] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
RESERVED1[5:0] | FSM_STOP_ACQ | FSM_START_ACQ |  |  |  |  |

- FSM_START_ACQ [write-only]: State machine acquisition_start command (ignore on read)
  1: ACQ_START (start acquisition, only when FSM is idle)
- FSM_STOP_ACQ [write-only]: State machine stop command (ignore on read)
  1: ACQ_STOP (stop acquisition, anytime)
- RESERVED1 [read/write]: Reserved1
  Ignore on read, write with 0's
- FSM_ACQ_NOW [read/write]: Acquire data immediately and don't wait for any trigger (ignore on read)
  1: Acquire immediately
  0: Wait for trigger
- RESERVED2 [read/write]: Reserved2
  Ignore on read, write with 0's

### 3.2. Status register

HW prefix: | acq_core_sta
HW address: | 0x1
C prefix: | STA
C offset: | 0x4

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
RESERVED3[14:7] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
RESERVED3[6:0] | DDR3_TRANS_DONE |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
RESERVED2[5:0] | FC_FULL | FC_TRANS_DONE |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
RESERVED1[3:0] | FSM_ACQ_DONE | FSM_STATE[2:0] |  |  |  |  |

- FSM_STATE [read-only]: State machine status
  States:
  0: illegal
  1: IDLE
  2: PRE_TRIG
  3: WAIT_TRIG
  4: POST_TRIG
  5: DECR_SHOT
  6: illegal
  7: illegal
- FSM_ACQ_DONE [read-only]: FSM acquisition status
  Values:
  0: in progress
  1: completed
- RESERVED1 [read-only]: Reserved
  Ignore on read, write with 0's
- FC_TRANS_DONE [read-only]: External flow control transfer status
  Values:
  0: in progress
  1: completed
- FC_FULL [read-only]: External flow control FIFO full status
  Values:
  0: not full
  1: full (data may be lost)
- RESERVED2 [read-only]: Reserved
  Ignore on read, write with 0's
- DDR3_TRANS_DONE [read-only]: DDR3 transfer status
  Values:
  0: in progress
  1: completed
- RESERVED3 [read-only]: Reserved
  Ignore on read, write with 0's

### 3.3. Trigger configuration

HW prefix: | acq_core_trig_cfg
HW address: | 0x2
C prefix: | TRIG_CFG
C offset: | 0x8

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
RESERVED[22:15] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
RESERVED[14:7] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
RESERVED[6:0] | INT_TRIG_SEL[4:4] |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
INT_TRIG_SEL[3:0] | SW_TRIG_EN | HW_TRIG_EN | HW_TRIG_POL | HW_TRIG_SEL |  |  |

- HW_TRIG_SEL [read/write]: Hardware trigger selection
  0: internal (data threshold)
  1: external (front panel trigger input)
- HW_TRIG_POL [read/write]: Hardware trigger polarity
  0: positive edge/slope
  1: negative edge/slope
- HW_TRIG_EN [read/write]: Hardware trigger enable
  0: disable
  1: enable
- SW_TRIG_EN [read/write]: Software trigger enable
  0: disable
  1: enable
- INT_TRIG_SEL [read/write]: Channel selection for internal trigger
  00: channel 1
  01: channel 2
  10: channel 3
  n: channel n+1
- RESERVED [read/write]: Reserved
  Ignore on read, write with 0's

### 3.4. Trigger data config threshold

HW prefix: | acq_core_trig_data_cfg
HW address: | 0x3
C prefix: | TRIG_DATA_CFG
C offset: | 0xc

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
RESERVED[23:16] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
RESERVED[15:8] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
RESERVED[7:0] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
THRES_FILT[7:0] |  |  |  |  |  |  |

- THRES_FILT [read/write]: Internal trigger threshold glitch filter
  Configures the internal trigger threshold glitch filter length.
- RESERVED [read/write]: Reserved
  Ignore on read, write with 0's

### 3.5. Trigger data threshold

HW prefix: | acq_core_trig_data_thres
HW address: | 0x4
C prefix: | TRIG_DATA_THRES
C offset: | 0x10

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
TRIG_DATA_THRES[31:24] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
TRIG_DATA_THRES[23:16] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
TRIG_DATA_THRES[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
TRIG_DATA_THRES[7:0] |  |  |  |  |  |  |

- TRIG_DATA_THRES [read/write]: Threshold for internal trigger
  Treated as binary two's complement and compared to the
  specified channel data

### 3.6. Trigger delay

HW prefix: | acq_core_trig_dly
HW address: | 0x5
C prefix: | TRIG_DLY
C offset: | 0x14

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
TRIG_DLY[31:24] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
TRIG_DLY[23:16] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
TRIG_DLY[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
TRIG_DLY[7:0] |  |  |  |  |  |  |

- TRIG_DLY [read/write]: Trigger delay value
  Delay to apply on the trigger in sampling clock period.
  The default clock frequency is 100MHz (period = 10ns).

### 3.7. Software trigger

HW prefix: | acq_core_sw_trig
HW address: | 0x6
C prefix: | SW_TRIG
C offset: | 0x18

Writing (anything) to this register generates a software trigger.

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
SW_TRIG[31:24] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
SW_TRIG[23:16] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
SW_TRIG[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
SW_TRIG[7:0] |  |  |  |  |  |  |

- SW_TRIG [write-only]: Software trigger (ignore on read)

### 3.8. Number of shots

HW prefix: | acq_core_shots
HW address: | 0x7
C prefix: | SHOTS
C offset: | 0x1c

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
RESERVED[15:8] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
RESERVED[7:0] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
NB[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
NB[7:0] |  |  |  |  |  |  |

- NB [read/write]: Number of shots
  Number of shots required in multi-shot mode, set to one for single-shot mode.
- RESERVED [read/write]: Reserved
  Ignore on read, write with 0's

### 3.9. Trigger address register

HW prefix: | acq_core_trig_pos
HW address: | 0x8
C prefix: | TRIG_POS
C offset: | 0x20

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
TRIG_POS[31:24] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
TRIG_POS[23:16] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
TRIG_POS[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
TRIG_POS[7:0] |  |  |  |  |  |  |

- TRIG_POS [read-only]: Trigger address
  Trigger address in DDR memory.
  Only used in single-shot mode.

### 3.10. Pre-trigger samples

HW prefix: | acq_core_pre_samples
HW address: | 0x9
C prefix: | PRE_SAMPLES
C offset: | 0x24

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
PRE_SAMPLES[31:24] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
PRE_SAMPLES[23:16] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
PRE_SAMPLES[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
PRE_SAMPLES[7:0] |  |  |  |  |  |  |

- PRE_SAMPLES [read/write]: Pre-trigger samples
  Number of requested pre-trigger samples

### 3.11. Post-trigger samples

HW prefix: | acq_core_post_samples
HW address: | 0xa
C prefix: | POST_SAMPLES
C offset: | 0x28

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
POST_SAMPLES[31:24] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
POST_SAMPLES[23:16] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
POST_SAMPLES[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
POST_SAMPLES[7:0] |  |  |  |  |  |  |

- POST_SAMPLES [read/write]: Post-trigger samples
  Number of requested post-trigger samples

### 3.12. Samples counter

HW prefix: | acq_core_samples_cnt
HW address: | 0xb
C prefix: | SAMPLES_CNT
C offset: | 0x2c

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
SAMPLES_CNT[31:24] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
SAMPLES_CNT[23:16] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
SAMPLES_CNT[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
SAMPLES_CNT[7:0] |  |  |  |  |  |  |

- SAMPLES_CNT [read-only]: Samples counter
  Counts the number of samples.
  It is reset on START and then counts the number of pre-trigger + post-trigger samples

### 3.13. DDR3 Start Address

HW prefix: | acq_core_ddr3_start_addr
HW address: | 0xc
C prefix: | DDR3_START_ADDR
C offset: | 0x30

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
DDR3_START_ADDR[31:24] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
DDR3_START_ADDR[23:16] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
DDR3_START_ADDR[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
DDR3_START_ADDR[7:0] |  |  |  |  |  |  |

- DDR3_START_ADDR [read/write]: DDR3 Start Address
  Start address in DDR3 memory for the next acquisition.
  Must be word aligned (2 LSB zeroed)

### 3.14. DDR3 End Address

HW prefix: | acq_core_ddr3_end_addr
HW address: | 0xd
C prefix: | DDR3_END_ADDR
C offset: | 0x34

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
DDR3_END_ADDR[31:24] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
DDR3_END_ADDR[23:16] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
DDR3_END_ADDR[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
DDR3_END_ADDR[7:0] |  |  |  |  |  |  |

- DDR3_END_ADDR [read/write]: DDR3 End Address
  End address in DDR3 memory for the next acquisition.
  Must be word aligned (2 LSB zeroed)

### 3.15. Acquisition channel control

HW prefix: | acq_core_acq_chan_ctl
HW address: | 0xe
C prefix: | ACQ_CHAN_CTL
C offset: | 0x38

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
RESERVED1[18:11] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
RESERVED1[10:3] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
RESERVED1[2:0] | DTRIG_WHICH[4:0] |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
RESERVED[2:0] | WHICH[4:0] |  |  |  |  |  |

- WHICH [read/write]: Acquisition channel selection
  Selection of path to acquire on next acquisition.
- RESERVED [read/write]: Reserved
  Ignore on read, write with 0's
- DTRIG_WHICH [read/write]: Data-driven channel selection
  Selection of path to detect data-driven trigger on next acquisition.
- RESERVED1 [read/write]: Reserved1
  Ignore on read, write with 0's

### 3.16. Channel 0 Description

HW prefix: | acq_core_ch0_desc
HW address: | 0xf
C prefix: | CH0_DESC
C offset: | 0x3c

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
NUM_COALESCE[15:8] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
NUM_COALESCE[7:0] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
INT_WIDTH[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
INT_WIDTH[7:0] |  |  |  |  |  |  |

- INT_WIDTH [read-only]: Channel Internal Width
  Internal Channel Width (must multiply by the
  number of coalesced words to get the total width)
- NUM_COALESCE [read-only]: Number of coalescing words
  Number of coalescing words to form the complete user word

### 3.17. Channel 0 Atom Description

HW prefix: | acq_core_ch0_atom_desc
HW address: | 0x10
C prefix: | CH0_ATOM_DESC
C offset: | 0x40

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
ATOM_WIDTH[15:8] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
ATOM_WIDTH[7:0] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
NUM_ATOMS[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
NUM_ATOMS[7:0] |  |  |  |  |  |  |

- NUM_ATOMS [read-only]: Number of atoms inside the complete data word (int_width*num_coalesce)
  Number of atoms inside the complete data word
- ATOM_WIDTH [read-only]: Atom width
  Atom width in bits

### 3.18. Channel 1 Description

HW prefix: | acq_core_ch1_desc
HW address: | 0x11
C prefix: | CH1_DESC
C offset: | 0x44

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
NUM_COALESCE[15:8] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
NUM_COALESCE[7:0] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
INT_WIDTH[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
INT_WIDTH[7:0] |  |  |  |  |  |  |

- INT_WIDTH [read-only]: Channel Internal Width
  Internal Channel Width (must multiply by the
  number of coalesced words to get the total width)
- NUM_COALESCE [read-only]: Number of coalescing words
  Number of coalescing words to form the complete user word

### 3.19. Channel 1 Atom Description

HW prefix: | acq_core_ch1_atom_desc
HW address: | 0x12
C prefix: | CH1_ATOM_DESC
C offset: | 0x48

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
ATOM_WIDTH[15:8] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
ATOM_WIDTH[7:0] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
NUM_ATOMS[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
NUM_ATOMS[7:0] |  |  |  |  |  |  |

- NUM_ATOMS [read-only]: Number of atoms inside the complete data word (int_width*num_coalesce)
  Number of atoms inside the complete data word
- ATOM_WIDTH [read-only]: Atom width
  Atom width in bits

### 3.20. Channel 2 Description

HW prefix: | acq_core_ch2_desc
HW address: | 0x13
C prefix: | CH2_DESC
C offset: | 0x4c

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
NUM_COALESCE[15:8] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
NUM_COALESCE[7:0] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
INT_WIDTH[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
INT_WIDTH[7:0] |  |  |  |  |  |  |

- INT_WIDTH [read-only]: Channel Internal Width
  Internal Channel Width (must multiply by the
  number of coalesced words to get the total width)
- NUM_COALESCE [read-only]: Number of coalescing words
  Number of coalescing words to form the complete user word

### 3.21. Channel 2 Atom Description

HW prefix: | acq_core_ch2_atom_desc
HW address: | 0x14
C prefix: | CH2_ATOM_DESC
C offset: | 0x50

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
ATOM_WIDTH[15:8] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
ATOM_WIDTH[7:0] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
NUM_ATOMS[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
NUM_ATOMS[7:0] |  |  |  |  |  |  |

- NUM_ATOMS [read-only]: Number of atoms inside the complete data word (int_width*num_coalesce)
  Number of atoms inside the complete data word
- ATOM_WIDTH [read-only]: Atom width
  Atom width in bits

### 3.22. Channel 3 Description

HW prefix: | acq_core_ch3_desc
HW address: | 0x15
C prefix: | CH3_DESC
C offset: | 0x54

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
NUM_COALESCE[15:8] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
NUM_COALESCE[7:0] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
INT_WIDTH[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
INT_WIDTH[7:0] |  |  |  |  |  |  |

- INT_WIDTH [read-only]: Channel Internal Width
  Internal Channel Width (must multiply by the
  number of coalesced words to get the total width)
- NUM_COALESCE [read-only]: Number of coalescing words
  Number of coalescing words to form the complete user word

### 3.23. Channel 3 Atom Description

HW prefix: | acq_core_ch3_atom_desc
HW address: | 0x16
C prefix: | CH3_ATOM_DESC
C offset: | 0x58

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
ATOM_WIDTH[15:8] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
ATOM_WIDTH[7:0] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
NUM_ATOMS[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
NUM_ATOMS[7:0] |  |  |  |  |  |  |

- NUM_ATOMS [read-only]: Number of atoms inside the complete data word (int_width*num_coalesce)
  Number of atoms inside the complete data word
- ATOM_WIDTH [read-only]: Atom width
  Atom width in bits

### 3.24. Channel 4 Description

HW prefix: | acq_core_ch4_desc
HW address: | 0x17
C prefix: | CH4_DESC
C offset: | 0x5c

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
NUM_COALESCE[15:8] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
NUM_COALESCE[7:0] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
INT_WIDTH[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
INT_WIDTH[7:0] |  |  |  |  |  |  |

- INT_WIDTH [read-only]: Channel Internal Width
  Internal Channel Width (must multiply by the
  number of coalesced words to get the total width)
- NUM_COALESCE [read-only]: Number of coalescing words
  Number of coalescing words to form the complete user word

### 3.25. Channel 4 Atom Description

HW prefix: | acq_core_ch4_atom_desc
HW address: | 0x18
C prefix: | CH4_ATOM_DESC
C offset: | 0x60

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
ATOM_WIDTH[15:8] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
ATOM_WIDTH[7:0] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
NUM_ATOMS[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
NUM_ATOMS[7:0] |  |  |  |  |  |  |

- NUM_ATOMS [read-only]: Number of atoms inside the complete data word (int_width*num_coalesce)
  Number of atoms inside the complete data word
- ATOM_WIDTH [read-only]: Atom width
  Atom width in bits

### 3.26. Channel 5 Description

HW prefix: | acq_core_ch5_desc
HW address: | 0x19
C prefix: | CH5_DESC
C offset: | 0x64

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
NUM_COALESCE[15:8] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
NUM_COALESCE[7:0] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
INT_WIDTH[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
INT_WIDTH[7:0] |  |  |  |  |  |  |

- INT_WIDTH [read-only]: Channel Internal Width
  Internal Channel Width (must multiply by the
  number of coalesced words to get the total width)
- NUM_COALESCE [read-only]: Number of coalescing words
  Number of coalescing words to form the complete user word

### 3.27. Channel 5 Atom Description

HW prefix: | acq_core_ch5_atom_desc
HW address: | 0x1a
C prefix: | CH5_ATOM_DESC
C offset: | 0x68

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
ATOM_WIDTH[15:8] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
ATOM_WIDTH[7:0] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
NUM_ATOMS[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
NUM_ATOMS[7:0] |  |  |  |  |  |  |

- NUM_ATOMS [read-only]: Number of atoms inside the complete data word (int_width*num_coalesce)
  Number of atoms inside the complete data word
- ATOM_WIDTH [read-only]: Atom width
  Atom width in bits

### 3.28. Channel 6 Description

HW prefix: | acq_core_ch6_desc
HW address: | 0x1b
C prefix: | CH6_DESC
C offset: | 0x6c

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
NUM_COALESCE[15:8] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
NUM_COALESCE[7:0] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
INT_WIDTH[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
INT_WIDTH[7:0] |  |  |  |  |  |  |

- INT_WIDTH [read-only]: Channel Internal Width
  Internal Channel Width (must multiply by the
  number of coalesced words to get the total width)
- NUM_COALESCE [read-only]: Number of coalescing words
  Number of coalescing words to form the complete user word

### 3.29. Channel 6 Atom Description

HW prefix: | acq_core_ch6_atom_desc
HW address: | 0x1c
C prefix: | CH6_ATOM_DESC
C offset: | 0x70

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
ATOM_WIDTH[15:8] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
ATOM_WIDTH[7:0] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
NUM_ATOMS[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
NUM_ATOMS[7:0] |  |  |  |  |  |  |

- NUM_ATOMS [read-only]: Number of atoms inside the complete data word (int_width*num_coalesce)
  Number of atoms inside the complete data word
- ATOM_WIDTH [read-only]: Atom width
  Atom width in bits

### 3.30. Channel 7 Description

HW prefix: | acq_core_ch7_desc
HW address: | 0x1d
C prefix: | CH7_DESC
C offset: | 0x74

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
NUM_COALESCE[15:8] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
NUM_COALESCE[7:0] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
INT_WIDTH[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
INT_WIDTH[7:0] |  |  |  |  |  |  |

- INT_WIDTH [read-only]: Channel Internal Width
  Internal Channel Width (must multiply by the
  number of coalesced words to get the total width)
- NUM_COALESCE [read-only]: Number of coalescing words
  Number of coalescing words to form the complete user word

### 3.31. Channel 7 Atom Description

HW prefix: | acq_core_ch7_atom_desc
HW address: | 0x1e
C prefix: | CH7_ATOM_DESC
C offset: | 0x78

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
ATOM_WIDTH[15:8] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
ATOM_WIDTH[7:0] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
NUM_ATOMS[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
NUM_ATOMS[7:0] |  |  |  |  |  |  |

- NUM_ATOMS [read-only]: Number of atoms inside the complete data word (int_width*num_coalesce)
  Number of atoms inside the complete data word
- ATOM_WIDTH [read-only]: Atom width
  Atom width in bits

### 3.32. Channel 8 Description

HW prefix: | acq_core_ch8_desc
HW address: | 0x1f
C prefix: | CH8_DESC
C offset: | 0x7c

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
NUM_COALESCE[15:8] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
NUM_COALESCE[7:0] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
INT_WIDTH[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
INT_WIDTH[7:0] |  |  |  |  |  |  |

- INT_WIDTH [read-only]: Channel Internal Width
  Internal Channel Width (must multiply by the
  number of coalesced words to get the total width)
- NUM_COALESCE [read-only]: Number of coalescing words
  Number of coalescing words to form the complete user word

### 3.33. Channel 8 Atom Description

HW prefix: | acq_core_ch8_atom_desc
HW address: | 0x20
C prefix: | CH8_ATOM_DESC
C offset: | 0x80

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
ATOM_WIDTH[15:8] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
ATOM_WIDTH[7:0] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
NUM_ATOMS[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
NUM_ATOMS[7:0] |  |  |  |  |  |  |

- NUM_ATOMS [read-only]: Number of atoms inside the complete data word (int_width*num_coalesce)
  Number of atoms inside the complete data word
- ATOM_WIDTH [read-only]: Atom width
  Atom width in bits

### 3.34. Channel 9 Description

HW prefix: | acq_core_ch9_desc
HW address: | 0x21
C prefix: | CH9_DESC
C offset: | 0x84

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
NUM_COALESCE[15:8] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
NUM_COALESCE[7:0] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
INT_WIDTH[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
INT_WIDTH[7:0] |  |  |  |  |  |  |

- INT_WIDTH [read-only]: Channel Internal Width
  Internal Channel Width (must multiply by the
  number of coalesced words to get the total width)
- NUM_COALESCE [read-only]: Number of coalescing words
  Number of coalescing words to form the complete user word

### 3.35. Channel 9 Atom Description

HW prefix: | acq_core_ch9_atom_desc
HW address: | 0x22
C prefix: | CH9_ATOM_DESC
C offset: | 0x88

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
ATOM_WIDTH[15:8] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
ATOM_WIDTH[7:0] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
NUM_ATOMS[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
NUM_ATOMS[7:0] |  |  |  |  |  |  |

- NUM_ATOMS [read-only]: Number of atoms inside the complete data word (int_width*num_coalesce)
  Number of atoms inside the complete data word
- ATOM_WIDTH [read-only]: Atom width
  Atom width in bits

### 3.36. Channel 10 Description

HW prefix: | acq_core_ch10_desc
HW address: | 0x23
C prefix: | CH10_DESC
C offset: | 0x8c

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
NUM_COALESCE[15:8] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
NUM_COALESCE[7:0] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
INT_WIDTH[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
INT_WIDTH[7:0] |  |  |  |  |  |  |

- INT_WIDTH [read-only]: Channel Internal Width
  Internal Channel Width (must multiply by the
  number of coalesced words to get the total width)
- NUM_COALESCE [read-only]: Number of coalescing words
  Number of coalescing words to form the complete user word

### 3.37. Channel 10 Atom Description

HW prefix: | acq_core_ch10_atom_desc
HW address: | 0x24
C prefix: | CH10_ATOM_DESC
C offset: | 0x90

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
ATOM_WIDTH[15:8] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
ATOM_WIDTH[7:0] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
NUM_ATOMS[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
NUM_ATOMS[7:0] |  |  |  |  |  |  |

- NUM_ATOMS [read-only]: Number of atoms inside the complete data word (int_width*num_coalesce)
  Number of atoms inside the complete data word
- ATOM_WIDTH [read-only]: Atom width
  Atom width in bits

### 3.38. Channel 11 Description

HW prefix: | acq_core_ch11_desc
HW address: | 0x25
C prefix: | CH11_DESC
C offset: | 0x94

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
NUM_COALESCE[15:8] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
NUM_COALESCE[7:0] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
INT_WIDTH[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
INT_WIDTH[7:0] |  |  |  |  |  |  |

- INT_WIDTH [read-only]: Channel Internal Width
  Internal Channel Width (must multiply by the
  number of coalesced words to get the total width)
- NUM_COALESCE [read-only]: Number of coalescing words
  Number of coalescing words to form the complete user word

### 3.39. Channel 11 Atom Description

HW prefix: | acq_core_ch11_atom_desc
HW address: | 0x26
C prefix: | CH11_ATOM_DESC
C offset: | 0x98

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
ATOM_WIDTH[15:8] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
ATOM_WIDTH[7:0] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
NUM_ATOMS[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
NUM_ATOMS[7:0] |  |  |  |  |  |  |

- NUM_ATOMS [read-only]: Number of atoms inside the complete data word (int_width*num_coalesce)
  Number of atoms inside the complete data word
- ATOM_WIDTH [read-only]: Atom width
  Atom width in bits

### 3.40. Channel 12 Description

HW prefix: | acq_core_ch12_desc
HW address: | 0x27
C prefix: | CH12_DESC
C offset: | 0x9c

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
NUM_COALESCE[15:8] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
NUM_COALESCE[7:0] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
INT_WIDTH[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
INT_WIDTH[7:0] |  |  |  |  |  |  |

- INT_WIDTH [read-only]: Channel Internal Width
  Internal Channel Width (must multiply by the
  number of coalesced words to get the total width)
- NUM_COALESCE [read-only]: Number of coalescing words
  Number of coalescing words to form the complete user word

### 3.41. Channel 12 Atom Description

HW prefix: | acq_core_ch12_atom_desc
HW address: | 0x28
C prefix: | CH12_ATOM_DESC
C offset: | 0xa0

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
ATOM_WIDTH[15:8] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
ATOM_WIDTH[7:0] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
NUM_ATOMS[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
NUM_ATOMS[7:0] |  |  |  |  |  |  |

- NUM_ATOMS [read-only]: Number of atoms inside the complete data word (int_width*num_coalesce)
  Number of atoms inside the complete data word
- ATOM_WIDTH [read-only]: Atom width
  Atom width in bits

### 3.42. Channel 13 Description

HW prefix: | acq_core_ch13_desc
HW address: | 0x29
C prefix: | CH13_DESC
C offset: | 0xa4

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
NUM_COALESCE[15:8] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
NUM_COALESCE[7:0] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
INT_WIDTH[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
INT_WIDTH[7:0] |  |  |  |  |  |  |

- INT_WIDTH [read-only]: Channel Internal Width
  Internal Channel Width (must multiply by the
  number of coalesced words to get the total width)
- NUM_COALESCE [read-only]: Number of coalescing words
  Number of coalescing words to form the complete user word

### 3.43. Channel 13 Atom Description

HW prefix: | acq_core_ch13_atom_desc
HW address: | 0x2a
C prefix: | CH13_ATOM_DESC
C offset: | 0xa8

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
ATOM_WIDTH[15:8] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
ATOM_WIDTH[7:0] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
NUM_ATOMS[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
NUM_ATOMS[7:0] |  |  |  |  |  |  |

- NUM_ATOMS [read-only]: Number of atoms inside the complete data word (int_width*num_coalesce)
  Number of atoms inside the complete data word
- ATOM_WIDTH [read-only]: Atom width
  Atom width in bits

### 3.44. Channel 14 Description

HW prefix: | acq_core_ch14_desc
HW address: | 0x2b
C prefix: | CH14_DESC
C offset: | 0xac

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
NUM_COALESCE[15:8] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
NUM_COALESCE[7:0] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
INT_WIDTH[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
INT_WIDTH[7:0] |  |  |  |  |  |  |

- INT_WIDTH [read-only]: Channel Internal Width
  Internal Channel Width (must multiply by the
  number of coalesced words to get the total width)
- NUM_COALESCE [read-only]: Number of coalescing words
  Number of coalescing words to form the complete user word

### 3.45. Channel 14 Atom Description

HW prefix: | acq_core_ch14_atom_desc
HW address: | 0x2c
C prefix: | CH14_ATOM_DESC
C offset: | 0xb0

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
ATOM_WIDTH[15:8] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
ATOM_WIDTH[7:0] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
NUM_ATOMS[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
NUM_ATOMS[7:0] |  |  |  |  |  |  |

- NUM_ATOMS [read-only]: Number of atoms inside the complete data word (int_width*num_coalesce)
  Number of atoms inside the complete data word
- ATOM_WIDTH [read-only]: Atom width
  Atom width in bits

### 3.46. Channel 15 Description

HW prefix: | acq_core_ch15_desc
HW address: | 0x2d
C prefix: | CH15_DESC
C offset: | 0xb4

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
NUM_COALESCE[15:8] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
NUM_COALESCE[7:0] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
INT_WIDTH[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
INT_WIDTH[7:0] |  |  |  |  |  |  |

- INT_WIDTH [read-only]: Channel Internal Width
  Internal Channel Width (must multiply by the
  number of coalesced words to get the total width)
- NUM_COALESCE [read-only]: Number of coalescing words
  Number of coalescing words to form the complete user word

### 3.47. Channel 15 Atom Description

HW prefix: | acq_core_ch15_atom_desc
HW address: | 0x2e
C prefix: | CH15_ATOM_DESC
C offset: | 0xb8

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
ATOM_WIDTH[15:8] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
ATOM_WIDTH[7:0] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
NUM_ATOMS[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
NUM_ATOMS[7:0] |  |  |  |  |  |  |

- NUM_ATOMS [read-only]: Number of atoms inside the complete data word (int_width*num_coalesce)
  Number of atoms inside the complete data word
- ATOM_WIDTH [read-only]: Atom width
  Atom width in bits

### 3.48. Channel 16 Description

HW prefix: | acq_core_ch16_desc
HW address: | 0x2f
C prefix: | CH16_DESC
C offset: | 0xbc

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
NUM_COALESCE[15:8] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
NUM_COALESCE[7:0] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
INT_WIDTH[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
INT_WIDTH[7:0] |  |  |  |  |  |  |

- INT_WIDTH [read-only]: Channel Internal Width
  Internal Channel Width (must multiply by the
  number of coalesced words to get the total width)
- NUM_COALESCE [read-only]: Number of coalescing words
  Number of coalescing words to form the complete user word

### 3.49. Channel 16 Atom Description

HW prefix: | acq_core_ch16_atom_desc
HW address: | 0x30
C prefix: | CH16_ATOM_DESC
C offset: | 0xc0

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
ATOM_WIDTH[15:8] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
ATOM_WIDTH[7:0] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
NUM_ATOMS[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
NUM_ATOMS[7:0] |  |  |  |  |  |  |

- NUM_ATOMS [read-only]: Number of atoms inside the complete data word (int_width*num_coalesce)
  Number of atoms inside the complete data word
- ATOM_WIDTH [read-only]: Atom width
  Atom width in bits

### 3.50. Channel 17 Description

HW prefix: | acq_core_ch17_desc
HW address: | 0x31
C prefix: | CH17_DESC
C offset: | 0xc4

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
NUM_COALESCE[15:8] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
NUM_COALESCE[7:0] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
INT_WIDTH[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
INT_WIDTH[7:0] |  |  |  |  |  |  |

- INT_WIDTH [read-only]: Channel Internal Width
  Internal Channel Width (must multiply by the
  number of coalesced words to get the total width)
- NUM_COALESCE [read-only]: Number of coalescing words
  Number of coalescing words to form the complete user word

### 3.51. Channel 17 Atom Description

HW prefix: | acq_core_ch17_atom_desc
HW address: | 0x32
C prefix: | CH17_ATOM_DESC
C offset: | 0xc8

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
ATOM_WIDTH[15:8] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
ATOM_WIDTH[7:0] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
NUM_ATOMS[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
NUM_ATOMS[7:0] |  |  |  |  |  |  |

- NUM_ATOMS [read-only]: Number of atoms inside the complete data word (int_width*num_coalesce)
  Number of atoms inside the complete data word
- ATOM_WIDTH [read-only]: Atom width
  Atom width in bits

### 3.52. Channel 18 Description

HW prefix: | acq_core_ch18_desc
HW address: | 0x33
C prefix: | CH18_DESC
C offset: | 0xcc

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
NUM_COALESCE[15:8] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
NUM_COALESCE[7:0] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
INT_WIDTH[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
INT_WIDTH[7:0] |  |  |  |  |  |  |

- INT_WIDTH [read-only]: Channel Internal Width
  Internal Channel Width (must multiply by the
  number of coalesced words to get the total width)
- NUM_COALESCE [read-only]: Number of coalescing words
  Number of coalescing words to form the complete user word

### 3.53. Channel 18 Atom Description

HW prefix: | acq_core_ch18_atom_desc
HW address: | 0x34
C prefix: | CH18_ATOM_DESC
C offset: | 0xd0

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
ATOM_WIDTH[15:8] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
ATOM_WIDTH[7:0] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
NUM_ATOMS[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
NUM_ATOMS[7:0] |  |  |  |  |  |  |

- NUM_ATOMS [read-only]: Number of atoms inside the complete data word (int_width*num_coalesce)
  Number of atoms inside the complete data word
- ATOM_WIDTH [read-only]: Atom width
  Atom width in bits

### 3.54. Channel 19 Description

HW prefix: | acq_core_ch19_desc
HW address: | 0x35
C prefix: | CH19_DESC
C offset: | 0xd4

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
NUM_COALESCE[15:8] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
NUM_COALESCE[7:0] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
INT_WIDTH[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
INT_WIDTH[7:0] |  |  |  |  |  |  |

- INT_WIDTH [read-only]: Channel Internal Width
  Internal Channel Width (must multiply by the
  number of coalesced words to get the total width)
- NUM_COALESCE [read-only]: Number of coalescing words
  Number of coalescing words to form the complete user word

### 3.55. Channel 19 Atom Description

HW prefix: | acq_core_ch19_atom_desc
HW address: | 0x36
C prefix: | CH19_ATOM_DESC
C offset: | 0xd8

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
ATOM_WIDTH[15:8] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
ATOM_WIDTH[7:0] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
NUM_ATOMS[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
NUM_ATOMS[7:0] |  |  |  |  |  |  |

- NUM_ATOMS [read-only]: Number of atoms inside the complete data word (int_width*num_coalesce)
  Number of atoms inside the complete data word
- ATOM_WIDTH [read-only]: Atom width
  Atom width in bits

### 3.56. Channel 20 Description

HW prefix: | acq_core_ch20_desc
HW address: | 0x37
C prefix: | CH20_DESC
C offset: | 0xdc

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
NUM_COALESCE[15:8] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
NUM_COALESCE[7:0] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
INT_WIDTH[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
INT_WIDTH[7:0] |  |  |  |  |  |  |

- INT_WIDTH [read-only]: Channel Internal Width
  Internal Channel Width (must multiply by the
  number of coalesced words to get the total width)
- NUM_COALESCE [read-only]: Number of coalescing words
  Number of coalescing words to form the complete user word

### 3.57. Channel 20 Atom Description

HW prefix: | acq_core_ch20_atom_desc
HW address: | 0x38
C prefix: | CH20_ATOM_DESC
C offset: | 0xe0

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
ATOM_WIDTH[15:8] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
ATOM_WIDTH[7:0] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
NUM_ATOMS[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
NUM_ATOMS[7:0] |  |  |  |  |  |  |

- NUM_ATOMS [read-only]: Number of atoms inside the complete data word (int_width*num_coalesce)
  Number of atoms inside the complete data word
- ATOM_WIDTH [read-only]: Atom width
  Atom width in bits

### 3.58. Channel 21 Description

HW prefix: | acq_core_ch21_desc
HW address: | 0x39
C prefix: | CH21_DESC
C offset: | 0xe4

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
NUM_COALESCE[15:8] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
NUM_COALESCE[7:0] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
INT_WIDTH[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
INT_WIDTH[7:0] |  |  |  |  |  |  |

- INT_WIDTH [read-only]: Channel Internal Width
  Internal Channel Width (must multiply by the
  number of coalesced words to get the total width)
- NUM_COALESCE [read-only]: Number of coalescing words
  Number of coalescing words to form the complete user word

### 3.59. Channel 21 Atom Description

HW prefix: | acq_core_ch21_atom_desc
HW address: | 0x3a
C prefix: | CH21_ATOM_DESC
C offset: | 0xe8

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
ATOM_WIDTH[15:8] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
ATOM_WIDTH[7:0] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
NUM_ATOMS[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
NUM_ATOMS[7:0] |  |  |  |  |  |  |

- NUM_ATOMS [read-only]: Number of atoms inside the complete data word (int_width*num_coalesce)
  Number of atoms inside the complete data word
- ATOM_WIDTH [read-only]: Atom width
  Atom width in bits

### 3.60. Channel 22 Description

HW prefix: | acq_core_ch22_desc
HW address: | 0x3b
C prefix: | CH22_DESC
C offset: | 0xec

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
NUM_COALESCE[15:8] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
NUM_COALESCE[7:0] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
INT_WIDTH[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
INT_WIDTH[7:0] |  |  |  |  |  |  |

- INT_WIDTH [read-only]: Channel Internal Width
  Internal Channel Width (must multiply by the
  number of coalesced words to get the total width)
- NUM_COALESCE [read-only]: Number of coalescing words
  Number of coalescing words to form the complete user word

### 3.61. Channel 22 Atom Description

HW prefix: | acq_core_ch22_atom_desc
HW address: | 0x3c
C prefix: | CH22_ATOM_DESC
C offset: | 0xf0

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
ATOM_WIDTH[15:8] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
ATOM_WIDTH[7:0] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
NUM_ATOMS[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
NUM_ATOMS[7:0] |  |  |  |  |  |  |

- NUM_ATOMS [read-only]: Number of atoms inside the complete data word (int_width*num_coalesce)
  Number of atoms inside the complete data word
- ATOM_WIDTH [read-only]: Atom width
  Atom width in bits

### 3.62. Channel 23 Description

HW prefix: | acq_core_ch23_desc
HW address: | 0x3d
C prefix: | CH23_DESC
C offset: | 0xf4

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
NUM_COALESCE[15:8] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
NUM_COALESCE[7:0] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
INT_WIDTH[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
INT_WIDTH[7:0] |  |  |  |  |  |  |

- INT_WIDTH [read-only]: Channel Internal Width
  Internal Channel Width (must multiply by the
  number of coalesced words to get the total width)
- NUM_COALESCE [read-only]: Number of coalescing words
  Number of coalescing words to form the complete user word

### 3.63. Channel 23 Atom Description

HW prefix: | acq_core_ch23_atom_desc
HW address: | 0x3e
C prefix: | CH23_ATOM_DESC
C offset: | 0xf8

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
ATOM_WIDTH[15:8] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
ATOM_WIDTH[7:0] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
NUM_ATOMS[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
NUM_ATOMS[7:0] |  |  |  |  |  |  |

- NUM_ATOMS [read-only]: Number of atoms inside the complete data word (int_width*num_coalesce)
  Number of atoms inside the complete data word
- ATOM_WIDTH [read-only]: Atom width
  Atom width in bits