# wb_fmcpico1m_4ch_csr

### Control and status registers for FMC PICO 1M 4CH

Wishbone slave for control and status registers related to FMC PICO 1M 4CH with access from CSR bus

### Contents:

1. Memory map summary
2. HDL symbol
3. Register description
3.1. FMC Status
3.2. FMC Control
3.3. Input Range Control
3.4. ADC Data Channel 0
3.5. ADC Data Channel 1
3.6. ADC Data Channel 2
3.7. ADC Data Channel 3

### 1. Memory map summary

H/W Address | Type | Name | VHDL/Verilog prefix | C prefix
--- | --- | --- | --- | ---
0x0 | REG | FMC Status | wb_fmcpico1m_4ch_csr_fmc_status | FMC_STATUS
0x1 | REG | FMC Control | wb_fmcpico1m_4ch_csr_fmc_ctl | FMC_CTL
0x2 | REG | Input Range Control | wb_fmcpico1m_4ch_csr_rng_ctl | RNG_CTL
0x3 | REG | ADC Data Channel 0 | wb_fmcpico1m_4ch_csr_data0 | DATA0
0x4 | REG | ADC Data Channel 1 | wb_fmcpico1m_4ch_csr_data1 | DATA1
0x5 | REG | ADC Data Channel 2 | wb_fmcpico1m_4ch_csr_data2 | DATA2
0x6 | REG | ADC Data Channel 3 | wb_fmcpico1m_4ch_csr_data3 | DATA3

### 2. HDL symbol

→ | rst_n_i |  | FMC Status: |
→ | clk_sys_i |  | wb_fmcpico1m_4ch_csr_fmc_status_prsnt_i | ←
⇒ | wb_adr_i[2:0] |  | wb_fmcpico1m_4ch_csr_fmc_status_pg_m2c_i | ←
⇒ | wb_dat_i[31:0] |  |  |
⇐ | wb_dat_o[31:0] |  | FMC Control: |
→ | wb_cyc_i |  | wb_fmcpico1m_4ch_csr_fmc_ctl_led1_o | →
⇒ | wb_sel_i[3:0] |  | wb_fmcpico1m_4ch_csr_fmc_ctl_led2_o | →
→ | wb_stb_i |  |  |
→ | wb_we_i |  | Input Range Control: |
← | wb_ack_o |  | wb_fmcpico1m_4ch_csr_rng_ctl_r0_o | →
← | wb_stall_o |  | wb_fmcpico1m_4ch_csr_rng_ctl_r1_o | →
|  |  | wb_fmcpico1m_4ch_csr_rng_ctl_r2_o | →
|  |  | wb_fmcpico1m_4ch_csr_rng_ctl_r3_o | →
|  |  | ADC Data Channel 0: |
|  |  | wb_fmcpico1m_4ch_csr_data0_i[31:0] | ⇐
|  |  | ADC Data Channel 1: |
|  |  | wb_fmcpico1m_4ch_csr_data1_i[31:0] | ⇐
|  |  | ADC Data Channel 2: |
|  |  | wb_fmcpico1m_4ch_csr_data2_i[31:0] | ⇐
|  |  | ADC Data Channel 3: |
|  |  | wb_fmcpico1m_4ch_csr_data3_i[31:0] | ⇐

### 3. Register description

### 3.1. FMC Status

HW prefix: | wb_fmcpico1m_4ch_csr_fmc_status
HW address: | 0x0
C prefix: | FMC_STATUS
C offset: | 0x0

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | - | - | - | - | PG_M2C | PRSNT

- PRSNT [read-only]: FMC Present
  FMC PRSNT_M2C Pin
  0 - FMC card present
  1 - no FMC card on carrier
- PG_M2C [read-only]: Power Good from mezzanine
  FMC Power Good Pin
  Not used

### 3.2. FMC Control

HW prefix: | wb_fmcpico1m_4ch_csr_fmc_ctl
HW address: | 0x1
C prefix: | FMC_CTL
C offset: | 0x4

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | -

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | -

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | -

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | - | - | - | - | LED2 | LED1

- LED1 [read/write]: LED 1 Control
  0 - Led Off
  1 - Led On
- LED2 [read/write]: LED 2 Control
  0 - Led Off
  1 - Led On

### 3.3. Input Range Control

HW prefix: | wb_fmcpico1m_4ch_csr_rng_ctl
HW address: | 0x2
C prefix: | RNG_CTL
C offset: | 0x8

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
- | - | - | - | - | - | - | R3

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | R2

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
- | - | - | - | - | - | - | R1

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | - | - | - | - | - | R0

- R0 [read/write]: R0
  Input Range Control for ADC0
  0 - RNG1 = +/- 1uA
  1 - RNG0 = +/- 1mA
- R1 [read/write]: R1
  Input Range Control for ADC1
  0 - RNG1 = +/- 1uA
  1 - RNG0 = +/- 1mA
- R2 [read/write]: R2
  Input Range Control for ADC2
  0 - RNG1 = +/- 1uA
  1 - RNG0 = +/- 1mA
- R3 [read/write]: R3
  Input Range Control for ADC3
  0 - RNG1 = +/- 1uA
  1 - RNG0 = +/- 1mA

### 3.4. ADC Data Channel 0

HW prefix: | wb_fmcpico1m_4ch_csr_data0
HW address: | 0x3
C prefix: | DATA0
C offset: | 0xc

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
DATA0[31:24] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
DATA0[23:16] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
DATA0[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
DATA0[7:0] |  |  |  |  |  |  |

- DATA0 [read-only]: DATA0
  ADC data from channel 0

### 3.5. ADC Data Channel 1

HW prefix: | wb_fmcpico1m_4ch_csr_data1
HW address: | 0x4
C prefix: | DATA1
C offset: | 0x10

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
DATA1[31:24] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
DATA1[23:16] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
DATA1[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
DATA1[7:0] |  |  |  |  |  |  |

- DATA1 [read-only]: DATA1
  ADC data from channel 1

### 3.6. ADC Data Channel 2

HW prefix: | wb_fmcpico1m_4ch_csr_data2
HW address: | 0x5
C prefix: | DATA2
C offset: | 0x14

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
DATA2[31:24] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
DATA2[23:16] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
DATA2[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
DATA2[7:0] |  |  |  |  |  |  |

- DATA2 [read-only]: DATA2
  ADC data from channel 2

### 3.7. ADC Data Channel 3

HW prefix: | wb_fmcpico1m_4ch_csr_data3
HW address: | 0x6
C prefix: | DATA3
C offset: | 0x18

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
DATA3[31:24] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
DATA3[23:16] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
DATA3[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
DATA3[7:0] |  |  |  |  |  |  |

- DATA3 [read-only]: DATA3
  ADC data from channel 3