if (action == "synthesis"):
    files = ["axi_interconnect.xci"]

else:
    files = ["axi_interconnect_v1_7/hdl/verilog/",
#            "blk_mem_gen_v8_2/hdl/blk_mem_gen_v8_2.vhd",
            "fifo_generator_v12_0/simulation/",
            "sim/"]
