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-- Title          : Wishbone slave core for Wishbone DMA Streaming Interface
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-- File           : xdma_interface_wb.vhd
-- Author         : auto-generated by wbgen2 from xdma_interface_wb.wb
-- Created        : Thu Sep 27 15:39:56 2012
-- Standard       : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE xdma_interface_wb.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wbgen2_pkg.all;

use work.dma_iface_wbgen2_pkg.all;


entity wb_dma_interface_port is
  port (
    rst_n_i                                  : in     std_logic;
    clk_sys_i                                : in     std_logic;
    wb_adr_i                                 : in     std_logic_vector(2 downto 0);
    wb_dat_i                                 : in     std_logic_vector(31 downto 0);
    wb_dat_o                                 : out    std_logic_vector(31 downto 0);
    wb_cyc_i                                 : in     std_logic;
    wb_sel_i                                 : in     std_logic_vector(3 downto 0);
    wb_stb_i                                 : in     std_logic;
    wb_we_i                                  : in     std_logic;
    wb_ack_o                                 : out    std_logic;
    wb_stall_o                               : out    std_logic;
    data_clk_i                               : in     std_logic;
    dma_clk_i                                : in     std_logic;
    regs_i                                   : in     t_dma_iface_in_registers;
    regs_o                                   : out    t_dma_iface_out_registers
  );
end wb_dma_interface_port;

architecture syn of wb_dma_interface_port is

signal dma_iface_ctl_start_int                  : std_logic      ;
signal dma_iface_ctl_start_int_delay            : std_logic      ;
signal dma_iface_ctl_start_sync0                : std_logic      ;
signal dma_iface_ctl_start_sync1                : std_logic      ;
signal dma_iface_ctl_start_sync2                : std_logic      ;
signal dma_iface_ctl_done_sync0                 : std_logic      ;
signal dma_iface_ctl_done_sync1                 : std_logic      ;
signal dma_iface_ctl_ovf_sync0                  : std_logic      ;
signal dma_iface_ctl_ovf_sync1                  : std_logic      ;
signal dma_iface_tr_cntr_int                    : std_logic_vector(31 downto 0);
signal dma_iface_tr_cntr_swb                    : std_logic      ;
signal dma_iface_tr_cntr_swb_delay              : std_logic      ;
signal dma_iface_tr_cntr_swb_s0                 : std_logic      ;
signal dma_iface_tr_cntr_swb_s1                 : std_logic      ;
signal dma_iface_tr_cntr_swb_s2                 : std_logic      ;
signal dma_iface_fifo_c2b_rst_n                 : std_logic      ;
signal dma_iface_fifo_c2b_in_int                : std_logic_vector(32 downto 0);
signal dma_iface_fifo_c2b_out_int               : std_logic_vector(32 downto 0);
signal dma_iface_fifo_c2b_rdreq_int             : std_logic      ;
signal dma_iface_fifo_c2b_rdreq_int_d0          : std_logic      ;
signal dma_iface_fifo_b2c_rst_n                 : std_logic      ;
signal dma_iface_fifo_b2c_in_int                : std_logic_vector(31 downto 0);
signal dma_iface_fifo_b2c_out_int               : std_logic_vector(31 downto 0);
signal dma_iface_fifo_b2c_wrreq_int             : std_logic      ;
signal dma_iface_fifo_c2b_full_int              : std_logic      ;
signal dma_iface_fifo_c2b_empty_int             : std_logic      ;
signal dma_iface_fifo_c2b_usedw_int             : std_logic_vector(7 downto 0);
signal dma_iface_fifo_b2c_full_int              : std_logic      ;
signal dma_iface_fifo_b2c_empty_int             : std_logic      ;
signal dma_iface_fifo_b2c_usedw_int             : std_logic_vector(7 downto 0);
signal ack_sreg                                 : std_logic_vector(9 downto 0);
signal rddata_reg                               : std_logic_vector(31 downto 0);
signal wrdata_reg                               : std_logic_vector(31 downto 0);
signal bwsel_reg                                : std_logic_vector(3 downto 0);
signal rwaddr_reg                               : std_logic_vector(2 downto 0);
signal ack_in_progress                          : std_logic      ;
signal wr_int                                   : std_logic      ;
signal rd_int                                   : std_logic      ;
signal allones                                  : std_logic_vector(31 downto 0);
signal allzeros                                 : std_logic_vector(31 downto 0);

begin
-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
  wrdata_reg <= wb_dat_i;
  bwsel_reg <= wb_sel_i;
  rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
  wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
  allones <= (others => '1');
  allzeros <= (others => '0');
-- 
-- Main register bank access process.
  process (clk_sys_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      ack_sreg <= "0000000000";
      ack_in_progress <= '0';
      rddata_reg <= "00000000000000000000000000000000";
      dma_iface_ctl_start_int <= '0';
      dma_iface_ctl_start_int_delay <= '0';
      dma_iface_tr_cntr_int <= "00000000000000000000000000000000";
      dma_iface_tr_cntr_swb <= '0';
      dma_iface_tr_cntr_swb_delay <= '0';
      dma_iface_fifo_c2b_rdreq_int <= '0';
      dma_iface_fifo_b2c_wrreq_int <= '0';
    elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
      ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
      ack_sreg(9) <= '0';
      if (ack_in_progress = '1') then
        if (ack_sreg(0) = '1') then
          dma_iface_fifo_b2c_wrreq_int <= '0';
          ack_in_progress <= '0';
        else
          dma_iface_ctl_start_int <= dma_iface_ctl_start_int_delay;
          dma_iface_ctl_start_int_delay <= '0';
          dma_iface_tr_cntr_swb <= dma_iface_tr_cntr_swb_delay;
          dma_iface_tr_cntr_swb_delay <= '0';
        end if;
      else
        if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
          case rwaddr_reg(2 downto 0) is
          when "000" => 
            if (wb_we_i = '1') then
              dma_iface_ctl_start_int <= wrdata_reg(0);
              dma_iface_ctl_start_int_delay <= wrdata_reg(0);
            end if;
            rddata_reg(0) <= 'X';
            rddata_reg(1) <= dma_iface_ctl_done_sync1;
            rddata_reg(2) <= dma_iface_ctl_ovf_sync1;
            rddata_reg(3) <= 'X';
            rddata_reg(4) <= 'X';
            rddata_reg(5) <= 'X';
            rddata_reg(6) <= 'X';
            rddata_reg(7) <= 'X';
            rddata_reg(8) <= 'X';
            rddata_reg(9) <= 'X';
            rddata_reg(10) <= 'X';
            rddata_reg(11) <= 'X';
            rddata_reg(12) <= 'X';
            rddata_reg(13) <= 'X';
            rddata_reg(14) <= 'X';
            rddata_reg(15) <= 'X';
            rddata_reg(16) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            rddata_reg(24) <= 'X';
            rddata_reg(25) <= 'X';
            rddata_reg(26) <= 'X';
            rddata_reg(27) <= 'X';
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(4) <= '1';
            ack_in_progress <= '1';
          when "001" => 
            if (wb_we_i = '1') then
              dma_iface_tr_cntr_int <= wrdata_reg(31 downto 0);
              dma_iface_tr_cntr_swb <= '1';
              dma_iface_tr_cntr_swb_delay <= '1';
            end if;
            rddata_reg(31 downto 0) <= dma_iface_tr_cntr_int;
            ack_sreg(3) <= '1';
            ack_in_progress <= '1';
          when "010" => 
            if (wb_we_i = '1') then
            end if;
            if (dma_iface_fifo_c2b_rdreq_int_d0 = '0') then
              dma_iface_fifo_c2b_rdreq_int <= not dma_iface_fifo_c2b_rdreq_int;
            else
              rddata_reg(31 downto 0) <= dma_iface_fifo_c2b_out_int(31 downto 0);
              ack_in_progress <= '1';
              ack_sreg(0) <= '1';
            end if;
          when "011" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(0) <= dma_iface_fifo_c2b_out_int(32);
            rddata_reg(1) <= 'X';
            rddata_reg(2) <= 'X';
            rddata_reg(3) <= 'X';
            rddata_reg(4) <= 'X';
            rddata_reg(5) <= 'X';
            rddata_reg(6) <= 'X';
            rddata_reg(7) <= 'X';
            rddata_reg(8) <= 'X';
            rddata_reg(9) <= 'X';
            rddata_reg(10) <= 'X';
            rddata_reg(11) <= 'X';
            rddata_reg(12) <= 'X';
            rddata_reg(13) <= 'X';
            rddata_reg(14) <= 'X';
            rddata_reg(15) <= 'X';
            rddata_reg(16) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            rddata_reg(24) <= 'X';
            rddata_reg(25) <= 'X';
            rddata_reg(26) <= 'X';
            rddata_reg(27) <= 'X';
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "100" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(16) <= dma_iface_fifo_c2b_full_int;
            rddata_reg(17) <= dma_iface_fifo_c2b_empty_int;
            rddata_reg(7 downto 0) <= dma_iface_fifo_c2b_usedw_int;
            rddata_reg(8) <= 'X';
            rddata_reg(9) <= 'X';
            rddata_reg(10) <= 'X';
            rddata_reg(11) <= 'X';
            rddata_reg(12) <= 'X';
            rddata_reg(13) <= 'X';
            rddata_reg(14) <= 'X';
            rddata_reg(15) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            rddata_reg(24) <= 'X';
            rddata_reg(25) <= 'X';
            rddata_reg(26) <= 'X';
            rddata_reg(27) <= 'X';
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "101" => 
            if (wb_we_i = '1') then
              dma_iface_fifo_b2c_in_int(31 downto 0) <= wrdata_reg(31 downto 0);
              dma_iface_fifo_b2c_wrreq_int <= '1';
            end if;
            rddata_reg(0) <= 'X';
            rddata_reg(1) <= 'X';
            rddata_reg(2) <= 'X';
            rddata_reg(3) <= 'X';
            rddata_reg(4) <= 'X';
            rddata_reg(5) <= 'X';
            rddata_reg(6) <= 'X';
            rddata_reg(7) <= 'X';
            rddata_reg(8) <= 'X';
            rddata_reg(9) <= 'X';
            rddata_reg(10) <= 'X';
            rddata_reg(11) <= 'X';
            rddata_reg(12) <= 'X';
            rddata_reg(13) <= 'X';
            rddata_reg(14) <= 'X';
            rddata_reg(15) <= 'X';
            rddata_reg(16) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            rddata_reg(24) <= 'X';
            rddata_reg(25) <= 'X';
            rddata_reg(26) <= 'X';
            rddata_reg(27) <= 'X';
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "110" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(16) <= dma_iface_fifo_b2c_full_int;
            rddata_reg(17) <= dma_iface_fifo_b2c_empty_int;
            rddata_reg(7 downto 0) <= dma_iface_fifo_b2c_usedw_int;
            rddata_reg(8) <= 'X';
            rddata_reg(9) <= 'X';
            rddata_reg(10) <= 'X';
            rddata_reg(11) <= 'X';
            rddata_reg(12) <= 'X';
            rddata_reg(13) <= 'X';
            rddata_reg(14) <= 'X';
            rddata_reg(15) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            rddata_reg(24) <= 'X';
            rddata_reg(25) <= 'X';
            rddata_reg(26) <= 'X';
            rddata_reg(27) <= 'X';
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when others =>
-- prevent the slave from hanging the bus on invalid address
            ack_in_progress <= '1';
            ack_sreg(0) <= '1';
          end case;
        end if;
      end if;
    end if;
  end process;
  
  
-- Drive the data output bus
  wb_dat_o <= rddata_reg;
-- Start Transaction
  process (data_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      regs_o.ctl_start_o <= '0';
      dma_iface_ctl_start_sync0 <= '0';
      dma_iface_ctl_start_sync1 <= '0';
      dma_iface_ctl_start_sync2 <= '0';
    elsif rising_edge(data_clk_i) then
      dma_iface_ctl_start_sync0 <= dma_iface_ctl_start_int;
      dma_iface_ctl_start_sync1 <= dma_iface_ctl_start_sync0;
      dma_iface_ctl_start_sync2 <= dma_iface_ctl_start_sync1;
      regs_o.ctl_start_o <= dma_iface_ctl_start_sync2 and (not dma_iface_ctl_start_sync1);
    end if;
  end process;
  
  
-- DMA complete
-- synchronizer chain for field : DMA complete (type RO/WO, dma_clk_i -> clk_sys_i)
  process (dma_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      dma_iface_ctl_done_sync0 <= '0';
      dma_iface_ctl_done_sync1 <= '0';
    elsif rising_edge(dma_clk_i) then
      dma_iface_ctl_done_sync0 <= regs_i.ctl_done_i;
      dma_iface_ctl_done_sync1 <= dma_iface_ctl_done_sync0;
    end if;
  end process;
  
  
-- DMA overflow
-- synchronizer chain for field : DMA overflow (type RO/WO, dma_clk_i -> clk_sys_i)
  process (dma_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      dma_iface_ctl_ovf_sync0 <= '0';
      dma_iface_ctl_ovf_sync1 <= '0';
    elsif rising_edge(dma_clk_i) then
      dma_iface_ctl_ovf_sync0 <= regs_i.ctl_ovf_i;
      dma_iface_ctl_ovf_sync1 <= dma_iface_ctl_ovf_sync0;
    end if;
  end process;
  
  
-- Transactions Counter
-- asynchronous std_logic_vector register : Transactions Counter (type RW/RO, data_clk_i <-> clk_sys_i)
  process (data_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      dma_iface_tr_cntr_swb_s0 <= '0';
      dma_iface_tr_cntr_swb_s1 <= '0';
      dma_iface_tr_cntr_swb_s2 <= '0';
      regs_o.tr_cntr_o <= "00000000000000000000000000000000";
    elsif rising_edge(data_clk_i) then
      dma_iface_tr_cntr_swb_s0 <= dma_iface_tr_cntr_swb;
      dma_iface_tr_cntr_swb_s1 <= dma_iface_tr_cntr_swb_s0;
      dma_iface_tr_cntr_swb_s2 <= dma_iface_tr_cntr_swb_s1;
      if ((dma_iface_tr_cntr_swb_s2 = '0') and (dma_iface_tr_cntr_swb_s1 = '1')) then
        regs_o.tr_cntr_o <= dma_iface_tr_cntr_int;
      end if;
    end if;
  end process;
  
  
-- extra code for reg/fifo/mem: FIFO C2B (Core -> DMA) synchronization
  dma_iface_fifo_c2b_in_int(31 downto 0) <= regs_i.fifo_c2b_data_i;
  dma_iface_fifo_c2b_in_int(32) <= regs_i.fifo_c2b_last_i;
  dma_iface_fifo_c2b_rst_n <= rst_n_i;
  dma_iface_fifo_c2b_INST : wbgen2_fifo_async
    generic map (
      g_size               => 256,
      g_width              => 33,
      g_usedw_size         => 8
    )
    port map (
      wr_req_i             => regs_i.fifo_c2b_wr_req_i,
      wr_full_o            => regs_o.fifo_c2b_wr_full_o,
      wr_empty_o           => regs_o.fifo_c2b_wr_empty_o,
      wr_usedw_o           => regs_o.fifo_c2b_wr_usedw_o,
      rd_full_o            => dma_iface_fifo_c2b_full_int,
      rd_empty_o           => dma_iface_fifo_c2b_empty_int,
      rd_usedw_o           => dma_iface_fifo_c2b_usedw_int,
      rd_req_i             => dma_iface_fifo_c2b_rdreq_int,
      rst_n_i              => dma_iface_fifo_c2b_rst_n,
      wr_clk_i             => dma_clk_i,
      rd_clk_i             => clk_sys_i,
      wr_data_i            => dma_iface_fifo_c2b_in_int,
      rd_data_o            => dma_iface_fifo_c2b_out_int
    );
  
-- extra code for reg/fifo/mem: FIFO B2C (Bus -> Core) synchronization
  regs_o.fifo_b2c_data_o <= dma_iface_fifo_b2c_out_int(31 downto 0);
  dma_iface_fifo_b2c_rst_n <= rst_n_i;
  dma_iface_fifo_b2c_INST : wbgen2_fifo_async
    generic map (
      g_size               => 256,
      g_width              => 32,
      g_usedw_size         => 8
    )
    port map (
      rd_req_i             => regs_i.fifo_b2c_rd_req_i,
      rd_full_o            => regs_o.fifo_b2c_rd_full_o,
      rd_empty_o           => regs_o.fifo_b2c_rd_empty_o,
      rd_usedw_o           => regs_o.fifo_b2c_rd_usedw_o,
      wr_full_o            => dma_iface_fifo_b2c_full_int,
      wr_empty_o           => dma_iface_fifo_b2c_empty_int,
      wr_usedw_o           => dma_iface_fifo_b2c_usedw_int,
      wr_req_i             => dma_iface_fifo_b2c_wrreq_int,
      rst_n_i              => dma_iface_fifo_b2c_rst_n,
      rd_clk_i             => data_clk_i,
      wr_clk_i             => clk_sys_i,
      wr_data_i            => dma_iface_fifo_b2c_in_int,
      rd_data_o            => dma_iface_fifo_b2c_out_int
    );
  
-- extra code for reg/fifo/mem: FIFO 'FIFO C2B (Core -> DMA) synchronization' data output register 0
  process (clk_sys_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      dma_iface_fifo_c2b_rdreq_int_d0 <= '0';
    elsif rising_edge(clk_sys_i) then
      dma_iface_fifo_c2b_rdreq_int_d0 <= dma_iface_fifo_c2b_rdreq_int;
    end if;
  end process;
  
  
-- extra code for reg/fifo/mem: FIFO 'FIFO C2B (Core -> DMA) synchronization' data output register 1
-- extra code for reg/fifo/mem: FIFO 'FIFO B2C (Bus -> Core) synchronization' data input register 0
  rwaddr_reg <= wb_adr_i;
  wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
-- ACK signal generation. Just pass the LSB of ACK counter.
  wb_ack_o <= ack_sreg(0);
end syn;
