// (c) Copyright 2012 Xilinx, Inc. All rights reserved.
//
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//-----------------------------------------------------------------------------
//
// Verilog-standard:  Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
//   axis_interconnect_v1_1_util_aclken_converter_wrapper
//     axis_interconnect_v1_1_util_axis2vector
//     axis_interconnect_v1_1_util_aclken_converter
//     axis_interconnect_v1_1_util_vector2axis 
//
//--------------------------------------------------------------------------

`timescale 1ps/1ps
`default_nettype none

module axis_interconnect_v1_1_util_aclken_converter_wrapper # (
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
  parameter integer C_TDATA_WIDTH = 32,
  parameter integer C_TID_WIDTH   = 1,
  parameter integer C_TDEST_WIDTH = 1,
  parameter integer C_TUSER_WIDTH = 1,
  parameter [31:0]  C_SIGNAL_SET  = 32'hFF,
  // C_AXIS_SIGNAL_SET: each bit if enabled specifies which axis optional signals are present
  //   [0] => TREADY present
  //   [1] => TDATA present
  //   [2] => TSTRB present, TDATA must be present
  //   [3] => TKEEP present, TDATA must be present
  //   [4] => TLAST present
  //   [5] => TID present
  //   [6] => TDEST present
  //   [7] => TUSER present
  parameter integer C_S_ACLKEN_CAN_TOGGLE = 1,
  parameter integer C_M_ACLKEN_CAN_TOGGLE = 1
  )
 (
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
  // Slave side
  input  wire                       ACLK,
  input  wire                       ARESETN,
  input  wire                       S_ACLKEN,
  input  wire                       S_VALID,
  output wire                       S_READY,
  input  wire [C_TDATA_WIDTH-1:0]   S_TDATA,
  input  wire [C_TDATA_WIDTH/8-1:0] S_TSTRB,
  input  wire [C_TDATA_WIDTH/8-1:0] S_TKEEP,
  input  wire                       S_TLAST,
  input  wire [C_TID_WIDTH-1:0]     S_TID,
  input  wire [C_TDEST_WIDTH-1:0]   S_TDEST,
  input  wire [C_TUSER_WIDTH-1:0]   S_TUSER,
                                    
  input  wire                       M_ACLKEN,
  output wire                       M_VALID,
  input  wire                       M_READY,
  output wire [C_TDATA_WIDTH-1:0]   M_TDATA,
  output wire [C_TDATA_WIDTH/8-1:0] M_TSTRB,
  output wire [C_TDATA_WIDTH/8-1:0] M_TKEEP,
  output wire                       M_TLAST,
  output wire [C_TID_WIDTH-1:0]     M_TID,
  output wire [C_TDEST_WIDTH-1:0]   M_TDEST,
  output wire [C_TUSER_WIDTH-1:0]   M_TUSER
);

////////////////////////////////////////////////////////////////////////////////
// Functions
////////////////////////////////////////////////////////////////////////////////
`include "axis_interconnect_v1_1_axis_infrastructure.vh"


////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////

localparam integer P_TPAYLOAD_WIDTH       = f_payload_width(C_TDATA_WIDTH, C_TID_WIDTH, 
                                                 C_TDEST_WIDTH, C_TUSER_WIDTH, 
                                                 C_SIGNAL_SET);
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
wire [P_TPAYLOAD_WIDTH-1:0] s_tpayload;
wire [P_TPAYLOAD_WIDTH-1:0] m_tpayload;

////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////

axis_interconnect_v1_1_util_axis2vector #(
  .C_TDATA_WIDTH    ( C_TDATA_WIDTH ) ,
  .C_TID_WIDTH      ( C_TID_WIDTH   ) ,
  .C_TDEST_WIDTH    ( C_TDEST_WIDTH ) ,
  .C_TUSER_WIDTH    ( C_TUSER_WIDTH ) ,
  .C_TPAYLOAD_WIDTH ( P_TPAYLOAD_WIDTH   ) ,
  .C_SIGNAL_SET     ( C_SIGNAL_SET  ) 
)
util_axis2vector_0 (
  .TDATA    ( S_TDATA    ) ,
  .TSTRB    ( S_TSTRB    ) ,
  .TKEEP    ( S_TKEEP    ) ,
  .TLAST    ( S_TLAST    ) ,
  .TID      ( S_TID      ) ,
  .TDEST    ( S_TDEST    ) ,
  .TUSER    ( S_TUSER    ) ,
  .TPAYLOAD ( s_tpayload )
);

if (C_S_ACLKEN_CAN_TOGGLE | C_M_ACLKEN_CAN_TOGGLE) begin : gen_aclken_converter
  axis_interconnect_v1_1_util_aclken_converter #( 
    .C_PAYLOAD_WIDTH       ( P_TPAYLOAD_WIDTH       ) ,
    .C_S_ACLKEN_CAN_TOGGLE ( C_S_ACLKEN_CAN_TOGGLE ) ,
    .C_M_ACLKEN_CAN_TOGGLE ( C_M_ACLKEN_CAN_TOGGLE ) 
  )
  s_util_aclken_converter_0 ( 
    .ACLK      ( ACLK       ) ,
    .ARESETN   ( ARESETN    ) ,
    .S_ACLKEN  ( S_ACLKEN   ) ,
    .S_PAYLOAD ( s_tpayload ) ,
    .S_VALID   ( S_VALID   ) ,
    .S_READY   ( S_READY   ) ,
    .M_ACLKEN  ( M_ACLKEN   ) ,
    .M_PAYLOAD ( m_tpayload ) ,
    .M_VALID   ( M_VALID   ) ,
    .M_READY   ( M_READY   ) 
  );
end
else begin : gen_aclken_passthru
  assign m_tpayload = s_tpayload;
  assign M_VALID   = S_VALID;
  assign S_READY = M_READY;
end

axis_interconnect_v1_1_util_vector2axis #(
  .C_TDATA_WIDTH    ( C_TDATA_WIDTH ) ,
  .C_TID_WIDTH      ( C_TID_WIDTH   ) ,
  .C_TDEST_WIDTH    ( C_TDEST_WIDTH ) ,
  .C_TUSER_WIDTH    ( C_TUSER_WIDTH ) ,
  .C_TPAYLOAD_WIDTH ( P_TPAYLOAD_WIDTH   ) ,
  .C_SIGNAL_SET     ( C_SIGNAL_SET  ) 
)
util_vector2axis_0 (
  .TPAYLOAD ( m_tpayload ) ,
  .TDATA    ( M_TDATA    ) ,
  .TSTRB    ( M_TSTRB    ) ,
  .TKEEP    ( M_TKEEP    ) ,
  .TLAST    ( M_TLAST    ) ,
  .TID      ( M_TID      ) ,
  .TDEST    ( M_TDEST    ) ,
  .TUSER    ( M_TUSER    ) 
);

endmodule // axis_interconnect_v1_1_util_aclken_converter_wrapper

`default_nettype wire
