#
# Vivado (TM) v2015.2 (64-bit)
#
# bpm_pcie_afck.tcl: Tcl script for re-creating project 'bpm_pcie_afck'
#
# Generated by Vivado on Fri Oct 02 20:17:24 CEST 2015
# IP Build 1264090 on Wed Jun 24 14:22:01 MDT 2015
#
# This file contains the Vivado Tcl commands for re-creating the project to the state*
# when this script was generated. In order to re-create the project, please source this
# file in the Vivado Tcl Shell.
#
# * Note that the runs in the created project will be configured the same way as the
#   original project, however they will not be launched automatically. To regenerate the
#   run results please launch the synthesis/implementation runs as needed.
#
#*****************************************************************************************
# NOTE: In order to use this script for source control purposes, please make sure that the
#       following files are added to the source control system:-
#
# 1. This project restoration tcl script (bpm_pcie_afck.tcl) that was generated.
#
# 2. The following source(s) files that were local or imported into the original project.
#    (Please see the '$orig_proj_dir' and '$origin_dir' variable setting below at the start of the script)
#
#    <none>
#
# 3. The following remote source files that were added to the original project:-
#
#    "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/ip_cores/general-cores/modules/genrams/genram_pkg.vhd"
#    "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd"
#    "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd"
#    "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd"
#    "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/ip_cores/general-cores/modules/genrams/xilinx/series7/s7_fifo_pkg.vhd"
#    "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd"
#    "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/ip_cores/general-cores/modules/genrams/xilinx/series7/s7_hwfifo_wrapper.vhd"
#    "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/ip_cores/general-cores/modules/genrams/inferred_sync_fifo.vhd"
#    "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/modules/pcie/pkgs/v6abb64Package_efifo_elink.vhd"
#    "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/modules/pcie/common/DMA_Calculate.vhd"
#    "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/ip_cores/general-cores/modules/genrams/xilinx/series7/generic_sync_fifo.vhd"
#    "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/modules/pcie/common/DMA_FSM.vhd"
#    "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/modules/pcie/common/Tx_Output_Arbitor.vhd"
#    "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/modules/pcie/common/tx_Mem_Reader.vhd"
#    "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/modules/pcie/common/rx_usDMA_Channel.vhd"
#    "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/modules/pcie/common/rx_MWr_Channel.vhd"
#    "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/modules/pcie/common/rx_MRd_Channel.vhd"
#    "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/modules/pcie/common/rx_dsDMA_Channel.vhd"
#    "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/modules/pcie/common/rx_CplD_Channel.vhd"
#    "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/modules/pcie/common/RxIn_Delays.vhd"
#    "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/modules/pcie/common/Interrupts.vhd"
#    "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/ip_cores/general-cores/modules/genrams/inferred_async_fifo.vhd"
#    "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/modules/pcie/common/Registers.vhd"
#    "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/modules/pcie/common/tx_Transact.vhd"
#    "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/modules/pcie/common/rx_Transact.vhd"
#    "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/ip_cores/general-cores/modules/genrams/xilinx/series7/generic_async_fifo.vhd"
#    "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/platform/kintex7/afck/ipcores_pkg.vhd"
#    "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/modules/pcie/common/wb_transact.vhd"
#    "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/modules/pcie/common/tlpControl.vhd"
#    "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/modules/pcie/common/ddr_Transact.vhd"
#    "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/modules/pcie/common/wb_mem.vhd"
#    "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/modules/pcie/bpm_pcie.vhd"
#    "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/top/pcie/top_afck.vhd"
#    "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/platform/kintex7/afck/ddr_core/mig_b.prj"
#    "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/platform/kintex7/afck/ddr_core/mig_a.prj"
#    "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/platform/kintex7/afck/axi_interconnect/axi_interconnect.xci"
#    "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/platform/kintex7/afck/axi_datamover_0/axi_datamover_0.xci"
#    "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/platform/kintex7/afck/pcie_core/pcie_core.xci"
#    "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/platform/kintex7/afck/ddr_core/ddr_core.xci"
#    "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/syn/pcie/afck.xdc"
#    "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/sim/pcie/sys_clk_gen.v"
#    "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/sim/pcie/tests.vh"
#    "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/testbench/pcie/tf64_pcie_axi.vh"
#    "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/sim/pcie/sample_tests1.vh"
#    "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/sim/pcie/board_common.vh"
#    "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/sim/pcie/helper_tasks.v"
#    "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/sim/pcie/pci_exp_usrapp_tx.v"
#    "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/sim/pcie/pci_exp_usrapp_rx.v"
#    "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/sim/pcie/pci_exp_usrapp_pl.v"
#    "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/sim/pcie/pci_exp_expect_tasks.vh"
#    "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/sim/pcie/pci_exp_usrapp_com.v"
#    "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/sim/pcie/pci_exp_usrapp_cfg.v"
#    "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/sim/pcie/pcie_axi_trn_bridge.v"
#    "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/sim/pcie/pcie_2_1_rport_7x.v"
#    "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/sim/pcie/xilinx_pcie_2_1_rport_7x.v"
#    "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/sim/ddr_model/wiredly.v"
#    "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/sim/pcie/sys_clk_gen_ds.v"
#    "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/sim/ddr_model/kintex7/ddr3_model_parameters.vh"
#    "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/sim/ddr_model/kintex7/ddr3_model.sv"
#    "/home/adrian/praca/creotech/pcie_brazil/bpm-gw/hdl/testbench/pcie/board.v"
#
#*****************************************************************************************

# Set the reference directory for source file relative paths (by default the value is script directory path)
set origin_dir "."

# Set the directory path for the original project from where this script was exported
set orig_proj_dir "[file normalize "$origin_dir/"]"

# Create project
create_project bpm_pcie_afck ./bpm_pcie_afck

# Set the directory path for the new project
set proj_dir [get_property directory [current_project]]

# Set project properties
set obj [get_projects bpm_pcie_afck]
set_property "default_lib" "xil_defaultlib" $obj
set_property "part" "xc7k325tffg900-2" $obj
set_property "simulator_language" "Mixed" $obj
set_property "source_mgmt_mode" "DisplayOnly" $obj
set_property "target_simulator" "Questa" $obj

# Create 'sources_1' fileset (if not found)
if {[string equal [get_filesets -quiet sources_1] ""]} {
  create_fileset -srcset sources_1
}

# Set 'sources_1' fileset object
set obj [get_filesets sources_1]
set files [list \
 "[file normalize "$origin_dir/../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd"]"\
 "[file normalize "$origin_dir/../../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd"]"\
 "[file normalize "$origin_dir/../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd"]"\
 "[file normalize "$origin_dir/../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd"]"\
 "[file normalize "$origin_dir/../../ip_cores/general-cores/modules/genrams/xilinx/series7/s7_fifo_pkg.vhd"]"\
 "[file normalize "$origin_dir/../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd"]"\
 "[file normalize "$origin_dir/../../ip_cores/general-cores/modules/genrams/xilinx/series7/s7_hwfifo_wrapper.vhd"]"\
 "[file normalize "$origin_dir/../../ip_cores/general-cores/modules/genrams/inferred_sync_fifo.vhd"]"\
 "[file normalize "$origin_dir/../../modules/pcie/pkgs/v6abb64Package_efifo_elink.vhd"]"\
 "[file normalize "$origin_dir/../../modules/pcie/common/DMA_Calculate.vhd"]"\
 "[file normalize "$origin_dir/../../ip_cores/general-cores/modules/genrams/xilinx/series7/generic_sync_fifo.vhd"]"\
 "[file normalize "$origin_dir/../../modules/pcie/common/DMA_FSM.vhd"]"\
 "[file normalize "$origin_dir/../../modules/pcie/common/Tx_Output_Arbitor.vhd"]"\
 "[file normalize "$origin_dir/../../modules/pcie/common/tx_Mem_Reader.vhd"]"\
 "[file normalize "$origin_dir/../../modules/pcie/common/rx_usDMA_Channel.vhd"]"\
 "[file normalize "$origin_dir/../../modules/pcie/common/rx_MWr_Channel.vhd"]"\
 "[file normalize "$origin_dir/../../modules/pcie/common/rx_MRd_Channel.vhd"]"\
 "[file normalize "$origin_dir/../../modules/pcie/common/rx_dsDMA_Channel.vhd"]"\
 "[file normalize "$origin_dir/../../modules/pcie/common/rx_CplD_Channel.vhd"]"\
 "[file normalize "$origin_dir/../../modules/pcie/common/RxIn_Delays.vhd"]"\
 "[file normalize "$origin_dir/../../modules/pcie/common/Interrupts.vhd"]"\
 "[file normalize "$origin_dir/../../ip_cores/general-cores/modules/genrams/inferred_async_fifo.vhd"]"\
 "[file normalize "$origin_dir/../../modules/pcie/common/Registers.vhd"]"\
 "[file normalize "$origin_dir/../../modules/pcie/common/tx_Transact.vhd"]"\
 "[file normalize "$origin_dir/../../modules/pcie/common/rx_Transact.vhd"]"\
 "[file normalize "$origin_dir/../../ip_cores/general-cores/modules/genrams/xilinx/series7/generic_async_fifo.vhd"]"\
 "[file normalize "$origin_dir/../../platform/kintex7/afck/ipcores_pkg.vhd"]"\
 "[file normalize "$origin_dir/../../modules/pcie/common/wb_transact.vhd"]"\
 "[file normalize "$origin_dir/../../modules/pcie/common/tlpControl.vhd"]"\
 "[file normalize "$origin_dir/../../modules/pcie/common/ddr_Transact.vhd"]"\
 "[file normalize "$origin_dir/../../modules/pcie/common/wb_mem.vhd"]"\
 "[file normalize "$origin_dir/../../modules/pcie/bpm_pcie.vhd"]"\
 "[file normalize "$origin_dir/../../top/pcie/top_afck.vhd"]"\
 "[file normalize "$origin_dir/../../platform/kintex7/afck/ddr_core/mig_b.prj"]"\
 "[file normalize "$origin_dir/../../platform/kintex7/afck/ddr_core/mig_a.prj"]"\
]
add_files -norecurse -fileset $obj $files

# Set 'sources_1' fileset file properties for remote files
set file "$origin_dir/../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "$origin_dir/../../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "$origin_dir/../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "$origin_dir/../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "$origin_dir/../../ip_cores/general-cores/modules/genrams/xilinx/series7/s7_fifo_pkg.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "$origin_dir/../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "$origin_dir/../../ip_cores/general-cores/modules/genrams/xilinx/series7/s7_hwfifo_wrapper.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "$origin_dir/../../ip_cores/general-cores/modules/genrams/inferred_sync_fifo.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "$origin_dir/../../modules/pcie/pkgs/v6abb64Package_efifo_elink.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "$origin_dir/../../modules/pcie/common/DMA_Calculate.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "$origin_dir/../../ip_cores/general-cores/modules/genrams/xilinx/series7/generic_sync_fifo.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "$origin_dir/../../modules/pcie/common/DMA_FSM.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "$origin_dir/../../modules/pcie/common/Tx_Output_Arbitor.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "$origin_dir/../../modules/pcie/common/tx_Mem_Reader.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "$origin_dir/../../modules/pcie/common/rx_usDMA_Channel.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "$origin_dir/../../modules/pcie/common/rx_MWr_Channel.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "$origin_dir/../../modules/pcie/common/rx_MRd_Channel.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "$origin_dir/../../modules/pcie/common/rx_dsDMA_Channel.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "$origin_dir/../../modules/pcie/common/rx_CplD_Channel.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "$origin_dir/../../modules/pcie/common/RxIn_Delays.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "$origin_dir/../../modules/pcie/common/Interrupts.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "$origin_dir/../../ip_cores/general-cores/modules/genrams/inferred_async_fifo.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "$origin_dir/../../modules/pcie/common/Registers.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "$origin_dir/../../modules/pcie/common/tx_Transact.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "$origin_dir/../../modules/pcie/common/rx_Transact.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "$origin_dir/../../ip_cores/general-cores/modules/genrams/xilinx/series7/generic_async_fifo.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "$origin_dir/../../platform/kintex7/afck/ipcores_pkg.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "$origin_dir/../../modules/pcie/common/wb_transact.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "$origin_dir/../../modules/pcie/common/tlpControl.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "$origin_dir/../../modules/pcie/common/ddr_Transact.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "$origin_dir/../../modules/pcie/common/wb_mem.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "$origin_dir/../../modules/pcie/bpm_pcie.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj

set file "$origin_dir/../../top/pcie/top_afck.vhd"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property "file_type" "VHDL" $file_obj


# Set 'sources_1' fileset file properties for local files
# None

# Set 'sources_1' fileset properties
set obj [get_filesets sources_1]
set_property "top" "top" $obj

# Set 'sources_1' fileset object
set obj [get_filesets sources_1]
set files [list \
 "[file normalize "$origin_dir/../../platform/kintex7/afck/axi_interconnect/axi_interconnect.xci"]"\
]
add_files -norecurse -fileset $obj $files

# Set 'sources_1' fileset file properties for remote files
set file "$origin_dir/../../platform/kintex7/afck/axi_interconnect/axi_interconnect.xci"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
if { ![get_property "is_locked" $file_obj] } {
  set_property "synth_checkpoint_mode" "Singular" $file_obj
}


# Set 'sources_1' fileset file properties for local files
# None

# Set 'sources_1' fileset object
set obj [get_filesets sources_1]
set files [list \
 "[file normalize "$origin_dir/../../platform/kintex7/afck/axi_datamover_0/axi_datamover_0.xci"]"\
]
add_files -norecurse -fileset $obj $files

# Set 'sources_1' fileset file properties for remote files
set file "$origin_dir/../../platform/kintex7/afck/axi_datamover_0/axi_datamover_0.xci"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
if { ![get_property "is_locked" $file_obj] } {
  set_property "synth_checkpoint_mode" "Singular" $file_obj
}


# Set 'sources_1' fileset file properties for local files
# None

# Set 'sources_1' fileset object
set obj [get_filesets sources_1]
set files [list \
 "[file normalize "$origin_dir/../../platform/kintex7/afck/pcie_core/pcie_core.xci"]"\
]
add_files -norecurse -fileset $obj $files

# Set 'sources_1' fileset file properties for remote files
set file "$origin_dir/../../platform/kintex7/afck/pcie_core/pcie_core.xci"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
if { ![get_property "is_locked" $file_obj] } {
  set_property "synth_checkpoint_mode" "Singular" $file_obj
}


# Set 'sources_1' fileset file properties for local files
# None

# Set 'sources_1' fileset object
set obj [get_filesets sources_1]
set files [list \
 "[file normalize "$origin_dir/../../platform/kintex7/afck/ddr_core/ddr_core.xci"]"\
]
add_files -norecurse -fileset $obj $files

# Set 'sources_1' fileset file properties for remote files
set file "$origin_dir/../../platform/kintex7/afck/ddr_core/ddr_core.xci"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
if { ![get_property "is_locked" $file_obj] } {
  set_property "synth_checkpoint_mode" "Singular" $file_obj
}


# Set 'sources_1' fileset file properties for local files
# None

# Create 'constrs_1' fileset (if not found)
if {[string equal [get_filesets -quiet constrs_1] ""]} {
  create_fileset -constrset constrs_1
}

# Set 'constrs_1' fileset object
set obj [get_filesets constrs_1]

# Add/Import constrs file and set constrs file properties
set file "[file normalize "$origin_dir/afck.xdc"]"
set file_added [add_files -norecurse -fileset $obj $file]
set file "$origin_dir/afck.xdc"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets constrs_1] [list "*$file"]]
set_property "file_type" "XDC" $file_obj
set_property "used_in_synthesis" "0" $file_obj

# Set 'constrs_1' fileset properties
set obj [get_filesets constrs_1]

# Create 'sim_1' fileset (if not found)
if {[string equal [get_filesets -quiet sim_1] ""]} {
  create_fileset -simset sim_1
}

# Set 'sim_1' fileset object
set obj [get_filesets sim_1]
set files [list \
 "[file normalize "$origin_dir/../../sim/pcie/sys_clk_gen.v"]"\
 "[file normalize "$origin_dir/../../sim/pcie/tests.vh"]"\
 "[file normalize "$origin_dir/../../testbench/pcie/tf64_pcie_axi.vh"]"\
 "[file normalize "$origin_dir/../../sim/pcie/sample_tests1.vh"]"\
 "[file normalize "$origin_dir/../../sim/pcie/board_common.vh"]"\
 "[file normalize "$origin_dir/../../sim/pcie/helper_tasks.v"]"\
 "[file normalize "$origin_dir/../../sim/pcie/pci_exp_usrapp_tx.v"]"\
 "[file normalize "$origin_dir/../../sim/pcie/pci_exp_usrapp_rx.v"]"\
 "[file normalize "$origin_dir/../../sim/pcie/pci_exp_usrapp_pl.v"]"\
 "[file normalize "$origin_dir/../../sim/pcie/pci_exp_expect_tasks.vh"]"\
 "[file normalize "$origin_dir/../../sim/pcie/pci_exp_usrapp_com.v"]"\
 "[file normalize "$origin_dir/../../sim/pcie/pci_exp_usrapp_cfg.v"]"\
 "[file normalize "$origin_dir/../../sim/pcie/pcie_axi_trn_bridge.v"]"\
 "[file normalize "$origin_dir/../../sim/pcie/pcie_2_1_rport_7x.v"]"\
 "[file normalize "$origin_dir/../../sim/pcie/xilinx_pcie_2_1_rport_7x.v"]"\
 "[file normalize "$origin_dir/../../sim/ddr_model/wiredly.v"]"\
 "[file normalize "$origin_dir/../../sim/pcie/sys_clk_gen_ds.v"]"\
 "[file normalize "$origin_dir/../../sim/ddr_model/kintex7/ddr3_model_parameters.vh"]"\
 "[file normalize "$origin_dir/../../sim/ddr_model/kintex7/ddr3_model.sv"]"\
 "[file normalize "$origin_dir/../../testbench/pcie/board.v"]"\
]
add_files -norecurse -fileset $obj $files

# Set 'sim_1' fileset file properties for remote files
set file "$origin_dir/../../sim/pcie/tests.vh"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sim_1] [list "*$file"]]
set_property "file_type" "Verilog Header" $file_obj

set file "$origin_dir/../../testbench/pcie/tf64_pcie_axi.vh"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sim_1] [list "*$file"]]
set_property "file_type" "Verilog Header" $file_obj

set file "$origin_dir/../../sim/pcie/sample_tests1.vh"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sim_1] [list "*$file"]]
set_property "file_type" "Verilog Header" $file_obj

set file "$origin_dir/../../sim/pcie/board_common.vh"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sim_1] [list "*$file"]]
set_property "file_type" "Verilog Header" $file_obj

set file "$origin_dir/../../sim/pcie/pci_exp_expect_tasks.vh"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sim_1] [list "*$file"]]
set_property "file_type" "Verilog Header" $file_obj

set file "$origin_dir/../../sim/ddr_model/kintex7/ddr3_model_parameters.vh"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sim_1] [list "*$file"]]
set_property "file_type" "Verilog Header" $file_obj

set file "$origin_dir/../../sim/ddr_model/kintex7/ddr3_model.sv"
set file [file normalize $file]
set file_obj [get_files -of_objects [get_filesets sim_1] [list "*$file"]]
set_property "file_type" "SystemVerilog" $file_obj


# Set 'sim_1' fileset file properties for local files
# None

# Set 'sim_1' fileset properties
set obj [get_filesets sim_1]
set_property "questa.compile.vlog.more_options" "+define+SIMULATION +define+x1Gb +define+sg125 +define+x8" $obj
set_property "questa.simulate.log_all_signals" "1" $obj
set_property "questa.simulate.runtime" "300000ns" $obj
set_property "questa.simulate.vsim.more_options" "+notimingchecks+" $obj
set_property "runtime" "" $obj
set_property "top" "board" $obj

# Create 'synth_1' run (if not found)
if {[string equal [get_runs -quiet synth_1] ""]} {
  create_run -name synth_1 -part xc7k325tffg900-2 -flow {Vivado Synthesis 2015} -strategy "Vivado Synthesis Defaults" -constrset constrs_1
} else {
  set_property strategy "Vivado Synthesis Defaults" [get_runs synth_1]
  set_property flow "Vivado Synthesis 2015" [get_runs synth_1]
}
set obj [get_runs synth_1]
set_property "part" "xc7k325tffg900-2" $obj

# set the current synth run
current_run -synthesis [get_runs synth_1]

# Create 'impl_1' run (if not found)
if {[string equal [get_runs -quiet impl_1] ""]} {
  create_run -name impl_1 -part xc7k325tffg900-2 -flow {Vivado Implementation 2015} -strategy "Vivado Implementation Defaults" -constrset constrs_1 -parent_run synth_1
} else {
  set_property strategy "Vivado Implementation Defaults" [get_runs impl_1]
  set_property flow "Vivado Implementation 2015" [get_runs impl_1]
}
set obj [get_runs impl_1]
set_property "part" "xc7k325tffg900-2" $obj
set_property "steps.opt_design.args.directive" "Explore" $obj
set_property "steps.place_design.args.directive" "Explore" $obj
set_property "steps.phys_opt_design.is_enabled" "1" $obj
set_property "steps.phys_opt_design.args.directive" "Explore" $obj
set_property "steps.route_design.args.directive" "Explore" $obj
set_property "steps.post_route_phys_opt_design.is_enabled" "1" $obj
set_property "steps.post_route_phys_opt_design.args.directive" "Explore" $obj
set_property "steps.write_bitstream.args.readback_file" "0" $obj
set_property "steps.write_bitstream.args.verbose" "0" $obj

# set the current impl run
current_run -implementation [get_runs impl_1]

puts "INFO: Project created:bpm_pcie_afck"
