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-- Title          : Wishbone slave core for Control and status register for the MLVDS trigger
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-- File           : wb_trigger_mux_regs.vhd
-- Author         : auto-generated by wbgen2 from wb_trigger_mux.wb
-- Created        : Wed May 11 18:21:31 2016
-- Standard       : VHDL'87
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-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wb_trigger_mux.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

use work.wb_trig_mux_wbgen2_pkg.all;


entity wb_trigger_mux_regs is
  port (
    rst_n_i                                  : in     std_logic;
    clk_sys_i                                : in     std_logic;
    wb_adr_i                                 : in     std_logic_vector(5 downto 0);
    wb_dat_i                                 : in     std_logic_vector(31 downto 0);
    wb_dat_o                                 : out    std_logic_vector(31 downto 0);
    wb_cyc_i                                 : in     std_logic;
    wb_sel_i                                 : in     std_logic_vector(3 downto 0);
    wb_stb_i                                 : in     std_logic;
    wb_we_i                                  : in     std_logic;
    wb_ack_o                                 : out    std_logic;
    wb_stall_o                               : out    std_logic;
    fs_clk_i                                 : in     std_logic;
    regs_i                                   : in     t_wb_trig_mux_in_registers;
    regs_o                                   : out    t_wb_trig_mux_out_registers
  );
end wb_trigger_mux_regs;

architecture syn of wb_trigger_mux_regs is

signal wb_trig_mux_ch0_ctl_rcv_src_int          : std_logic      ;
signal wb_trig_mux_ch0_ctl_rcv_in_sel_int       : std_logic_vector(7 downto 0);
signal wb_trig_mux_ch0_ctl_rcv_in_sel_swb       : std_logic      ;
signal wb_trig_mux_ch0_ctl_rcv_in_sel_swb_delay : std_logic      ;
signal wb_trig_mux_ch0_ctl_rcv_in_sel_swb_s0    : std_logic      ;
signal wb_trig_mux_ch0_ctl_rcv_in_sel_swb_s1    : std_logic      ;
signal wb_trig_mux_ch0_ctl_rcv_in_sel_swb_s2    : std_logic      ;
signal wb_trig_mux_ch0_ctl_transm_src_int       : std_logic      ;
signal wb_trig_mux_ch0_ctl_transm_out_sel_int   : std_logic_vector(7 downto 0);
signal wb_trig_mux_ch0_ctl_transm_out_sel_swb   : std_logic      ;
signal wb_trig_mux_ch0_ctl_transm_out_sel_swb_delay : std_logic      ;
signal wb_trig_mux_ch0_ctl_transm_out_sel_swb_s0 : std_logic      ;
signal wb_trig_mux_ch0_ctl_transm_out_sel_swb_s1 : std_logic      ;
signal wb_trig_mux_ch0_ctl_transm_out_sel_swb_s2 : std_logic      ;
signal wb_trig_mux_ch1_ctl_rcv_src_int          : std_logic      ;
signal wb_trig_mux_ch1_ctl_rcv_in_sel_int       : std_logic_vector(7 downto 0);
signal wb_trig_mux_ch1_ctl_rcv_in_sel_swb       : std_logic      ;
signal wb_trig_mux_ch1_ctl_rcv_in_sel_swb_delay : std_logic      ;
signal wb_trig_mux_ch1_ctl_rcv_in_sel_swb_s0    : std_logic      ;
signal wb_trig_mux_ch1_ctl_rcv_in_sel_swb_s1    : std_logic      ;
signal wb_trig_mux_ch1_ctl_rcv_in_sel_swb_s2    : std_logic      ;
signal wb_trig_mux_ch1_ctl_transm_src_int       : std_logic      ;
signal wb_trig_mux_ch1_ctl_transm_out_sel_int   : std_logic_vector(7 downto 0);
signal wb_trig_mux_ch1_ctl_transm_out_sel_swb   : std_logic      ;
signal wb_trig_mux_ch1_ctl_transm_out_sel_swb_delay : std_logic      ;
signal wb_trig_mux_ch1_ctl_transm_out_sel_swb_s0 : std_logic      ;
signal wb_trig_mux_ch1_ctl_transm_out_sel_swb_s1 : std_logic      ;
signal wb_trig_mux_ch1_ctl_transm_out_sel_swb_s2 : std_logic      ;
signal wb_trig_mux_ch2_ctl_rcv_src_int          : std_logic      ;
signal wb_trig_mux_ch2_ctl_rcv_in_sel_int       : std_logic_vector(7 downto 0);
signal wb_trig_mux_ch2_ctl_rcv_in_sel_swb       : std_logic      ;
signal wb_trig_mux_ch2_ctl_rcv_in_sel_swb_delay : std_logic      ;
signal wb_trig_mux_ch2_ctl_rcv_in_sel_swb_s0    : std_logic      ;
signal wb_trig_mux_ch2_ctl_rcv_in_sel_swb_s1    : std_logic      ;
signal wb_trig_mux_ch2_ctl_rcv_in_sel_swb_s2    : std_logic      ;
signal wb_trig_mux_ch2_ctl_transm_src_int       : std_logic      ;
signal wb_trig_mux_ch2_ctl_transm_out_sel_int   : std_logic_vector(7 downto 0);
signal wb_trig_mux_ch2_ctl_transm_out_sel_swb   : std_logic      ;
signal wb_trig_mux_ch2_ctl_transm_out_sel_swb_delay : std_logic      ;
signal wb_trig_mux_ch2_ctl_transm_out_sel_swb_s0 : std_logic      ;
signal wb_trig_mux_ch2_ctl_transm_out_sel_swb_s1 : std_logic      ;
signal wb_trig_mux_ch2_ctl_transm_out_sel_swb_s2 : std_logic      ;
signal wb_trig_mux_ch3_ctl_rcv_src_int          : std_logic      ;
signal wb_trig_mux_ch3_ctl_rcv_in_sel_int       : std_logic_vector(7 downto 0);
signal wb_trig_mux_ch3_ctl_rcv_in_sel_swb       : std_logic      ;
signal wb_trig_mux_ch3_ctl_rcv_in_sel_swb_delay : std_logic      ;
signal wb_trig_mux_ch3_ctl_rcv_in_sel_swb_s0    : std_logic      ;
signal wb_trig_mux_ch3_ctl_rcv_in_sel_swb_s1    : std_logic      ;
signal wb_trig_mux_ch3_ctl_rcv_in_sel_swb_s2    : std_logic      ;
signal wb_trig_mux_ch3_ctl_transm_src_int       : std_logic      ;
signal wb_trig_mux_ch3_ctl_transm_out_sel_int   : std_logic_vector(7 downto 0);
signal wb_trig_mux_ch3_ctl_transm_out_sel_swb   : std_logic      ;
signal wb_trig_mux_ch3_ctl_transm_out_sel_swb_delay : std_logic      ;
signal wb_trig_mux_ch3_ctl_transm_out_sel_swb_s0 : std_logic      ;
signal wb_trig_mux_ch3_ctl_transm_out_sel_swb_s1 : std_logic      ;
signal wb_trig_mux_ch3_ctl_transm_out_sel_swb_s2 : std_logic      ;
signal wb_trig_mux_ch4_ctl_rcv_src_int          : std_logic      ;
signal wb_trig_mux_ch4_ctl_rcv_in_sel_int       : std_logic_vector(7 downto 0);
signal wb_trig_mux_ch4_ctl_rcv_in_sel_swb       : std_logic      ;
signal wb_trig_mux_ch4_ctl_rcv_in_sel_swb_delay : std_logic      ;
signal wb_trig_mux_ch4_ctl_rcv_in_sel_swb_s0    : std_logic      ;
signal wb_trig_mux_ch4_ctl_rcv_in_sel_swb_s1    : std_logic      ;
signal wb_trig_mux_ch4_ctl_rcv_in_sel_swb_s2    : std_logic      ;
signal wb_trig_mux_ch4_ctl_transm_src_int       : std_logic      ;
signal wb_trig_mux_ch4_ctl_transm_out_sel_int   : std_logic_vector(7 downto 0);
signal wb_trig_mux_ch4_ctl_transm_out_sel_swb   : std_logic      ;
signal wb_trig_mux_ch4_ctl_transm_out_sel_swb_delay : std_logic      ;
signal wb_trig_mux_ch4_ctl_transm_out_sel_swb_s0 : std_logic      ;
signal wb_trig_mux_ch4_ctl_transm_out_sel_swb_s1 : std_logic      ;
signal wb_trig_mux_ch4_ctl_transm_out_sel_swb_s2 : std_logic      ;
signal wb_trig_mux_ch5_ctl_rcv_src_int          : std_logic      ;
signal wb_trig_mux_ch5_ctl_rcv_in_sel_int       : std_logic_vector(7 downto 0);
signal wb_trig_mux_ch5_ctl_rcv_in_sel_swb       : std_logic      ;
signal wb_trig_mux_ch5_ctl_rcv_in_sel_swb_delay : std_logic      ;
signal wb_trig_mux_ch5_ctl_rcv_in_sel_swb_s0    : std_logic      ;
signal wb_trig_mux_ch5_ctl_rcv_in_sel_swb_s1    : std_logic      ;
signal wb_trig_mux_ch5_ctl_rcv_in_sel_swb_s2    : std_logic      ;
signal wb_trig_mux_ch5_ctl_transm_src_int       : std_logic      ;
signal wb_trig_mux_ch5_ctl_transm_out_sel_int   : std_logic_vector(7 downto 0);
signal wb_trig_mux_ch5_ctl_transm_out_sel_swb   : std_logic      ;
signal wb_trig_mux_ch5_ctl_transm_out_sel_swb_delay : std_logic      ;
signal wb_trig_mux_ch5_ctl_transm_out_sel_swb_s0 : std_logic      ;
signal wb_trig_mux_ch5_ctl_transm_out_sel_swb_s1 : std_logic      ;
signal wb_trig_mux_ch5_ctl_transm_out_sel_swb_s2 : std_logic      ;
signal wb_trig_mux_ch6_ctl_rcv_src_int          : std_logic      ;
signal wb_trig_mux_ch6_ctl_rcv_in_sel_int       : std_logic_vector(7 downto 0);
signal wb_trig_mux_ch6_ctl_rcv_in_sel_swb       : std_logic      ;
signal wb_trig_mux_ch6_ctl_rcv_in_sel_swb_delay : std_logic      ;
signal wb_trig_mux_ch6_ctl_rcv_in_sel_swb_s0    : std_logic      ;
signal wb_trig_mux_ch6_ctl_rcv_in_sel_swb_s1    : std_logic      ;
signal wb_trig_mux_ch6_ctl_rcv_in_sel_swb_s2    : std_logic      ;
signal wb_trig_mux_ch6_ctl_transm_src_int       : std_logic      ;
signal wb_trig_mux_ch6_ctl_transm_out_sel_int   : std_logic_vector(7 downto 0);
signal wb_trig_mux_ch6_ctl_transm_out_sel_swb   : std_logic      ;
signal wb_trig_mux_ch6_ctl_transm_out_sel_swb_delay : std_logic      ;
signal wb_trig_mux_ch6_ctl_transm_out_sel_swb_s0 : std_logic      ;
signal wb_trig_mux_ch6_ctl_transm_out_sel_swb_s1 : std_logic      ;
signal wb_trig_mux_ch6_ctl_transm_out_sel_swb_s2 : std_logic      ;
signal wb_trig_mux_ch7_ctl_rcv_src_int          : std_logic      ;
signal wb_trig_mux_ch7_ctl_rcv_in_sel_int       : std_logic_vector(7 downto 0);
signal wb_trig_mux_ch7_ctl_rcv_in_sel_swb       : std_logic      ;
signal wb_trig_mux_ch7_ctl_rcv_in_sel_swb_delay : std_logic      ;
signal wb_trig_mux_ch7_ctl_rcv_in_sel_swb_s0    : std_logic      ;
signal wb_trig_mux_ch7_ctl_rcv_in_sel_swb_s1    : std_logic      ;
signal wb_trig_mux_ch7_ctl_rcv_in_sel_swb_s2    : std_logic      ;
signal wb_trig_mux_ch7_ctl_transm_src_int       : std_logic      ;
signal wb_trig_mux_ch7_ctl_transm_out_sel_int   : std_logic_vector(7 downto 0);
signal wb_trig_mux_ch7_ctl_transm_out_sel_swb   : std_logic      ;
signal wb_trig_mux_ch7_ctl_transm_out_sel_swb_delay : std_logic      ;
signal wb_trig_mux_ch7_ctl_transm_out_sel_swb_s0 : std_logic      ;
signal wb_trig_mux_ch7_ctl_transm_out_sel_swb_s1 : std_logic      ;
signal wb_trig_mux_ch7_ctl_transm_out_sel_swb_s2 : std_logic      ;
signal wb_trig_mux_ch8_ctl_rcv_src_int          : std_logic      ;
signal wb_trig_mux_ch8_ctl_rcv_in_sel_int       : std_logic_vector(7 downto 0);
signal wb_trig_mux_ch8_ctl_rcv_in_sel_swb       : std_logic      ;
signal wb_trig_mux_ch8_ctl_rcv_in_sel_swb_delay : std_logic      ;
signal wb_trig_mux_ch8_ctl_rcv_in_sel_swb_s0    : std_logic      ;
signal wb_trig_mux_ch8_ctl_rcv_in_sel_swb_s1    : std_logic      ;
signal wb_trig_mux_ch8_ctl_rcv_in_sel_swb_s2    : std_logic      ;
signal wb_trig_mux_ch8_ctl_transm_src_int       : std_logic      ;
signal wb_trig_mux_ch8_ctl_transm_out_sel_int   : std_logic_vector(7 downto 0);
signal wb_trig_mux_ch8_ctl_transm_out_sel_swb   : std_logic      ;
signal wb_trig_mux_ch8_ctl_transm_out_sel_swb_delay : std_logic      ;
signal wb_trig_mux_ch8_ctl_transm_out_sel_swb_s0 : std_logic      ;
signal wb_trig_mux_ch8_ctl_transm_out_sel_swb_s1 : std_logic      ;
signal wb_trig_mux_ch8_ctl_transm_out_sel_swb_s2 : std_logic      ;
signal wb_trig_mux_ch9_ctl_rcv_src_int          : std_logic      ;
signal wb_trig_mux_ch9_ctl_rcv_in_sel_int       : std_logic_vector(7 downto 0);
signal wb_trig_mux_ch9_ctl_rcv_in_sel_swb       : std_logic      ;
signal wb_trig_mux_ch9_ctl_rcv_in_sel_swb_delay : std_logic      ;
signal wb_trig_mux_ch9_ctl_rcv_in_sel_swb_s0    : std_logic      ;
signal wb_trig_mux_ch9_ctl_rcv_in_sel_swb_s1    : std_logic      ;
signal wb_trig_mux_ch9_ctl_rcv_in_sel_swb_s2    : std_logic      ;
signal wb_trig_mux_ch9_ctl_transm_src_int       : std_logic      ;
signal wb_trig_mux_ch9_ctl_transm_out_sel_int   : std_logic_vector(7 downto 0);
signal wb_trig_mux_ch9_ctl_transm_out_sel_swb   : std_logic      ;
signal wb_trig_mux_ch9_ctl_transm_out_sel_swb_delay : std_logic      ;
signal wb_trig_mux_ch9_ctl_transm_out_sel_swb_s0 : std_logic      ;
signal wb_trig_mux_ch9_ctl_transm_out_sel_swb_s1 : std_logic      ;
signal wb_trig_mux_ch9_ctl_transm_out_sel_swb_s2 : std_logic      ;
signal wb_trig_mux_ch10_ctl_rcv_src_int         : std_logic      ;
signal wb_trig_mux_ch10_ctl_rcv_in_sel_int      : std_logic_vector(7 downto 0);
signal wb_trig_mux_ch10_ctl_rcv_in_sel_swb      : std_logic      ;
signal wb_trig_mux_ch10_ctl_rcv_in_sel_swb_delay : std_logic      ;
signal wb_trig_mux_ch10_ctl_rcv_in_sel_swb_s0   : std_logic      ;
signal wb_trig_mux_ch10_ctl_rcv_in_sel_swb_s1   : std_logic      ;
signal wb_trig_mux_ch10_ctl_rcv_in_sel_swb_s2   : std_logic      ;
signal wb_trig_mux_ch10_ctl_transm_src_int      : std_logic      ;
signal wb_trig_mux_ch10_ctl_transm_out_sel_int  : std_logic_vector(7 downto 0);
signal wb_trig_mux_ch10_ctl_transm_out_sel_swb  : std_logic      ;
signal wb_trig_mux_ch10_ctl_transm_out_sel_swb_delay : std_logic      ;
signal wb_trig_mux_ch10_ctl_transm_out_sel_swb_s0 : std_logic      ;
signal wb_trig_mux_ch10_ctl_transm_out_sel_swb_s1 : std_logic      ;
signal wb_trig_mux_ch10_ctl_transm_out_sel_swb_s2 : std_logic      ;
signal wb_trig_mux_ch11_ctl_rcv_src_int         : std_logic      ;
signal wb_trig_mux_ch11_ctl_rcv_in_sel_int      : std_logic_vector(7 downto 0);
signal wb_trig_mux_ch11_ctl_rcv_in_sel_swb      : std_logic      ;
signal wb_trig_mux_ch11_ctl_rcv_in_sel_swb_delay : std_logic      ;
signal wb_trig_mux_ch11_ctl_rcv_in_sel_swb_s0   : std_logic      ;
signal wb_trig_mux_ch11_ctl_rcv_in_sel_swb_s1   : std_logic      ;
signal wb_trig_mux_ch11_ctl_rcv_in_sel_swb_s2   : std_logic      ;
signal wb_trig_mux_ch11_ctl_transm_src_int      : std_logic      ;
signal wb_trig_mux_ch11_ctl_transm_out_sel_int  : std_logic_vector(7 downto 0);
signal wb_trig_mux_ch11_ctl_transm_out_sel_swb  : std_logic      ;
signal wb_trig_mux_ch11_ctl_transm_out_sel_swb_delay : std_logic      ;
signal wb_trig_mux_ch11_ctl_transm_out_sel_swb_s0 : std_logic      ;
signal wb_trig_mux_ch11_ctl_transm_out_sel_swb_s1 : std_logic      ;
signal wb_trig_mux_ch11_ctl_transm_out_sel_swb_s2 : std_logic      ;
signal wb_trig_mux_ch12_ctl_rcv_src_int         : std_logic      ;
signal wb_trig_mux_ch12_ctl_rcv_in_sel_int      : std_logic_vector(7 downto 0);
signal wb_trig_mux_ch12_ctl_rcv_in_sel_swb      : std_logic      ;
signal wb_trig_mux_ch12_ctl_rcv_in_sel_swb_delay : std_logic      ;
signal wb_trig_mux_ch12_ctl_rcv_in_sel_swb_s0   : std_logic      ;
signal wb_trig_mux_ch12_ctl_rcv_in_sel_swb_s1   : std_logic      ;
signal wb_trig_mux_ch12_ctl_rcv_in_sel_swb_s2   : std_logic      ;
signal wb_trig_mux_ch12_ctl_transm_src_int      : std_logic      ;
signal wb_trig_mux_ch12_ctl_transm_out_sel_int  : std_logic_vector(7 downto 0);
signal wb_trig_mux_ch12_ctl_transm_out_sel_swb  : std_logic      ;
signal wb_trig_mux_ch12_ctl_transm_out_sel_swb_delay : std_logic      ;
signal wb_trig_mux_ch12_ctl_transm_out_sel_swb_s0 : std_logic      ;
signal wb_trig_mux_ch12_ctl_transm_out_sel_swb_s1 : std_logic      ;
signal wb_trig_mux_ch12_ctl_transm_out_sel_swb_s2 : std_logic      ;
signal wb_trig_mux_ch13_ctl_rcv_src_int         : std_logic      ;
signal wb_trig_mux_ch13_ctl_rcv_in_sel_int      : std_logic_vector(7 downto 0);
signal wb_trig_mux_ch13_ctl_rcv_in_sel_swb      : std_logic      ;
signal wb_trig_mux_ch13_ctl_rcv_in_sel_swb_delay : std_logic      ;
signal wb_trig_mux_ch13_ctl_rcv_in_sel_swb_s0   : std_logic      ;
signal wb_trig_mux_ch13_ctl_rcv_in_sel_swb_s1   : std_logic      ;
signal wb_trig_mux_ch13_ctl_rcv_in_sel_swb_s2   : std_logic      ;
signal wb_trig_mux_ch13_ctl_transm_src_int      : std_logic      ;
signal wb_trig_mux_ch13_ctl_transm_out_sel_int  : std_logic_vector(7 downto 0);
signal wb_trig_mux_ch13_ctl_transm_out_sel_swb  : std_logic      ;
signal wb_trig_mux_ch13_ctl_transm_out_sel_swb_delay : std_logic      ;
signal wb_trig_mux_ch13_ctl_transm_out_sel_swb_s0 : std_logic      ;
signal wb_trig_mux_ch13_ctl_transm_out_sel_swb_s1 : std_logic      ;
signal wb_trig_mux_ch13_ctl_transm_out_sel_swb_s2 : std_logic      ;
signal wb_trig_mux_ch14_ctl_rcv_src_int         : std_logic      ;
signal wb_trig_mux_ch14_ctl_rcv_in_sel_int      : std_logic_vector(7 downto 0);
signal wb_trig_mux_ch14_ctl_rcv_in_sel_swb      : std_logic      ;
signal wb_trig_mux_ch14_ctl_rcv_in_sel_swb_delay : std_logic      ;
signal wb_trig_mux_ch14_ctl_rcv_in_sel_swb_s0   : std_logic      ;
signal wb_trig_mux_ch14_ctl_rcv_in_sel_swb_s1   : std_logic      ;
signal wb_trig_mux_ch14_ctl_rcv_in_sel_swb_s2   : std_logic      ;
signal wb_trig_mux_ch14_ctl_transm_src_int      : std_logic      ;
signal wb_trig_mux_ch14_ctl_transm_out_sel_int  : std_logic_vector(7 downto 0);
signal wb_trig_mux_ch14_ctl_transm_out_sel_swb  : std_logic      ;
signal wb_trig_mux_ch14_ctl_transm_out_sel_swb_delay : std_logic      ;
signal wb_trig_mux_ch14_ctl_transm_out_sel_swb_s0 : std_logic      ;
signal wb_trig_mux_ch14_ctl_transm_out_sel_swb_s1 : std_logic      ;
signal wb_trig_mux_ch14_ctl_transm_out_sel_swb_s2 : std_logic      ;
signal wb_trig_mux_ch15_ctl_rcv_src_int         : std_logic      ;
signal wb_trig_mux_ch15_ctl_rcv_in_sel_int      : std_logic_vector(7 downto 0);
signal wb_trig_mux_ch15_ctl_rcv_in_sel_swb      : std_logic      ;
signal wb_trig_mux_ch15_ctl_rcv_in_sel_swb_delay : std_logic      ;
signal wb_trig_mux_ch15_ctl_rcv_in_sel_swb_s0   : std_logic      ;
signal wb_trig_mux_ch15_ctl_rcv_in_sel_swb_s1   : std_logic      ;
signal wb_trig_mux_ch15_ctl_rcv_in_sel_swb_s2   : std_logic      ;
signal wb_trig_mux_ch15_ctl_transm_src_int      : std_logic      ;
signal wb_trig_mux_ch15_ctl_transm_out_sel_int  : std_logic_vector(7 downto 0);
signal wb_trig_mux_ch15_ctl_transm_out_sel_swb  : std_logic      ;
signal wb_trig_mux_ch15_ctl_transm_out_sel_swb_delay : std_logic      ;
signal wb_trig_mux_ch15_ctl_transm_out_sel_swb_s0 : std_logic      ;
signal wb_trig_mux_ch15_ctl_transm_out_sel_swb_s1 : std_logic      ;
signal wb_trig_mux_ch15_ctl_transm_out_sel_swb_s2 : std_logic      ;
signal wb_trig_mux_ch16_ctl_rcv_src_int         : std_logic      ;
signal wb_trig_mux_ch16_ctl_rcv_in_sel_int      : std_logic_vector(7 downto 0);
signal wb_trig_mux_ch16_ctl_rcv_in_sel_swb      : std_logic      ;
signal wb_trig_mux_ch16_ctl_rcv_in_sel_swb_delay : std_logic      ;
signal wb_trig_mux_ch16_ctl_rcv_in_sel_swb_s0   : std_logic      ;
signal wb_trig_mux_ch16_ctl_rcv_in_sel_swb_s1   : std_logic      ;
signal wb_trig_mux_ch16_ctl_rcv_in_sel_swb_s2   : std_logic      ;
signal wb_trig_mux_ch16_ctl_transm_src_int      : std_logic      ;
signal wb_trig_mux_ch16_ctl_transm_out_sel_int  : std_logic_vector(7 downto 0);
signal wb_trig_mux_ch16_ctl_transm_out_sel_swb  : std_logic      ;
signal wb_trig_mux_ch16_ctl_transm_out_sel_swb_delay : std_logic      ;
signal wb_trig_mux_ch16_ctl_transm_out_sel_swb_s0 : std_logic      ;
signal wb_trig_mux_ch16_ctl_transm_out_sel_swb_s1 : std_logic      ;
signal wb_trig_mux_ch16_ctl_transm_out_sel_swb_s2 : std_logic      ;
signal wb_trig_mux_ch17_ctl_rcv_src_int         : std_logic      ;
signal wb_trig_mux_ch17_ctl_rcv_in_sel_int      : std_logic_vector(7 downto 0);
signal wb_trig_mux_ch17_ctl_rcv_in_sel_swb      : std_logic      ;
signal wb_trig_mux_ch17_ctl_rcv_in_sel_swb_delay : std_logic      ;
signal wb_trig_mux_ch17_ctl_rcv_in_sel_swb_s0   : std_logic      ;
signal wb_trig_mux_ch17_ctl_rcv_in_sel_swb_s1   : std_logic      ;
signal wb_trig_mux_ch17_ctl_rcv_in_sel_swb_s2   : std_logic      ;
signal wb_trig_mux_ch17_ctl_transm_src_int      : std_logic      ;
signal wb_trig_mux_ch17_ctl_transm_out_sel_int  : std_logic_vector(7 downto 0);
signal wb_trig_mux_ch17_ctl_transm_out_sel_swb  : std_logic      ;
signal wb_trig_mux_ch17_ctl_transm_out_sel_swb_delay : std_logic      ;
signal wb_trig_mux_ch17_ctl_transm_out_sel_swb_s0 : std_logic      ;
signal wb_trig_mux_ch17_ctl_transm_out_sel_swb_s1 : std_logic      ;
signal wb_trig_mux_ch17_ctl_transm_out_sel_swb_s2 : std_logic      ;
signal wb_trig_mux_ch18_ctl_rcv_src_int         : std_logic      ;
signal wb_trig_mux_ch18_ctl_rcv_in_sel_int      : std_logic_vector(7 downto 0);
signal wb_trig_mux_ch18_ctl_rcv_in_sel_swb      : std_logic      ;
signal wb_trig_mux_ch18_ctl_rcv_in_sel_swb_delay : std_logic      ;
signal wb_trig_mux_ch18_ctl_rcv_in_sel_swb_s0   : std_logic      ;
signal wb_trig_mux_ch18_ctl_rcv_in_sel_swb_s1   : std_logic      ;
signal wb_trig_mux_ch18_ctl_rcv_in_sel_swb_s2   : std_logic      ;
signal wb_trig_mux_ch18_ctl_transm_src_int      : std_logic      ;
signal wb_trig_mux_ch18_ctl_transm_out_sel_int  : std_logic_vector(7 downto 0);
signal wb_trig_mux_ch18_ctl_transm_out_sel_swb  : std_logic      ;
signal wb_trig_mux_ch18_ctl_transm_out_sel_swb_delay : std_logic      ;
signal wb_trig_mux_ch18_ctl_transm_out_sel_swb_s0 : std_logic      ;
signal wb_trig_mux_ch18_ctl_transm_out_sel_swb_s1 : std_logic      ;
signal wb_trig_mux_ch18_ctl_transm_out_sel_swb_s2 : std_logic      ;
signal wb_trig_mux_ch19_ctl_rcv_src_int         : std_logic      ;
signal wb_trig_mux_ch19_ctl_rcv_in_sel_int      : std_logic_vector(7 downto 0);
signal wb_trig_mux_ch19_ctl_rcv_in_sel_swb      : std_logic      ;
signal wb_trig_mux_ch19_ctl_rcv_in_sel_swb_delay : std_logic      ;
signal wb_trig_mux_ch19_ctl_rcv_in_sel_swb_s0   : std_logic      ;
signal wb_trig_mux_ch19_ctl_rcv_in_sel_swb_s1   : std_logic      ;
signal wb_trig_mux_ch19_ctl_rcv_in_sel_swb_s2   : std_logic      ;
signal wb_trig_mux_ch19_ctl_transm_src_int      : std_logic      ;
signal wb_trig_mux_ch19_ctl_transm_out_sel_int  : std_logic_vector(7 downto 0);
signal wb_trig_mux_ch19_ctl_transm_out_sel_swb  : std_logic      ;
signal wb_trig_mux_ch19_ctl_transm_out_sel_swb_delay : std_logic      ;
signal wb_trig_mux_ch19_ctl_transm_out_sel_swb_s0 : std_logic      ;
signal wb_trig_mux_ch19_ctl_transm_out_sel_swb_s1 : std_logic      ;
signal wb_trig_mux_ch19_ctl_transm_out_sel_swb_s2 : std_logic      ;
signal wb_trig_mux_ch20_ctl_rcv_src_int         : std_logic      ;
signal wb_trig_mux_ch20_ctl_rcv_in_sel_int      : std_logic_vector(7 downto 0);
signal wb_trig_mux_ch20_ctl_rcv_in_sel_swb      : std_logic      ;
signal wb_trig_mux_ch20_ctl_rcv_in_sel_swb_delay : std_logic      ;
signal wb_trig_mux_ch20_ctl_rcv_in_sel_swb_s0   : std_logic      ;
signal wb_trig_mux_ch20_ctl_rcv_in_sel_swb_s1   : std_logic      ;
signal wb_trig_mux_ch20_ctl_rcv_in_sel_swb_s2   : std_logic      ;
signal wb_trig_mux_ch20_ctl_transm_src_int      : std_logic      ;
signal wb_trig_mux_ch20_ctl_transm_out_sel_int  : std_logic_vector(7 downto 0);
signal wb_trig_mux_ch20_ctl_transm_out_sel_swb  : std_logic      ;
signal wb_trig_mux_ch20_ctl_transm_out_sel_swb_delay : std_logic      ;
signal wb_trig_mux_ch20_ctl_transm_out_sel_swb_s0 : std_logic      ;
signal wb_trig_mux_ch20_ctl_transm_out_sel_swb_s1 : std_logic      ;
signal wb_trig_mux_ch20_ctl_transm_out_sel_swb_s2 : std_logic      ;
signal wb_trig_mux_ch21_ctl_rcv_src_int         : std_logic      ;
signal wb_trig_mux_ch21_ctl_rcv_in_sel_int      : std_logic_vector(7 downto 0);
signal wb_trig_mux_ch21_ctl_rcv_in_sel_swb      : std_logic      ;
signal wb_trig_mux_ch21_ctl_rcv_in_sel_swb_delay : std_logic      ;
signal wb_trig_mux_ch21_ctl_rcv_in_sel_swb_s0   : std_logic      ;
signal wb_trig_mux_ch21_ctl_rcv_in_sel_swb_s1   : std_logic      ;
signal wb_trig_mux_ch21_ctl_rcv_in_sel_swb_s2   : std_logic      ;
signal wb_trig_mux_ch21_ctl_transm_src_int      : std_logic      ;
signal wb_trig_mux_ch21_ctl_transm_out_sel_int  : std_logic_vector(7 downto 0);
signal wb_trig_mux_ch21_ctl_transm_out_sel_swb  : std_logic      ;
signal wb_trig_mux_ch21_ctl_transm_out_sel_swb_delay : std_logic      ;
signal wb_trig_mux_ch21_ctl_transm_out_sel_swb_s0 : std_logic      ;
signal wb_trig_mux_ch21_ctl_transm_out_sel_swb_s1 : std_logic      ;
signal wb_trig_mux_ch21_ctl_transm_out_sel_swb_s2 : std_logic      ;
signal wb_trig_mux_ch22_ctl_rcv_src_int         : std_logic      ;
signal wb_trig_mux_ch22_ctl_rcv_in_sel_int      : std_logic_vector(7 downto 0);
signal wb_trig_mux_ch22_ctl_rcv_in_sel_swb      : std_logic      ;
signal wb_trig_mux_ch22_ctl_rcv_in_sel_swb_delay : std_logic      ;
signal wb_trig_mux_ch22_ctl_rcv_in_sel_swb_s0   : std_logic      ;
signal wb_trig_mux_ch22_ctl_rcv_in_sel_swb_s1   : std_logic      ;
signal wb_trig_mux_ch22_ctl_rcv_in_sel_swb_s2   : std_logic      ;
signal wb_trig_mux_ch22_ctl_transm_src_int      : std_logic      ;
signal wb_trig_mux_ch22_ctl_transm_out_sel_int  : std_logic_vector(7 downto 0);
signal wb_trig_mux_ch22_ctl_transm_out_sel_swb  : std_logic      ;
signal wb_trig_mux_ch22_ctl_transm_out_sel_swb_delay : std_logic      ;
signal wb_trig_mux_ch22_ctl_transm_out_sel_swb_s0 : std_logic      ;
signal wb_trig_mux_ch22_ctl_transm_out_sel_swb_s1 : std_logic      ;
signal wb_trig_mux_ch22_ctl_transm_out_sel_swb_s2 : std_logic      ;
signal wb_trig_mux_ch23_ctl_rcv_src_int         : std_logic      ;
signal wb_trig_mux_ch23_ctl_rcv_in_sel_int      : std_logic_vector(7 downto 0);
signal wb_trig_mux_ch23_ctl_rcv_in_sel_swb      : std_logic      ;
signal wb_trig_mux_ch23_ctl_rcv_in_sel_swb_delay : std_logic      ;
signal wb_trig_mux_ch23_ctl_rcv_in_sel_swb_s0   : std_logic      ;
signal wb_trig_mux_ch23_ctl_rcv_in_sel_swb_s1   : std_logic      ;
signal wb_trig_mux_ch23_ctl_rcv_in_sel_swb_s2   : std_logic      ;
signal wb_trig_mux_ch23_ctl_transm_src_int      : std_logic      ;
signal wb_trig_mux_ch23_ctl_transm_out_sel_int  : std_logic_vector(7 downto 0);
signal wb_trig_mux_ch23_ctl_transm_out_sel_swb  : std_logic      ;
signal wb_trig_mux_ch23_ctl_transm_out_sel_swb_delay : std_logic      ;
signal wb_trig_mux_ch23_ctl_transm_out_sel_swb_s0 : std_logic      ;
signal wb_trig_mux_ch23_ctl_transm_out_sel_swb_s1 : std_logic      ;
signal wb_trig_mux_ch23_ctl_transm_out_sel_swb_s2 : std_logic      ;
signal ack_sreg                                 : std_logic_vector(9 downto 0);
signal rddata_reg                               : std_logic_vector(31 downto 0);
signal wrdata_reg                               : std_logic_vector(31 downto 0);
signal bwsel_reg                                : std_logic_vector(3 downto 0);
signal rwaddr_reg                               : std_logic_vector(5 downto 0);
signal ack_in_progress                          : std_logic      ;
signal wr_int                                   : std_logic      ;
signal rd_int                                   : std_logic      ;
signal allones                                  : std_logic_vector(31 downto 0);
signal allzeros                                 : std_logic_vector(31 downto 0);

begin
-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
  wrdata_reg <= wb_dat_i;
  bwsel_reg <= wb_sel_i;
  rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
  wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
  allones <= (others => '1');
  allzeros <= (others => '0');
-- 
-- Main register bank access process.
  process (clk_sys_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      ack_sreg <= "0000000000";
      ack_in_progress <= '0';
      rddata_reg <= "00000000000000000000000000000000";
      wb_trig_mux_ch0_ctl_rcv_src_int <= '0';
      wb_trig_mux_ch0_ctl_rcv_in_sel_int <= "00000000";
      wb_trig_mux_ch0_ctl_rcv_in_sel_swb <= '0';
      wb_trig_mux_ch0_ctl_rcv_in_sel_swb_delay <= '0';
      wb_trig_mux_ch0_ctl_transm_src_int <= '0';
      wb_trig_mux_ch0_ctl_transm_out_sel_int <= "00000000";
      wb_trig_mux_ch0_ctl_transm_out_sel_swb <= '0';
      wb_trig_mux_ch0_ctl_transm_out_sel_swb_delay <= '0';
      wb_trig_mux_ch1_ctl_rcv_src_int <= '0';
      wb_trig_mux_ch1_ctl_rcv_in_sel_int <= "00000000";
      wb_trig_mux_ch1_ctl_rcv_in_sel_swb <= '0';
      wb_trig_mux_ch1_ctl_rcv_in_sel_swb_delay <= '0';
      wb_trig_mux_ch1_ctl_transm_src_int <= '0';
      wb_trig_mux_ch1_ctl_transm_out_sel_int <= "00000000";
      wb_trig_mux_ch1_ctl_transm_out_sel_swb <= '0';
      wb_trig_mux_ch1_ctl_transm_out_sel_swb_delay <= '0';
      wb_trig_mux_ch2_ctl_rcv_src_int <= '0';
      wb_trig_mux_ch2_ctl_rcv_in_sel_int <= "00000000";
      wb_trig_mux_ch2_ctl_rcv_in_sel_swb <= '0';
      wb_trig_mux_ch2_ctl_rcv_in_sel_swb_delay <= '0';
      wb_trig_mux_ch2_ctl_transm_src_int <= '0';
      wb_trig_mux_ch2_ctl_transm_out_sel_int <= "00000000";
      wb_trig_mux_ch2_ctl_transm_out_sel_swb <= '0';
      wb_trig_mux_ch2_ctl_transm_out_sel_swb_delay <= '0';
      wb_trig_mux_ch3_ctl_rcv_src_int <= '0';
      wb_trig_mux_ch3_ctl_rcv_in_sel_int <= "00000000";
      wb_trig_mux_ch3_ctl_rcv_in_sel_swb <= '0';
      wb_trig_mux_ch3_ctl_rcv_in_sel_swb_delay <= '0';
      wb_trig_mux_ch3_ctl_transm_src_int <= '0';
      wb_trig_mux_ch3_ctl_transm_out_sel_int <= "00000000";
      wb_trig_mux_ch3_ctl_transm_out_sel_swb <= '0';
      wb_trig_mux_ch3_ctl_transm_out_sel_swb_delay <= '0';
      wb_trig_mux_ch4_ctl_rcv_src_int <= '0';
      wb_trig_mux_ch4_ctl_rcv_in_sel_int <= "00000000";
      wb_trig_mux_ch4_ctl_rcv_in_sel_swb <= '0';
      wb_trig_mux_ch4_ctl_rcv_in_sel_swb_delay <= '0';
      wb_trig_mux_ch4_ctl_transm_src_int <= '0';
      wb_trig_mux_ch4_ctl_transm_out_sel_int <= "00000000";
      wb_trig_mux_ch4_ctl_transm_out_sel_swb <= '0';
      wb_trig_mux_ch4_ctl_transm_out_sel_swb_delay <= '0';
      wb_trig_mux_ch5_ctl_rcv_src_int <= '0';
      wb_trig_mux_ch5_ctl_rcv_in_sel_int <= "00000000";
      wb_trig_mux_ch5_ctl_rcv_in_sel_swb <= '0';
      wb_trig_mux_ch5_ctl_rcv_in_sel_swb_delay <= '0';
      wb_trig_mux_ch5_ctl_transm_src_int <= '0';
      wb_trig_mux_ch5_ctl_transm_out_sel_int <= "00000000";
      wb_trig_mux_ch5_ctl_transm_out_sel_swb <= '0';
      wb_trig_mux_ch5_ctl_transm_out_sel_swb_delay <= '0';
      wb_trig_mux_ch6_ctl_rcv_src_int <= '0';
      wb_trig_mux_ch6_ctl_rcv_in_sel_int <= "00000000";
      wb_trig_mux_ch6_ctl_rcv_in_sel_swb <= '0';
      wb_trig_mux_ch6_ctl_rcv_in_sel_swb_delay <= '0';
      wb_trig_mux_ch6_ctl_transm_src_int <= '0';
      wb_trig_mux_ch6_ctl_transm_out_sel_int <= "00000000";
      wb_trig_mux_ch6_ctl_transm_out_sel_swb <= '0';
      wb_trig_mux_ch6_ctl_transm_out_sel_swb_delay <= '0';
      wb_trig_mux_ch7_ctl_rcv_src_int <= '0';
      wb_trig_mux_ch7_ctl_rcv_in_sel_int <= "00000000";
      wb_trig_mux_ch7_ctl_rcv_in_sel_swb <= '0';
      wb_trig_mux_ch7_ctl_rcv_in_sel_swb_delay <= '0';
      wb_trig_mux_ch7_ctl_transm_src_int <= '0';
      wb_trig_mux_ch7_ctl_transm_out_sel_int <= "00000000";
      wb_trig_mux_ch7_ctl_transm_out_sel_swb <= '0';
      wb_trig_mux_ch7_ctl_transm_out_sel_swb_delay <= '0';
      wb_trig_mux_ch8_ctl_rcv_src_int <= '0';
      wb_trig_mux_ch8_ctl_rcv_in_sel_int <= "00000000";
      wb_trig_mux_ch8_ctl_rcv_in_sel_swb <= '0';
      wb_trig_mux_ch8_ctl_rcv_in_sel_swb_delay <= '0';
      wb_trig_mux_ch8_ctl_transm_src_int <= '0';
      wb_trig_mux_ch8_ctl_transm_out_sel_int <= "00000000";
      wb_trig_mux_ch8_ctl_transm_out_sel_swb <= '0';
      wb_trig_mux_ch8_ctl_transm_out_sel_swb_delay <= '0';
      wb_trig_mux_ch9_ctl_rcv_src_int <= '0';
      wb_trig_mux_ch9_ctl_rcv_in_sel_int <= "00000000";
      wb_trig_mux_ch9_ctl_rcv_in_sel_swb <= '0';
      wb_trig_mux_ch9_ctl_rcv_in_sel_swb_delay <= '0';
      wb_trig_mux_ch9_ctl_transm_src_int <= '0';
      wb_trig_mux_ch9_ctl_transm_out_sel_int <= "00000000";
      wb_trig_mux_ch9_ctl_transm_out_sel_swb <= '0';
      wb_trig_mux_ch9_ctl_transm_out_sel_swb_delay <= '0';
      wb_trig_mux_ch10_ctl_rcv_src_int <= '0';
      wb_trig_mux_ch10_ctl_rcv_in_sel_int <= "00000000";
      wb_trig_mux_ch10_ctl_rcv_in_sel_swb <= '0';
      wb_trig_mux_ch10_ctl_rcv_in_sel_swb_delay <= '0';
      wb_trig_mux_ch10_ctl_transm_src_int <= '0';
      wb_trig_mux_ch10_ctl_transm_out_sel_int <= "00000000";
      wb_trig_mux_ch10_ctl_transm_out_sel_swb <= '0';
      wb_trig_mux_ch10_ctl_transm_out_sel_swb_delay <= '0';
      wb_trig_mux_ch11_ctl_rcv_src_int <= '0';
      wb_trig_mux_ch11_ctl_rcv_in_sel_int <= "00000000";
      wb_trig_mux_ch11_ctl_rcv_in_sel_swb <= '0';
      wb_trig_mux_ch11_ctl_rcv_in_sel_swb_delay <= '0';
      wb_trig_mux_ch11_ctl_transm_src_int <= '0';
      wb_trig_mux_ch11_ctl_transm_out_sel_int <= "00000000";
      wb_trig_mux_ch11_ctl_transm_out_sel_swb <= '0';
      wb_trig_mux_ch11_ctl_transm_out_sel_swb_delay <= '0';
      wb_trig_mux_ch12_ctl_rcv_src_int <= '0';
      wb_trig_mux_ch12_ctl_rcv_in_sel_int <= "00000000";
      wb_trig_mux_ch12_ctl_rcv_in_sel_swb <= '0';
      wb_trig_mux_ch12_ctl_rcv_in_sel_swb_delay <= '0';
      wb_trig_mux_ch12_ctl_transm_src_int <= '0';
      wb_trig_mux_ch12_ctl_transm_out_sel_int <= "00000000";
      wb_trig_mux_ch12_ctl_transm_out_sel_swb <= '0';
      wb_trig_mux_ch12_ctl_transm_out_sel_swb_delay <= '0';
      wb_trig_mux_ch13_ctl_rcv_src_int <= '0';
      wb_trig_mux_ch13_ctl_rcv_in_sel_int <= "00000000";
      wb_trig_mux_ch13_ctl_rcv_in_sel_swb <= '0';
      wb_trig_mux_ch13_ctl_rcv_in_sel_swb_delay <= '0';
      wb_trig_mux_ch13_ctl_transm_src_int <= '0';
      wb_trig_mux_ch13_ctl_transm_out_sel_int <= "00000000";
      wb_trig_mux_ch13_ctl_transm_out_sel_swb <= '0';
      wb_trig_mux_ch13_ctl_transm_out_sel_swb_delay <= '0';
      wb_trig_mux_ch14_ctl_rcv_src_int <= '0';
      wb_trig_mux_ch14_ctl_rcv_in_sel_int <= "00000000";
      wb_trig_mux_ch14_ctl_rcv_in_sel_swb <= '0';
      wb_trig_mux_ch14_ctl_rcv_in_sel_swb_delay <= '0';
      wb_trig_mux_ch14_ctl_transm_src_int <= '0';
      wb_trig_mux_ch14_ctl_transm_out_sel_int <= "00000000";
      wb_trig_mux_ch14_ctl_transm_out_sel_swb <= '0';
      wb_trig_mux_ch14_ctl_transm_out_sel_swb_delay <= '0';
      wb_trig_mux_ch15_ctl_rcv_src_int <= '0';
      wb_trig_mux_ch15_ctl_rcv_in_sel_int <= "00000000";
      wb_trig_mux_ch15_ctl_rcv_in_sel_swb <= '0';
      wb_trig_mux_ch15_ctl_rcv_in_sel_swb_delay <= '0';
      wb_trig_mux_ch15_ctl_transm_src_int <= '0';
      wb_trig_mux_ch15_ctl_transm_out_sel_int <= "00000000";
      wb_trig_mux_ch15_ctl_transm_out_sel_swb <= '0';
      wb_trig_mux_ch15_ctl_transm_out_sel_swb_delay <= '0';
      wb_trig_mux_ch16_ctl_rcv_src_int <= '0';
      wb_trig_mux_ch16_ctl_rcv_in_sel_int <= "00000000";
      wb_trig_mux_ch16_ctl_rcv_in_sel_swb <= '0';
      wb_trig_mux_ch16_ctl_rcv_in_sel_swb_delay <= '0';
      wb_trig_mux_ch16_ctl_transm_src_int <= '0';
      wb_trig_mux_ch16_ctl_transm_out_sel_int <= "00000000";
      wb_trig_mux_ch16_ctl_transm_out_sel_swb <= '0';
      wb_trig_mux_ch16_ctl_transm_out_sel_swb_delay <= '0';
      wb_trig_mux_ch17_ctl_rcv_src_int <= '0';
      wb_trig_mux_ch17_ctl_rcv_in_sel_int <= "00000000";
      wb_trig_mux_ch17_ctl_rcv_in_sel_swb <= '0';
      wb_trig_mux_ch17_ctl_rcv_in_sel_swb_delay <= '0';
      wb_trig_mux_ch17_ctl_transm_src_int <= '0';
      wb_trig_mux_ch17_ctl_transm_out_sel_int <= "00000000";
      wb_trig_mux_ch17_ctl_transm_out_sel_swb <= '0';
      wb_trig_mux_ch17_ctl_transm_out_sel_swb_delay <= '0';
      wb_trig_mux_ch18_ctl_rcv_src_int <= '0';
      wb_trig_mux_ch18_ctl_rcv_in_sel_int <= "00000000";
      wb_trig_mux_ch18_ctl_rcv_in_sel_swb <= '0';
      wb_trig_mux_ch18_ctl_rcv_in_sel_swb_delay <= '0';
      wb_trig_mux_ch18_ctl_transm_src_int <= '0';
      wb_trig_mux_ch18_ctl_transm_out_sel_int <= "00000000";
      wb_trig_mux_ch18_ctl_transm_out_sel_swb <= '0';
      wb_trig_mux_ch18_ctl_transm_out_sel_swb_delay <= '0';
      wb_trig_mux_ch19_ctl_rcv_src_int <= '0';
      wb_trig_mux_ch19_ctl_rcv_in_sel_int <= "00000000";
      wb_trig_mux_ch19_ctl_rcv_in_sel_swb <= '0';
      wb_trig_mux_ch19_ctl_rcv_in_sel_swb_delay <= '0';
      wb_trig_mux_ch19_ctl_transm_src_int <= '0';
      wb_trig_mux_ch19_ctl_transm_out_sel_int <= "00000000";
      wb_trig_mux_ch19_ctl_transm_out_sel_swb <= '0';
      wb_trig_mux_ch19_ctl_transm_out_sel_swb_delay <= '0';
      wb_trig_mux_ch20_ctl_rcv_src_int <= '0';
      wb_trig_mux_ch20_ctl_rcv_in_sel_int <= "00000000";
      wb_trig_mux_ch20_ctl_rcv_in_sel_swb <= '0';
      wb_trig_mux_ch20_ctl_rcv_in_sel_swb_delay <= '0';
      wb_trig_mux_ch20_ctl_transm_src_int <= '0';
      wb_trig_mux_ch20_ctl_transm_out_sel_int <= "00000000";
      wb_trig_mux_ch20_ctl_transm_out_sel_swb <= '0';
      wb_trig_mux_ch20_ctl_transm_out_sel_swb_delay <= '0';
      wb_trig_mux_ch21_ctl_rcv_src_int <= '0';
      wb_trig_mux_ch21_ctl_rcv_in_sel_int <= "00000000";
      wb_trig_mux_ch21_ctl_rcv_in_sel_swb <= '0';
      wb_trig_mux_ch21_ctl_rcv_in_sel_swb_delay <= '0';
      wb_trig_mux_ch21_ctl_transm_src_int <= '0';
      wb_trig_mux_ch21_ctl_transm_out_sel_int <= "00000000";
      wb_trig_mux_ch21_ctl_transm_out_sel_swb <= '0';
      wb_trig_mux_ch21_ctl_transm_out_sel_swb_delay <= '0';
      wb_trig_mux_ch22_ctl_rcv_src_int <= '0';
      wb_trig_mux_ch22_ctl_rcv_in_sel_int <= "00000000";
      wb_trig_mux_ch22_ctl_rcv_in_sel_swb <= '0';
      wb_trig_mux_ch22_ctl_rcv_in_sel_swb_delay <= '0';
      wb_trig_mux_ch22_ctl_transm_src_int <= '0';
      wb_trig_mux_ch22_ctl_transm_out_sel_int <= "00000000";
      wb_trig_mux_ch22_ctl_transm_out_sel_swb <= '0';
      wb_trig_mux_ch22_ctl_transm_out_sel_swb_delay <= '0';
      wb_trig_mux_ch23_ctl_rcv_src_int <= '0';
      wb_trig_mux_ch23_ctl_rcv_in_sel_int <= "00000000";
      wb_trig_mux_ch23_ctl_rcv_in_sel_swb <= '0';
      wb_trig_mux_ch23_ctl_rcv_in_sel_swb_delay <= '0';
      wb_trig_mux_ch23_ctl_transm_src_int <= '0';
      wb_trig_mux_ch23_ctl_transm_out_sel_int <= "00000000";
      wb_trig_mux_ch23_ctl_transm_out_sel_swb <= '0';
      wb_trig_mux_ch23_ctl_transm_out_sel_swb_delay <= '0';
    elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
      ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
      ack_sreg(9) <= '0';
      if (ack_in_progress = '1') then
        if (ack_sreg(0) = '1') then
          ack_in_progress <= '0';
        else
          wb_trig_mux_ch0_ctl_rcv_in_sel_swb <= wb_trig_mux_ch0_ctl_rcv_in_sel_swb_delay;
          wb_trig_mux_ch0_ctl_rcv_in_sel_swb_delay <= '0';
          wb_trig_mux_ch0_ctl_transm_out_sel_swb <= wb_trig_mux_ch0_ctl_transm_out_sel_swb_delay;
          wb_trig_mux_ch0_ctl_transm_out_sel_swb_delay <= '0';
          wb_trig_mux_ch1_ctl_rcv_in_sel_swb <= wb_trig_mux_ch1_ctl_rcv_in_sel_swb_delay;
          wb_trig_mux_ch1_ctl_rcv_in_sel_swb_delay <= '0';
          wb_trig_mux_ch1_ctl_transm_out_sel_swb <= wb_trig_mux_ch1_ctl_transm_out_sel_swb_delay;
          wb_trig_mux_ch1_ctl_transm_out_sel_swb_delay <= '0';
          wb_trig_mux_ch2_ctl_rcv_in_sel_swb <= wb_trig_mux_ch2_ctl_rcv_in_sel_swb_delay;
          wb_trig_mux_ch2_ctl_rcv_in_sel_swb_delay <= '0';
          wb_trig_mux_ch2_ctl_transm_out_sel_swb <= wb_trig_mux_ch2_ctl_transm_out_sel_swb_delay;
          wb_trig_mux_ch2_ctl_transm_out_sel_swb_delay <= '0';
          wb_trig_mux_ch3_ctl_rcv_in_sel_swb <= wb_trig_mux_ch3_ctl_rcv_in_sel_swb_delay;
          wb_trig_mux_ch3_ctl_rcv_in_sel_swb_delay <= '0';
          wb_trig_mux_ch3_ctl_transm_out_sel_swb <= wb_trig_mux_ch3_ctl_transm_out_sel_swb_delay;
          wb_trig_mux_ch3_ctl_transm_out_sel_swb_delay <= '0';
          wb_trig_mux_ch4_ctl_rcv_in_sel_swb <= wb_trig_mux_ch4_ctl_rcv_in_sel_swb_delay;
          wb_trig_mux_ch4_ctl_rcv_in_sel_swb_delay <= '0';
          wb_trig_mux_ch4_ctl_transm_out_sel_swb <= wb_trig_mux_ch4_ctl_transm_out_sel_swb_delay;
          wb_trig_mux_ch4_ctl_transm_out_sel_swb_delay <= '0';
          wb_trig_mux_ch5_ctl_rcv_in_sel_swb <= wb_trig_mux_ch5_ctl_rcv_in_sel_swb_delay;
          wb_trig_mux_ch5_ctl_rcv_in_sel_swb_delay <= '0';
          wb_trig_mux_ch5_ctl_transm_out_sel_swb <= wb_trig_mux_ch5_ctl_transm_out_sel_swb_delay;
          wb_trig_mux_ch5_ctl_transm_out_sel_swb_delay <= '0';
          wb_trig_mux_ch6_ctl_rcv_in_sel_swb <= wb_trig_mux_ch6_ctl_rcv_in_sel_swb_delay;
          wb_trig_mux_ch6_ctl_rcv_in_sel_swb_delay <= '0';
          wb_trig_mux_ch6_ctl_transm_out_sel_swb <= wb_trig_mux_ch6_ctl_transm_out_sel_swb_delay;
          wb_trig_mux_ch6_ctl_transm_out_sel_swb_delay <= '0';
          wb_trig_mux_ch7_ctl_rcv_in_sel_swb <= wb_trig_mux_ch7_ctl_rcv_in_sel_swb_delay;
          wb_trig_mux_ch7_ctl_rcv_in_sel_swb_delay <= '0';
          wb_trig_mux_ch7_ctl_transm_out_sel_swb <= wb_trig_mux_ch7_ctl_transm_out_sel_swb_delay;
          wb_trig_mux_ch7_ctl_transm_out_sel_swb_delay <= '0';
          wb_trig_mux_ch8_ctl_rcv_in_sel_swb <= wb_trig_mux_ch8_ctl_rcv_in_sel_swb_delay;
          wb_trig_mux_ch8_ctl_rcv_in_sel_swb_delay <= '0';
          wb_trig_mux_ch8_ctl_transm_out_sel_swb <= wb_trig_mux_ch8_ctl_transm_out_sel_swb_delay;
          wb_trig_mux_ch8_ctl_transm_out_sel_swb_delay <= '0';
          wb_trig_mux_ch9_ctl_rcv_in_sel_swb <= wb_trig_mux_ch9_ctl_rcv_in_sel_swb_delay;
          wb_trig_mux_ch9_ctl_rcv_in_sel_swb_delay <= '0';
          wb_trig_mux_ch9_ctl_transm_out_sel_swb <= wb_trig_mux_ch9_ctl_transm_out_sel_swb_delay;
          wb_trig_mux_ch9_ctl_transm_out_sel_swb_delay <= '0';
          wb_trig_mux_ch10_ctl_rcv_in_sel_swb <= wb_trig_mux_ch10_ctl_rcv_in_sel_swb_delay;
          wb_trig_mux_ch10_ctl_rcv_in_sel_swb_delay <= '0';
          wb_trig_mux_ch10_ctl_transm_out_sel_swb <= wb_trig_mux_ch10_ctl_transm_out_sel_swb_delay;
          wb_trig_mux_ch10_ctl_transm_out_sel_swb_delay <= '0';
          wb_trig_mux_ch11_ctl_rcv_in_sel_swb <= wb_trig_mux_ch11_ctl_rcv_in_sel_swb_delay;
          wb_trig_mux_ch11_ctl_rcv_in_sel_swb_delay <= '0';
          wb_trig_mux_ch11_ctl_transm_out_sel_swb <= wb_trig_mux_ch11_ctl_transm_out_sel_swb_delay;
          wb_trig_mux_ch11_ctl_transm_out_sel_swb_delay <= '0';
          wb_trig_mux_ch12_ctl_rcv_in_sel_swb <= wb_trig_mux_ch12_ctl_rcv_in_sel_swb_delay;
          wb_trig_mux_ch12_ctl_rcv_in_sel_swb_delay <= '0';
          wb_trig_mux_ch12_ctl_transm_out_sel_swb <= wb_trig_mux_ch12_ctl_transm_out_sel_swb_delay;
          wb_trig_mux_ch12_ctl_transm_out_sel_swb_delay <= '0';
          wb_trig_mux_ch13_ctl_rcv_in_sel_swb <= wb_trig_mux_ch13_ctl_rcv_in_sel_swb_delay;
          wb_trig_mux_ch13_ctl_rcv_in_sel_swb_delay <= '0';
          wb_trig_mux_ch13_ctl_transm_out_sel_swb <= wb_trig_mux_ch13_ctl_transm_out_sel_swb_delay;
          wb_trig_mux_ch13_ctl_transm_out_sel_swb_delay <= '0';
          wb_trig_mux_ch14_ctl_rcv_in_sel_swb <= wb_trig_mux_ch14_ctl_rcv_in_sel_swb_delay;
          wb_trig_mux_ch14_ctl_rcv_in_sel_swb_delay <= '0';
          wb_trig_mux_ch14_ctl_transm_out_sel_swb <= wb_trig_mux_ch14_ctl_transm_out_sel_swb_delay;
          wb_trig_mux_ch14_ctl_transm_out_sel_swb_delay <= '0';
          wb_trig_mux_ch15_ctl_rcv_in_sel_swb <= wb_trig_mux_ch15_ctl_rcv_in_sel_swb_delay;
          wb_trig_mux_ch15_ctl_rcv_in_sel_swb_delay <= '0';
          wb_trig_mux_ch15_ctl_transm_out_sel_swb <= wb_trig_mux_ch15_ctl_transm_out_sel_swb_delay;
          wb_trig_mux_ch15_ctl_transm_out_sel_swb_delay <= '0';
          wb_trig_mux_ch16_ctl_rcv_in_sel_swb <= wb_trig_mux_ch16_ctl_rcv_in_sel_swb_delay;
          wb_trig_mux_ch16_ctl_rcv_in_sel_swb_delay <= '0';
          wb_trig_mux_ch16_ctl_transm_out_sel_swb <= wb_trig_mux_ch16_ctl_transm_out_sel_swb_delay;
          wb_trig_mux_ch16_ctl_transm_out_sel_swb_delay <= '0';
          wb_trig_mux_ch17_ctl_rcv_in_sel_swb <= wb_trig_mux_ch17_ctl_rcv_in_sel_swb_delay;
          wb_trig_mux_ch17_ctl_rcv_in_sel_swb_delay <= '0';
          wb_trig_mux_ch17_ctl_transm_out_sel_swb <= wb_trig_mux_ch17_ctl_transm_out_sel_swb_delay;
          wb_trig_mux_ch17_ctl_transm_out_sel_swb_delay <= '0';
          wb_trig_mux_ch18_ctl_rcv_in_sel_swb <= wb_trig_mux_ch18_ctl_rcv_in_sel_swb_delay;
          wb_trig_mux_ch18_ctl_rcv_in_sel_swb_delay <= '0';
          wb_trig_mux_ch18_ctl_transm_out_sel_swb <= wb_trig_mux_ch18_ctl_transm_out_sel_swb_delay;
          wb_trig_mux_ch18_ctl_transm_out_sel_swb_delay <= '0';
          wb_trig_mux_ch19_ctl_rcv_in_sel_swb <= wb_trig_mux_ch19_ctl_rcv_in_sel_swb_delay;
          wb_trig_mux_ch19_ctl_rcv_in_sel_swb_delay <= '0';
          wb_trig_mux_ch19_ctl_transm_out_sel_swb <= wb_trig_mux_ch19_ctl_transm_out_sel_swb_delay;
          wb_trig_mux_ch19_ctl_transm_out_sel_swb_delay <= '0';
          wb_trig_mux_ch20_ctl_rcv_in_sel_swb <= wb_trig_mux_ch20_ctl_rcv_in_sel_swb_delay;
          wb_trig_mux_ch20_ctl_rcv_in_sel_swb_delay <= '0';
          wb_trig_mux_ch20_ctl_transm_out_sel_swb <= wb_trig_mux_ch20_ctl_transm_out_sel_swb_delay;
          wb_trig_mux_ch20_ctl_transm_out_sel_swb_delay <= '0';
          wb_trig_mux_ch21_ctl_rcv_in_sel_swb <= wb_trig_mux_ch21_ctl_rcv_in_sel_swb_delay;
          wb_trig_mux_ch21_ctl_rcv_in_sel_swb_delay <= '0';
          wb_trig_mux_ch21_ctl_transm_out_sel_swb <= wb_trig_mux_ch21_ctl_transm_out_sel_swb_delay;
          wb_trig_mux_ch21_ctl_transm_out_sel_swb_delay <= '0';
          wb_trig_mux_ch22_ctl_rcv_in_sel_swb <= wb_trig_mux_ch22_ctl_rcv_in_sel_swb_delay;
          wb_trig_mux_ch22_ctl_rcv_in_sel_swb_delay <= '0';
          wb_trig_mux_ch22_ctl_transm_out_sel_swb <= wb_trig_mux_ch22_ctl_transm_out_sel_swb_delay;
          wb_trig_mux_ch22_ctl_transm_out_sel_swb_delay <= '0';
          wb_trig_mux_ch23_ctl_rcv_in_sel_swb <= wb_trig_mux_ch23_ctl_rcv_in_sel_swb_delay;
          wb_trig_mux_ch23_ctl_rcv_in_sel_swb_delay <= '0';
          wb_trig_mux_ch23_ctl_transm_out_sel_swb <= wb_trig_mux_ch23_ctl_transm_out_sel_swb_delay;
          wb_trig_mux_ch23_ctl_transm_out_sel_swb_delay <= '0';
        end if;
      else
        if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
          case rwaddr_reg(5 downto 0) is
          when "000000" => 
            if (wb_we_i = '1') then
              wb_trig_mux_ch0_ctl_rcv_src_int <= wrdata_reg(0);
              wb_trig_mux_ch0_ctl_rcv_in_sel_int <= wrdata_reg(15 downto 8);
              wb_trig_mux_ch0_ctl_rcv_in_sel_swb <= '1';
              wb_trig_mux_ch0_ctl_rcv_in_sel_swb_delay <= '1';
              wb_trig_mux_ch0_ctl_transm_src_int <= wrdata_reg(16);
              wb_trig_mux_ch0_ctl_transm_out_sel_int <= wrdata_reg(31 downto 24);
              wb_trig_mux_ch0_ctl_transm_out_sel_swb <= '1';
              wb_trig_mux_ch0_ctl_transm_out_sel_swb_delay <= '1';
            end if;
            rddata_reg(0) <= wb_trig_mux_ch0_ctl_rcv_src_int;
            rddata_reg(15 downto 8) <= wb_trig_mux_ch0_ctl_rcv_in_sel_int;
            rddata_reg(16) <= wb_trig_mux_ch0_ctl_transm_src_int;
            rddata_reg(31 downto 24) <= wb_trig_mux_ch0_ctl_transm_out_sel_int;
            rddata_reg(1) <= 'X';
            rddata_reg(2) <= 'X';
            rddata_reg(3) <= 'X';
            rddata_reg(4) <= 'X';
            rddata_reg(5) <= 'X';
            rddata_reg(6) <= 'X';
            rddata_reg(7) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            ack_sreg(3) <= '1';
            ack_in_progress <= '1';
          when "000001" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(31 downto 0) <= regs_i.ch0_dummy_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "000010" => 
            if (wb_we_i = '1') then
              wb_trig_mux_ch1_ctl_rcv_src_int <= wrdata_reg(0);
              wb_trig_mux_ch1_ctl_rcv_in_sel_int <= wrdata_reg(15 downto 8);
              wb_trig_mux_ch1_ctl_rcv_in_sel_swb <= '1';
              wb_trig_mux_ch1_ctl_rcv_in_sel_swb_delay <= '1';
              wb_trig_mux_ch1_ctl_transm_src_int <= wrdata_reg(16);
              wb_trig_mux_ch1_ctl_transm_out_sel_int <= wrdata_reg(31 downto 24);
              wb_trig_mux_ch1_ctl_transm_out_sel_swb <= '1';
              wb_trig_mux_ch1_ctl_transm_out_sel_swb_delay <= '1';
            end if;
            rddata_reg(0) <= wb_trig_mux_ch1_ctl_rcv_src_int;
            rddata_reg(15 downto 8) <= wb_trig_mux_ch1_ctl_rcv_in_sel_int;
            rddata_reg(16) <= wb_trig_mux_ch1_ctl_transm_src_int;
            rddata_reg(31 downto 24) <= wb_trig_mux_ch1_ctl_transm_out_sel_int;
            rddata_reg(1) <= 'X';
            rddata_reg(2) <= 'X';
            rddata_reg(3) <= 'X';
            rddata_reg(4) <= 'X';
            rddata_reg(5) <= 'X';
            rddata_reg(6) <= 'X';
            rddata_reg(7) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            ack_sreg(3) <= '1';
            ack_in_progress <= '1';
          when "000011" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(31 downto 0) <= regs_i.ch1_dummy_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "000100" => 
            if (wb_we_i = '1') then
              wb_trig_mux_ch2_ctl_rcv_src_int <= wrdata_reg(0);
              wb_trig_mux_ch2_ctl_rcv_in_sel_int <= wrdata_reg(15 downto 8);
              wb_trig_mux_ch2_ctl_rcv_in_sel_swb <= '1';
              wb_trig_mux_ch2_ctl_rcv_in_sel_swb_delay <= '1';
              wb_trig_mux_ch2_ctl_transm_src_int <= wrdata_reg(16);
              wb_trig_mux_ch2_ctl_transm_out_sel_int <= wrdata_reg(31 downto 24);
              wb_trig_mux_ch2_ctl_transm_out_sel_swb <= '1';
              wb_trig_mux_ch2_ctl_transm_out_sel_swb_delay <= '1';
            end if;
            rddata_reg(0) <= wb_trig_mux_ch2_ctl_rcv_src_int;
            rddata_reg(15 downto 8) <= wb_trig_mux_ch2_ctl_rcv_in_sel_int;
            rddata_reg(16) <= wb_trig_mux_ch2_ctl_transm_src_int;
            rddata_reg(31 downto 24) <= wb_trig_mux_ch2_ctl_transm_out_sel_int;
            rddata_reg(1) <= 'X';
            rddata_reg(2) <= 'X';
            rddata_reg(3) <= 'X';
            rddata_reg(4) <= 'X';
            rddata_reg(5) <= 'X';
            rddata_reg(6) <= 'X';
            rddata_reg(7) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            ack_sreg(3) <= '1';
            ack_in_progress <= '1';
          when "000101" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(31 downto 0) <= regs_i.ch2_dummy_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "000110" => 
            if (wb_we_i = '1') then
              wb_trig_mux_ch3_ctl_rcv_src_int <= wrdata_reg(0);
              wb_trig_mux_ch3_ctl_rcv_in_sel_int <= wrdata_reg(15 downto 8);
              wb_trig_mux_ch3_ctl_rcv_in_sel_swb <= '1';
              wb_trig_mux_ch3_ctl_rcv_in_sel_swb_delay <= '1';
              wb_trig_mux_ch3_ctl_transm_src_int <= wrdata_reg(16);
              wb_trig_mux_ch3_ctl_transm_out_sel_int <= wrdata_reg(31 downto 24);
              wb_trig_mux_ch3_ctl_transm_out_sel_swb <= '1';
              wb_trig_mux_ch3_ctl_transm_out_sel_swb_delay <= '1';
            end if;
            rddata_reg(0) <= wb_trig_mux_ch3_ctl_rcv_src_int;
            rddata_reg(15 downto 8) <= wb_trig_mux_ch3_ctl_rcv_in_sel_int;
            rddata_reg(16) <= wb_trig_mux_ch3_ctl_transm_src_int;
            rddata_reg(31 downto 24) <= wb_trig_mux_ch3_ctl_transm_out_sel_int;
            rddata_reg(1) <= 'X';
            rddata_reg(2) <= 'X';
            rddata_reg(3) <= 'X';
            rddata_reg(4) <= 'X';
            rddata_reg(5) <= 'X';
            rddata_reg(6) <= 'X';
            rddata_reg(7) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            ack_sreg(3) <= '1';
            ack_in_progress <= '1';
          when "000111" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(31 downto 0) <= regs_i.ch3_dummy_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "001000" => 
            if (wb_we_i = '1') then
              wb_trig_mux_ch4_ctl_rcv_src_int <= wrdata_reg(0);
              wb_trig_mux_ch4_ctl_rcv_in_sel_int <= wrdata_reg(15 downto 8);
              wb_trig_mux_ch4_ctl_rcv_in_sel_swb <= '1';
              wb_trig_mux_ch4_ctl_rcv_in_sel_swb_delay <= '1';
              wb_trig_mux_ch4_ctl_transm_src_int <= wrdata_reg(16);
              wb_trig_mux_ch4_ctl_transm_out_sel_int <= wrdata_reg(31 downto 24);
              wb_trig_mux_ch4_ctl_transm_out_sel_swb <= '1';
              wb_trig_mux_ch4_ctl_transm_out_sel_swb_delay <= '1';
            end if;
            rddata_reg(0) <= wb_trig_mux_ch4_ctl_rcv_src_int;
            rddata_reg(15 downto 8) <= wb_trig_mux_ch4_ctl_rcv_in_sel_int;
            rddata_reg(16) <= wb_trig_mux_ch4_ctl_transm_src_int;
            rddata_reg(31 downto 24) <= wb_trig_mux_ch4_ctl_transm_out_sel_int;
            rddata_reg(1) <= 'X';
            rddata_reg(2) <= 'X';
            rddata_reg(3) <= 'X';
            rddata_reg(4) <= 'X';
            rddata_reg(5) <= 'X';
            rddata_reg(6) <= 'X';
            rddata_reg(7) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            ack_sreg(3) <= '1';
            ack_in_progress <= '1';
          when "001001" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(31 downto 0) <= regs_i.ch4_dummy_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "001010" => 
            if (wb_we_i = '1') then
              wb_trig_mux_ch5_ctl_rcv_src_int <= wrdata_reg(0);
              wb_trig_mux_ch5_ctl_rcv_in_sel_int <= wrdata_reg(15 downto 8);
              wb_trig_mux_ch5_ctl_rcv_in_sel_swb <= '1';
              wb_trig_mux_ch5_ctl_rcv_in_sel_swb_delay <= '1';
              wb_trig_mux_ch5_ctl_transm_src_int <= wrdata_reg(16);
              wb_trig_mux_ch5_ctl_transm_out_sel_int <= wrdata_reg(31 downto 24);
              wb_trig_mux_ch5_ctl_transm_out_sel_swb <= '1';
              wb_trig_mux_ch5_ctl_transm_out_sel_swb_delay <= '1';
            end if;
            rddata_reg(0) <= wb_trig_mux_ch5_ctl_rcv_src_int;
            rddata_reg(15 downto 8) <= wb_trig_mux_ch5_ctl_rcv_in_sel_int;
            rddata_reg(16) <= wb_trig_mux_ch5_ctl_transm_src_int;
            rddata_reg(31 downto 24) <= wb_trig_mux_ch5_ctl_transm_out_sel_int;
            rddata_reg(1) <= 'X';
            rddata_reg(2) <= 'X';
            rddata_reg(3) <= 'X';
            rddata_reg(4) <= 'X';
            rddata_reg(5) <= 'X';
            rddata_reg(6) <= 'X';
            rddata_reg(7) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            ack_sreg(3) <= '1';
            ack_in_progress <= '1';
          when "001011" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(31 downto 0) <= regs_i.ch5_dummy_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "001100" => 
            if (wb_we_i = '1') then
              wb_trig_mux_ch6_ctl_rcv_src_int <= wrdata_reg(0);
              wb_trig_mux_ch6_ctl_rcv_in_sel_int <= wrdata_reg(15 downto 8);
              wb_trig_mux_ch6_ctl_rcv_in_sel_swb <= '1';
              wb_trig_mux_ch6_ctl_rcv_in_sel_swb_delay <= '1';
              wb_trig_mux_ch6_ctl_transm_src_int <= wrdata_reg(16);
              wb_trig_mux_ch6_ctl_transm_out_sel_int <= wrdata_reg(31 downto 24);
              wb_trig_mux_ch6_ctl_transm_out_sel_swb <= '1';
              wb_trig_mux_ch6_ctl_transm_out_sel_swb_delay <= '1';
            end if;
            rddata_reg(0) <= wb_trig_mux_ch6_ctl_rcv_src_int;
            rddata_reg(15 downto 8) <= wb_trig_mux_ch6_ctl_rcv_in_sel_int;
            rddata_reg(16) <= wb_trig_mux_ch6_ctl_transm_src_int;
            rddata_reg(31 downto 24) <= wb_trig_mux_ch6_ctl_transm_out_sel_int;
            rddata_reg(1) <= 'X';
            rddata_reg(2) <= 'X';
            rddata_reg(3) <= 'X';
            rddata_reg(4) <= 'X';
            rddata_reg(5) <= 'X';
            rddata_reg(6) <= 'X';
            rddata_reg(7) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            ack_sreg(3) <= '1';
            ack_in_progress <= '1';
          when "001101" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(31 downto 0) <= regs_i.ch6_dummy_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "001110" => 
            if (wb_we_i = '1') then
              wb_trig_mux_ch7_ctl_rcv_src_int <= wrdata_reg(0);
              wb_trig_mux_ch7_ctl_rcv_in_sel_int <= wrdata_reg(15 downto 8);
              wb_trig_mux_ch7_ctl_rcv_in_sel_swb <= '1';
              wb_trig_mux_ch7_ctl_rcv_in_sel_swb_delay <= '1';
              wb_trig_mux_ch7_ctl_transm_src_int <= wrdata_reg(16);
              wb_trig_mux_ch7_ctl_transm_out_sel_int <= wrdata_reg(31 downto 24);
              wb_trig_mux_ch7_ctl_transm_out_sel_swb <= '1';
              wb_trig_mux_ch7_ctl_transm_out_sel_swb_delay <= '1';
            end if;
            rddata_reg(0) <= wb_trig_mux_ch7_ctl_rcv_src_int;
            rddata_reg(15 downto 8) <= wb_trig_mux_ch7_ctl_rcv_in_sel_int;
            rddata_reg(16) <= wb_trig_mux_ch7_ctl_transm_src_int;
            rddata_reg(31 downto 24) <= wb_trig_mux_ch7_ctl_transm_out_sel_int;
            rddata_reg(1) <= 'X';
            rddata_reg(2) <= 'X';
            rddata_reg(3) <= 'X';
            rddata_reg(4) <= 'X';
            rddata_reg(5) <= 'X';
            rddata_reg(6) <= 'X';
            rddata_reg(7) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            ack_sreg(3) <= '1';
            ack_in_progress <= '1';
          when "001111" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(31 downto 0) <= regs_i.ch7_dummy_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "010000" => 
            if (wb_we_i = '1') then
              wb_trig_mux_ch8_ctl_rcv_src_int <= wrdata_reg(0);
              wb_trig_mux_ch8_ctl_rcv_in_sel_int <= wrdata_reg(15 downto 8);
              wb_trig_mux_ch8_ctl_rcv_in_sel_swb <= '1';
              wb_trig_mux_ch8_ctl_rcv_in_sel_swb_delay <= '1';
              wb_trig_mux_ch8_ctl_transm_src_int <= wrdata_reg(16);
              wb_trig_mux_ch8_ctl_transm_out_sel_int <= wrdata_reg(31 downto 24);
              wb_trig_mux_ch8_ctl_transm_out_sel_swb <= '1';
              wb_trig_mux_ch8_ctl_transm_out_sel_swb_delay <= '1';
            end if;
            rddata_reg(0) <= wb_trig_mux_ch8_ctl_rcv_src_int;
            rddata_reg(15 downto 8) <= wb_trig_mux_ch8_ctl_rcv_in_sel_int;
            rddata_reg(16) <= wb_trig_mux_ch8_ctl_transm_src_int;
            rddata_reg(31 downto 24) <= wb_trig_mux_ch8_ctl_transm_out_sel_int;
            rddata_reg(1) <= 'X';
            rddata_reg(2) <= 'X';
            rddata_reg(3) <= 'X';
            rddata_reg(4) <= 'X';
            rddata_reg(5) <= 'X';
            rddata_reg(6) <= 'X';
            rddata_reg(7) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            ack_sreg(3) <= '1';
            ack_in_progress <= '1';
          when "010001" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(31 downto 0) <= regs_i.ch8_dummy_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "010010" => 
            if (wb_we_i = '1') then
              wb_trig_mux_ch9_ctl_rcv_src_int <= wrdata_reg(0);
              wb_trig_mux_ch9_ctl_rcv_in_sel_int <= wrdata_reg(15 downto 8);
              wb_trig_mux_ch9_ctl_rcv_in_sel_swb <= '1';
              wb_trig_mux_ch9_ctl_rcv_in_sel_swb_delay <= '1';
              wb_trig_mux_ch9_ctl_transm_src_int <= wrdata_reg(16);
              wb_trig_mux_ch9_ctl_transm_out_sel_int <= wrdata_reg(31 downto 24);
              wb_trig_mux_ch9_ctl_transm_out_sel_swb <= '1';
              wb_trig_mux_ch9_ctl_transm_out_sel_swb_delay <= '1';
            end if;
            rddata_reg(0) <= wb_trig_mux_ch9_ctl_rcv_src_int;
            rddata_reg(15 downto 8) <= wb_trig_mux_ch9_ctl_rcv_in_sel_int;
            rddata_reg(16) <= wb_trig_mux_ch9_ctl_transm_src_int;
            rddata_reg(31 downto 24) <= wb_trig_mux_ch9_ctl_transm_out_sel_int;
            rddata_reg(1) <= 'X';
            rddata_reg(2) <= 'X';
            rddata_reg(3) <= 'X';
            rddata_reg(4) <= 'X';
            rddata_reg(5) <= 'X';
            rddata_reg(6) <= 'X';
            rddata_reg(7) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            ack_sreg(3) <= '1';
            ack_in_progress <= '1';
          when "010011" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(31 downto 0) <= regs_i.ch9_dummy_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "010100" => 
            if (wb_we_i = '1') then
              wb_trig_mux_ch10_ctl_rcv_src_int <= wrdata_reg(0);
              wb_trig_mux_ch10_ctl_rcv_in_sel_int <= wrdata_reg(15 downto 8);
              wb_trig_mux_ch10_ctl_rcv_in_sel_swb <= '1';
              wb_trig_mux_ch10_ctl_rcv_in_sel_swb_delay <= '1';
              wb_trig_mux_ch10_ctl_transm_src_int <= wrdata_reg(16);
              wb_trig_mux_ch10_ctl_transm_out_sel_int <= wrdata_reg(31 downto 24);
              wb_trig_mux_ch10_ctl_transm_out_sel_swb <= '1';
              wb_trig_mux_ch10_ctl_transm_out_sel_swb_delay <= '1';
            end if;
            rddata_reg(0) <= wb_trig_mux_ch10_ctl_rcv_src_int;
            rddata_reg(15 downto 8) <= wb_trig_mux_ch10_ctl_rcv_in_sel_int;
            rddata_reg(16) <= wb_trig_mux_ch10_ctl_transm_src_int;
            rddata_reg(31 downto 24) <= wb_trig_mux_ch10_ctl_transm_out_sel_int;
            rddata_reg(1) <= 'X';
            rddata_reg(2) <= 'X';
            rddata_reg(3) <= 'X';
            rddata_reg(4) <= 'X';
            rddata_reg(5) <= 'X';
            rddata_reg(6) <= 'X';
            rddata_reg(7) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            ack_sreg(3) <= '1';
            ack_in_progress <= '1';
          when "010101" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(31 downto 0) <= regs_i.ch10_dummy_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "010110" => 
            if (wb_we_i = '1') then
              wb_trig_mux_ch11_ctl_rcv_src_int <= wrdata_reg(0);
              wb_trig_mux_ch11_ctl_rcv_in_sel_int <= wrdata_reg(15 downto 8);
              wb_trig_mux_ch11_ctl_rcv_in_sel_swb <= '1';
              wb_trig_mux_ch11_ctl_rcv_in_sel_swb_delay <= '1';
              wb_trig_mux_ch11_ctl_transm_src_int <= wrdata_reg(16);
              wb_trig_mux_ch11_ctl_transm_out_sel_int <= wrdata_reg(31 downto 24);
              wb_trig_mux_ch11_ctl_transm_out_sel_swb <= '1';
              wb_trig_mux_ch11_ctl_transm_out_sel_swb_delay <= '1';
            end if;
            rddata_reg(0) <= wb_trig_mux_ch11_ctl_rcv_src_int;
            rddata_reg(15 downto 8) <= wb_trig_mux_ch11_ctl_rcv_in_sel_int;
            rddata_reg(16) <= wb_trig_mux_ch11_ctl_transm_src_int;
            rddata_reg(31 downto 24) <= wb_trig_mux_ch11_ctl_transm_out_sel_int;
            rddata_reg(1) <= 'X';
            rddata_reg(2) <= 'X';
            rddata_reg(3) <= 'X';
            rddata_reg(4) <= 'X';
            rddata_reg(5) <= 'X';
            rddata_reg(6) <= 'X';
            rddata_reg(7) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            ack_sreg(3) <= '1';
            ack_in_progress <= '1';
          when "010111" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(31 downto 0) <= regs_i.ch11_dummy_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "011000" => 
            if (wb_we_i = '1') then
              wb_trig_mux_ch12_ctl_rcv_src_int <= wrdata_reg(0);
              wb_trig_mux_ch12_ctl_rcv_in_sel_int <= wrdata_reg(15 downto 8);
              wb_trig_mux_ch12_ctl_rcv_in_sel_swb <= '1';
              wb_trig_mux_ch12_ctl_rcv_in_sel_swb_delay <= '1';
              wb_trig_mux_ch12_ctl_transm_src_int <= wrdata_reg(16);
              wb_trig_mux_ch12_ctl_transm_out_sel_int <= wrdata_reg(31 downto 24);
              wb_trig_mux_ch12_ctl_transm_out_sel_swb <= '1';
              wb_trig_mux_ch12_ctl_transm_out_sel_swb_delay <= '1';
            end if;
            rddata_reg(0) <= wb_trig_mux_ch12_ctl_rcv_src_int;
            rddata_reg(15 downto 8) <= wb_trig_mux_ch12_ctl_rcv_in_sel_int;
            rddata_reg(16) <= wb_trig_mux_ch12_ctl_transm_src_int;
            rddata_reg(31 downto 24) <= wb_trig_mux_ch12_ctl_transm_out_sel_int;
            rddata_reg(1) <= 'X';
            rddata_reg(2) <= 'X';
            rddata_reg(3) <= 'X';
            rddata_reg(4) <= 'X';
            rddata_reg(5) <= 'X';
            rddata_reg(6) <= 'X';
            rddata_reg(7) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            ack_sreg(3) <= '1';
            ack_in_progress <= '1';
          when "011001" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(31 downto 0) <= regs_i.ch12_dummy_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "011010" => 
            if (wb_we_i = '1') then
              wb_trig_mux_ch13_ctl_rcv_src_int <= wrdata_reg(0);
              wb_trig_mux_ch13_ctl_rcv_in_sel_int <= wrdata_reg(15 downto 8);
              wb_trig_mux_ch13_ctl_rcv_in_sel_swb <= '1';
              wb_trig_mux_ch13_ctl_rcv_in_sel_swb_delay <= '1';
              wb_trig_mux_ch13_ctl_transm_src_int <= wrdata_reg(16);
              wb_trig_mux_ch13_ctl_transm_out_sel_int <= wrdata_reg(31 downto 24);
              wb_trig_mux_ch13_ctl_transm_out_sel_swb <= '1';
              wb_trig_mux_ch13_ctl_transm_out_sel_swb_delay <= '1';
            end if;
            rddata_reg(0) <= wb_trig_mux_ch13_ctl_rcv_src_int;
            rddata_reg(15 downto 8) <= wb_trig_mux_ch13_ctl_rcv_in_sel_int;
            rddata_reg(16) <= wb_trig_mux_ch13_ctl_transm_src_int;
            rddata_reg(31 downto 24) <= wb_trig_mux_ch13_ctl_transm_out_sel_int;
            rddata_reg(1) <= 'X';
            rddata_reg(2) <= 'X';
            rddata_reg(3) <= 'X';
            rddata_reg(4) <= 'X';
            rddata_reg(5) <= 'X';
            rddata_reg(6) <= 'X';
            rddata_reg(7) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            ack_sreg(3) <= '1';
            ack_in_progress <= '1';
          when "011011" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(31 downto 0) <= regs_i.ch13_dummy_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "011100" => 
            if (wb_we_i = '1') then
              wb_trig_mux_ch14_ctl_rcv_src_int <= wrdata_reg(0);
              wb_trig_mux_ch14_ctl_rcv_in_sel_int <= wrdata_reg(15 downto 8);
              wb_trig_mux_ch14_ctl_rcv_in_sel_swb <= '1';
              wb_trig_mux_ch14_ctl_rcv_in_sel_swb_delay <= '1';
              wb_trig_mux_ch14_ctl_transm_src_int <= wrdata_reg(16);
              wb_trig_mux_ch14_ctl_transm_out_sel_int <= wrdata_reg(31 downto 24);
              wb_trig_mux_ch14_ctl_transm_out_sel_swb <= '1';
              wb_trig_mux_ch14_ctl_transm_out_sel_swb_delay <= '1';
            end if;
            rddata_reg(0) <= wb_trig_mux_ch14_ctl_rcv_src_int;
            rddata_reg(15 downto 8) <= wb_trig_mux_ch14_ctl_rcv_in_sel_int;
            rddata_reg(16) <= wb_trig_mux_ch14_ctl_transm_src_int;
            rddata_reg(31 downto 24) <= wb_trig_mux_ch14_ctl_transm_out_sel_int;
            rddata_reg(1) <= 'X';
            rddata_reg(2) <= 'X';
            rddata_reg(3) <= 'X';
            rddata_reg(4) <= 'X';
            rddata_reg(5) <= 'X';
            rddata_reg(6) <= 'X';
            rddata_reg(7) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            ack_sreg(3) <= '1';
            ack_in_progress <= '1';
          when "011101" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(31 downto 0) <= regs_i.ch14_dummy_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "011110" => 
            if (wb_we_i = '1') then
              wb_trig_mux_ch15_ctl_rcv_src_int <= wrdata_reg(0);
              wb_trig_mux_ch15_ctl_rcv_in_sel_int <= wrdata_reg(15 downto 8);
              wb_trig_mux_ch15_ctl_rcv_in_sel_swb <= '1';
              wb_trig_mux_ch15_ctl_rcv_in_sel_swb_delay <= '1';
              wb_trig_mux_ch15_ctl_transm_src_int <= wrdata_reg(16);
              wb_trig_mux_ch15_ctl_transm_out_sel_int <= wrdata_reg(31 downto 24);
              wb_trig_mux_ch15_ctl_transm_out_sel_swb <= '1';
              wb_trig_mux_ch15_ctl_transm_out_sel_swb_delay <= '1';
            end if;
            rddata_reg(0) <= wb_trig_mux_ch15_ctl_rcv_src_int;
            rddata_reg(15 downto 8) <= wb_trig_mux_ch15_ctl_rcv_in_sel_int;
            rddata_reg(16) <= wb_trig_mux_ch15_ctl_transm_src_int;
            rddata_reg(31 downto 24) <= wb_trig_mux_ch15_ctl_transm_out_sel_int;
            rddata_reg(1) <= 'X';
            rddata_reg(2) <= 'X';
            rddata_reg(3) <= 'X';
            rddata_reg(4) <= 'X';
            rddata_reg(5) <= 'X';
            rddata_reg(6) <= 'X';
            rddata_reg(7) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            ack_sreg(3) <= '1';
            ack_in_progress <= '1';
          when "011111" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(31 downto 0) <= regs_i.ch15_dummy_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "100000" => 
            if (wb_we_i = '1') then
              wb_trig_mux_ch16_ctl_rcv_src_int <= wrdata_reg(0);
              wb_trig_mux_ch16_ctl_rcv_in_sel_int <= wrdata_reg(15 downto 8);
              wb_trig_mux_ch16_ctl_rcv_in_sel_swb <= '1';
              wb_trig_mux_ch16_ctl_rcv_in_sel_swb_delay <= '1';
              wb_trig_mux_ch16_ctl_transm_src_int <= wrdata_reg(16);
              wb_trig_mux_ch16_ctl_transm_out_sel_int <= wrdata_reg(31 downto 24);
              wb_trig_mux_ch16_ctl_transm_out_sel_swb <= '1';
              wb_trig_mux_ch16_ctl_transm_out_sel_swb_delay <= '1';
            end if;
            rddata_reg(0) <= wb_trig_mux_ch16_ctl_rcv_src_int;
            rddata_reg(15 downto 8) <= wb_trig_mux_ch16_ctl_rcv_in_sel_int;
            rddata_reg(16) <= wb_trig_mux_ch16_ctl_transm_src_int;
            rddata_reg(31 downto 24) <= wb_trig_mux_ch16_ctl_transm_out_sel_int;
            rddata_reg(1) <= 'X';
            rddata_reg(2) <= 'X';
            rddata_reg(3) <= 'X';
            rddata_reg(4) <= 'X';
            rddata_reg(5) <= 'X';
            rddata_reg(6) <= 'X';
            rddata_reg(7) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            ack_sreg(3) <= '1';
            ack_in_progress <= '1';
          when "100001" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(31 downto 0) <= regs_i.ch16_dummy_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "100010" => 
            if (wb_we_i = '1') then
              wb_trig_mux_ch17_ctl_rcv_src_int <= wrdata_reg(0);
              wb_trig_mux_ch17_ctl_rcv_in_sel_int <= wrdata_reg(15 downto 8);
              wb_trig_mux_ch17_ctl_rcv_in_sel_swb <= '1';
              wb_trig_mux_ch17_ctl_rcv_in_sel_swb_delay <= '1';
              wb_trig_mux_ch17_ctl_transm_src_int <= wrdata_reg(16);
              wb_trig_mux_ch17_ctl_transm_out_sel_int <= wrdata_reg(31 downto 24);
              wb_trig_mux_ch17_ctl_transm_out_sel_swb <= '1';
              wb_trig_mux_ch17_ctl_transm_out_sel_swb_delay <= '1';
            end if;
            rddata_reg(0) <= wb_trig_mux_ch17_ctl_rcv_src_int;
            rddata_reg(15 downto 8) <= wb_trig_mux_ch17_ctl_rcv_in_sel_int;
            rddata_reg(16) <= wb_trig_mux_ch17_ctl_transm_src_int;
            rddata_reg(31 downto 24) <= wb_trig_mux_ch17_ctl_transm_out_sel_int;
            rddata_reg(1) <= 'X';
            rddata_reg(2) <= 'X';
            rddata_reg(3) <= 'X';
            rddata_reg(4) <= 'X';
            rddata_reg(5) <= 'X';
            rddata_reg(6) <= 'X';
            rddata_reg(7) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            ack_sreg(3) <= '1';
            ack_in_progress <= '1';
          when "100011" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(31 downto 0) <= regs_i.ch17_dummy_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "100100" => 
            if (wb_we_i = '1') then
              wb_trig_mux_ch18_ctl_rcv_src_int <= wrdata_reg(0);
              wb_trig_mux_ch18_ctl_rcv_in_sel_int <= wrdata_reg(15 downto 8);
              wb_trig_mux_ch18_ctl_rcv_in_sel_swb <= '1';
              wb_trig_mux_ch18_ctl_rcv_in_sel_swb_delay <= '1';
              wb_trig_mux_ch18_ctl_transm_src_int <= wrdata_reg(16);
              wb_trig_mux_ch18_ctl_transm_out_sel_int <= wrdata_reg(31 downto 24);
              wb_trig_mux_ch18_ctl_transm_out_sel_swb <= '1';
              wb_trig_mux_ch18_ctl_transm_out_sel_swb_delay <= '1';
            end if;
            rddata_reg(0) <= wb_trig_mux_ch18_ctl_rcv_src_int;
            rddata_reg(15 downto 8) <= wb_trig_mux_ch18_ctl_rcv_in_sel_int;
            rddata_reg(16) <= wb_trig_mux_ch18_ctl_transm_src_int;
            rddata_reg(31 downto 24) <= wb_trig_mux_ch18_ctl_transm_out_sel_int;
            rddata_reg(1) <= 'X';
            rddata_reg(2) <= 'X';
            rddata_reg(3) <= 'X';
            rddata_reg(4) <= 'X';
            rddata_reg(5) <= 'X';
            rddata_reg(6) <= 'X';
            rddata_reg(7) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            ack_sreg(3) <= '1';
            ack_in_progress <= '1';
          when "100101" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(31 downto 0) <= regs_i.ch18_dummy_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "100110" => 
            if (wb_we_i = '1') then
              wb_trig_mux_ch19_ctl_rcv_src_int <= wrdata_reg(0);
              wb_trig_mux_ch19_ctl_rcv_in_sel_int <= wrdata_reg(15 downto 8);
              wb_trig_mux_ch19_ctl_rcv_in_sel_swb <= '1';
              wb_trig_mux_ch19_ctl_rcv_in_sel_swb_delay <= '1';
              wb_trig_mux_ch19_ctl_transm_src_int <= wrdata_reg(16);
              wb_trig_mux_ch19_ctl_transm_out_sel_int <= wrdata_reg(31 downto 24);
              wb_trig_mux_ch19_ctl_transm_out_sel_swb <= '1';
              wb_trig_mux_ch19_ctl_transm_out_sel_swb_delay <= '1';
            end if;
            rddata_reg(0) <= wb_trig_mux_ch19_ctl_rcv_src_int;
            rddata_reg(15 downto 8) <= wb_trig_mux_ch19_ctl_rcv_in_sel_int;
            rddata_reg(16) <= wb_trig_mux_ch19_ctl_transm_src_int;
            rddata_reg(31 downto 24) <= wb_trig_mux_ch19_ctl_transm_out_sel_int;
            rddata_reg(1) <= 'X';
            rddata_reg(2) <= 'X';
            rddata_reg(3) <= 'X';
            rddata_reg(4) <= 'X';
            rddata_reg(5) <= 'X';
            rddata_reg(6) <= 'X';
            rddata_reg(7) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            ack_sreg(3) <= '1';
            ack_in_progress <= '1';
          when "100111" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(31 downto 0) <= regs_i.ch19_dummy_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "101000" => 
            if (wb_we_i = '1') then
              wb_trig_mux_ch20_ctl_rcv_src_int <= wrdata_reg(0);
              wb_trig_mux_ch20_ctl_rcv_in_sel_int <= wrdata_reg(15 downto 8);
              wb_trig_mux_ch20_ctl_rcv_in_sel_swb <= '1';
              wb_trig_mux_ch20_ctl_rcv_in_sel_swb_delay <= '1';
              wb_trig_mux_ch20_ctl_transm_src_int <= wrdata_reg(16);
              wb_trig_mux_ch20_ctl_transm_out_sel_int <= wrdata_reg(31 downto 24);
              wb_trig_mux_ch20_ctl_transm_out_sel_swb <= '1';
              wb_trig_mux_ch20_ctl_transm_out_sel_swb_delay <= '1';
            end if;
            rddata_reg(0) <= wb_trig_mux_ch20_ctl_rcv_src_int;
            rddata_reg(15 downto 8) <= wb_trig_mux_ch20_ctl_rcv_in_sel_int;
            rddata_reg(16) <= wb_trig_mux_ch20_ctl_transm_src_int;
            rddata_reg(31 downto 24) <= wb_trig_mux_ch20_ctl_transm_out_sel_int;
            rddata_reg(1) <= 'X';
            rddata_reg(2) <= 'X';
            rddata_reg(3) <= 'X';
            rddata_reg(4) <= 'X';
            rddata_reg(5) <= 'X';
            rddata_reg(6) <= 'X';
            rddata_reg(7) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            ack_sreg(3) <= '1';
            ack_in_progress <= '1';
          when "101001" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(31 downto 0) <= regs_i.ch20_dummy_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "101010" => 
            if (wb_we_i = '1') then
              wb_trig_mux_ch21_ctl_rcv_src_int <= wrdata_reg(0);
              wb_trig_mux_ch21_ctl_rcv_in_sel_int <= wrdata_reg(15 downto 8);
              wb_trig_mux_ch21_ctl_rcv_in_sel_swb <= '1';
              wb_trig_mux_ch21_ctl_rcv_in_sel_swb_delay <= '1';
              wb_trig_mux_ch21_ctl_transm_src_int <= wrdata_reg(16);
              wb_trig_mux_ch21_ctl_transm_out_sel_int <= wrdata_reg(31 downto 24);
              wb_trig_mux_ch21_ctl_transm_out_sel_swb <= '1';
              wb_trig_mux_ch21_ctl_transm_out_sel_swb_delay <= '1';
            end if;
            rddata_reg(0) <= wb_trig_mux_ch21_ctl_rcv_src_int;
            rddata_reg(15 downto 8) <= wb_trig_mux_ch21_ctl_rcv_in_sel_int;
            rddata_reg(16) <= wb_trig_mux_ch21_ctl_transm_src_int;
            rddata_reg(31 downto 24) <= wb_trig_mux_ch21_ctl_transm_out_sel_int;
            rddata_reg(1) <= 'X';
            rddata_reg(2) <= 'X';
            rddata_reg(3) <= 'X';
            rddata_reg(4) <= 'X';
            rddata_reg(5) <= 'X';
            rddata_reg(6) <= 'X';
            rddata_reg(7) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            ack_sreg(3) <= '1';
            ack_in_progress <= '1';
          when "101011" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(31 downto 0) <= regs_i.ch21_dummy_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "101100" => 
            if (wb_we_i = '1') then
              wb_trig_mux_ch22_ctl_rcv_src_int <= wrdata_reg(0);
              wb_trig_mux_ch22_ctl_rcv_in_sel_int <= wrdata_reg(15 downto 8);
              wb_trig_mux_ch22_ctl_rcv_in_sel_swb <= '1';
              wb_trig_mux_ch22_ctl_rcv_in_sel_swb_delay <= '1';
              wb_trig_mux_ch22_ctl_transm_src_int <= wrdata_reg(16);
              wb_trig_mux_ch22_ctl_transm_out_sel_int <= wrdata_reg(31 downto 24);
              wb_trig_mux_ch22_ctl_transm_out_sel_swb <= '1';
              wb_trig_mux_ch22_ctl_transm_out_sel_swb_delay <= '1';
            end if;
            rddata_reg(0) <= wb_trig_mux_ch22_ctl_rcv_src_int;
            rddata_reg(15 downto 8) <= wb_trig_mux_ch22_ctl_rcv_in_sel_int;
            rddata_reg(16) <= wb_trig_mux_ch22_ctl_transm_src_int;
            rddata_reg(31 downto 24) <= wb_trig_mux_ch22_ctl_transm_out_sel_int;
            rddata_reg(1) <= 'X';
            rddata_reg(2) <= 'X';
            rddata_reg(3) <= 'X';
            rddata_reg(4) <= 'X';
            rddata_reg(5) <= 'X';
            rddata_reg(6) <= 'X';
            rddata_reg(7) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            ack_sreg(3) <= '1';
            ack_in_progress <= '1';
          when "101101" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(31 downto 0) <= regs_i.ch22_dummy_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "101110" => 
            if (wb_we_i = '1') then
              wb_trig_mux_ch23_ctl_rcv_src_int <= wrdata_reg(0);
              wb_trig_mux_ch23_ctl_rcv_in_sel_int <= wrdata_reg(15 downto 8);
              wb_trig_mux_ch23_ctl_rcv_in_sel_swb <= '1';
              wb_trig_mux_ch23_ctl_rcv_in_sel_swb_delay <= '1';
              wb_trig_mux_ch23_ctl_transm_src_int <= wrdata_reg(16);
              wb_trig_mux_ch23_ctl_transm_out_sel_int <= wrdata_reg(31 downto 24);
              wb_trig_mux_ch23_ctl_transm_out_sel_swb <= '1';
              wb_trig_mux_ch23_ctl_transm_out_sel_swb_delay <= '1';
            end if;
            rddata_reg(0) <= wb_trig_mux_ch23_ctl_rcv_src_int;
            rddata_reg(15 downto 8) <= wb_trig_mux_ch23_ctl_rcv_in_sel_int;
            rddata_reg(16) <= wb_trig_mux_ch23_ctl_transm_src_int;
            rddata_reg(31 downto 24) <= wb_trig_mux_ch23_ctl_transm_out_sel_int;
            rddata_reg(1) <= 'X';
            rddata_reg(2) <= 'X';
            rddata_reg(3) <= 'X';
            rddata_reg(4) <= 'X';
            rddata_reg(5) <= 'X';
            rddata_reg(6) <= 'X';
            rddata_reg(7) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            ack_sreg(3) <= '1';
            ack_in_progress <= '1';
          when "101111" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(31 downto 0) <= regs_i.ch23_dummy_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when others =>
-- prevent the slave from hanging the bus on invalid address
            ack_in_progress <= '1';
            ack_sreg(0) <= '1';
          end case;
        end if;
      end if;
    end if;
  end process;
  
  
-- Drive the data output bus
  wb_dat_o <= rddata_reg;
-- Receiver Source
  regs_o.ch0_ctl_rcv_src_o <= wb_trig_mux_ch0_ctl_rcv_src_int;
-- Select Receiver Input
-- asynchronous std_logic_vector register : Select Receiver Input (type RW/RO, fs_clk_i <-> clk_sys_i)
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_trig_mux_ch0_ctl_rcv_in_sel_swb_s0 <= '0';
      wb_trig_mux_ch0_ctl_rcv_in_sel_swb_s1 <= '0';
      wb_trig_mux_ch0_ctl_rcv_in_sel_swb_s2 <= '0';
      regs_o.ch0_ctl_rcv_in_sel_o <= "00000000";
    elsif rising_edge(fs_clk_i) then
      wb_trig_mux_ch0_ctl_rcv_in_sel_swb_s0 <= wb_trig_mux_ch0_ctl_rcv_in_sel_swb;
      wb_trig_mux_ch0_ctl_rcv_in_sel_swb_s1 <= wb_trig_mux_ch0_ctl_rcv_in_sel_swb_s0;
      wb_trig_mux_ch0_ctl_rcv_in_sel_swb_s2 <= wb_trig_mux_ch0_ctl_rcv_in_sel_swb_s1;
      if ((wb_trig_mux_ch0_ctl_rcv_in_sel_swb_s2 = '0') and (wb_trig_mux_ch0_ctl_rcv_in_sel_swb_s1 = '1')) then
        regs_o.ch0_ctl_rcv_in_sel_o <= wb_trig_mux_ch0_ctl_rcv_in_sel_int;
      end if;
    end if;
  end process;
  
  
-- Transmitter Source
  regs_o.ch0_ctl_transm_src_o <= wb_trig_mux_ch0_ctl_transm_src_int;
-- Select Transmitter Output
-- asynchronous std_logic_vector register : Select Transmitter Output (type RW/RO, fs_clk_i <-> clk_sys_i)
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_trig_mux_ch0_ctl_transm_out_sel_swb_s0 <= '0';
      wb_trig_mux_ch0_ctl_transm_out_sel_swb_s1 <= '0';
      wb_trig_mux_ch0_ctl_transm_out_sel_swb_s2 <= '0';
      regs_o.ch0_ctl_transm_out_sel_o <= "00000000";
    elsif rising_edge(fs_clk_i) then
      wb_trig_mux_ch0_ctl_transm_out_sel_swb_s0 <= wb_trig_mux_ch0_ctl_transm_out_sel_swb;
      wb_trig_mux_ch0_ctl_transm_out_sel_swb_s1 <= wb_trig_mux_ch0_ctl_transm_out_sel_swb_s0;
      wb_trig_mux_ch0_ctl_transm_out_sel_swb_s2 <= wb_trig_mux_ch0_ctl_transm_out_sel_swb_s1;
      if ((wb_trig_mux_ch0_ctl_transm_out_sel_swb_s2 = '0') and (wb_trig_mux_ch0_ctl_transm_out_sel_swb_s1 = '1')) then
        regs_o.ch0_ctl_transm_out_sel_o <= wb_trig_mux_ch0_ctl_transm_out_sel_int;
      end if;
    end if;
  end process;
  
  
-- Dummy
-- Receiver Source
  regs_o.ch1_ctl_rcv_src_o <= wb_trig_mux_ch1_ctl_rcv_src_int;
-- Select Receiver Input
-- asynchronous std_logic_vector register : Select Receiver Input (type RW/RO, fs_clk_i <-> clk_sys_i)
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_trig_mux_ch1_ctl_rcv_in_sel_swb_s0 <= '0';
      wb_trig_mux_ch1_ctl_rcv_in_sel_swb_s1 <= '0';
      wb_trig_mux_ch1_ctl_rcv_in_sel_swb_s2 <= '0';
      regs_o.ch1_ctl_rcv_in_sel_o <= "00000000";
    elsif rising_edge(fs_clk_i) then
      wb_trig_mux_ch1_ctl_rcv_in_sel_swb_s0 <= wb_trig_mux_ch1_ctl_rcv_in_sel_swb;
      wb_trig_mux_ch1_ctl_rcv_in_sel_swb_s1 <= wb_trig_mux_ch1_ctl_rcv_in_sel_swb_s0;
      wb_trig_mux_ch1_ctl_rcv_in_sel_swb_s2 <= wb_trig_mux_ch1_ctl_rcv_in_sel_swb_s1;
      if ((wb_trig_mux_ch1_ctl_rcv_in_sel_swb_s2 = '0') and (wb_trig_mux_ch1_ctl_rcv_in_sel_swb_s1 = '1')) then
        regs_o.ch1_ctl_rcv_in_sel_o <= wb_trig_mux_ch1_ctl_rcv_in_sel_int;
      end if;
    end if;
  end process;
  
  
-- Transmitter Source
  regs_o.ch1_ctl_transm_src_o <= wb_trig_mux_ch1_ctl_transm_src_int;
-- Select Transmitter Output
-- asynchronous std_logic_vector register : Select Transmitter Output (type RW/RO, fs_clk_i <-> clk_sys_i)
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_trig_mux_ch1_ctl_transm_out_sel_swb_s0 <= '0';
      wb_trig_mux_ch1_ctl_transm_out_sel_swb_s1 <= '0';
      wb_trig_mux_ch1_ctl_transm_out_sel_swb_s2 <= '0';
      regs_o.ch1_ctl_transm_out_sel_o <= "00000000";
    elsif rising_edge(fs_clk_i) then
      wb_trig_mux_ch1_ctl_transm_out_sel_swb_s0 <= wb_trig_mux_ch1_ctl_transm_out_sel_swb;
      wb_trig_mux_ch1_ctl_transm_out_sel_swb_s1 <= wb_trig_mux_ch1_ctl_transm_out_sel_swb_s0;
      wb_trig_mux_ch1_ctl_transm_out_sel_swb_s2 <= wb_trig_mux_ch1_ctl_transm_out_sel_swb_s1;
      if ((wb_trig_mux_ch1_ctl_transm_out_sel_swb_s2 = '0') and (wb_trig_mux_ch1_ctl_transm_out_sel_swb_s1 = '1')) then
        regs_o.ch1_ctl_transm_out_sel_o <= wb_trig_mux_ch1_ctl_transm_out_sel_int;
      end if;
    end if;
  end process;
  
  
-- Dummy
-- Receiver Source
  regs_o.ch2_ctl_rcv_src_o <= wb_trig_mux_ch2_ctl_rcv_src_int;
-- Select Receiver Input
-- asynchronous std_logic_vector register : Select Receiver Input (type RW/RO, fs_clk_i <-> clk_sys_i)
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_trig_mux_ch2_ctl_rcv_in_sel_swb_s0 <= '0';
      wb_trig_mux_ch2_ctl_rcv_in_sel_swb_s1 <= '0';
      wb_trig_mux_ch2_ctl_rcv_in_sel_swb_s2 <= '0';
      regs_o.ch2_ctl_rcv_in_sel_o <= "00000000";
    elsif rising_edge(fs_clk_i) then
      wb_trig_mux_ch2_ctl_rcv_in_sel_swb_s0 <= wb_trig_mux_ch2_ctl_rcv_in_sel_swb;
      wb_trig_mux_ch2_ctl_rcv_in_sel_swb_s1 <= wb_trig_mux_ch2_ctl_rcv_in_sel_swb_s0;
      wb_trig_mux_ch2_ctl_rcv_in_sel_swb_s2 <= wb_trig_mux_ch2_ctl_rcv_in_sel_swb_s1;
      if ((wb_trig_mux_ch2_ctl_rcv_in_sel_swb_s2 = '0') and (wb_trig_mux_ch2_ctl_rcv_in_sel_swb_s1 = '1')) then
        regs_o.ch2_ctl_rcv_in_sel_o <= wb_trig_mux_ch2_ctl_rcv_in_sel_int;
      end if;
    end if;
  end process;
  
  
-- Transmitter Source
  regs_o.ch2_ctl_transm_src_o <= wb_trig_mux_ch2_ctl_transm_src_int;
-- Select Transmitter Output
-- asynchronous std_logic_vector register : Select Transmitter Output (type RW/RO, fs_clk_i <-> clk_sys_i)
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_trig_mux_ch2_ctl_transm_out_sel_swb_s0 <= '0';
      wb_trig_mux_ch2_ctl_transm_out_sel_swb_s1 <= '0';
      wb_trig_mux_ch2_ctl_transm_out_sel_swb_s2 <= '0';
      regs_o.ch2_ctl_transm_out_sel_o <= "00000000";
    elsif rising_edge(fs_clk_i) then
      wb_trig_mux_ch2_ctl_transm_out_sel_swb_s0 <= wb_trig_mux_ch2_ctl_transm_out_sel_swb;
      wb_trig_mux_ch2_ctl_transm_out_sel_swb_s1 <= wb_trig_mux_ch2_ctl_transm_out_sel_swb_s0;
      wb_trig_mux_ch2_ctl_transm_out_sel_swb_s2 <= wb_trig_mux_ch2_ctl_transm_out_sel_swb_s1;
      if ((wb_trig_mux_ch2_ctl_transm_out_sel_swb_s2 = '0') and (wb_trig_mux_ch2_ctl_transm_out_sel_swb_s1 = '1')) then
        regs_o.ch2_ctl_transm_out_sel_o <= wb_trig_mux_ch2_ctl_transm_out_sel_int;
      end if;
    end if;
  end process;
  
  
-- Dummy
-- Receiver Source
  regs_o.ch3_ctl_rcv_src_o <= wb_trig_mux_ch3_ctl_rcv_src_int;
-- Select Receiver Input
-- asynchronous std_logic_vector register : Select Receiver Input (type RW/RO, fs_clk_i <-> clk_sys_i)
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_trig_mux_ch3_ctl_rcv_in_sel_swb_s0 <= '0';
      wb_trig_mux_ch3_ctl_rcv_in_sel_swb_s1 <= '0';
      wb_trig_mux_ch3_ctl_rcv_in_sel_swb_s2 <= '0';
      regs_o.ch3_ctl_rcv_in_sel_o <= "00000000";
    elsif rising_edge(fs_clk_i) then
      wb_trig_mux_ch3_ctl_rcv_in_sel_swb_s0 <= wb_trig_mux_ch3_ctl_rcv_in_sel_swb;
      wb_trig_mux_ch3_ctl_rcv_in_sel_swb_s1 <= wb_trig_mux_ch3_ctl_rcv_in_sel_swb_s0;
      wb_trig_mux_ch3_ctl_rcv_in_sel_swb_s2 <= wb_trig_mux_ch3_ctl_rcv_in_sel_swb_s1;
      if ((wb_trig_mux_ch3_ctl_rcv_in_sel_swb_s2 = '0') and (wb_trig_mux_ch3_ctl_rcv_in_sel_swb_s1 = '1')) then
        regs_o.ch3_ctl_rcv_in_sel_o <= wb_trig_mux_ch3_ctl_rcv_in_sel_int;
      end if;
    end if;
  end process;
  
  
-- Transmitter Source
  regs_o.ch3_ctl_transm_src_o <= wb_trig_mux_ch3_ctl_transm_src_int;
-- Select Transmitter Output
-- asynchronous std_logic_vector register : Select Transmitter Output (type RW/RO, fs_clk_i <-> clk_sys_i)
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_trig_mux_ch3_ctl_transm_out_sel_swb_s0 <= '0';
      wb_trig_mux_ch3_ctl_transm_out_sel_swb_s1 <= '0';
      wb_trig_mux_ch3_ctl_transm_out_sel_swb_s2 <= '0';
      regs_o.ch3_ctl_transm_out_sel_o <= "00000000";
    elsif rising_edge(fs_clk_i) then
      wb_trig_mux_ch3_ctl_transm_out_sel_swb_s0 <= wb_trig_mux_ch3_ctl_transm_out_sel_swb;
      wb_trig_mux_ch3_ctl_transm_out_sel_swb_s1 <= wb_trig_mux_ch3_ctl_transm_out_sel_swb_s0;
      wb_trig_mux_ch3_ctl_transm_out_sel_swb_s2 <= wb_trig_mux_ch3_ctl_transm_out_sel_swb_s1;
      if ((wb_trig_mux_ch3_ctl_transm_out_sel_swb_s2 = '0') and (wb_trig_mux_ch3_ctl_transm_out_sel_swb_s1 = '1')) then
        regs_o.ch3_ctl_transm_out_sel_o <= wb_trig_mux_ch3_ctl_transm_out_sel_int;
      end if;
    end if;
  end process;
  
  
-- Dummy
-- Receiver Source
  regs_o.ch4_ctl_rcv_src_o <= wb_trig_mux_ch4_ctl_rcv_src_int;
-- Select Receiver Input
-- asynchronous std_logic_vector register : Select Receiver Input (type RW/RO, fs_clk_i <-> clk_sys_i)
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_trig_mux_ch4_ctl_rcv_in_sel_swb_s0 <= '0';
      wb_trig_mux_ch4_ctl_rcv_in_sel_swb_s1 <= '0';
      wb_trig_mux_ch4_ctl_rcv_in_sel_swb_s2 <= '0';
      regs_o.ch4_ctl_rcv_in_sel_o <= "00000000";
    elsif rising_edge(fs_clk_i) then
      wb_trig_mux_ch4_ctl_rcv_in_sel_swb_s0 <= wb_trig_mux_ch4_ctl_rcv_in_sel_swb;
      wb_trig_mux_ch4_ctl_rcv_in_sel_swb_s1 <= wb_trig_mux_ch4_ctl_rcv_in_sel_swb_s0;
      wb_trig_mux_ch4_ctl_rcv_in_sel_swb_s2 <= wb_trig_mux_ch4_ctl_rcv_in_sel_swb_s1;
      if ((wb_trig_mux_ch4_ctl_rcv_in_sel_swb_s2 = '0') and (wb_trig_mux_ch4_ctl_rcv_in_sel_swb_s1 = '1')) then
        regs_o.ch4_ctl_rcv_in_sel_o <= wb_trig_mux_ch4_ctl_rcv_in_sel_int;
      end if;
    end if;
  end process;
  
  
-- Transmitter Source
  regs_o.ch4_ctl_transm_src_o <= wb_trig_mux_ch4_ctl_transm_src_int;
-- Select Transmitter Output
-- asynchronous std_logic_vector register : Select Transmitter Output (type RW/RO, fs_clk_i <-> clk_sys_i)
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_trig_mux_ch4_ctl_transm_out_sel_swb_s0 <= '0';
      wb_trig_mux_ch4_ctl_transm_out_sel_swb_s1 <= '0';
      wb_trig_mux_ch4_ctl_transm_out_sel_swb_s2 <= '0';
      regs_o.ch4_ctl_transm_out_sel_o <= "00000000";
    elsif rising_edge(fs_clk_i) then
      wb_trig_mux_ch4_ctl_transm_out_sel_swb_s0 <= wb_trig_mux_ch4_ctl_transm_out_sel_swb;
      wb_trig_mux_ch4_ctl_transm_out_sel_swb_s1 <= wb_trig_mux_ch4_ctl_transm_out_sel_swb_s0;
      wb_trig_mux_ch4_ctl_transm_out_sel_swb_s2 <= wb_trig_mux_ch4_ctl_transm_out_sel_swb_s1;
      if ((wb_trig_mux_ch4_ctl_transm_out_sel_swb_s2 = '0') and (wb_trig_mux_ch4_ctl_transm_out_sel_swb_s1 = '1')) then
        regs_o.ch4_ctl_transm_out_sel_o <= wb_trig_mux_ch4_ctl_transm_out_sel_int;
      end if;
    end if;
  end process;
  
  
-- Dummy
-- Receiver Source
  regs_o.ch5_ctl_rcv_src_o <= wb_trig_mux_ch5_ctl_rcv_src_int;
-- Select Receiver Input
-- asynchronous std_logic_vector register : Select Receiver Input (type RW/RO, fs_clk_i <-> clk_sys_i)
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_trig_mux_ch5_ctl_rcv_in_sel_swb_s0 <= '0';
      wb_trig_mux_ch5_ctl_rcv_in_sel_swb_s1 <= '0';
      wb_trig_mux_ch5_ctl_rcv_in_sel_swb_s2 <= '0';
      regs_o.ch5_ctl_rcv_in_sel_o <= "00000000";
    elsif rising_edge(fs_clk_i) then
      wb_trig_mux_ch5_ctl_rcv_in_sel_swb_s0 <= wb_trig_mux_ch5_ctl_rcv_in_sel_swb;
      wb_trig_mux_ch5_ctl_rcv_in_sel_swb_s1 <= wb_trig_mux_ch5_ctl_rcv_in_sel_swb_s0;
      wb_trig_mux_ch5_ctl_rcv_in_sel_swb_s2 <= wb_trig_mux_ch5_ctl_rcv_in_sel_swb_s1;
      if ((wb_trig_mux_ch5_ctl_rcv_in_sel_swb_s2 = '0') and (wb_trig_mux_ch5_ctl_rcv_in_sel_swb_s1 = '1')) then
        regs_o.ch5_ctl_rcv_in_sel_o <= wb_trig_mux_ch5_ctl_rcv_in_sel_int;
      end if;
    end if;
  end process;
  
  
-- Transmitter Source
  regs_o.ch5_ctl_transm_src_o <= wb_trig_mux_ch5_ctl_transm_src_int;
-- Select Transmitter Output
-- asynchronous std_logic_vector register : Select Transmitter Output (type RW/RO, fs_clk_i <-> clk_sys_i)
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_trig_mux_ch5_ctl_transm_out_sel_swb_s0 <= '0';
      wb_trig_mux_ch5_ctl_transm_out_sel_swb_s1 <= '0';
      wb_trig_mux_ch5_ctl_transm_out_sel_swb_s2 <= '0';
      regs_o.ch5_ctl_transm_out_sel_o <= "00000000";
    elsif rising_edge(fs_clk_i) then
      wb_trig_mux_ch5_ctl_transm_out_sel_swb_s0 <= wb_trig_mux_ch5_ctl_transm_out_sel_swb;
      wb_trig_mux_ch5_ctl_transm_out_sel_swb_s1 <= wb_trig_mux_ch5_ctl_transm_out_sel_swb_s0;
      wb_trig_mux_ch5_ctl_transm_out_sel_swb_s2 <= wb_trig_mux_ch5_ctl_transm_out_sel_swb_s1;
      if ((wb_trig_mux_ch5_ctl_transm_out_sel_swb_s2 = '0') and (wb_trig_mux_ch5_ctl_transm_out_sel_swb_s1 = '1')) then
        regs_o.ch5_ctl_transm_out_sel_o <= wb_trig_mux_ch5_ctl_transm_out_sel_int;
      end if;
    end if;
  end process;
  
  
-- Dummy
-- Receiver Source
  regs_o.ch6_ctl_rcv_src_o <= wb_trig_mux_ch6_ctl_rcv_src_int;
-- Select Receiver Input
-- asynchronous std_logic_vector register : Select Receiver Input (type RW/RO, fs_clk_i <-> clk_sys_i)
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_trig_mux_ch6_ctl_rcv_in_sel_swb_s0 <= '0';
      wb_trig_mux_ch6_ctl_rcv_in_sel_swb_s1 <= '0';
      wb_trig_mux_ch6_ctl_rcv_in_sel_swb_s2 <= '0';
      regs_o.ch6_ctl_rcv_in_sel_o <= "00000000";
    elsif rising_edge(fs_clk_i) then
      wb_trig_mux_ch6_ctl_rcv_in_sel_swb_s0 <= wb_trig_mux_ch6_ctl_rcv_in_sel_swb;
      wb_trig_mux_ch6_ctl_rcv_in_sel_swb_s1 <= wb_trig_mux_ch6_ctl_rcv_in_sel_swb_s0;
      wb_trig_mux_ch6_ctl_rcv_in_sel_swb_s2 <= wb_trig_mux_ch6_ctl_rcv_in_sel_swb_s1;
      if ((wb_trig_mux_ch6_ctl_rcv_in_sel_swb_s2 = '0') and (wb_trig_mux_ch6_ctl_rcv_in_sel_swb_s1 = '1')) then
        regs_o.ch6_ctl_rcv_in_sel_o <= wb_trig_mux_ch6_ctl_rcv_in_sel_int;
      end if;
    end if;
  end process;
  
  
-- Transmitter Source
  regs_o.ch6_ctl_transm_src_o <= wb_trig_mux_ch6_ctl_transm_src_int;
-- Select Transmitter Output
-- asynchronous std_logic_vector register : Select Transmitter Output (type RW/RO, fs_clk_i <-> clk_sys_i)
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_trig_mux_ch6_ctl_transm_out_sel_swb_s0 <= '0';
      wb_trig_mux_ch6_ctl_transm_out_sel_swb_s1 <= '0';
      wb_trig_mux_ch6_ctl_transm_out_sel_swb_s2 <= '0';
      regs_o.ch6_ctl_transm_out_sel_o <= "00000000";
    elsif rising_edge(fs_clk_i) then
      wb_trig_mux_ch6_ctl_transm_out_sel_swb_s0 <= wb_trig_mux_ch6_ctl_transm_out_sel_swb;
      wb_trig_mux_ch6_ctl_transm_out_sel_swb_s1 <= wb_trig_mux_ch6_ctl_transm_out_sel_swb_s0;
      wb_trig_mux_ch6_ctl_transm_out_sel_swb_s2 <= wb_trig_mux_ch6_ctl_transm_out_sel_swb_s1;
      if ((wb_trig_mux_ch6_ctl_transm_out_sel_swb_s2 = '0') and (wb_trig_mux_ch6_ctl_transm_out_sel_swb_s1 = '1')) then
        regs_o.ch6_ctl_transm_out_sel_o <= wb_trig_mux_ch6_ctl_transm_out_sel_int;
      end if;
    end if;
  end process;
  
  
-- Dummy
-- Receiver Source
  regs_o.ch7_ctl_rcv_src_o <= wb_trig_mux_ch7_ctl_rcv_src_int;
-- Select Receiver Input
-- asynchronous std_logic_vector register : Select Receiver Input (type RW/RO, fs_clk_i <-> clk_sys_i)
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_trig_mux_ch7_ctl_rcv_in_sel_swb_s0 <= '0';
      wb_trig_mux_ch7_ctl_rcv_in_sel_swb_s1 <= '0';
      wb_trig_mux_ch7_ctl_rcv_in_sel_swb_s2 <= '0';
      regs_o.ch7_ctl_rcv_in_sel_o <= "00000000";
    elsif rising_edge(fs_clk_i) then
      wb_trig_mux_ch7_ctl_rcv_in_sel_swb_s0 <= wb_trig_mux_ch7_ctl_rcv_in_sel_swb;
      wb_trig_mux_ch7_ctl_rcv_in_sel_swb_s1 <= wb_trig_mux_ch7_ctl_rcv_in_sel_swb_s0;
      wb_trig_mux_ch7_ctl_rcv_in_sel_swb_s2 <= wb_trig_mux_ch7_ctl_rcv_in_sel_swb_s1;
      if ((wb_trig_mux_ch7_ctl_rcv_in_sel_swb_s2 = '0') and (wb_trig_mux_ch7_ctl_rcv_in_sel_swb_s1 = '1')) then
        regs_o.ch7_ctl_rcv_in_sel_o <= wb_trig_mux_ch7_ctl_rcv_in_sel_int;
      end if;
    end if;
  end process;
  
  
-- Transmitter Source
  regs_o.ch7_ctl_transm_src_o <= wb_trig_mux_ch7_ctl_transm_src_int;
-- Select Transmitter Output
-- asynchronous std_logic_vector register : Select Transmitter Output (type RW/RO, fs_clk_i <-> clk_sys_i)
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_trig_mux_ch7_ctl_transm_out_sel_swb_s0 <= '0';
      wb_trig_mux_ch7_ctl_transm_out_sel_swb_s1 <= '0';
      wb_trig_mux_ch7_ctl_transm_out_sel_swb_s2 <= '0';
      regs_o.ch7_ctl_transm_out_sel_o <= "00000000";
    elsif rising_edge(fs_clk_i) then
      wb_trig_mux_ch7_ctl_transm_out_sel_swb_s0 <= wb_trig_mux_ch7_ctl_transm_out_sel_swb;
      wb_trig_mux_ch7_ctl_transm_out_sel_swb_s1 <= wb_trig_mux_ch7_ctl_transm_out_sel_swb_s0;
      wb_trig_mux_ch7_ctl_transm_out_sel_swb_s2 <= wb_trig_mux_ch7_ctl_transm_out_sel_swb_s1;
      if ((wb_trig_mux_ch7_ctl_transm_out_sel_swb_s2 = '0') and (wb_trig_mux_ch7_ctl_transm_out_sel_swb_s1 = '1')) then
        regs_o.ch7_ctl_transm_out_sel_o <= wb_trig_mux_ch7_ctl_transm_out_sel_int;
      end if;
    end if;
  end process;
  
  
-- Dummy
-- Receiver Source
  regs_o.ch8_ctl_rcv_src_o <= wb_trig_mux_ch8_ctl_rcv_src_int;
-- Select Receiver Input
-- asynchronous std_logic_vector register : Select Receiver Input (type RW/RO, fs_clk_i <-> clk_sys_i)
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_trig_mux_ch8_ctl_rcv_in_sel_swb_s0 <= '0';
      wb_trig_mux_ch8_ctl_rcv_in_sel_swb_s1 <= '0';
      wb_trig_mux_ch8_ctl_rcv_in_sel_swb_s2 <= '0';
      regs_o.ch8_ctl_rcv_in_sel_o <= "00000000";
    elsif rising_edge(fs_clk_i) then
      wb_trig_mux_ch8_ctl_rcv_in_sel_swb_s0 <= wb_trig_mux_ch8_ctl_rcv_in_sel_swb;
      wb_trig_mux_ch8_ctl_rcv_in_sel_swb_s1 <= wb_trig_mux_ch8_ctl_rcv_in_sel_swb_s0;
      wb_trig_mux_ch8_ctl_rcv_in_sel_swb_s2 <= wb_trig_mux_ch8_ctl_rcv_in_sel_swb_s1;
      if ((wb_trig_mux_ch8_ctl_rcv_in_sel_swb_s2 = '0') and (wb_trig_mux_ch8_ctl_rcv_in_sel_swb_s1 = '1')) then
        regs_o.ch8_ctl_rcv_in_sel_o <= wb_trig_mux_ch8_ctl_rcv_in_sel_int;
      end if;
    end if;
  end process;
  
  
-- Transmitter Source
  regs_o.ch8_ctl_transm_src_o <= wb_trig_mux_ch8_ctl_transm_src_int;
-- Select Transmitter Output
-- asynchronous std_logic_vector register : Select Transmitter Output (type RW/RO, fs_clk_i <-> clk_sys_i)
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_trig_mux_ch8_ctl_transm_out_sel_swb_s0 <= '0';
      wb_trig_mux_ch8_ctl_transm_out_sel_swb_s1 <= '0';
      wb_trig_mux_ch8_ctl_transm_out_sel_swb_s2 <= '0';
      regs_o.ch8_ctl_transm_out_sel_o <= "00000000";
    elsif rising_edge(fs_clk_i) then
      wb_trig_mux_ch8_ctl_transm_out_sel_swb_s0 <= wb_trig_mux_ch8_ctl_transm_out_sel_swb;
      wb_trig_mux_ch8_ctl_transm_out_sel_swb_s1 <= wb_trig_mux_ch8_ctl_transm_out_sel_swb_s0;
      wb_trig_mux_ch8_ctl_transm_out_sel_swb_s2 <= wb_trig_mux_ch8_ctl_transm_out_sel_swb_s1;
      if ((wb_trig_mux_ch8_ctl_transm_out_sel_swb_s2 = '0') and (wb_trig_mux_ch8_ctl_transm_out_sel_swb_s1 = '1')) then
        regs_o.ch8_ctl_transm_out_sel_o <= wb_trig_mux_ch8_ctl_transm_out_sel_int;
      end if;
    end if;
  end process;
  
  
-- Dummy
-- Receiver Source
  regs_o.ch9_ctl_rcv_src_o <= wb_trig_mux_ch9_ctl_rcv_src_int;
-- Select Receiver Input
-- asynchronous std_logic_vector register : Select Receiver Input (type RW/RO, fs_clk_i <-> clk_sys_i)
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_trig_mux_ch9_ctl_rcv_in_sel_swb_s0 <= '0';
      wb_trig_mux_ch9_ctl_rcv_in_sel_swb_s1 <= '0';
      wb_trig_mux_ch9_ctl_rcv_in_sel_swb_s2 <= '0';
      regs_o.ch9_ctl_rcv_in_sel_o <= "00000000";
    elsif rising_edge(fs_clk_i) then
      wb_trig_mux_ch9_ctl_rcv_in_sel_swb_s0 <= wb_trig_mux_ch9_ctl_rcv_in_sel_swb;
      wb_trig_mux_ch9_ctl_rcv_in_sel_swb_s1 <= wb_trig_mux_ch9_ctl_rcv_in_sel_swb_s0;
      wb_trig_mux_ch9_ctl_rcv_in_sel_swb_s2 <= wb_trig_mux_ch9_ctl_rcv_in_sel_swb_s1;
      if ((wb_trig_mux_ch9_ctl_rcv_in_sel_swb_s2 = '0') and (wb_trig_mux_ch9_ctl_rcv_in_sel_swb_s1 = '1')) then
        regs_o.ch9_ctl_rcv_in_sel_o <= wb_trig_mux_ch9_ctl_rcv_in_sel_int;
      end if;
    end if;
  end process;
  
  
-- Transmitter Source
  regs_o.ch9_ctl_transm_src_o <= wb_trig_mux_ch9_ctl_transm_src_int;
-- Select Transmitter Output
-- asynchronous std_logic_vector register : Select Transmitter Output (type RW/RO, fs_clk_i <-> clk_sys_i)
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_trig_mux_ch9_ctl_transm_out_sel_swb_s0 <= '0';
      wb_trig_mux_ch9_ctl_transm_out_sel_swb_s1 <= '0';
      wb_trig_mux_ch9_ctl_transm_out_sel_swb_s2 <= '0';
      regs_o.ch9_ctl_transm_out_sel_o <= "00000000";
    elsif rising_edge(fs_clk_i) then
      wb_trig_mux_ch9_ctl_transm_out_sel_swb_s0 <= wb_trig_mux_ch9_ctl_transm_out_sel_swb;
      wb_trig_mux_ch9_ctl_transm_out_sel_swb_s1 <= wb_trig_mux_ch9_ctl_transm_out_sel_swb_s0;
      wb_trig_mux_ch9_ctl_transm_out_sel_swb_s2 <= wb_trig_mux_ch9_ctl_transm_out_sel_swb_s1;
      if ((wb_trig_mux_ch9_ctl_transm_out_sel_swb_s2 = '0') and (wb_trig_mux_ch9_ctl_transm_out_sel_swb_s1 = '1')) then
        regs_o.ch9_ctl_transm_out_sel_o <= wb_trig_mux_ch9_ctl_transm_out_sel_int;
      end if;
    end if;
  end process;
  
  
-- Dummy
-- Receiver Source
  regs_o.ch10_ctl_rcv_src_o <= wb_trig_mux_ch10_ctl_rcv_src_int;
-- Select Receiver Input
-- asynchronous std_logic_vector register : Select Receiver Input (type RW/RO, fs_clk_i <-> clk_sys_i)
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_trig_mux_ch10_ctl_rcv_in_sel_swb_s0 <= '0';
      wb_trig_mux_ch10_ctl_rcv_in_sel_swb_s1 <= '0';
      wb_trig_mux_ch10_ctl_rcv_in_sel_swb_s2 <= '0';
      regs_o.ch10_ctl_rcv_in_sel_o <= "00000000";
    elsif rising_edge(fs_clk_i) then
      wb_trig_mux_ch10_ctl_rcv_in_sel_swb_s0 <= wb_trig_mux_ch10_ctl_rcv_in_sel_swb;
      wb_trig_mux_ch10_ctl_rcv_in_sel_swb_s1 <= wb_trig_mux_ch10_ctl_rcv_in_sel_swb_s0;
      wb_trig_mux_ch10_ctl_rcv_in_sel_swb_s2 <= wb_trig_mux_ch10_ctl_rcv_in_sel_swb_s1;
      if ((wb_trig_mux_ch10_ctl_rcv_in_sel_swb_s2 = '0') and (wb_trig_mux_ch10_ctl_rcv_in_sel_swb_s1 = '1')) then
        regs_o.ch10_ctl_rcv_in_sel_o <= wb_trig_mux_ch10_ctl_rcv_in_sel_int;
      end if;
    end if;
  end process;
  
  
-- Transmitter Source
  regs_o.ch10_ctl_transm_src_o <= wb_trig_mux_ch10_ctl_transm_src_int;
-- Select Transmitter Output
-- asynchronous std_logic_vector register : Select Transmitter Output (type RW/RO, fs_clk_i <-> clk_sys_i)
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_trig_mux_ch10_ctl_transm_out_sel_swb_s0 <= '0';
      wb_trig_mux_ch10_ctl_transm_out_sel_swb_s1 <= '0';
      wb_trig_mux_ch10_ctl_transm_out_sel_swb_s2 <= '0';
      regs_o.ch10_ctl_transm_out_sel_o <= "00000000";
    elsif rising_edge(fs_clk_i) then
      wb_trig_mux_ch10_ctl_transm_out_sel_swb_s0 <= wb_trig_mux_ch10_ctl_transm_out_sel_swb;
      wb_trig_mux_ch10_ctl_transm_out_sel_swb_s1 <= wb_trig_mux_ch10_ctl_transm_out_sel_swb_s0;
      wb_trig_mux_ch10_ctl_transm_out_sel_swb_s2 <= wb_trig_mux_ch10_ctl_transm_out_sel_swb_s1;
      if ((wb_trig_mux_ch10_ctl_transm_out_sel_swb_s2 = '0') and (wb_trig_mux_ch10_ctl_transm_out_sel_swb_s1 = '1')) then
        regs_o.ch10_ctl_transm_out_sel_o <= wb_trig_mux_ch10_ctl_transm_out_sel_int;
      end if;
    end if;
  end process;
  
  
-- Dummy
-- Receiver Source
  regs_o.ch11_ctl_rcv_src_o <= wb_trig_mux_ch11_ctl_rcv_src_int;
-- Select Receiver Input
-- asynchronous std_logic_vector register : Select Receiver Input (type RW/RO, fs_clk_i <-> clk_sys_i)
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_trig_mux_ch11_ctl_rcv_in_sel_swb_s0 <= '0';
      wb_trig_mux_ch11_ctl_rcv_in_sel_swb_s1 <= '0';
      wb_trig_mux_ch11_ctl_rcv_in_sel_swb_s2 <= '0';
      regs_o.ch11_ctl_rcv_in_sel_o <= "00000000";
    elsif rising_edge(fs_clk_i) then
      wb_trig_mux_ch11_ctl_rcv_in_sel_swb_s0 <= wb_trig_mux_ch11_ctl_rcv_in_sel_swb;
      wb_trig_mux_ch11_ctl_rcv_in_sel_swb_s1 <= wb_trig_mux_ch11_ctl_rcv_in_sel_swb_s0;
      wb_trig_mux_ch11_ctl_rcv_in_sel_swb_s2 <= wb_trig_mux_ch11_ctl_rcv_in_sel_swb_s1;
      if ((wb_trig_mux_ch11_ctl_rcv_in_sel_swb_s2 = '0') and (wb_trig_mux_ch11_ctl_rcv_in_sel_swb_s1 = '1')) then
        regs_o.ch11_ctl_rcv_in_sel_o <= wb_trig_mux_ch11_ctl_rcv_in_sel_int;
      end if;
    end if;
  end process;
  
  
-- Transmitter Source
  regs_o.ch11_ctl_transm_src_o <= wb_trig_mux_ch11_ctl_transm_src_int;
-- Select Transmitter Output
-- asynchronous std_logic_vector register : Select Transmitter Output (type RW/RO, fs_clk_i <-> clk_sys_i)
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_trig_mux_ch11_ctl_transm_out_sel_swb_s0 <= '0';
      wb_trig_mux_ch11_ctl_transm_out_sel_swb_s1 <= '0';
      wb_trig_mux_ch11_ctl_transm_out_sel_swb_s2 <= '0';
      regs_o.ch11_ctl_transm_out_sel_o <= "00000000";
    elsif rising_edge(fs_clk_i) then
      wb_trig_mux_ch11_ctl_transm_out_sel_swb_s0 <= wb_trig_mux_ch11_ctl_transm_out_sel_swb;
      wb_trig_mux_ch11_ctl_transm_out_sel_swb_s1 <= wb_trig_mux_ch11_ctl_transm_out_sel_swb_s0;
      wb_trig_mux_ch11_ctl_transm_out_sel_swb_s2 <= wb_trig_mux_ch11_ctl_transm_out_sel_swb_s1;
      if ((wb_trig_mux_ch11_ctl_transm_out_sel_swb_s2 = '0') and (wb_trig_mux_ch11_ctl_transm_out_sel_swb_s1 = '1')) then
        regs_o.ch11_ctl_transm_out_sel_o <= wb_trig_mux_ch11_ctl_transm_out_sel_int;
      end if;
    end if;
  end process;
  
  
-- Dummy
-- Receiver Source
  regs_o.ch12_ctl_rcv_src_o <= wb_trig_mux_ch12_ctl_rcv_src_int;
-- Select Receiver Input
-- asynchronous std_logic_vector register : Select Receiver Input (type RW/RO, fs_clk_i <-> clk_sys_i)
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_trig_mux_ch12_ctl_rcv_in_sel_swb_s0 <= '0';
      wb_trig_mux_ch12_ctl_rcv_in_sel_swb_s1 <= '0';
      wb_trig_mux_ch12_ctl_rcv_in_sel_swb_s2 <= '0';
      regs_o.ch12_ctl_rcv_in_sel_o <= "00000000";
    elsif rising_edge(fs_clk_i) then
      wb_trig_mux_ch12_ctl_rcv_in_sel_swb_s0 <= wb_trig_mux_ch12_ctl_rcv_in_sel_swb;
      wb_trig_mux_ch12_ctl_rcv_in_sel_swb_s1 <= wb_trig_mux_ch12_ctl_rcv_in_sel_swb_s0;
      wb_trig_mux_ch12_ctl_rcv_in_sel_swb_s2 <= wb_trig_mux_ch12_ctl_rcv_in_sel_swb_s1;
      if ((wb_trig_mux_ch12_ctl_rcv_in_sel_swb_s2 = '0') and (wb_trig_mux_ch12_ctl_rcv_in_sel_swb_s1 = '1')) then
        regs_o.ch12_ctl_rcv_in_sel_o <= wb_trig_mux_ch12_ctl_rcv_in_sel_int;
      end if;
    end if;
  end process;
  
  
-- Transmitter Source
  regs_o.ch12_ctl_transm_src_o <= wb_trig_mux_ch12_ctl_transm_src_int;
-- Select Transmitter Output
-- asynchronous std_logic_vector register : Select Transmitter Output (type RW/RO, fs_clk_i <-> clk_sys_i)
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_trig_mux_ch12_ctl_transm_out_sel_swb_s0 <= '0';
      wb_trig_mux_ch12_ctl_transm_out_sel_swb_s1 <= '0';
      wb_trig_mux_ch12_ctl_transm_out_sel_swb_s2 <= '0';
      regs_o.ch12_ctl_transm_out_sel_o <= "00000000";
    elsif rising_edge(fs_clk_i) then
      wb_trig_mux_ch12_ctl_transm_out_sel_swb_s0 <= wb_trig_mux_ch12_ctl_transm_out_sel_swb;
      wb_trig_mux_ch12_ctl_transm_out_sel_swb_s1 <= wb_trig_mux_ch12_ctl_transm_out_sel_swb_s0;
      wb_trig_mux_ch12_ctl_transm_out_sel_swb_s2 <= wb_trig_mux_ch12_ctl_transm_out_sel_swb_s1;
      if ((wb_trig_mux_ch12_ctl_transm_out_sel_swb_s2 = '0') and (wb_trig_mux_ch12_ctl_transm_out_sel_swb_s1 = '1')) then
        regs_o.ch12_ctl_transm_out_sel_o <= wb_trig_mux_ch12_ctl_transm_out_sel_int;
      end if;
    end if;
  end process;
  
  
-- Dummy
-- Receiver Source
  regs_o.ch13_ctl_rcv_src_o <= wb_trig_mux_ch13_ctl_rcv_src_int;
-- Select Receiver Input
-- asynchronous std_logic_vector register : Select Receiver Input (type RW/RO, fs_clk_i <-> clk_sys_i)
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_trig_mux_ch13_ctl_rcv_in_sel_swb_s0 <= '0';
      wb_trig_mux_ch13_ctl_rcv_in_sel_swb_s1 <= '0';
      wb_trig_mux_ch13_ctl_rcv_in_sel_swb_s2 <= '0';
      regs_o.ch13_ctl_rcv_in_sel_o <= "00000000";
    elsif rising_edge(fs_clk_i) then
      wb_trig_mux_ch13_ctl_rcv_in_sel_swb_s0 <= wb_trig_mux_ch13_ctl_rcv_in_sel_swb;
      wb_trig_mux_ch13_ctl_rcv_in_sel_swb_s1 <= wb_trig_mux_ch13_ctl_rcv_in_sel_swb_s0;
      wb_trig_mux_ch13_ctl_rcv_in_sel_swb_s2 <= wb_trig_mux_ch13_ctl_rcv_in_sel_swb_s1;
      if ((wb_trig_mux_ch13_ctl_rcv_in_sel_swb_s2 = '0') and (wb_trig_mux_ch13_ctl_rcv_in_sel_swb_s1 = '1')) then
        regs_o.ch13_ctl_rcv_in_sel_o <= wb_trig_mux_ch13_ctl_rcv_in_sel_int;
      end if;
    end if;
  end process;
  
  
-- Transmitter Source
  regs_o.ch13_ctl_transm_src_o <= wb_trig_mux_ch13_ctl_transm_src_int;
-- Select Transmitter Output
-- asynchronous std_logic_vector register : Select Transmitter Output (type RW/RO, fs_clk_i <-> clk_sys_i)
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_trig_mux_ch13_ctl_transm_out_sel_swb_s0 <= '0';
      wb_trig_mux_ch13_ctl_transm_out_sel_swb_s1 <= '0';
      wb_trig_mux_ch13_ctl_transm_out_sel_swb_s2 <= '0';
      regs_o.ch13_ctl_transm_out_sel_o <= "00000000";
    elsif rising_edge(fs_clk_i) then
      wb_trig_mux_ch13_ctl_transm_out_sel_swb_s0 <= wb_trig_mux_ch13_ctl_transm_out_sel_swb;
      wb_trig_mux_ch13_ctl_transm_out_sel_swb_s1 <= wb_trig_mux_ch13_ctl_transm_out_sel_swb_s0;
      wb_trig_mux_ch13_ctl_transm_out_sel_swb_s2 <= wb_trig_mux_ch13_ctl_transm_out_sel_swb_s1;
      if ((wb_trig_mux_ch13_ctl_transm_out_sel_swb_s2 = '0') and (wb_trig_mux_ch13_ctl_transm_out_sel_swb_s1 = '1')) then
        regs_o.ch13_ctl_transm_out_sel_o <= wb_trig_mux_ch13_ctl_transm_out_sel_int;
      end if;
    end if;
  end process;
  
  
-- Dummy
-- Receiver Source
  regs_o.ch14_ctl_rcv_src_o <= wb_trig_mux_ch14_ctl_rcv_src_int;
-- Select Receiver Input
-- asynchronous std_logic_vector register : Select Receiver Input (type RW/RO, fs_clk_i <-> clk_sys_i)
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_trig_mux_ch14_ctl_rcv_in_sel_swb_s0 <= '0';
      wb_trig_mux_ch14_ctl_rcv_in_sel_swb_s1 <= '0';
      wb_trig_mux_ch14_ctl_rcv_in_sel_swb_s2 <= '0';
      regs_o.ch14_ctl_rcv_in_sel_o <= "00000000";
    elsif rising_edge(fs_clk_i) then
      wb_trig_mux_ch14_ctl_rcv_in_sel_swb_s0 <= wb_trig_mux_ch14_ctl_rcv_in_sel_swb;
      wb_trig_mux_ch14_ctl_rcv_in_sel_swb_s1 <= wb_trig_mux_ch14_ctl_rcv_in_sel_swb_s0;
      wb_trig_mux_ch14_ctl_rcv_in_sel_swb_s2 <= wb_trig_mux_ch14_ctl_rcv_in_sel_swb_s1;
      if ((wb_trig_mux_ch14_ctl_rcv_in_sel_swb_s2 = '0') and (wb_trig_mux_ch14_ctl_rcv_in_sel_swb_s1 = '1')) then
        regs_o.ch14_ctl_rcv_in_sel_o <= wb_trig_mux_ch14_ctl_rcv_in_sel_int;
      end if;
    end if;
  end process;
  
  
-- Transmitter Source
  regs_o.ch14_ctl_transm_src_o <= wb_trig_mux_ch14_ctl_transm_src_int;
-- Select Transmitter Output
-- asynchronous std_logic_vector register : Select Transmitter Output (type RW/RO, fs_clk_i <-> clk_sys_i)
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_trig_mux_ch14_ctl_transm_out_sel_swb_s0 <= '0';
      wb_trig_mux_ch14_ctl_transm_out_sel_swb_s1 <= '0';
      wb_trig_mux_ch14_ctl_transm_out_sel_swb_s2 <= '0';
      regs_o.ch14_ctl_transm_out_sel_o <= "00000000";
    elsif rising_edge(fs_clk_i) then
      wb_trig_mux_ch14_ctl_transm_out_sel_swb_s0 <= wb_trig_mux_ch14_ctl_transm_out_sel_swb;
      wb_trig_mux_ch14_ctl_transm_out_sel_swb_s1 <= wb_trig_mux_ch14_ctl_transm_out_sel_swb_s0;
      wb_trig_mux_ch14_ctl_transm_out_sel_swb_s2 <= wb_trig_mux_ch14_ctl_transm_out_sel_swb_s1;
      if ((wb_trig_mux_ch14_ctl_transm_out_sel_swb_s2 = '0') and (wb_trig_mux_ch14_ctl_transm_out_sel_swb_s1 = '1')) then
        regs_o.ch14_ctl_transm_out_sel_o <= wb_trig_mux_ch14_ctl_transm_out_sel_int;
      end if;
    end if;
  end process;
  
  
-- Dummy
-- Receiver Source
  regs_o.ch15_ctl_rcv_src_o <= wb_trig_mux_ch15_ctl_rcv_src_int;
-- Select Receiver Input
-- asynchronous std_logic_vector register : Select Receiver Input (type RW/RO, fs_clk_i <-> clk_sys_i)
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_trig_mux_ch15_ctl_rcv_in_sel_swb_s0 <= '0';
      wb_trig_mux_ch15_ctl_rcv_in_sel_swb_s1 <= '0';
      wb_trig_mux_ch15_ctl_rcv_in_sel_swb_s2 <= '0';
      regs_o.ch15_ctl_rcv_in_sel_o <= "00000000";
    elsif rising_edge(fs_clk_i) then
      wb_trig_mux_ch15_ctl_rcv_in_sel_swb_s0 <= wb_trig_mux_ch15_ctl_rcv_in_sel_swb;
      wb_trig_mux_ch15_ctl_rcv_in_sel_swb_s1 <= wb_trig_mux_ch15_ctl_rcv_in_sel_swb_s0;
      wb_trig_mux_ch15_ctl_rcv_in_sel_swb_s2 <= wb_trig_mux_ch15_ctl_rcv_in_sel_swb_s1;
      if ((wb_trig_mux_ch15_ctl_rcv_in_sel_swb_s2 = '0') and (wb_trig_mux_ch15_ctl_rcv_in_sel_swb_s1 = '1')) then
        regs_o.ch15_ctl_rcv_in_sel_o <= wb_trig_mux_ch15_ctl_rcv_in_sel_int;
      end if;
    end if;
  end process;
  
  
-- Transmitter Source
  regs_o.ch15_ctl_transm_src_o <= wb_trig_mux_ch15_ctl_transm_src_int;
-- Select Transmitter Output
-- asynchronous std_logic_vector register : Select Transmitter Output (type RW/RO, fs_clk_i <-> clk_sys_i)
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_trig_mux_ch15_ctl_transm_out_sel_swb_s0 <= '0';
      wb_trig_mux_ch15_ctl_transm_out_sel_swb_s1 <= '0';
      wb_trig_mux_ch15_ctl_transm_out_sel_swb_s2 <= '0';
      regs_o.ch15_ctl_transm_out_sel_o <= "00000000";
    elsif rising_edge(fs_clk_i) then
      wb_trig_mux_ch15_ctl_transm_out_sel_swb_s0 <= wb_trig_mux_ch15_ctl_transm_out_sel_swb;
      wb_trig_mux_ch15_ctl_transm_out_sel_swb_s1 <= wb_trig_mux_ch15_ctl_transm_out_sel_swb_s0;
      wb_trig_mux_ch15_ctl_transm_out_sel_swb_s2 <= wb_trig_mux_ch15_ctl_transm_out_sel_swb_s1;
      if ((wb_trig_mux_ch15_ctl_transm_out_sel_swb_s2 = '0') and (wb_trig_mux_ch15_ctl_transm_out_sel_swb_s1 = '1')) then
        regs_o.ch15_ctl_transm_out_sel_o <= wb_trig_mux_ch15_ctl_transm_out_sel_int;
      end if;
    end if;
  end process;
  
  
-- Dummy
-- Receiver Source
  regs_o.ch16_ctl_rcv_src_o <= wb_trig_mux_ch16_ctl_rcv_src_int;
-- Select Receiver Input
-- asynchronous std_logic_vector register : Select Receiver Input (type RW/RO, fs_clk_i <-> clk_sys_i)
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_trig_mux_ch16_ctl_rcv_in_sel_swb_s0 <= '0';
      wb_trig_mux_ch16_ctl_rcv_in_sel_swb_s1 <= '0';
      wb_trig_mux_ch16_ctl_rcv_in_sel_swb_s2 <= '0';
      regs_o.ch16_ctl_rcv_in_sel_o <= "00000000";
    elsif rising_edge(fs_clk_i) then
      wb_trig_mux_ch16_ctl_rcv_in_sel_swb_s0 <= wb_trig_mux_ch16_ctl_rcv_in_sel_swb;
      wb_trig_mux_ch16_ctl_rcv_in_sel_swb_s1 <= wb_trig_mux_ch16_ctl_rcv_in_sel_swb_s0;
      wb_trig_mux_ch16_ctl_rcv_in_sel_swb_s2 <= wb_trig_mux_ch16_ctl_rcv_in_sel_swb_s1;
      if ((wb_trig_mux_ch16_ctl_rcv_in_sel_swb_s2 = '0') and (wb_trig_mux_ch16_ctl_rcv_in_sel_swb_s1 = '1')) then
        regs_o.ch16_ctl_rcv_in_sel_o <= wb_trig_mux_ch16_ctl_rcv_in_sel_int;
      end if;
    end if;
  end process;
  
  
-- Transmitter Source
  regs_o.ch16_ctl_transm_src_o <= wb_trig_mux_ch16_ctl_transm_src_int;
-- Select Transmitter Output
-- asynchronous std_logic_vector register : Select Transmitter Output (type RW/RO, fs_clk_i <-> clk_sys_i)
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_trig_mux_ch16_ctl_transm_out_sel_swb_s0 <= '0';
      wb_trig_mux_ch16_ctl_transm_out_sel_swb_s1 <= '0';
      wb_trig_mux_ch16_ctl_transm_out_sel_swb_s2 <= '0';
      regs_o.ch16_ctl_transm_out_sel_o <= "00000000";
    elsif rising_edge(fs_clk_i) then
      wb_trig_mux_ch16_ctl_transm_out_sel_swb_s0 <= wb_trig_mux_ch16_ctl_transm_out_sel_swb;
      wb_trig_mux_ch16_ctl_transm_out_sel_swb_s1 <= wb_trig_mux_ch16_ctl_transm_out_sel_swb_s0;
      wb_trig_mux_ch16_ctl_transm_out_sel_swb_s2 <= wb_trig_mux_ch16_ctl_transm_out_sel_swb_s1;
      if ((wb_trig_mux_ch16_ctl_transm_out_sel_swb_s2 = '0') and (wb_trig_mux_ch16_ctl_transm_out_sel_swb_s1 = '1')) then
        regs_o.ch16_ctl_transm_out_sel_o <= wb_trig_mux_ch16_ctl_transm_out_sel_int;
      end if;
    end if;
  end process;
  
  
-- Dummy
-- Receiver Source
  regs_o.ch17_ctl_rcv_src_o <= wb_trig_mux_ch17_ctl_rcv_src_int;
-- Select Receiver Input
-- asynchronous std_logic_vector register : Select Receiver Input (type RW/RO, fs_clk_i <-> clk_sys_i)
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_trig_mux_ch17_ctl_rcv_in_sel_swb_s0 <= '0';
      wb_trig_mux_ch17_ctl_rcv_in_sel_swb_s1 <= '0';
      wb_trig_mux_ch17_ctl_rcv_in_sel_swb_s2 <= '0';
      regs_o.ch17_ctl_rcv_in_sel_o <= "00000000";
    elsif rising_edge(fs_clk_i) then
      wb_trig_mux_ch17_ctl_rcv_in_sel_swb_s0 <= wb_trig_mux_ch17_ctl_rcv_in_sel_swb;
      wb_trig_mux_ch17_ctl_rcv_in_sel_swb_s1 <= wb_trig_mux_ch17_ctl_rcv_in_sel_swb_s0;
      wb_trig_mux_ch17_ctl_rcv_in_sel_swb_s2 <= wb_trig_mux_ch17_ctl_rcv_in_sel_swb_s1;
      if ((wb_trig_mux_ch17_ctl_rcv_in_sel_swb_s2 = '0') and (wb_trig_mux_ch17_ctl_rcv_in_sel_swb_s1 = '1')) then
        regs_o.ch17_ctl_rcv_in_sel_o <= wb_trig_mux_ch17_ctl_rcv_in_sel_int;
      end if;
    end if;
  end process;
  
  
-- Transmitter Source
  regs_o.ch17_ctl_transm_src_o <= wb_trig_mux_ch17_ctl_transm_src_int;
-- Select Transmitter Output
-- asynchronous std_logic_vector register : Select Transmitter Output (type RW/RO, fs_clk_i <-> clk_sys_i)
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_trig_mux_ch17_ctl_transm_out_sel_swb_s0 <= '0';
      wb_trig_mux_ch17_ctl_transm_out_sel_swb_s1 <= '0';
      wb_trig_mux_ch17_ctl_transm_out_sel_swb_s2 <= '0';
      regs_o.ch17_ctl_transm_out_sel_o <= "00000000";
    elsif rising_edge(fs_clk_i) then
      wb_trig_mux_ch17_ctl_transm_out_sel_swb_s0 <= wb_trig_mux_ch17_ctl_transm_out_sel_swb;
      wb_trig_mux_ch17_ctl_transm_out_sel_swb_s1 <= wb_trig_mux_ch17_ctl_transm_out_sel_swb_s0;
      wb_trig_mux_ch17_ctl_transm_out_sel_swb_s2 <= wb_trig_mux_ch17_ctl_transm_out_sel_swb_s1;
      if ((wb_trig_mux_ch17_ctl_transm_out_sel_swb_s2 = '0') and (wb_trig_mux_ch17_ctl_transm_out_sel_swb_s1 = '1')) then
        regs_o.ch17_ctl_transm_out_sel_o <= wb_trig_mux_ch17_ctl_transm_out_sel_int;
      end if;
    end if;
  end process;
  
  
-- Dummy
-- Receiver Source
  regs_o.ch18_ctl_rcv_src_o <= wb_trig_mux_ch18_ctl_rcv_src_int;
-- Select Receiver Input
-- asynchronous std_logic_vector register : Select Receiver Input (type RW/RO, fs_clk_i <-> clk_sys_i)
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_trig_mux_ch18_ctl_rcv_in_sel_swb_s0 <= '0';
      wb_trig_mux_ch18_ctl_rcv_in_sel_swb_s1 <= '0';
      wb_trig_mux_ch18_ctl_rcv_in_sel_swb_s2 <= '0';
      regs_o.ch18_ctl_rcv_in_sel_o <= "00000000";
    elsif rising_edge(fs_clk_i) then
      wb_trig_mux_ch18_ctl_rcv_in_sel_swb_s0 <= wb_trig_mux_ch18_ctl_rcv_in_sel_swb;
      wb_trig_mux_ch18_ctl_rcv_in_sel_swb_s1 <= wb_trig_mux_ch18_ctl_rcv_in_sel_swb_s0;
      wb_trig_mux_ch18_ctl_rcv_in_sel_swb_s2 <= wb_trig_mux_ch18_ctl_rcv_in_sel_swb_s1;
      if ((wb_trig_mux_ch18_ctl_rcv_in_sel_swb_s2 = '0') and (wb_trig_mux_ch18_ctl_rcv_in_sel_swb_s1 = '1')) then
        regs_o.ch18_ctl_rcv_in_sel_o <= wb_trig_mux_ch18_ctl_rcv_in_sel_int;
      end if;
    end if;
  end process;
  
  
-- Transmitter Source
  regs_o.ch18_ctl_transm_src_o <= wb_trig_mux_ch18_ctl_transm_src_int;
-- Select Transmitter Output
-- asynchronous std_logic_vector register : Select Transmitter Output (type RW/RO, fs_clk_i <-> clk_sys_i)
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_trig_mux_ch18_ctl_transm_out_sel_swb_s0 <= '0';
      wb_trig_mux_ch18_ctl_transm_out_sel_swb_s1 <= '0';
      wb_trig_mux_ch18_ctl_transm_out_sel_swb_s2 <= '0';
      regs_o.ch18_ctl_transm_out_sel_o <= "00000000";
    elsif rising_edge(fs_clk_i) then
      wb_trig_mux_ch18_ctl_transm_out_sel_swb_s0 <= wb_trig_mux_ch18_ctl_transm_out_sel_swb;
      wb_trig_mux_ch18_ctl_transm_out_sel_swb_s1 <= wb_trig_mux_ch18_ctl_transm_out_sel_swb_s0;
      wb_trig_mux_ch18_ctl_transm_out_sel_swb_s2 <= wb_trig_mux_ch18_ctl_transm_out_sel_swb_s1;
      if ((wb_trig_mux_ch18_ctl_transm_out_sel_swb_s2 = '0') and (wb_trig_mux_ch18_ctl_transm_out_sel_swb_s1 = '1')) then
        regs_o.ch18_ctl_transm_out_sel_o <= wb_trig_mux_ch18_ctl_transm_out_sel_int;
      end if;
    end if;
  end process;
  
  
-- Dummy
-- Receiver Source
  regs_o.ch19_ctl_rcv_src_o <= wb_trig_mux_ch19_ctl_rcv_src_int;
-- Select Receiver Input
-- asynchronous std_logic_vector register : Select Receiver Input (type RW/RO, fs_clk_i <-> clk_sys_i)
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_trig_mux_ch19_ctl_rcv_in_sel_swb_s0 <= '0';
      wb_trig_mux_ch19_ctl_rcv_in_sel_swb_s1 <= '0';
      wb_trig_mux_ch19_ctl_rcv_in_sel_swb_s2 <= '0';
      regs_o.ch19_ctl_rcv_in_sel_o <= "00000000";
    elsif rising_edge(fs_clk_i) then
      wb_trig_mux_ch19_ctl_rcv_in_sel_swb_s0 <= wb_trig_mux_ch19_ctl_rcv_in_sel_swb;
      wb_trig_mux_ch19_ctl_rcv_in_sel_swb_s1 <= wb_trig_mux_ch19_ctl_rcv_in_sel_swb_s0;
      wb_trig_mux_ch19_ctl_rcv_in_sel_swb_s2 <= wb_trig_mux_ch19_ctl_rcv_in_sel_swb_s1;
      if ((wb_trig_mux_ch19_ctl_rcv_in_sel_swb_s2 = '0') and (wb_trig_mux_ch19_ctl_rcv_in_sel_swb_s1 = '1')) then
        regs_o.ch19_ctl_rcv_in_sel_o <= wb_trig_mux_ch19_ctl_rcv_in_sel_int;
      end if;
    end if;
  end process;
  
  
-- Transmitter Source
  regs_o.ch19_ctl_transm_src_o <= wb_trig_mux_ch19_ctl_transm_src_int;
-- Select Transmitter Output
-- asynchronous std_logic_vector register : Select Transmitter Output (type RW/RO, fs_clk_i <-> clk_sys_i)
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_trig_mux_ch19_ctl_transm_out_sel_swb_s0 <= '0';
      wb_trig_mux_ch19_ctl_transm_out_sel_swb_s1 <= '0';
      wb_trig_mux_ch19_ctl_transm_out_sel_swb_s2 <= '0';
      regs_o.ch19_ctl_transm_out_sel_o <= "00000000";
    elsif rising_edge(fs_clk_i) then
      wb_trig_mux_ch19_ctl_transm_out_sel_swb_s0 <= wb_trig_mux_ch19_ctl_transm_out_sel_swb;
      wb_trig_mux_ch19_ctl_transm_out_sel_swb_s1 <= wb_trig_mux_ch19_ctl_transm_out_sel_swb_s0;
      wb_trig_mux_ch19_ctl_transm_out_sel_swb_s2 <= wb_trig_mux_ch19_ctl_transm_out_sel_swb_s1;
      if ((wb_trig_mux_ch19_ctl_transm_out_sel_swb_s2 = '0') and (wb_trig_mux_ch19_ctl_transm_out_sel_swb_s1 = '1')) then
        regs_o.ch19_ctl_transm_out_sel_o <= wb_trig_mux_ch19_ctl_transm_out_sel_int;
      end if;
    end if;
  end process;
  
  
-- Dummy
-- Receiver Source
  regs_o.ch20_ctl_rcv_src_o <= wb_trig_mux_ch20_ctl_rcv_src_int;
-- Select Receiver Input
-- asynchronous std_logic_vector register : Select Receiver Input (type RW/RO, fs_clk_i <-> clk_sys_i)
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_trig_mux_ch20_ctl_rcv_in_sel_swb_s0 <= '0';
      wb_trig_mux_ch20_ctl_rcv_in_sel_swb_s1 <= '0';
      wb_trig_mux_ch20_ctl_rcv_in_sel_swb_s2 <= '0';
      regs_o.ch20_ctl_rcv_in_sel_o <= "00000000";
    elsif rising_edge(fs_clk_i) then
      wb_trig_mux_ch20_ctl_rcv_in_sel_swb_s0 <= wb_trig_mux_ch20_ctl_rcv_in_sel_swb;
      wb_trig_mux_ch20_ctl_rcv_in_sel_swb_s1 <= wb_trig_mux_ch20_ctl_rcv_in_sel_swb_s0;
      wb_trig_mux_ch20_ctl_rcv_in_sel_swb_s2 <= wb_trig_mux_ch20_ctl_rcv_in_sel_swb_s1;
      if ((wb_trig_mux_ch20_ctl_rcv_in_sel_swb_s2 = '0') and (wb_trig_mux_ch20_ctl_rcv_in_sel_swb_s1 = '1')) then
        regs_o.ch20_ctl_rcv_in_sel_o <= wb_trig_mux_ch20_ctl_rcv_in_sel_int;
      end if;
    end if;
  end process;
  
  
-- Transmitter Source
  regs_o.ch20_ctl_transm_src_o <= wb_trig_mux_ch20_ctl_transm_src_int;
-- Select Transmitter Output
-- asynchronous std_logic_vector register : Select Transmitter Output (type RW/RO, fs_clk_i <-> clk_sys_i)
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_trig_mux_ch20_ctl_transm_out_sel_swb_s0 <= '0';
      wb_trig_mux_ch20_ctl_transm_out_sel_swb_s1 <= '0';
      wb_trig_mux_ch20_ctl_transm_out_sel_swb_s2 <= '0';
      regs_o.ch20_ctl_transm_out_sel_o <= "00000000";
    elsif rising_edge(fs_clk_i) then
      wb_trig_mux_ch20_ctl_transm_out_sel_swb_s0 <= wb_trig_mux_ch20_ctl_transm_out_sel_swb;
      wb_trig_mux_ch20_ctl_transm_out_sel_swb_s1 <= wb_trig_mux_ch20_ctl_transm_out_sel_swb_s0;
      wb_trig_mux_ch20_ctl_transm_out_sel_swb_s2 <= wb_trig_mux_ch20_ctl_transm_out_sel_swb_s1;
      if ((wb_trig_mux_ch20_ctl_transm_out_sel_swb_s2 = '0') and (wb_trig_mux_ch20_ctl_transm_out_sel_swb_s1 = '1')) then
        regs_o.ch20_ctl_transm_out_sel_o <= wb_trig_mux_ch20_ctl_transm_out_sel_int;
      end if;
    end if;
  end process;
  
  
-- Dummy
-- Receiver Source
  regs_o.ch21_ctl_rcv_src_o <= wb_trig_mux_ch21_ctl_rcv_src_int;
-- Select Receiver Input
-- asynchronous std_logic_vector register : Select Receiver Input (type RW/RO, fs_clk_i <-> clk_sys_i)
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_trig_mux_ch21_ctl_rcv_in_sel_swb_s0 <= '0';
      wb_trig_mux_ch21_ctl_rcv_in_sel_swb_s1 <= '0';
      wb_trig_mux_ch21_ctl_rcv_in_sel_swb_s2 <= '0';
      regs_o.ch21_ctl_rcv_in_sel_o <= "00000000";
    elsif rising_edge(fs_clk_i) then
      wb_trig_mux_ch21_ctl_rcv_in_sel_swb_s0 <= wb_trig_mux_ch21_ctl_rcv_in_sel_swb;
      wb_trig_mux_ch21_ctl_rcv_in_sel_swb_s1 <= wb_trig_mux_ch21_ctl_rcv_in_sel_swb_s0;
      wb_trig_mux_ch21_ctl_rcv_in_sel_swb_s2 <= wb_trig_mux_ch21_ctl_rcv_in_sel_swb_s1;
      if ((wb_trig_mux_ch21_ctl_rcv_in_sel_swb_s2 = '0') and (wb_trig_mux_ch21_ctl_rcv_in_sel_swb_s1 = '1')) then
        regs_o.ch21_ctl_rcv_in_sel_o <= wb_trig_mux_ch21_ctl_rcv_in_sel_int;
      end if;
    end if;
  end process;
  
  
-- Transmitter Source
  regs_o.ch21_ctl_transm_src_o <= wb_trig_mux_ch21_ctl_transm_src_int;
-- Select Transmitter Output
-- asynchronous std_logic_vector register : Select Transmitter Output (type RW/RO, fs_clk_i <-> clk_sys_i)
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_trig_mux_ch21_ctl_transm_out_sel_swb_s0 <= '0';
      wb_trig_mux_ch21_ctl_transm_out_sel_swb_s1 <= '0';
      wb_trig_mux_ch21_ctl_transm_out_sel_swb_s2 <= '0';
      regs_o.ch21_ctl_transm_out_sel_o <= "00000000";
    elsif rising_edge(fs_clk_i) then
      wb_trig_mux_ch21_ctl_transm_out_sel_swb_s0 <= wb_trig_mux_ch21_ctl_transm_out_sel_swb;
      wb_trig_mux_ch21_ctl_transm_out_sel_swb_s1 <= wb_trig_mux_ch21_ctl_transm_out_sel_swb_s0;
      wb_trig_mux_ch21_ctl_transm_out_sel_swb_s2 <= wb_trig_mux_ch21_ctl_transm_out_sel_swb_s1;
      if ((wb_trig_mux_ch21_ctl_transm_out_sel_swb_s2 = '0') and (wb_trig_mux_ch21_ctl_transm_out_sel_swb_s1 = '1')) then
        regs_o.ch21_ctl_transm_out_sel_o <= wb_trig_mux_ch21_ctl_transm_out_sel_int;
      end if;
    end if;
  end process;
  
  
-- Dummy
-- Receiver Source
  regs_o.ch22_ctl_rcv_src_o <= wb_trig_mux_ch22_ctl_rcv_src_int;
-- Select Receiver Input
-- asynchronous std_logic_vector register : Select Receiver Input (type RW/RO, fs_clk_i <-> clk_sys_i)
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_trig_mux_ch22_ctl_rcv_in_sel_swb_s0 <= '0';
      wb_trig_mux_ch22_ctl_rcv_in_sel_swb_s1 <= '0';
      wb_trig_mux_ch22_ctl_rcv_in_sel_swb_s2 <= '0';
      regs_o.ch22_ctl_rcv_in_sel_o <= "00000000";
    elsif rising_edge(fs_clk_i) then
      wb_trig_mux_ch22_ctl_rcv_in_sel_swb_s0 <= wb_trig_mux_ch22_ctl_rcv_in_sel_swb;
      wb_trig_mux_ch22_ctl_rcv_in_sel_swb_s1 <= wb_trig_mux_ch22_ctl_rcv_in_sel_swb_s0;
      wb_trig_mux_ch22_ctl_rcv_in_sel_swb_s2 <= wb_trig_mux_ch22_ctl_rcv_in_sel_swb_s1;
      if ((wb_trig_mux_ch22_ctl_rcv_in_sel_swb_s2 = '0') and (wb_trig_mux_ch22_ctl_rcv_in_sel_swb_s1 = '1')) then
        regs_o.ch22_ctl_rcv_in_sel_o <= wb_trig_mux_ch22_ctl_rcv_in_sel_int;
      end if;
    end if;
  end process;
  
  
-- Transmitter Source
  regs_o.ch22_ctl_transm_src_o <= wb_trig_mux_ch22_ctl_transm_src_int;
-- Select Transmitter Output
-- asynchronous std_logic_vector register : Select Transmitter Output (type RW/RO, fs_clk_i <-> clk_sys_i)
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_trig_mux_ch22_ctl_transm_out_sel_swb_s0 <= '0';
      wb_trig_mux_ch22_ctl_transm_out_sel_swb_s1 <= '0';
      wb_trig_mux_ch22_ctl_transm_out_sel_swb_s2 <= '0';
      regs_o.ch22_ctl_transm_out_sel_o <= "00000000";
    elsif rising_edge(fs_clk_i) then
      wb_trig_mux_ch22_ctl_transm_out_sel_swb_s0 <= wb_trig_mux_ch22_ctl_transm_out_sel_swb;
      wb_trig_mux_ch22_ctl_transm_out_sel_swb_s1 <= wb_trig_mux_ch22_ctl_transm_out_sel_swb_s0;
      wb_trig_mux_ch22_ctl_transm_out_sel_swb_s2 <= wb_trig_mux_ch22_ctl_transm_out_sel_swb_s1;
      if ((wb_trig_mux_ch22_ctl_transm_out_sel_swb_s2 = '0') and (wb_trig_mux_ch22_ctl_transm_out_sel_swb_s1 = '1')) then
        regs_o.ch22_ctl_transm_out_sel_o <= wb_trig_mux_ch22_ctl_transm_out_sel_int;
      end if;
    end if;
  end process;
  
  
-- Dummy
-- Receiver Source
  regs_o.ch23_ctl_rcv_src_o <= wb_trig_mux_ch23_ctl_rcv_src_int;
-- Select Receiver Input
-- asynchronous std_logic_vector register : Select Receiver Input (type RW/RO, fs_clk_i <-> clk_sys_i)
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_trig_mux_ch23_ctl_rcv_in_sel_swb_s0 <= '0';
      wb_trig_mux_ch23_ctl_rcv_in_sel_swb_s1 <= '0';
      wb_trig_mux_ch23_ctl_rcv_in_sel_swb_s2 <= '0';
      regs_o.ch23_ctl_rcv_in_sel_o <= "00000000";
    elsif rising_edge(fs_clk_i) then
      wb_trig_mux_ch23_ctl_rcv_in_sel_swb_s0 <= wb_trig_mux_ch23_ctl_rcv_in_sel_swb;
      wb_trig_mux_ch23_ctl_rcv_in_sel_swb_s1 <= wb_trig_mux_ch23_ctl_rcv_in_sel_swb_s0;
      wb_trig_mux_ch23_ctl_rcv_in_sel_swb_s2 <= wb_trig_mux_ch23_ctl_rcv_in_sel_swb_s1;
      if ((wb_trig_mux_ch23_ctl_rcv_in_sel_swb_s2 = '0') and (wb_trig_mux_ch23_ctl_rcv_in_sel_swb_s1 = '1')) then
        regs_o.ch23_ctl_rcv_in_sel_o <= wb_trig_mux_ch23_ctl_rcv_in_sel_int;
      end if;
    end if;
  end process;
  
  
-- Transmitter Source
  regs_o.ch23_ctl_transm_src_o <= wb_trig_mux_ch23_ctl_transm_src_int;
-- Select Transmitter Output
-- asynchronous std_logic_vector register : Select Transmitter Output (type RW/RO, fs_clk_i <-> clk_sys_i)
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      wb_trig_mux_ch23_ctl_transm_out_sel_swb_s0 <= '0';
      wb_trig_mux_ch23_ctl_transm_out_sel_swb_s1 <= '0';
      wb_trig_mux_ch23_ctl_transm_out_sel_swb_s2 <= '0';
      regs_o.ch23_ctl_transm_out_sel_o <= "00000000";
    elsif rising_edge(fs_clk_i) then
      wb_trig_mux_ch23_ctl_transm_out_sel_swb_s0 <= wb_trig_mux_ch23_ctl_transm_out_sel_swb;
      wb_trig_mux_ch23_ctl_transm_out_sel_swb_s1 <= wb_trig_mux_ch23_ctl_transm_out_sel_swb_s0;
      wb_trig_mux_ch23_ctl_transm_out_sel_swb_s2 <= wb_trig_mux_ch23_ctl_transm_out_sel_swb_s1;
      if ((wb_trig_mux_ch23_ctl_transm_out_sel_swb_s2 = '0') and (wb_trig_mux_ch23_ctl_transm_out_sel_swb_s1 = '1')) then
        regs_o.ch23_ctl_transm_out_sel_o <= wb_trig_mux_ch23_ctl_transm_out_sel_int;
      end if;
    end if;
  end process;
  
  
-- Dummy
  rwaddr_reg <= wb_adr_i;
  wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
-- ACK signal generation. Just pass the LSB of ACK counter.
  wb_ack_o <= ack_sreg(0);
end syn;
