# wb_fmc_130m_4ch_csr

### Control and status registers for FMC 130M 4CH

Wishbone slave for control and status registers related to FMC 130M 4CH with access from CSR bus

### Contents:

1. Memory map summary
2. HDL symbol
3. Register description
3.1. ADC LTC2208 control register (4 chips)
3.2. FPGA control
3.3. IDELAY ADC0 calibration
3.4. IDELAY ADC1 calibration
3.5. IDELAY ADC2 calibration
3.6. IDELAY ADC3 calibration
3.7. ADC Data Channel 0
3.8. ADC Data Channel 1
3.9. ADC Data Channel 2
3.10. ADC Data Channel 3
3.11. ADC DCM control

### 1. Memory map summary

H/W Address | Type | Name | VHDL/Verilog prefix | C prefix
--- | --- | --- | --- | ---
0x0 | REG | ADC LTC2208 control register (4 chips) | wb_fmc_130m_4ch_csr_adc | ADC
0x1 | REG | FPGA control | wb_fmc_130m_4ch_csr_fpga_ctrl | FPGA_CTRL
0x2 | REG | IDELAY ADC0 calibration | wb_fmc_130m_4ch_csr_idelay0_cal | IDELAY0_CAL
0x3 | REG | IDELAY ADC1 calibration | wb_fmc_130m_4ch_csr_idelay1_cal | IDELAY1_CAL
0x4 | REG | IDELAY ADC2 calibration | wb_fmc_130m_4ch_csr_idelay2_cal | IDELAY2_CAL
0x5 | REG | IDELAY ADC3 calibration | wb_fmc_130m_4ch_csr_idelay3_cal | IDELAY3_CAL
0x6 | REG | ADC Data Channel 0 | wb_fmc_130m_4ch_csr_data0 | DATA0
0x7 | REG | ADC Data Channel 1 | wb_fmc_130m_4ch_csr_data1 | DATA1
0x8 | REG | ADC Data Channel 2 | wb_fmc_130m_4ch_csr_data2 | DATA2
0x9 | REG | ADC Data Channel 3 | wb_fmc_130m_4ch_csr_data3 | DATA3
0xa | REG | ADC DCM control | wb_fmc_130m_4ch_csr_dcm | DCM

### 2. HDL symbol

→ | rst_n_i |  | ADC LTC2208 control register (4 chips): |
→ | clk_sys_i |  | wb_fmc_130m_4ch_csr_adc_rand_o | →
⇒ | wb_adr_i[3:0] |  | wb_fmc_130m_4ch_csr_adc_dith_o | →
⇒ | wb_dat_i[31:0] |  | wb_fmc_130m_4ch_csr_adc_shdn_o | →
⇐ | wb_dat_o[31:0] |  | wb_fmc_130m_4ch_csr_adc_pga_o | →
→ | wb_cyc_i |  | wb_fmc_130m_4ch_csr_adc_reserved_i[27:0] | ⇐
⇒ | wb_sel_i[3:0] |  |  |
→ | wb_stb_i |  | FPGA control: |
→ | wb_we_i |  | wb_fmc_130m_4ch_csr_fpga_ctrl_fmc_idelay_rst_o | →
← | wb_ack_o |  | wb_fmc_130m_4ch_csr_fpga_ctrl_fmc_fifo_rst_o | →
← | wb_stall_o |  | wb_fmc_130m_4ch_csr_fpga_ctrl_fmc_idelay0_rdy_i | ←
|  |  | wb_fmc_130m_4ch_csr_fpga_ctrl_fmc_idelay1_rdy_i | ←
|  |  | wb_fmc_130m_4ch_csr_fpga_ctrl_fmc_idelay2_rdy_i | ←
|  |  | wb_fmc_130m_4ch_csr_fpga_ctrl_fmc_idelay3_rdy_i | ←
|  |  | wb_fmc_130m_4ch_csr_fpga_ctrl_reserved1_i[1:0] | ⇐
|  |  | wb_fmc_130m_4ch_csr_fpga_ctrl_temp_alarm_i | ←
|  |  | wb_fmc_130m_4ch_csr_fpga_ctrl_reserved2_i[22:0] | ⇐
|  |  | IDELAY ADC0 calibration: |
|  |  | wb_fmc_130m_4ch_csr_idelay0_cal_update_o | →
|  |  | wb_fmc_130m_4ch_csr_idelay0_cal_line_o[16:0] | ⇒
|  |  | wb_fmc_130m_4ch_csr_idelay0_cal_val_o[4:0] | ⇒
|  |  | wb_fmc_130m_4ch_csr_idelay0_cal_val_i[4:0] | ⇐
|  |  | wb_fmc_130m_4ch_csr_idelay0_cal_val_load_o | →
|  |  | wb_fmc_130m_4ch_csr_idelay0_cal_reserved_i[8:0] | ⇐
|  |  | IDELAY ADC1 calibration: |
|  |  | wb_fmc_130m_4ch_csr_idelay1_cal_update_o | →
|  |  | wb_fmc_130m_4ch_csr_idelay1_cal_line_o[16:0] | ⇒
|  |  | wb_fmc_130m_4ch_csr_idelay1_cal_val_o[4:0] | ⇒
|  |  | wb_fmc_130m_4ch_csr_idelay1_cal_val_i[4:0] | ⇐
|  |  | wb_fmc_130m_4ch_csr_idelay1_cal_val_load_o | →
|  |  | wb_fmc_130m_4ch_csr_idelay1_cal_reserved_i[8:0] | ⇐
|  |  | IDELAY ADC2 calibration: |
|  |  | wb_fmc_130m_4ch_csr_idelay2_cal_update_o | →
|  |  | wb_fmc_130m_4ch_csr_idelay2_cal_line_o[16:0] | ⇒
|  |  | wb_fmc_130m_4ch_csr_idelay2_cal_val_o[4:0] | ⇒
|  |  | wb_fmc_130m_4ch_csr_idelay2_cal_val_i[4:0] | ⇐
|  |  | wb_fmc_130m_4ch_csr_idelay2_cal_val_load_o | →
|  |  | wb_fmc_130m_4ch_csr_idelay2_cal_reserved_i[8:0] | ⇐
|  |  | IDELAY ADC3 calibration: |
|  |  | wb_fmc_130m_4ch_csr_idelay3_cal_update_o | →
|  |  | wb_fmc_130m_4ch_csr_idelay3_cal_line_o[16:0] | ⇒
|  |  | wb_fmc_130m_4ch_csr_idelay3_cal_val_o[4:0] | ⇒
|  |  | wb_fmc_130m_4ch_csr_idelay3_cal_val_i[4:0] | ⇐
|  |  | wb_fmc_130m_4ch_csr_idelay3_cal_val_load_o | →
|  |  | wb_fmc_130m_4ch_csr_idelay3_cal_reserved_i[8:0] | ⇐
|  |  | ADC Data Channel 0: |
|  |  | wb_fmc_130m_4ch_csr_data0_val_i[31:0] | ⇐
|  |  | ADC Data Channel 1: |
|  |  | wb_fmc_130m_4ch_csr_data1_val_i[31:0] | ⇐
|  |  | ADC Data Channel 2: |
|  |  | wb_fmc_130m_4ch_csr_data2_val_i[31:0] | ⇐
|  |  | ADC Data Channel 3: |
|  |  | wb_fmc_130m_4ch_csr_data3_val_i[31:0] | ⇐
|  |  | ADC DCM control: |
|  |  | wb_fmc_130m_4ch_csr_dcm_adc_en_o | →
|  |  | wb_fmc_130m_4ch_csr_dcm_adc_phase_o | →
|  |  | wb_fmc_130m_4ch_csr_dcm_adc_done_i | ←
|  |  | wb_fmc_130m_4ch_csr_dcm_adc_status0_i | ←
|  |  | wb_fmc_130m_4ch_csr_dcm_adc_reset_o | →
|  |  | wb_fmc_130m_4ch_csr_dcm_reserved_i[26:0] | ⇐

### 3. Register description

### 3.1. ADC LTC2208 control register (4 chips)

HW prefix: | wb_fmc_130m_4ch_csr_adc
HW address: | 0x0
C prefix: | ADC
C offset: | 0x0

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
RESERVED[27:20] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
RESERVED[19:12] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
RESERVED[11:4] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
RESERVED[3:0] | PGA | SHDN | DITH | RAND |  |  |

- RAND [read/write]: RAND
  RAND pin
- DITH [read/write]: DITH
  DITH pin
- SHDN [read/write]: SHDN
  SHDN pin
- PGA [read/write]: PGA
  PGA pin
- RESERVED [read-only]: Reserved
  Ignore on read, write with 0's.

### 3.2. FPGA control

HW prefix: | wb_fmc_130m_4ch_csr_fpga_ctrl
HW address: | 0x1
C prefix: | FPGA_CTRL
C offset: | 0x4

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
RESERVED2[22:15] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
RESERVED2[14:7] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
RESERVED2[6:0] | TEMP_ALARM |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
RESERVED1[1:0] | FMC_IDELAY3_RDY | FMC_IDELAY2_RDY | FMC_IDELAY1_RDY | FMC_IDELAY0_RDY | FMC_FIFO_RST | FMC_IDELAY_RST |

- FMC_IDELAY_RST [read/write]: FMC_IDELAY_RST
  Reset IDELAY components in FPGA (for data transmission from ISLA ADC chips). Need to calibrate IDELAY lines. 0 - reset off, 1 - reset on
- FMC_FIFO_RST [read/write]: FMC_FIFO_RST
  Reset FIFOs in FPGA (data aquisition from ISLA ADC chips). Useful for calibration. 0 - reset off, 1 - reset on
- FMC_IDELAY0_RDY [read-only]: FMC_IDELAY0_RDY
  Calibration status of IDELAY lines for ADC0 chip
- FMC_IDELAY1_RDY [read-only]: FMC_IDELAY1_RDY
  Calibration status of IDELAY lines for ADC1 chip
- FMC_IDELAY2_RDY [read-only]: FMC_IDELAY2_RDY
  Calibration status of IDELAY lines for ADC2 chip
- FMC_IDELAY3_RDY [read-only]: FMC_IDELAY3_RDY
  Calibration status of IDELAY lines for ADC3 chip
- RESERVED1 [read-only]: Reserved
  Ignore on read, write with 0's.
- TEMP_ALARM [read-only]: Temperature Alarm
  Temperature alarm from LM75 chips
- RESERVED2 [read-only]: Reserved
  Ignore on read, write with 0's.

### 3.3. IDELAY ADC0 calibration

HW prefix: | wb_fmc_130m_4ch_csr_idelay0_cal
HW address: | 0x2
C prefix: | IDELAY0_CAL
C offset: | 0x8

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
RESERVED[8:1] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
RESERVED[0:0] | VAL[4:0] | LINE[16:15] |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
LINE[14:7] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
LINE[6:0] | UPDATE |  |  |  |  |  |

- UPDATE [read/write]: UPDATE
  Send value to IDELAY components
- LINE [read/write]: LINE
  IDELAY Line to update tap value (multiple lines at one can be set), including clock line, bit 16 - clk, bits 15-0 - data
- VAL [read/write]: VAL
  Value of tap (0 to 31)
- RESERVED [read-only]: Reserved
  Ignore on read, write with 0's.

### 3.4. IDELAY ADC1 calibration

HW prefix: | wb_fmc_130m_4ch_csr_idelay1_cal
HW address: | 0x3
C prefix: | IDELAY1_CAL
C offset: | 0xc

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
RESERVED[8:1] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
RESERVED[0:0] | VAL[4:0] | LINE[16:15] |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
LINE[14:7] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
LINE[6:0] | UPDATE |  |  |  |  |  |

- UPDATE [read/write]: UPDATE
  Send value to IDELAY components
- LINE [read/write]: LINE
  IDELAY Line to update tap value (multiple lines at one can be set), including clock line, bit 16 - clk, bits 15-0 - data
- VAL [read/write]: VAL
  Value of tap (0 to 31)
- RESERVED [read-only]: Reserved
  Ignore on read, write with 0's.

### 3.5. IDELAY ADC2 calibration

HW prefix: | wb_fmc_130m_4ch_csr_idelay2_cal
HW address: | 0x4
C prefix: | IDELAY2_CAL
C offset: | 0x10

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
RESERVED[8:1] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
RESERVED[0:0] | VAL[4:0] | LINE[16:15] |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
LINE[14:7] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
LINE[6:0] | UPDATE |  |  |  |  |  |

- UPDATE [read/write]: UPDATE
  Send value to IDELAY components
- LINE [read/write]: LINE
  IDELAY Line to update tap value (multiple lines at one can be set), including clock line, bit 16 - clk, bits 15-0 - data
- VAL [read/write]: VAL
  Value of tap (0 to 31)
- RESERVED [read-only]: Reserved
  Ignore on read, write with 0's.

### 3.6. IDELAY ADC3 calibration

HW prefix: | wb_fmc_130m_4ch_csr_idelay3_cal
HW address: | 0x5
C prefix: | IDELAY3_CAL
C offset: | 0x14

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
RESERVED[8:1] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
RESERVED[0:0] | VAL[4:0] | LINE[16:15] |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
LINE[14:7] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
LINE[6:0] | UPDATE |  |  |  |  |  |

- UPDATE [read/write]: UPDATE
  Send value to IDELAY components
- LINE [read/write]: LINE
  IDELAY Line to update tap value (multiple lines at one can be set), including clock line, bit 16 - clk, bits 15-0 - data
- VAL [read/write]: VAL
  Value of tap (0 to 31)
- RESERVED [read-only]: Reserved
  Ignore on read, write with 0's.

### 3.7. ADC Data Channel 0

HW prefix: | wb_fmc_130m_4ch_csr_data0
HW address: | 0x6
C prefix: | DATA0
C offset: | 0x18

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
VAL[31:24] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
VAL[23:16] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
VAL[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
VAL[7:0] |  |  |  |  |  |  |

- VAL [read-only]: DATA0
  ADC data from channel 0

### 3.8. ADC Data Channel 1

HW prefix: | wb_fmc_130m_4ch_csr_data1
HW address: | 0x7
C prefix: | DATA1
C offset: | 0x1c

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
VAL[31:24] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
VAL[23:16] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
VAL[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
VAL[7:0] |  |  |  |  |  |  |

- VAL [read-only]: DATA1
  ADC data from channel 1

### 3.9. ADC Data Channel 2

HW prefix: | wb_fmc_130m_4ch_csr_data2
HW address: | 0x8
C prefix: | DATA2
C offset: | 0x20

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
VAL[31:24] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
VAL[23:16] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
VAL[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
VAL[7:0] |  |  |  |  |  |  |

- VAL [read-only]: DATA2
  ADC data from channel 2

### 3.10. ADC Data Channel 3

HW prefix: | wb_fmc_130m_4ch_csr_data3
HW address: | 0x9
C prefix: | DATA3
C offset: | 0x24

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
VAL[31:24] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
VAL[23:16] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
VAL[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
VAL[7:0] |  |  |  |  |  |  |

- VAL [read-only]: DATA3
  ADC data from channel 3

### 3.11. ADC DCM control

HW prefix: | wb_fmc_130m_4ch_csr_dcm
HW address: | 0xa
C prefix: | DCM
C offset: | 0x28

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
RESERVED[26:19] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
RESERVED[18:11] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
RESERVED[10:3] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
RESERVED[2:0] | ADC_RESET | ADC_STATUS0 | ADC_DONE | ADC_PHASE | ADC_EN |  |

- ADC_EN [read/write]: ADC_DCM
  Enable one phase shift for ADC DCM
- ADC_PHASE [read/write]: ADC_PHASE_INC
  ADC phase shift: 1 - increment, 0 - decrement
- ADC_DONE [read-only]: ADC_DCM_DONE
  Phase shifting done (ADC DCM): 1 - done, 0 - in progress
- ADC_STATUS0 [read-only]: ADC_DCM_STATUS0
  Status of phase shifting (ADC DCM, status bit 0): 1 - error, outside the limits, 0 - ok
- ADC_RESET [read/write]: ADC_RESET
  Reset ADC DCM (should be done on startup)
- RESERVED [read-only]: Reserved
  Ignore on read, write with 0's.