if (action == "synthesis"):
    files = ["axi_datamover_bpm.xci"]

else:
    files = ["axi_datamover_v5_1/hdl/src/vhdl/",
#            "blk_mem_gen_v8_2/hdl/blk_mem_gen_v8_2.vhd",
#            "fifo_generator_v12_0/simulation/",
#            "lib_cdc_v1_0/hdl/src/vhdl/",
#            "lib_fifo_v1_0/hdl/src/vhdl/",
#            "lib_pkg_v1_0/hdl/src/vhdl/",
#            "lib_srl_fifo_v1_0/hdl/src/vhdl/",
            "sim/"]
