---------------------------------------------------------------------------------------
-- Title          : Wishbone slave core for Control and status registers for FMC PICO 1M 4CH
---------------------------------------------------------------------------------------
-- File           : wb_fmcpico1m_4ch_regs.vhd
-- Author         : auto-generated by wbgen2 from wb_fmcpico1m_4ch_regs.wb
-- Created        : Wed Mar 15 18:50:17 2017
-- Standard       : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wb_fmcpico1m_4ch_regs.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

use work.wb_fmcpico1m_4ch_csr_wbgen2_pkg.all;


entity wb_fmcpico1m_4ch_csr is
  port (
    rst_n_i                                  : in     std_logic;
    clk_sys_i                                : in     std_logic;
    wb_adr_i                                 : in     std_logic_vector(2 downto 0);
    wb_dat_i                                 : in     std_logic_vector(31 downto 0);
    wb_dat_o                                 : out    std_logic_vector(31 downto 0);
    wb_cyc_i                                 : in     std_logic;
    wb_sel_i                                 : in     std_logic_vector(3 downto 0);
    wb_stb_i                                 : in     std_logic;
    wb_we_i                                  : in     std_logic;
    wb_ack_o                                 : out    std_logic;
    wb_stall_o                               : out    std_logic;
    regs_i                                   : in     t_wb_fmcpico1m_4ch_csr_in_registers;
    regs_o                                   : out    t_wb_fmcpico1m_4ch_csr_out_registers
  );
end wb_fmcpico1m_4ch_csr;

architecture syn of wb_fmcpico1m_4ch_csr is

signal wb_fmcpico1m_4ch_csr_fmc_ctl_led1_int    : std_logic      ;
signal wb_fmcpico1m_4ch_csr_fmc_ctl_led2_int    : std_logic      ;
signal wb_fmcpico1m_4ch_csr_rng_ctl_r0_int      : std_logic      ;
signal wb_fmcpico1m_4ch_csr_rng_ctl_r1_int      : std_logic      ;
signal wb_fmcpico1m_4ch_csr_rng_ctl_r2_int      : std_logic      ;
signal wb_fmcpico1m_4ch_csr_rng_ctl_r3_int      : std_logic      ;
signal ack_sreg                                 : std_logic_vector(9 downto 0);
signal rddata_reg                               : std_logic_vector(31 downto 0);
signal wrdata_reg                               : std_logic_vector(31 downto 0);
signal bwsel_reg                                : std_logic_vector(3 downto 0);
signal rwaddr_reg                               : std_logic_vector(2 downto 0);
signal ack_in_progress                          : std_logic      ;
signal wr_int                                   : std_logic      ;
signal rd_int                                   : std_logic      ;
signal allones                                  : std_logic_vector(31 downto 0);
signal allzeros                                 : std_logic_vector(31 downto 0);

begin
-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
  wrdata_reg <= wb_dat_i;
  bwsel_reg <= wb_sel_i;
  rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
  wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
  allones <= (others => '1');
  allzeros <= (others => '0');
-- 
-- Main register bank access process.
  process (clk_sys_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      ack_sreg <= "0000000000";
      ack_in_progress <= '0';
      rddata_reg <= "00000000000000000000000000000000";
      wb_fmcpico1m_4ch_csr_fmc_ctl_led1_int <= '0';
      wb_fmcpico1m_4ch_csr_fmc_ctl_led2_int <= '0';
      wb_fmcpico1m_4ch_csr_rng_ctl_r0_int <= '0';
      wb_fmcpico1m_4ch_csr_rng_ctl_r1_int <= '0';
      wb_fmcpico1m_4ch_csr_rng_ctl_r2_int <= '0';
      wb_fmcpico1m_4ch_csr_rng_ctl_r3_int <= '0';
    elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
      ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
      ack_sreg(9) <= '0';
      if (ack_in_progress = '1') then
        if (ack_sreg(0) = '1') then
          ack_in_progress <= '0';
        else
        end if;
      else
        if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
          case rwaddr_reg(2 downto 0) is
          when "000" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(0) <= regs_i.fmc_status_prsnt_i;
            rddata_reg(1) <= regs_i.fmc_status_pg_m2c_i;
            rddata_reg(2) <= 'X';
            rddata_reg(3) <= 'X';
            rddata_reg(4) <= 'X';
            rddata_reg(5) <= 'X';
            rddata_reg(6) <= 'X';
            rddata_reg(7) <= 'X';
            rddata_reg(8) <= 'X';
            rddata_reg(9) <= 'X';
            rddata_reg(10) <= 'X';
            rddata_reg(11) <= 'X';
            rddata_reg(12) <= 'X';
            rddata_reg(13) <= 'X';
            rddata_reg(14) <= 'X';
            rddata_reg(15) <= 'X';
            rddata_reg(16) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            rddata_reg(24) <= 'X';
            rddata_reg(25) <= 'X';
            rddata_reg(26) <= 'X';
            rddata_reg(27) <= 'X';
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "001" => 
            if (wb_we_i = '1') then
              wb_fmcpico1m_4ch_csr_fmc_ctl_led1_int <= wrdata_reg(0);
              wb_fmcpico1m_4ch_csr_fmc_ctl_led2_int <= wrdata_reg(1);
            end if;
            rddata_reg(0) <= wb_fmcpico1m_4ch_csr_fmc_ctl_led1_int;
            rddata_reg(1) <= wb_fmcpico1m_4ch_csr_fmc_ctl_led2_int;
            rddata_reg(2) <= 'X';
            rddata_reg(3) <= 'X';
            rddata_reg(4) <= 'X';
            rddata_reg(5) <= 'X';
            rddata_reg(6) <= 'X';
            rddata_reg(7) <= 'X';
            rddata_reg(8) <= 'X';
            rddata_reg(9) <= 'X';
            rddata_reg(10) <= 'X';
            rddata_reg(11) <= 'X';
            rddata_reg(12) <= 'X';
            rddata_reg(13) <= 'X';
            rddata_reg(14) <= 'X';
            rddata_reg(15) <= 'X';
            rddata_reg(16) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            rddata_reg(24) <= 'X';
            rddata_reg(25) <= 'X';
            rddata_reg(26) <= 'X';
            rddata_reg(27) <= 'X';
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "010" => 
            if (wb_we_i = '1') then
              wb_fmcpico1m_4ch_csr_rng_ctl_r0_int <= wrdata_reg(0);
              wb_fmcpico1m_4ch_csr_rng_ctl_r1_int <= wrdata_reg(8);
              wb_fmcpico1m_4ch_csr_rng_ctl_r2_int <= wrdata_reg(16);
              wb_fmcpico1m_4ch_csr_rng_ctl_r3_int <= wrdata_reg(24);
            end if;
            rddata_reg(0) <= wb_fmcpico1m_4ch_csr_rng_ctl_r0_int;
            rddata_reg(8) <= wb_fmcpico1m_4ch_csr_rng_ctl_r1_int;
            rddata_reg(16) <= wb_fmcpico1m_4ch_csr_rng_ctl_r2_int;
            rddata_reg(24) <= wb_fmcpico1m_4ch_csr_rng_ctl_r3_int;
            rddata_reg(1) <= 'X';
            rddata_reg(2) <= 'X';
            rddata_reg(3) <= 'X';
            rddata_reg(4) <= 'X';
            rddata_reg(5) <= 'X';
            rddata_reg(6) <= 'X';
            rddata_reg(7) <= 'X';
            rddata_reg(9) <= 'X';
            rddata_reg(10) <= 'X';
            rddata_reg(11) <= 'X';
            rddata_reg(12) <= 'X';
            rddata_reg(13) <= 'X';
            rddata_reg(14) <= 'X';
            rddata_reg(15) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(18) <= 'X';
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
            rddata_reg(22) <= 'X';
            rddata_reg(23) <= 'X';
            rddata_reg(25) <= 'X';
            rddata_reg(26) <= 'X';
            rddata_reg(27) <= 'X';
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
            rddata_reg(31) <= 'X';
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "011" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(31 downto 0) <= regs_i.data0_val_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "100" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(31 downto 0) <= regs_i.data1_val_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "101" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(31 downto 0) <= regs_i.data2_val_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "110" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(31 downto 0) <= regs_i.data3_val_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when others =>
-- prevent the slave from hanging the bus on invalid address
            ack_in_progress <= '1';
            ack_sreg(0) <= '1';
          end case;
        end if;
      end if;
    end if;
  end process;
  
  
-- Drive the data output bus
  wb_dat_o <= rddata_reg;
-- FMC Present
-- Power Good from mezzanine
-- LED 1 Control
  regs_o.fmc_ctl_led1_o <= wb_fmcpico1m_4ch_csr_fmc_ctl_led1_int;
-- LED 2 Control
  regs_o.fmc_ctl_led2_o <= wb_fmcpico1m_4ch_csr_fmc_ctl_led2_int;
-- R0
  regs_o.rng_ctl_r0_o <= wb_fmcpico1m_4ch_csr_rng_ctl_r0_int;
-- R1
  regs_o.rng_ctl_r1_o <= wb_fmcpico1m_4ch_csr_rng_ctl_r1_int;
-- R2
  regs_o.rng_ctl_r2_o <= wb_fmcpico1m_4ch_csr_rng_ctl_r2_int;
-- R3
  regs_o.rng_ctl_r3_o <= wb_fmcpico1m_4ch_csr_rng_ctl_r3_int;
-- DATA0
-- DATA1
-- DATA2
-- DATA3
  rwaddr_reg <= wb_adr_i;
  wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
-- ACK signal generation. Just pass the LSB of ACK counter.
  wb_ack_o <= ack_sreg(0);
end syn;
