# wb_trigger_mux_regs

### Control and status register for the MLVDS trigger

Wishbone slave for control and status registers related to the MLVDS trigger

### Contents:

1. Memory map summary
2. HDL symbol
3. Register description
3.1. Channel 0 Control
3.2. Channel 0 Dummy Register
3.3. Channel 1 Control
3.4. Channel 1 Dummy Register
3.5. Channel 2 Control
3.6. Channel 2 Dummy Register
3.7. Channel 3 Control
3.8. Channel 3 Dummy Register
3.9. Channel 4 Control
3.10. Channel 4 Dummy Register
3.11. Channel 5 Control
3.12. Channel 5 Dummy Register
3.13. Channel 6 Control
3.14. Channel 6 Dummy Register
3.15. Channel 7 Control
3.16. Channel 7 Dummy Register
3.17. Channel 8 Control
3.18. Channel 8 Dummy Register
3.19. Channel 9 Control
3.20. Channel 9 Dummy Register
3.21. Channel 10 Control
3.22. Channel 10 Dummy Register
3.23. Channel 11 Control
3.24. Channel 11 Dummy Register
3.25. Channel 12 Control
3.26. Channel 12 Dummy Register
3.27. Channel 13 Control
3.28. Channel 13 Dummy Register
3.29. Channel 14 Control
3.30. Channel 14 Dummy Register
3.31. Channel 15 Control
3.32. Channel 15 Dummy Register
3.33. Channel 16 Control
3.34. Channel 16 Dummy Register
3.35. Channel 17 Control
3.36. Channel 17 Dummy Register
3.37. Channel 18 Control
3.38. Channel 18 Dummy Register
3.39. Channel 19 Control
3.40. Channel 19 Dummy Register
3.41. Channel 20 Control
3.42. Channel 20 Dummy Register
3.43. Channel 21 Control
3.44. Channel 21 Dummy Register
3.45. Channel 22 Control
3.46. Channel 22 Dummy Register
3.47. Channel 23 Control
3.48. Channel 23 Dummy Register

### 1. Memory map summary

H/W Address | Type | Name | VHDL/Verilog prefix | C prefix
--- | --- | --- | --- | ---
0x0 | REG | Channel 0 Control | wb_trig_mux_ch0_ctl | CH0_CTL
0x1 | REG | Channel 0 Dummy Register | wb_trig_mux_ch0_dummy | CH0_DUMMY
0x2 | REG | Channel 1 Control | wb_trig_mux_ch1_ctl | CH1_CTL
0x3 | REG | Channel 1 Dummy Register | wb_trig_mux_ch1_dummy | CH1_DUMMY
0x4 | REG | Channel 2 Control | wb_trig_mux_ch2_ctl | CH2_CTL
0x5 | REG | Channel 2 Dummy Register | wb_trig_mux_ch2_dummy | CH2_DUMMY
0x6 | REG | Channel 3 Control | wb_trig_mux_ch3_ctl | CH3_CTL
0x7 | REG | Channel 3 Dummy Register | wb_trig_mux_ch3_dummy | CH3_DUMMY
0x8 | REG | Channel 4 Control | wb_trig_mux_ch4_ctl | CH4_CTL
0x9 | REG | Channel 4 Dummy Register | wb_trig_mux_ch4_dummy | CH4_DUMMY
0xa | REG | Channel 5 Control | wb_trig_mux_ch5_ctl | CH5_CTL
0xb | REG | Channel 5 Dummy Register | wb_trig_mux_ch5_dummy | CH5_DUMMY
0xc | REG | Channel 6 Control | wb_trig_mux_ch6_ctl | CH6_CTL
0xd | REG | Channel 6 Dummy Register | wb_trig_mux_ch6_dummy | CH6_DUMMY
0xe | REG | Channel 7 Control | wb_trig_mux_ch7_ctl | CH7_CTL
0xf | REG | Channel 7 Dummy Register | wb_trig_mux_ch7_dummy | CH7_DUMMY
0x10 | REG | Channel 8 Control | wb_trig_mux_ch8_ctl | CH8_CTL
0x11 | REG | Channel 8 Dummy Register | wb_trig_mux_ch8_dummy | CH8_DUMMY
0x12 | REG | Channel 9 Control | wb_trig_mux_ch9_ctl | CH9_CTL
0x13 | REG | Channel 9 Dummy Register | wb_trig_mux_ch9_dummy | CH9_DUMMY
0x14 | REG | Channel 10 Control | wb_trig_mux_ch10_ctl | CH10_CTL
0x15 | REG | Channel 10 Dummy Register | wb_trig_mux_ch10_dummy | CH10_DUMMY
0x16 | REG | Channel 11 Control | wb_trig_mux_ch11_ctl | CH11_CTL
0x17 | REG | Channel 11 Dummy Register | wb_trig_mux_ch11_dummy | CH11_DUMMY
0x18 | REG | Channel 12 Control | wb_trig_mux_ch12_ctl | CH12_CTL
0x19 | REG | Channel 12 Dummy Register | wb_trig_mux_ch12_dummy | CH12_DUMMY
0x1a | REG | Channel 13 Control | wb_trig_mux_ch13_ctl | CH13_CTL
0x1b | REG | Channel 13 Dummy Register | wb_trig_mux_ch13_dummy | CH13_DUMMY
0x1c | REG | Channel 14 Control | wb_trig_mux_ch14_ctl | CH14_CTL
0x1d | REG | Channel 14 Dummy Register | wb_trig_mux_ch14_dummy | CH14_DUMMY
0x1e | REG | Channel 15 Control | wb_trig_mux_ch15_ctl | CH15_CTL
0x1f | REG | Channel 15 Dummy Register | wb_trig_mux_ch15_dummy | CH15_DUMMY
0x20 | REG | Channel 16 Control | wb_trig_mux_ch16_ctl | CH16_CTL
0x21 | REG | Channel 16 Dummy Register | wb_trig_mux_ch16_dummy | CH16_DUMMY
0x22 | REG | Channel 17 Control | wb_trig_mux_ch17_ctl | CH17_CTL
0x23 | REG | Channel 17 Dummy Register | wb_trig_mux_ch17_dummy | CH17_DUMMY
0x24 | REG | Channel 18 Control | wb_trig_mux_ch18_ctl | CH18_CTL
0x25 | REG | Channel 18 Dummy Register | wb_trig_mux_ch18_dummy | CH18_DUMMY
0x26 | REG | Channel 19 Control | wb_trig_mux_ch19_ctl | CH19_CTL
0x27 | REG | Channel 19 Dummy Register | wb_trig_mux_ch19_dummy | CH19_DUMMY
0x28 | REG | Channel 20 Control | wb_trig_mux_ch20_ctl | CH20_CTL
0x29 | REG | Channel 20 Dummy Register | wb_trig_mux_ch20_dummy | CH20_DUMMY
0x2a | REG | Channel 21 Control | wb_trig_mux_ch21_ctl | CH21_CTL
0x2b | REG | Channel 21 Dummy Register | wb_trig_mux_ch21_dummy | CH21_DUMMY
0x2c | REG | Channel 22 Control | wb_trig_mux_ch22_ctl | CH22_CTL
0x2d | REG | Channel 22 Dummy Register | wb_trig_mux_ch22_dummy | CH22_DUMMY
0x2e | REG | Channel 23 Control | wb_trig_mux_ch23_ctl | CH23_CTL
0x2f | REG | Channel 23 Dummy Register | wb_trig_mux_ch23_dummy | CH23_DUMMY

### 2. HDL symbol

→ | rst_n_i |  | Channel 0 Control: |
→ | clk_sys_i |  | wb_trig_mux_ch0_ctl_rcv_src_o | →
⇒ | wb_adr_i[5:0] |  | wb_trig_mux_ch0_ctl_rcv_in_sel_o[7:0] | ⇒
⇒ | wb_dat_i[31:0] |  | wb_trig_mux_ch0_ctl_transm_src_o | →
⇐ | wb_dat_o[31:0] |  | wb_trig_mux_ch0_ctl_transm_out_sel_o[7:0] | ⇒
→ | wb_cyc_i |  |  |
⇒ | wb_sel_i[3:0] |  | Channel 0 Dummy Register: |
→ | wb_stb_i |  | wb_trig_mux_ch0_dummy_i[31:0] | ⇐
→ | wb_we_i |  |  |
← | wb_ack_o |  | Channel 1 Control: |
← | wb_stall_o |  | wb_trig_mux_ch1_ctl_rcv_src_o | →
|  |  | wb_trig_mux_ch1_ctl_rcv_in_sel_o[7:0] | ⇒
|  |  | wb_trig_mux_ch1_ctl_transm_src_o | →
|  |  | wb_trig_mux_ch1_ctl_transm_out_sel_o[7:0] | ⇒
|  |  | Channel 1 Dummy Register: |
|  |  | wb_trig_mux_ch1_dummy_i[31:0] | ⇐
|  |  | Channel 2 Control: |
|  |  | wb_trig_mux_ch2_ctl_rcv_src_o | →
|  |  | wb_trig_mux_ch2_ctl_rcv_in_sel_o[7:0] | ⇒
|  |  | wb_trig_mux_ch2_ctl_transm_src_o | →
|  |  | wb_trig_mux_ch2_ctl_transm_out_sel_o[7:0] | ⇒
|  |  | Channel 2 Dummy Register: |
|  |  | wb_trig_mux_ch2_dummy_i[31:0] | ⇐
|  |  | Channel 3 Control: |
|  |  | wb_trig_mux_ch3_ctl_rcv_src_o | →
|  |  | wb_trig_mux_ch3_ctl_rcv_in_sel_o[7:0] | ⇒
|  |  | wb_trig_mux_ch3_ctl_transm_src_o | →
|  |  | wb_trig_mux_ch3_ctl_transm_out_sel_o[7:0] | ⇒
|  |  | Channel 3 Dummy Register: |
|  |  | wb_trig_mux_ch3_dummy_i[31:0] | ⇐
|  |  | Channel 4 Control: |
|  |  | wb_trig_mux_ch4_ctl_rcv_src_o | →
|  |  | wb_trig_mux_ch4_ctl_rcv_in_sel_o[7:0] | ⇒
|  |  | wb_trig_mux_ch4_ctl_transm_src_o | →
|  |  | wb_trig_mux_ch4_ctl_transm_out_sel_o[7:0] | ⇒
|  |  | Channel 4 Dummy Register: |
|  |  | wb_trig_mux_ch4_dummy_i[31:0] | ⇐
|  |  | Channel 5 Control: |
|  |  | wb_trig_mux_ch5_ctl_rcv_src_o | →
|  |  | wb_trig_mux_ch5_ctl_rcv_in_sel_o[7:0] | ⇒
|  |  | wb_trig_mux_ch5_ctl_transm_src_o | →
|  |  | wb_trig_mux_ch5_ctl_transm_out_sel_o[7:0] | ⇒
|  |  | Channel 5 Dummy Register: |
|  |  | wb_trig_mux_ch5_dummy_i[31:0] | ⇐
|  |  | Channel 6 Control: |
|  |  | wb_trig_mux_ch6_ctl_rcv_src_o | →
|  |  | wb_trig_mux_ch6_ctl_rcv_in_sel_o[7:0] | ⇒
|  |  | wb_trig_mux_ch6_ctl_transm_src_o | →
|  |  | wb_trig_mux_ch6_ctl_transm_out_sel_o[7:0] | ⇒
|  |  | Channel 6 Dummy Register: |
|  |  | wb_trig_mux_ch6_dummy_i[31:0] | ⇐
|  |  | Channel 7 Control: |
|  |  | wb_trig_mux_ch7_ctl_rcv_src_o | →
|  |  | wb_trig_mux_ch7_ctl_rcv_in_sel_o[7:0] | ⇒
|  |  | wb_trig_mux_ch7_ctl_transm_src_o | →
|  |  | wb_trig_mux_ch7_ctl_transm_out_sel_o[7:0] | ⇒
|  |  | Channel 7 Dummy Register: |
|  |  | wb_trig_mux_ch7_dummy_i[31:0] | ⇐
|  |  | Channel 8 Control: |
|  |  | wb_trig_mux_ch8_ctl_rcv_src_o | →
|  |  | wb_trig_mux_ch8_ctl_rcv_in_sel_o[7:0] | ⇒
|  |  | wb_trig_mux_ch8_ctl_transm_src_o | →
|  |  | wb_trig_mux_ch8_ctl_transm_out_sel_o[7:0] | ⇒
|  |  | Channel 8 Dummy Register: |
|  |  | wb_trig_mux_ch8_dummy_i[31:0] | ⇐
|  |  | Channel 9 Control: |
|  |  | wb_trig_mux_ch9_ctl_rcv_src_o | →
|  |  | wb_trig_mux_ch9_ctl_rcv_in_sel_o[7:0] | ⇒
|  |  | wb_trig_mux_ch9_ctl_transm_src_o | →
|  |  | wb_trig_mux_ch9_ctl_transm_out_sel_o[7:0] | ⇒
|  |  | Channel 9 Dummy Register: |
|  |  | wb_trig_mux_ch9_dummy_i[31:0] | ⇐
|  |  | Channel 10 Control: |
|  |  | wb_trig_mux_ch10_ctl_rcv_src_o | →
|  |  | wb_trig_mux_ch10_ctl_rcv_in_sel_o[7:0] | ⇒
|  |  | wb_trig_mux_ch10_ctl_transm_src_o | →
|  |  | wb_trig_mux_ch10_ctl_transm_out_sel_o[7:0] | ⇒
|  |  | Channel 10 Dummy Register: |
|  |  | wb_trig_mux_ch10_dummy_i[31:0] | ⇐
|  |  | Channel 11 Control: |
|  |  | wb_trig_mux_ch11_ctl_rcv_src_o | →
|  |  | wb_trig_mux_ch11_ctl_rcv_in_sel_o[7:0] | ⇒
|  |  | wb_trig_mux_ch11_ctl_transm_src_o | →
|  |  | wb_trig_mux_ch11_ctl_transm_out_sel_o[7:0] | ⇒
|  |  | Channel 11 Dummy Register: |
|  |  | wb_trig_mux_ch11_dummy_i[31:0] | ⇐
|  |  | Channel 12 Control: |
|  |  | wb_trig_mux_ch12_ctl_rcv_src_o | →
|  |  | wb_trig_mux_ch12_ctl_rcv_in_sel_o[7:0] | ⇒
|  |  | wb_trig_mux_ch12_ctl_transm_src_o | →
|  |  | wb_trig_mux_ch12_ctl_transm_out_sel_o[7:0] | ⇒
|  |  | Channel 12 Dummy Register: |
|  |  | wb_trig_mux_ch12_dummy_i[31:0] | ⇐
|  |  | Channel 13 Control: |
|  |  | wb_trig_mux_ch13_ctl_rcv_src_o | →
|  |  | wb_trig_mux_ch13_ctl_rcv_in_sel_o[7:0] | ⇒
|  |  | wb_trig_mux_ch13_ctl_transm_src_o | →
|  |  | wb_trig_mux_ch13_ctl_transm_out_sel_o[7:0] | ⇒
|  |  | Channel 13 Dummy Register: |
|  |  | wb_trig_mux_ch13_dummy_i[31:0] | ⇐
|  |  | Channel 14 Control: |
|  |  | wb_trig_mux_ch14_ctl_rcv_src_o | →
|  |  | wb_trig_mux_ch14_ctl_rcv_in_sel_o[7:0] | ⇒
|  |  | wb_trig_mux_ch14_ctl_transm_src_o | →
|  |  | wb_trig_mux_ch14_ctl_transm_out_sel_o[7:0] | ⇒
|  |  | Channel 14 Dummy Register: |
|  |  | wb_trig_mux_ch14_dummy_i[31:0] | ⇐
|  |  | Channel 15 Control: |
|  |  | wb_trig_mux_ch15_ctl_rcv_src_o | →
|  |  | wb_trig_mux_ch15_ctl_rcv_in_sel_o[7:0] | ⇒
|  |  | wb_trig_mux_ch15_ctl_transm_src_o | →
|  |  | wb_trig_mux_ch15_ctl_transm_out_sel_o[7:0] | ⇒
|  |  | Channel 15 Dummy Register: |
|  |  | wb_trig_mux_ch15_dummy_i[31:0] | ⇐
|  |  | Channel 16 Control: |
|  |  | wb_trig_mux_ch16_ctl_rcv_src_o | →
|  |  | wb_trig_mux_ch16_ctl_rcv_in_sel_o[7:0] | ⇒
|  |  | wb_trig_mux_ch16_ctl_transm_src_o | →
|  |  | wb_trig_mux_ch16_ctl_transm_out_sel_o[7:0] | ⇒
|  |  | Channel 16 Dummy Register: |
|  |  | wb_trig_mux_ch16_dummy_i[31:0] | ⇐
|  |  | Channel 17 Control: |
|  |  | wb_trig_mux_ch17_ctl_rcv_src_o | →
|  |  | wb_trig_mux_ch17_ctl_rcv_in_sel_o[7:0] | ⇒
|  |  | wb_trig_mux_ch17_ctl_transm_src_o | →
|  |  | wb_trig_mux_ch17_ctl_transm_out_sel_o[7:0] | ⇒
|  |  | Channel 17 Dummy Register: |
|  |  | wb_trig_mux_ch17_dummy_i[31:0] | ⇐
|  |  | Channel 18 Control: |
|  |  | wb_trig_mux_ch18_ctl_rcv_src_o | →
|  |  | wb_trig_mux_ch18_ctl_rcv_in_sel_o[7:0] | ⇒
|  |  | wb_trig_mux_ch18_ctl_transm_src_o | →
|  |  | wb_trig_mux_ch18_ctl_transm_out_sel_o[7:0] | ⇒
|  |  | Channel 18 Dummy Register: |
|  |  | wb_trig_mux_ch18_dummy_i[31:0] | ⇐
|  |  | Channel 19 Control: |
|  |  | wb_trig_mux_ch19_ctl_rcv_src_o | →
|  |  | wb_trig_mux_ch19_ctl_rcv_in_sel_o[7:0] | ⇒
|  |  | wb_trig_mux_ch19_ctl_transm_src_o | →
|  |  | wb_trig_mux_ch19_ctl_transm_out_sel_o[7:0] | ⇒
|  |  | Channel 19 Dummy Register: |
|  |  | wb_trig_mux_ch19_dummy_i[31:0] | ⇐
|  |  | Channel 20 Control: |
|  |  | wb_trig_mux_ch20_ctl_rcv_src_o | →
|  |  | wb_trig_mux_ch20_ctl_rcv_in_sel_o[7:0] | ⇒
|  |  | wb_trig_mux_ch20_ctl_transm_src_o | →
|  |  | wb_trig_mux_ch20_ctl_transm_out_sel_o[7:0] | ⇒
|  |  | Channel 20 Dummy Register: |
|  |  | wb_trig_mux_ch20_dummy_i[31:0] | ⇐
|  |  | Channel 21 Control: |
|  |  | wb_trig_mux_ch21_ctl_rcv_src_o | →
|  |  | wb_trig_mux_ch21_ctl_rcv_in_sel_o[7:0] | ⇒
|  |  | wb_trig_mux_ch21_ctl_transm_src_o | →
|  |  | wb_trig_mux_ch21_ctl_transm_out_sel_o[7:0] | ⇒
|  |  | Channel 21 Dummy Register: |
|  |  | wb_trig_mux_ch21_dummy_i[31:0] | ⇐
|  |  | Channel 22 Control: |
|  |  | wb_trig_mux_ch22_ctl_rcv_src_o | →
|  |  | wb_trig_mux_ch22_ctl_rcv_in_sel_o[7:0] | ⇒
|  |  | wb_trig_mux_ch22_ctl_transm_src_o | →
|  |  | wb_trig_mux_ch22_ctl_transm_out_sel_o[7:0] | ⇒
|  |  | Channel 22 Dummy Register: |
|  |  | wb_trig_mux_ch22_dummy_i[31:0] | ⇐
|  |  | Channel 23 Control: |
|  |  | wb_trig_mux_ch23_ctl_rcv_src_o | →
|  |  | wb_trig_mux_ch23_ctl_rcv_in_sel_o[7:0] | ⇒
|  |  | wb_trig_mux_ch23_ctl_transm_src_o | →
|  |  | wb_trig_mux_ch23_ctl_transm_out_sel_o[7:0] | ⇒
|  |  | Channel 23 Dummy Register: |
|  |  | wb_trig_mux_ch23_dummy_i[31:0] | ⇐

### 3. Register description

### 3.1. Channel 0 Control

HW prefix: | wb_trig_mux_ch0_ctl
HW address: | 0x0
C prefix: | CH0_CTL
C offset: | 0x0

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
TRANSM_OUT_SEL[7:0] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | TRANSM_SRC

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
RCV_IN_SEL[7:0] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | - | - | - | - | - | RCV_SRC

- RCV_SRC [read/write]: Receiver Source
  1 - Internal Signals
  0 - Triggers
- RCV_IN_SEL [read/write]: Select Receiver Input
  Select input that will be used by the receiver
- TRANSM_SRC [read/write]: Transmitter Source
  1 - Internal Signals
  0 - Triggers
- TRANSM_OUT_SEL [read/write]: Select Transmitter Output
  Select output that will be used by the transmitter

### 3.2. Channel 0 Dummy Register

HW prefix: | wb_trig_mux_ch0_dummy
HW address: | 0x1
C prefix: | CH0_DUMMY
C offset: | 0x4

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
CH0_DUMMY[31:24] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
CH0_DUMMY[23:16] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
CH0_DUMMY[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
CH0_DUMMY[7:0] |  |  |  |  |  |  |

- CH0_DUMMY [read-only]: Dummy
  Dummy register

### 3.3. Channel 1 Control

HW prefix: | wb_trig_mux_ch1_ctl
HW address: | 0x2
C prefix: | CH1_CTL
C offset: | 0x8

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
TRANSM_OUT_SEL[7:0] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | TRANSM_SRC

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
RCV_IN_SEL[7:0] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | - | - | - | - | - | RCV_SRC

- RCV_SRC [read/write]: Receiver Source
  1 - Internal Signals
  0 - Triggers
- RCV_IN_SEL [read/write]: Select Receiver Input
  Select input that will be used by the receiver
- TRANSM_SRC [read/write]: Transmitter Source
  1 - Internal Signals
  0 - Triggers
- TRANSM_OUT_SEL [read/write]: Select Transmitter Output
  Select output that will be used by the transmitter

### 3.4. Channel 1 Dummy Register

HW prefix: | wb_trig_mux_ch1_dummy
HW address: | 0x3
C prefix: | CH1_DUMMY
C offset: | 0xc

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
CH1_DUMMY[31:24] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
CH1_DUMMY[23:16] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
CH1_DUMMY[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
CH1_DUMMY[7:0] |  |  |  |  |  |  |

- CH1_DUMMY [read-only]: Dummy
  Dummy register

### 3.5. Channel 2 Control

HW prefix: | wb_trig_mux_ch2_ctl
HW address: | 0x4
C prefix: | CH2_CTL
C offset: | 0x10

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
TRANSM_OUT_SEL[7:0] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | TRANSM_SRC

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
RCV_IN_SEL[7:0] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | - | - | - | - | - | RCV_SRC

- RCV_SRC [read/write]: Receiver Source
  1 - Internal Signals
  0 - Triggers
- RCV_IN_SEL [read/write]: Select Receiver Input
  Select input that will be used by the receiver
- TRANSM_SRC [read/write]: Transmitter Source
  1 - Internal Signals
  0 - Triggers
- TRANSM_OUT_SEL [read/write]: Select Transmitter Output
  Select output that will be used by the transmitter

### 3.6. Channel 2 Dummy Register

HW prefix: | wb_trig_mux_ch2_dummy
HW address: | 0x5
C prefix: | CH2_DUMMY
C offset: | 0x14

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
CH2_DUMMY[31:24] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
CH2_DUMMY[23:16] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
CH2_DUMMY[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
CH2_DUMMY[7:0] |  |  |  |  |  |  |

- CH2_DUMMY [read-only]: Dummy
  Dummy register

### 3.7. Channel 3 Control

HW prefix: | wb_trig_mux_ch3_ctl
HW address: | 0x6
C prefix: | CH3_CTL
C offset: | 0x18

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
TRANSM_OUT_SEL[7:0] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | TRANSM_SRC

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
RCV_IN_SEL[7:0] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | - | - | - | - | - | RCV_SRC

- RCV_SRC [read/write]: Receiver Source
  1 - Internal Signals
  0 - Triggers
- RCV_IN_SEL [read/write]: Select Receiver Input
  Select input that will be used by the receiver
- TRANSM_SRC [read/write]: Transmitter Source
  1 - Internal Signals
  0 - Triggers
- TRANSM_OUT_SEL [read/write]: Select Transmitter Output
  Select output that will be used by the transmitter

### 3.8. Channel 3 Dummy Register

HW prefix: | wb_trig_mux_ch3_dummy
HW address: | 0x7
C prefix: | CH3_DUMMY
C offset: | 0x1c

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
CH3_DUMMY[31:24] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
CH3_DUMMY[23:16] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
CH3_DUMMY[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
CH3_DUMMY[7:0] |  |  |  |  |  |  |

- CH3_DUMMY [read-only]: Dummy
  Dummy register

### 3.9. Channel 4 Control

HW prefix: | wb_trig_mux_ch4_ctl
HW address: | 0x8
C prefix: | CH4_CTL
C offset: | 0x20

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
TRANSM_OUT_SEL[7:0] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | TRANSM_SRC

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
RCV_IN_SEL[7:0] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | - | - | - | - | - | RCV_SRC

- RCV_SRC [read/write]: Receiver Source
  1 - Internal Signals
  0 - Triggers
- RCV_IN_SEL [read/write]: Select Receiver Input
  Select input that will be used by the receiver
- TRANSM_SRC [read/write]: Transmitter Source
  1 - Internal Signals
  0 - Triggers
- TRANSM_OUT_SEL [read/write]: Select Transmitter Output
  Select output that will be used by the transmitter

### 3.10. Channel 4 Dummy Register

HW prefix: | wb_trig_mux_ch4_dummy
HW address: | 0x9
C prefix: | CH4_DUMMY
C offset: | 0x24

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
CH4_DUMMY[31:24] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
CH4_DUMMY[23:16] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
CH4_DUMMY[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
CH4_DUMMY[7:0] |  |  |  |  |  |  |

- CH4_DUMMY [read-only]: Dummy
  Dummy register

### 3.11. Channel 5 Control

HW prefix: | wb_trig_mux_ch5_ctl
HW address: | 0xa
C prefix: | CH5_CTL
C offset: | 0x28

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
TRANSM_OUT_SEL[7:0] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | TRANSM_SRC

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
RCV_IN_SEL[7:0] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | - | - | - | - | - | RCV_SRC

- RCV_SRC [read/write]: Receiver Source
  1 - Internal Signals
  0 - Triggers
- RCV_IN_SEL [read/write]: Select Receiver Input
  Select input that will be used by the receiver
- TRANSM_SRC [read/write]: Transmitter Source
  1 - Internal Signals
  0 - Triggers
- TRANSM_OUT_SEL [read/write]: Select Transmitter Output
  Select output that will be used by the transmitter

### 3.12. Channel 5 Dummy Register

HW prefix: | wb_trig_mux_ch5_dummy
HW address: | 0xb
C prefix: | CH5_DUMMY
C offset: | 0x2c

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
CH5_DUMMY[31:24] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
CH5_DUMMY[23:16] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
CH5_DUMMY[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
CH5_DUMMY[7:0] |  |  |  |  |  |  |

- CH5_DUMMY [read-only]: Dummy
  Dummy register

### 3.13. Channel 6 Control

HW prefix: | wb_trig_mux_ch6_ctl
HW address: | 0xc
C prefix: | CH6_CTL
C offset: | 0x30

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
TRANSM_OUT_SEL[7:0] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | TRANSM_SRC

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
RCV_IN_SEL[7:0] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | - | - | - | - | - | RCV_SRC

- RCV_SRC [read/write]: Receiver Source
  1 - Internal Signals
  0 - Triggers
- RCV_IN_SEL [read/write]: Select Receiver Input
  Select input that will be used by the receiver
- TRANSM_SRC [read/write]: Transmitter Source
  1 - Internal Signals
  0 - Triggers
- TRANSM_OUT_SEL [read/write]: Select Transmitter Output
  Select output that will be used by the transmitter

### 3.14. Channel 6 Dummy Register

HW prefix: | wb_trig_mux_ch6_dummy
HW address: | 0xd
C prefix: | CH6_DUMMY
C offset: | 0x34

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
CH6_DUMMY[31:24] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
CH6_DUMMY[23:16] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
CH6_DUMMY[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
CH6_DUMMY[7:0] |  |  |  |  |  |  |

- CH6_DUMMY [read-only]: Dummy
  Dummy register

### 3.15. Channel 7 Control

HW prefix: | wb_trig_mux_ch7_ctl
HW address: | 0xe
C prefix: | CH7_CTL
C offset: | 0x38

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
TRANSM_OUT_SEL[7:0] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | TRANSM_SRC

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
RCV_IN_SEL[7:0] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | - | - | - | - | - | RCV_SRC

- RCV_SRC [read/write]: Receiver Source
  1 - Internal Signals
  0 - Triggers
- RCV_IN_SEL [read/write]: Select Receiver Input
  Select input that will be used by the receiver
- TRANSM_SRC [read/write]: Transmitter Source
  1 - Internal Signals
  0 - Triggers
- TRANSM_OUT_SEL [read/write]: Select Transmitter Output
  Select output that will be used by the transmitter

### 3.16. Channel 7 Dummy Register

HW prefix: | wb_trig_mux_ch7_dummy
HW address: | 0xf
C prefix: | CH7_DUMMY
C offset: | 0x3c

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
CH7_DUMMY[31:24] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
CH7_DUMMY[23:16] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
CH7_DUMMY[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
CH7_DUMMY[7:0] |  |  |  |  |  |  |

- CH7_DUMMY [read-only]: Dummy
  Dummy register

### 3.17. Channel 8 Control

HW prefix: | wb_trig_mux_ch8_ctl
HW address: | 0x10
C prefix: | CH8_CTL
C offset: | 0x40

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
TRANSM_OUT_SEL[7:0] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | TRANSM_SRC

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
RCV_IN_SEL[7:0] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | - | - | - | - | - | RCV_SRC

- RCV_SRC [read/write]: Receiver Source
  1 - Internal Signals
  0 - Triggers
- RCV_IN_SEL [read/write]: Select Receiver Input
  Select input that will be used by the receiver
- TRANSM_SRC [read/write]: Transmitter Source
  1 - Internal Signals
  0 - Triggers
- TRANSM_OUT_SEL [read/write]: Select Transmitter Output
  Select output that will be used by the transmitter

### 3.18. Channel 8 Dummy Register

HW prefix: | wb_trig_mux_ch8_dummy
HW address: | 0x11
C prefix: | CH8_DUMMY
C offset: | 0x44

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
CH8_DUMMY[31:24] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
CH8_DUMMY[23:16] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
CH8_DUMMY[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
CH8_DUMMY[7:0] |  |  |  |  |  |  |

- CH8_DUMMY [read-only]: Dummy
  Dummy register

### 3.19. Channel 9 Control

HW prefix: | wb_trig_mux_ch9_ctl
HW address: | 0x12
C prefix: | CH9_CTL
C offset: | 0x48

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
TRANSM_OUT_SEL[7:0] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | TRANSM_SRC

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
RCV_IN_SEL[7:0] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | - | - | - | - | - | RCV_SRC

- RCV_SRC [read/write]: Receiver Source
  1 - Internal Signals
  0 - Triggers
- RCV_IN_SEL [read/write]: Select Receiver Input
  Select input that will be used by the receiver
- TRANSM_SRC [read/write]: Transmitter Source
  1 - Internal Signals
  0 - Triggers
- TRANSM_OUT_SEL [read/write]: Select Transmitter Output
  Select output that will be used by the transmitter

### 3.20. Channel 9 Dummy Register

HW prefix: | wb_trig_mux_ch9_dummy
HW address: | 0x13
C prefix: | CH9_DUMMY
C offset: | 0x4c

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
CH9_DUMMY[31:24] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
CH9_DUMMY[23:16] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
CH9_DUMMY[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
CH9_DUMMY[7:0] |  |  |  |  |  |  |

- CH9_DUMMY [read-only]: Dummy
  Dummy register

### 3.21. Channel 10 Control

HW prefix: | wb_trig_mux_ch10_ctl
HW address: | 0x14
C prefix: | CH10_CTL
C offset: | 0x50

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
TRANSM_OUT_SEL[7:0] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | TRANSM_SRC

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
RCV_IN_SEL[7:0] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | - | - | - | - | - | RCV_SRC

- RCV_SRC [read/write]: Receiver Source
  1 - Internal Signals
  0 - Triggers
- RCV_IN_SEL [read/write]: Select Receiver Input
  Select input that will be used by the receiver
- TRANSM_SRC [read/write]: Transmitter Source
  1 - Internal Signals
  0 - Triggers
- TRANSM_OUT_SEL [read/write]: Select Transmitter Output
  Select output that will be used by the transmitter

### 3.22. Channel 10 Dummy Register

HW prefix: | wb_trig_mux_ch10_dummy
HW address: | 0x15
C prefix: | CH10_DUMMY
C offset: | 0x54

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
CH10_DUMMY[31:24] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
CH10_DUMMY[23:16] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
CH10_DUMMY[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
CH10_DUMMY[7:0] |  |  |  |  |  |  |

- CH10_DUMMY [read-only]: Dummy
  Dummy register

### 3.23. Channel 11 Control

HW prefix: | wb_trig_mux_ch11_ctl
HW address: | 0x16
C prefix: | CH11_CTL
C offset: | 0x58

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
TRANSM_OUT_SEL[7:0] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | TRANSM_SRC

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
RCV_IN_SEL[7:0] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | - | - | - | - | - | RCV_SRC

- RCV_SRC [read/write]: Receiver Source
  1 - Internal Signals
  0 - Triggers
- RCV_IN_SEL [read/write]: Select Receiver Input
  Select input that will be used by the receiver
- TRANSM_SRC [read/write]: Transmitter Source
  1 - Internal Signals
  0 - Triggers
- TRANSM_OUT_SEL [read/write]: Select Transmitter Output
  Select output that will be used by the transmitter

### 3.24. Channel 11 Dummy Register

HW prefix: | wb_trig_mux_ch11_dummy
HW address: | 0x17
C prefix: | CH11_DUMMY
C offset: | 0x5c

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
CH11_DUMMY[31:24] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
CH11_DUMMY[23:16] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
CH11_DUMMY[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
CH11_DUMMY[7:0] |  |  |  |  |  |  |

- CH11_DUMMY [read-only]: Dummy
  Dummy register

### 3.25. Channel 12 Control

HW prefix: | wb_trig_mux_ch12_ctl
HW address: | 0x18
C prefix: | CH12_CTL
C offset: | 0x60

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
TRANSM_OUT_SEL[7:0] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | TRANSM_SRC

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
RCV_IN_SEL[7:0] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | - | - | - | - | - | RCV_SRC

- RCV_SRC [read/write]: Receiver Source
  1 - Internal Signals
  0 - Triggers
- RCV_IN_SEL [read/write]: Select Receiver Input
  Select input that will be used by the receiver
- TRANSM_SRC [read/write]: Transmitter Source
  1 - Internal Signals
  0 - Triggers
- TRANSM_OUT_SEL [read/write]: Select Transmitter Output
  Select output that will be used by the transmitter

### 3.26. Channel 12 Dummy Register

HW prefix: | wb_trig_mux_ch12_dummy
HW address: | 0x19
C prefix: | CH12_DUMMY
C offset: | 0x64

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
CH12_DUMMY[31:24] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
CH12_DUMMY[23:16] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
CH12_DUMMY[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
CH12_DUMMY[7:0] |  |  |  |  |  |  |

- CH12_DUMMY [read-only]: Dummy
  Dummy register

### 3.27. Channel 13 Control

HW prefix: | wb_trig_mux_ch13_ctl
HW address: | 0x1a
C prefix: | CH13_CTL
C offset: | 0x68

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
TRANSM_OUT_SEL[7:0] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | TRANSM_SRC

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
RCV_IN_SEL[7:0] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | - | - | - | - | - | RCV_SRC

- RCV_SRC [read/write]: Receiver Source
  1 - Internal Signals
  0 - Triggers
- RCV_IN_SEL [read/write]: Select Receiver Input
  Select input that will be used by the receiver
- TRANSM_SRC [read/write]: Transmitter Source
  1 - Internal Signals
  0 - Triggers
- TRANSM_OUT_SEL [read/write]: Select Transmitter Output
  Select output that will be used by the transmitter

### 3.28. Channel 13 Dummy Register

HW prefix: | wb_trig_mux_ch13_dummy
HW address: | 0x1b
C prefix: | CH13_DUMMY
C offset: | 0x6c

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
CH13_DUMMY[31:24] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
CH13_DUMMY[23:16] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
CH13_DUMMY[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
CH13_DUMMY[7:0] |  |  |  |  |  |  |

- CH13_DUMMY [read-only]: Dummy
  Dummy register

### 3.29. Channel 14 Control

HW prefix: | wb_trig_mux_ch14_ctl
HW address: | 0x1c
C prefix: | CH14_CTL
C offset: | 0x70

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
TRANSM_OUT_SEL[7:0] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | TRANSM_SRC

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
RCV_IN_SEL[7:0] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | - | - | - | - | - | RCV_SRC

- RCV_SRC [read/write]: Receiver Source
  1 - Internal Signals
  0 - Triggers
- RCV_IN_SEL [read/write]: Select Receiver Input
  Select input that will be used by the receiver
- TRANSM_SRC [read/write]: Transmitter Source
  1 - Internal Signals
  0 - Triggers
- TRANSM_OUT_SEL [read/write]: Select Transmitter Output
  Select output that will be used by the transmitter

### 3.30. Channel 14 Dummy Register

HW prefix: | wb_trig_mux_ch14_dummy
HW address: | 0x1d
C prefix: | CH14_DUMMY
C offset: | 0x74

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
CH14_DUMMY[31:24] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
CH14_DUMMY[23:16] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
CH14_DUMMY[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
CH14_DUMMY[7:0] |  |  |  |  |  |  |

- CH14_DUMMY [read-only]: Dummy
  Dummy register

### 3.31. Channel 15 Control

HW prefix: | wb_trig_mux_ch15_ctl
HW address: | 0x1e
C prefix: | CH15_CTL
C offset: | 0x78

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
TRANSM_OUT_SEL[7:0] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | TRANSM_SRC

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
RCV_IN_SEL[7:0] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | - | - | - | - | - | RCV_SRC

- RCV_SRC [read/write]: Receiver Source
  1 - Internal Signals
  0 - Triggers
- RCV_IN_SEL [read/write]: Select Receiver Input
  Select input that will be used by the receiver
- TRANSM_SRC [read/write]: Transmitter Source
  1 - Internal Signals
  0 - Triggers
- TRANSM_OUT_SEL [read/write]: Select Transmitter Output
  Select output that will be used by the transmitter

### 3.32. Channel 15 Dummy Register

HW prefix: | wb_trig_mux_ch15_dummy
HW address: | 0x1f
C prefix: | CH15_DUMMY
C offset: | 0x7c

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
CH15_DUMMY[31:24] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
CH15_DUMMY[23:16] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
CH15_DUMMY[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
CH15_DUMMY[7:0] |  |  |  |  |  |  |

- CH15_DUMMY [read-only]: Dummy
  Dummy register

### 3.33. Channel 16 Control

HW prefix: | wb_trig_mux_ch16_ctl
HW address: | 0x20
C prefix: | CH16_CTL
C offset: | 0x80

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
TRANSM_OUT_SEL[7:0] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | TRANSM_SRC

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
RCV_IN_SEL[7:0] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | - | - | - | - | - | RCV_SRC

- RCV_SRC [read/write]: Receiver Source
  1 - Internal Signals
  0 - Triggers
- RCV_IN_SEL [read/write]: Select Receiver Input
  Select input that will be used by the receiver
- TRANSM_SRC [read/write]: Transmitter Source
  1 - Internal Signals
  0 - Triggers
- TRANSM_OUT_SEL [read/write]: Select Transmitter Output
  Select output that will be used by the transmitter

### 3.34. Channel 16 Dummy Register

HW prefix: | wb_trig_mux_ch16_dummy
HW address: | 0x21
C prefix: | CH16_DUMMY
C offset: | 0x84

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
CH16_DUMMY[31:24] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
CH16_DUMMY[23:16] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
CH16_DUMMY[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
CH16_DUMMY[7:0] |  |  |  |  |  |  |

- CH16_DUMMY [read-only]: Dummy
  Dummy register

### 3.35. Channel 17 Control

HW prefix: | wb_trig_mux_ch17_ctl
HW address: | 0x22
C prefix: | CH17_CTL
C offset: | 0x88

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
TRANSM_OUT_SEL[7:0] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | TRANSM_SRC

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
RCV_IN_SEL[7:0] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | - | - | - | - | - | RCV_SRC

- RCV_SRC [read/write]: Receiver Source
  1 - Internal Signals
  0 - Triggers
- RCV_IN_SEL [read/write]: Select Receiver Input
  Select input that will be used by the receiver
- TRANSM_SRC [read/write]: Transmitter Source
  1 - Internal Signals
  0 - Triggers
- TRANSM_OUT_SEL [read/write]: Select Transmitter Output
  Select output that will be used by the transmitter

### 3.36. Channel 17 Dummy Register

HW prefix: | wb_trig_mux_ch17_dummy
HW address: | 0x23
C prefix: | CH17_DUMMY
C offset: | 0x8c

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
CH17_DUMMY[31:24] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
CH17_DUMMY[23:16] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
CH17_DUMMY[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
CH17_DUMMY[7:0] |  |  |  |  |  |  |

- CH17_DUMMY [read-only]: Dummy
  Dummy register

### 3.37. Channel 18 Control

HW prefix: | wb_trig_mux_ch18_ctl
HW address: | 0x24
C prefix: | CH18_CTL
C offset: | 0x90

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
TRANSM_OUT_SEL[7:0] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | TRANSM_SRC

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
RCV_IN_SEL[7:0] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | - | - | - | - | - | RCV_SRC

- RCV_SRC [read/write]: Receiver Source
  1 - Internal Signals
  0 - Triggers
- RCV_IN_SEL [read/write]: Select Receiver Input
  Select input that will be used by the receiver
- TRANSM_SRC [read/write]: Transmitter Source
  1 - Internal Signals
  0 - Triggers
- TRANSM_OUT_SEL [read/write]: Select Transmitter Output
  Select output that will be used by the transmitter

### 3.38. Channel 18 Dummy Register

HW prefix: | wb_trig_mux_ch18_dummy
HW address: | 0x25
C prefix: | CH18_DUMMY
C offset: | 0x94

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
CH18_DUMMY[31:24] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
CH18_DUMMY[23:16] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
CH18_DUMMY[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
CH18_DUMMY[7:0] |  |  |  |  |  |  |

- CH18_DUMMY [read-only]: Dummy
  Dummy register

### 3.39. Channel 19 Control

HW prefix: | wb_trig_mux_ch19_ctl
HW address: | 0x26
C prefix: | CH19_CTL
C offset: | 0x98

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
TRANSM_OUT_SEL[7:0] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | TRANSM_SRC

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
RCV_IN_SEL[7:0] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | - | - | - | - | - | RCV_SRC

- RCV_SRC [read/write]: Receiver Source
  1 - Internal Signals
  0 - Triggers
- RCV_IN_SEL [read/write]: Select Receiver Input
  Select input that will be used by the receiver
- TRANSM_SRC [read/write]: Transmitter Source
  1 - Internal Signals
  0 - Triggers
- TRANSM_OUT_SEL [read/write]: Select Transmitter Output
  Select output that will be used by the transmitter

### 3.40. Channel 19 Dummy Register

HW prefix: | wb_trig_mux_ch19_dummy
HW address: | 0x27
C prefix: | CH19_DUMMY
C offset: | 0x9c

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
CH19_DUMMY[31:24] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
CH19_DUMMY[23:16] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
CH19_DUMMY[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
CH19_DUMMY[7:0] |  |  |  |  |  |  |

- CH19_DUMMY [read-only]: Dummy
  Dummy register

### 3.41. Channel 20 Control

HW prefix: | wb_trig_mux_ch20_ctl
HW address: | 0x28
C prefix: | CH20_CTL
C offset: | 0xa0

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
TRANSM_OUT_SEL[7:0] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | TRANSM_SRC

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
RCV_IN_SEL[7:0] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | - | - | - | - | - | RCV_SRC

- RCV_SRC [read/write]: Receiver Source
  1 - Internal Signals
  0 - Triggers
- RCV_IN_SEL [read/write]: Select Receiver Input
  Select input that will be used by the receiver
- TRANSM_SRC [read/write]: Transmitter Source
  1 - Internal Signals
  0 - Triggers
- TRANSM_OUT_SEL [read/write]: Select Transmitter Output
  Select output that will be used by the transmitter

### 3.42. Channel 20 Dummy Register

HW prefix: | wb_trig_mux_ch20_dummy
HW address: | 0x29
C prefix: | CH20_DUMMY
C offset: | 0xa4

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
CH20_DUMMY[31:24] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
CH20_DUMMY[23:16] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
CH20_DUMMY[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
CH20_DUMMY[7:0] |  |  |  |  |  |  |

- CH20_DUMMY [read-only]: Dummy
  Dummy register

### 3.43. Channel 21 Control

HW prefix: | wb_trig_mux_ch21_ctl
HW address: | 0x2a
C prefix: | CH21_CTL
C offset: | 0xa8

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
TRANSM_OUT_SEL[7:0] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | TRANSM_SRC

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
RCV_IN_SEL[7:0] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | - | - | - | - | - | RCV_SRC

- RCV_SRC [read/write]: Receiver Source
  1 - Internal Signals
  0 - Triggers
- RCV_IN_SEL [read/write]: Select Receiver Input
  Select input that will be used by the receiver
- TRANSM_SRC [read/write]: Transmitter Source
  1 - Internal Signals
  0 - Triggers
- TRANSM_OUT_SEL [read/write]: Select Transmitter Output
  Select output that will be used by the transmitter

### 3.44. Channel 21 Dummy Register

HW prefix: | wb_trig_mux_ch21_dummy
HW address: | 0x2b
C prefix: | CH21_DUMMY
C offset: | 0xac

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
CH21_DUMMY[31:24] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
CH21_DUMMY[23:16] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
CH21_DUMMY[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
CH21_DUMMY[7:0] |  |  |  |  |  |  |

- CH21_DUMMY [read-only]: Dummy
  Dummy register

### 3.45. Channel 22 Control

HW prefix: | wb_trig_mux_ch22_ctl
HW address: | 0x2c
C prefix: | CH22_CTL
C offset: | 0xb0

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
TRANSM_OUT_SEL[7:0] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | TRANSM_SRC

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
RCV_IN_SEL[7:0] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | - | - | - | - | - | RCV_SRC

- RCV_SRC [read/write]: Receiver Source
  1 - Internal Signals
  0 - Triggers
- RCV_IN_SEL [read/write]: Select Receiver Input
  Select input that will be used by the receiver
- TRANSM_SRC [read/write]: Transmitter Source
  1 - Internal Signals
  0 - Triggers
- TRANSM_OUT_SEL [read/write]: Select Transmitter Output
  Select output that will be used by the transmitter

### 3.46. Channel 22 Dummy Register

HW prefix: | wb_trig_mux_ch22_dummy
HW address: | 0x2d
C prefix: | CH22_DUMMY
C offset: | 0xb4

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
CH22_DUMMY[31:24] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
CH22_DUMMY[23:16] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
CH22_DUMMY[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
CH22_DUMMY[7:0] |  |  |  |  |  |  |

- CH22_DUMMY [read-only]: Dummy
  Dummy register

### 3.47. Channel 23 Control

HW prefix: | wb_trig_mux_ch23_ctl
HW address: | 0x2e
C prefix: | CH23_CTL
C offset: | 0xb8

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
TRANSM_OUT_SEL[7:0] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
- | - | - | - | - | - | - | TRANSM_SRC

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
RCV_IN_SEL[7:0] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
- | - | - | - | - | - | - | RCV_SRC

- RCV_SRC [read/write]: Receiver Source
  1 - Internal Signals
  0 - Triggers
- RCV_IN_SEL [read/write]: Select Receiver Input
  Select input that will be used by the receiver
- TRANSM_SRC [read/write]: Transmitter Source
  1 - Internal Signals
  0 - Triggers
- TRANSM_OUT_SEL [read/write]: Select Transmitter Output
  Select output that will be used by the transmitter

### 3.48. Channel 23 Dummy Register

HW prefix: | wb_trig_mux_ch23_dummy
HW address: | 0x2f
C prefix: | CH23_DUMMY
C offset: | 0xbc

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
CH23_DUMMY[31:24] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
CH23_DUMMY[23:16] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
CH23_DUMMY[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
CH23_DUMMY[7:0] |  |  |  |  |  |  |

- CH23_DUMMY [read-only]: Dummy
  Dummy register