    CHANGE LOG for AXI4-Stream Interconnect 1.1

    Release Date:  July 25, 2012
    --------------------------------------------------------------------------------

    Table of Contents

    1. INTRODUCTION
    2. DEVICE SUPPORT
    3. NEW FEATURE HISTORY
    4. RESOLVED ISSUES
    5. KNOWN ISSUES & LIMITATIONS
    6. TECHNICAL SUPPORT & FEEDBACK
    7. CORE RELEASE HISTORY
    8. LEGAL DISCLAIMER

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    1. INTRODUCTION

      This file contains the change log for all released versions of the Xilinx
      LogiCORE IP core AXI4-Stream Interconnect.

      For the latest core updates, see the product page at:

       www.xilinx.com/products/intellectual-property/axi4-stream_interconnect.htm

      For installation instructions for this release, please go to:

        www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm

      For system requirements, see:

        www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm

    2. DEVICE SUPPORT

      2.1. ISE

        The following device families are supported by the core for this release:

        All Series 7 devices
        All Virtex-6 devices
        All Spartan-6 devices

      2.2. VIVADO

        The following device families are supported by the core for this release:

        All Series 7 devices

    3. NEW FEATURE HISTORY

      3.1 ISE

      v1.1

        - Support for ACLKEN across clock converters and FIFO.

        - Area improvements in data width convertrs.

        - Enhanced GUI layout.

      v1.0

        - Initial Release

      3.2 Vivado

      v1.1

        - Same features as for ISE.

      v1.0

        - Initial Release

    4. RESOLVED ISSUES

      4.1 ISE

        - 2012/12/18 - Updated FIFO Generator instantiation to match the case of the verilog model.

      4.2 Vivado

        - 2012/12/18 - Updated FIFO Generator instantiation to match the case of the verilog model.

    5. KNOWN ISSUES & LIMITATIONS

      - None

      - For a comprehensive listing of Known Issues for this core, please see the IP
        Release Notes Guide,

        www.xilinx.com/support/documentation/ip_documentation/axis_interconnect/v1_1/pg035_axis_interconnect.pdf

    6. TECHNICAL SUPPORT & FEEDBACK

       To obtain technical support, create a WebCase at www.xilinx.com/support.
       Questions are routed to a team with expertise using this product.
       Feedback on this IP core may also be submitted under the "Leave Feedback"
       menu item in Vivado/PlanAhead.

       Xilinx provides technical support for use of this product when used
       according to the guidelines described in the core documentation, and
       cannot guarantee timing, functionality, or support of this product for
       designs that do not follow specified guidelines.

    7. CORE RELEASE HISTORY

    Date        By            Version      Description
    ================================================================================
    07/25/2012  Xilinx, Inc.  1.1         ISE 14.2 and Vivado 2012.2 support

    04/24/2012  Xilinx, Inc.  1.0         ISE 14.1 support and Vivado 2012.1 beta
                                          support, Initial Release
    ================================================================================

    8. LEGAL DISCLAIMER

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