/*
  Register definitions for slave core: Control and status register for the MLVDS trigger

  * File           : wb_trigger_mux_regs.h
  * Author         : auto-generated by wbgen2 from wb_trigger_mux.wb
  * Created        : Wed May 11 18:21:31 2016
  * Standard       : ANSI C

    THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wb_trigger_mux.wb
    DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!

*/

#ifndef __WBGEN2_REGDEFS_WB_TRIGGER_MUX_WB
#define __WBGEN2_REGDEFS_WB_TRIGGER_MUX_WB

#include <inttypes.h>

#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
#else
#error "Unsupported compiler?"
#endif

#ifndef __WBGEN2_MACROS_DEFINED__
#define __WBGEN2_MACROS_DEFINED__
#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
#endif


/* definitions for register: Channel 0 Control */

/* definitions for field: Receiver Source in reg: Channel 0 Control */
#define WB_TRIG_MUX_CH0_CTL_RCV_SRC           WBGEN2_GEN_MASK(0, 1)

/* definitions for field: Select Receiver Input in reg: Channel 0 Control */
#define WB_TRIG_MUX_CH0_CTL_RCV_IN_SEL_MASK   WBGEN2_GEN_MASK(8, 8)
#define WB_TRIG_MUX_CH0_CTL_RCV_IN_SEL_SHIFT  8
#define WB_TRIG_MUX_CH0_CTL_RCV_IN_SEL_W(value) WBGEN2_GEN_WRITE(value, 8, 8)
#define WB_TRIG_MUX_CH0_CTL_RCV_IN_SEL_R(reg) WBGEN2_GEN_READ(reg, 8, 8)

/* definitions for field: Transmitter Source in reg: Channel 0 Control */
#define WB_TRIG_MUX_CH0_CTL_TRANSM_SRC        WBGEN2_GEN_MASK(16, 1)

/* definitions for field: Select Transmitter Output in reg: Channel 0 Control */
#define WB_TRIG_MUX_CH0_CTL_TRANSM_OUT_SEL_MASK WBGEN2_GEN_MASK(24, 8)
#define WB_TRIG_MUX_CH0_CTL_TRANSM_OUT_SEL_SHIFT 24
#define WB_TRIG_MUX_CH0_CTL_TRANSM_OUT_SEL_W(value) WBGEN2_GEN_WRITE(value, 24, 8)
#define WB_TRIG_MUX_CH0_CTL_TRANSM_OUT_SEL_R(reg) WBGEN2_GEN_READ(reg, 24, 8)

/* definitions for register: Channel 0 Dummy Register */

/* definitions for register: Channel 1 Control */

/* definitions for field: Receiver Source in reg: Channel 1 Control */
#define WB_TRIG_MUX_CH1_CTL_RCV_SRC           WBGEN2_GEN_MASK(0, 1)

/* definitions for field: Select Receiver Input in reg: Channel 1 Control */
#define WB_TRIG_MUX_CH1_CTL_RCV_IN_SEL_MASK   WBGEN2_GEN_MASK(8, 8)
#define WB_TRIG_MUX_CH1_CTL_RCV_IN_SEL_SHIFT  8
#define WB_TRIG_MUX_CH1_CTL_RCV_IN_SEL_W(value) WBGEN2_GEN_WRITE(value, 8, 8)
#define WB_TRIG_MUX_CH1_CTL_RCV_IN_SEL_R(reg) WBGEN2_GEN_READ(reg, 8, 8)

/* definitions for field: Transmitter Source in reg: Channel 1 Control */
#define WB_TRIG_MUX_CH1_CTL_TRANSM_SRC        WBGEN2_GEN_MASK(16, 1)

/* definitions for field: Select Transmitter Output in reg: Channel 1 Control */
#define WB_TRIG_MUX_CH1_CTL_TRANSM_OUT_SEL_MASK WBGEN2_GEN_MASK(24, 8)
#define WB_TRIG_MUX_CH1_CTL_TRANSM_OUT_SEL_SHIFT 24
#define WB_TRIG_MUX_CH1_CTL_TRANSM_OUT_SEL_W(value) WBGEN2_GEN_WRITE(value, 24, 8)
#define WB_TRIG_MUX_CH1_CTL_TRANSM_OUT_SEL_R(reg) WBGEN2_GEN_READ(reg, 24, 8)

/* definitions for register: Channel 1 Dummy Register */

/* definitions for register: Channel 2 Control */

/* definitions for field: Receiver Source in reg: Channel 2 Control */
#define WB_TRIG_MUX_CH2_CTL_RCV_SRC           WBGEN2_GEN_MASK(0, 1)

/* definitions for field: Select Receiver Input in reg: Channel 2 Control */
#define WB_TRIG_MUX_CH2_CTL_RCV_IN_SEL_MASK   WBGEN2_GEN_MASK(8, 8)
#define WB_TRIG_MUX_CH2_CTL_RCV_IN_SEL_SHIFT  8
#define WB_TRIG_MUX_CH2_CTL_RCV_IN_SEL_W(value) WBGEN2_GEN_WRITE(value, 8, 8)
#define WB_TRIG_MUX_CH2_CTL_RCV_IN_SEL_R(reg) WBGEN2_GEN_READ(reg, 8, 8)

/* definitions for field: Transmitter Source in reg: Channel 2 Control */
#define WB_TRIG_MUX_CH2_CTL_TRANSM_SRC        WBGEN2_GEN_MASK(16, 1)

/* definitions for field: Select Transmitter Output in reg: Channel 2 Control */
#define WB_TRIG_MUX_CH2_CTL_TRANSM_OUT_SEL_MASK WBGEN2_GEN_MASK(24, 8)
#define WB_TRIG_MUX_CH2_CTL_TRANSM_OUT_SEL_SHIFT 24
#define WB_TRIG_MUX_CH2_CTL_TRANSM_OUT_SEL_W(value) WBGEN2_GEN_WRITE(value, 24, 8)
#define WB_TRIG_MUX_CH2_CTL_TRANSM_OUT_SEL_R(reg) WBGEN2_GEN_READ(reg, 24, 8)

/* definitions for register: Channel 2 Dummy Register */

/* definitions for register: Channel 3 Control */

/* definitions for field: Receiver Source in reg: Channel 3 Control */
#define WB_TRIG_MUX_CH3_CTL_RCV_SRC           WBGEN2_GEN_MASK(0, 1)

/* definitions for field: Select Receiver Input in reg: Channel 3 Control */
#define WB_TRIG_MUX_CH3_CTL_RCV_IN_SEL_MASK   WBGEN2_GEN_MASK(8, 8)
#define WB_TRIG_MUX_CH3_CTL_RCV_IN_SEL_SHIFT  8
#define WB_TRIG_MUX_CH3_CTL_RCV_IN_SEL_W(value) WBGEN2_GEN_WRITE(value, 8, 8)
#define WB_TRIG_MUX_CH3_CTL_RCV_IN_SEL_R(reg) WBGEN2_GEN_READ(reg, 8, 8)

/* definitions for field: Transmitter Source in reg: Channel 3 Control */
#define WB_TRIG_MUX_CH3_CTL_TRANSM_SRC        WBGEN2_GEN_MASK(16, 1)

/* definitions for field: Select Transmitter Output in reg: Channel 3 Control */
#define WB_TRIG_MUX_CH3_CTL_TRANSM_OUT_SEL_MASK WBGEN2_GEN_MASK(24, 8)
#define WB_TRIG_MUX_CH3_CTL_TRANSM_OUT_SEL_SHIFT 24
#define WB_TRIG_MUX_CH3_CTL_TRANSM_OUT_SEL_W(value) WBGEN2_GEN_WRITE(value, 24, 8)
#define WB_TRIG_MUX_CH3_CTL_TRANSM_OUT_SEL_R(reg) WBGEN2_GEN_READ(reg, 24, 8)

/* definitions for register: Channel 3 Dummy Register */

/* definitions for register: Channel 4 Control */

/* definitions for field: Receiver Source in reg: Channel 4 Control */
#define WB_TRIG_MUX_CH4_CTL_RCV_SRC           WBGEN2_GEN_MASK(0, 1)

/* definitions for field: Select Receiver Input in reg: Channel 4 Control */
#define WB_TRIG_MUX_CH4_CTL_RCV_IN_SEL_MASK   WBGEN2_GEN_MASK(8, 8)
#define WB_TRIG_MUX_CH4_CTL_RCV_IN_SEL_SHIFT  8
#define WB_TRIG_MUX_CH4_CTL_RCV_IN_SEL_W(value) WBGEN2_GEN_WRITE(value, 8, 8)
#define WB_TRIG_MUX_CH4_CTL_RCV_IN_SEL_R(reg) WBGEN2_GEN_READ(reg, 8, 8)

/* definitions for field: Transmitter Source in reg: Channel 4 Control */
#define WB_TRIG_MUX_CH4_CTL_TRANSM_SRC        WBGEN2_GEN_MASK(16, 1)

/* definitions for field: Select Transmitter Output in reg: Channel 4 Control */
#define WB_TRIG_MUX_CH4_CTL_TRANSM_OUT_SEL_MASK WBGEN2_GEN_MASK(24, 8)
#define WB_TRIG_MUX_CH4_CTL_TRANSM_OUT_SEL_SHIFT 24
#define WB_TRIG_MUX_CH4_CTL_TRANSM_OUT_SEL_W(value) WBGEN2_GEN_WRITE(value, 24, 8)
#define WB_TRIG_MUX_CH4_CTL_TRANSM_OUT_SEL_R(reg) WBGEN2_GEN_READ(reg, 24, 8)

/* definitions for register: Channel 4 Dummy Register */

/* definitions for register: Channel 5 Control */

/* definitions for field: Receiver Source in reg: Channel 5 Control */
#define WB_TRIG_MUX_CH5_CTL_RCV_SRC           WBGEN2_GEN_MASK(0, 1)

/* definitions for field: Select Receiver Input in reg: Channel 5 Control */
#define WB_TRIG_MUX_CH5_CTL_RCV_IN_SEL_MASK   WBGEN2_GEN_MASK(8, 8)
#define WB_TRIG_MUX_CH5_CTL_RCV_IN_SEL_SHIFT  8
#define WB_TRIG_MUX_CH5_CTL_RCV_IN_SEL_W(value) WBGEN2_GEN_WRITE(value, 8, 8)
#define WB_TRIG_MUX_CH5_CTL_RCV_IN_SEL_R(reg) WBGEN2_GEN_READ(reg, 8, 8)

/* definitions for field: Transmitter Source in reg: Channel 5 Control */
#define WB_TRIG_MUX_CH5_CTL_TRANSM_SRC        WBGEN2_GEN_MASK(16, 1)

/* definitions for field: Select Transmitter Output in reg: Channel 5 Control */
#define WB_TRIG_MUX_CH5_CTL_TRANSM_OUT_SEL_MASK WBGEN2_GEN_MASK(24, 8)
#define WB_TRIG_MUX_CH5_CTL_TRANSM_OUT_SEL_SHIFT 24
#define WB_TRIG_MUX_CH5_CTL_TRANSM_OUT_SEL_W(value) WBGEN2_GEN_WRITE(value, 24, 8)
#define WB_TRIG_MUX_CH5_CTL_TRANSM_OUT_SEL_R(reg) WBGEN2_GEN_READ(reg, 24, 8)

/* definitions for register: Channel 5 Dummy Register */

/* definitions for register: Channel 6 Control */

/* definitions for field: Receiver Source in reg: Channel 6 Control */
#define WB_TRIG_MUX_CH6_CTL_RCV_SRC           WBGEN2_GEN_MASK(0, 1)

/* definitions for field: Select Receiver Input in reg: Channel 6 Control */
#define WB_TRIG_MUX_CH6_CTL_RCV_IN_SEL_MASK   WBGEN2_GEN_MASK(8, 8)
#define WB_TRIG_MUX_CH6_CTL_RCV_IN_SEL_SHIFT  8
#define WB_TRIG_MUX_CH6_CTL_RCV_IN_SEL_W(value) WBGEN2_GEN_WRITE(value, 8, 8)
#define WB_TRIG_MUX_CH6_CTL_RCV_IN_SEL_R(reg) WBGEN2_GEN_READ(reg, 8, 8)

/* definitions for field: Transmitter Source in reg: Channel 6 Control */
#define WB_TRIG_MUX_CH6_CTL_TRANSM_SRC        WBGEN2_GEN_MASK(16, 1)

/* definitions for field: Select Transmitter Output in reg: Channel 6 Control */
#define WB_TRIG_MUX_CH6_CTL_TRANSM_OUT_SEL_MASK WBGEN2_GEN_MASK(24, 8)
#define WB_TRIG_MUX_CH6_CTL_TRANSM_OUT_SEL_SHIFT 24
#define WB_TRIG_MUX_CH6_CTL_TRANSM_OUT_SEL_W(value) WBGEN2_GEN_WRITE(value, 24, 8)
#define WB_TRIG_MUX_CH6_CTL_TRANSM_OUT_SEL_R(reg) WBGEN2_GEN_READ(reg, 24, 8)

/* definitions for register: Channel 6 Dummy Register */

/* definitions for register: Channel 7 Control */

/* definitions for field: Receiver Source in reg: Channel 7 Control */
#define WB_TRIG_MUX_CH7_CTL_RCV_SRC           WBGEN2_GEN_MASK(0, 1)

/* definitions for field: Select Receiver Input in reg: Channel 7 Control */
#define WB_TRIG_MUX_CH7_CTL_RCV_IN_SEL_MASK   WBGEN2_GEN_MASK(8, 8)
#define WB_TRIG_MUX_CH7_CTL_RCV_IN_SEL_SHIFT  8
#define WB_TRIG_MUX_CH7_CTL_RCV_IN_SEL_W(value) WBGEN2_GEN_WRITE(value, 8, 8)
#define WB_TRIG_MUX_CH7_CTL_RCV_IN_SEL_R(reg) WBGEN2_GEN_READ(reg, 8, 8)

/* definitions for field: Transmitter Source in reg: Channel 7 Control */
#define WB_TRIG_MUX_CH7_CTL_TRANSM_SRC        WBGEN2_GEN_MASK(16, 1)

/* definitions for field: Select Transmitter Output in reg: Channel 7 Control */
#define WB_TRIG_MUX_CH7_CTL_TRANSM_OUT_SEL_MASK WBGEN2_GEN_MASK(24, 8)
#define WB_TRIG_MUX_CH7_CTL_TRANSM_OUT_SEL_SHIFT 24
#define WB_TRIG_MUX_CH7_CTL_TRANSM_OUT_SEL_W(value) WBGEN2_GEN_WRITE(value, 24, 8)
#define WB_TRIG_MUX_CH7_CTL_TRANSM_OUT_SEL_R(reg) WBGEN2_GEN_READ(reg, 24, 8)

/* definitions for register: Channel 7 Dummy Register */

/* definitions for register: Channel 8 Control */

/* definitions for field: Receiver Source in reg: Channel 8 Control */
#define WB_TRIG_MUX_CH8_CTL_RCV_SRC           WBGEN2_GEN_MASK(0, 1)

/* definitions for field: Select Receiver Input in reg: Channel 8 Control */
#define WB_TRIG_MUX_CH8_CTL_RCV_IN_SEL_MASK   WBGEN2_GEN_MASK(8, 8)
#define WB_TRIG_MUX_CH8_CTL_RCV_IN_SEL_SHIFT  8
#define WB_TRIG_MUX_CH8_CTL_RCV_IN_SEL_W(value) WBGEN2_GEN_WRITE(value, 8, 8)
#define WB_TRIG_MUX_CH8_CTL_RCV_IN_SEL_R(reg) WBGEN2_GEN_READ(reg, 8, 8)

/* definitions for field: Transmitter Source in reg: Channel 8 Control */
#define WB_TRIG_MUX_CH8_CTL_TRANSM_SRC        WBGEN2_GEN_MASK(16, 1)

/* definitions for field: Select Transmitter Output in reg: Channel 8 Control */
#define WB_TRIG_MUX_CH8_CTL_TRANSM_OUT_SEL_MASK WBGEN2_GEN_MASK(24, 8)
#define WB_TRIG_MUX_CH8_CTL_TRANSM_OUT_SEL_SHIFT 24
#define WB_TRIG_MUX_CH8_CTL_TRANSM_OUT_SEL_W(value) WBGEN2_GEN_WRITE(value, 24, 8)
#define WB_TRIG_MUX_CH8_CTL_TRANSM_OUT_SEL_R(reg) WBGEN2_GEN_READ(reg, 24, 8)

/* definitions for register: Channel 8 Dummy Register */

/* definitions for register: Channel 9 Control */

/* definitions for field: Receiver Source in reg: Channel 9 Control */
#define WB_TRIG_MUX_CH9_CTL_RCV_SRC           WBGEN2_GEN_MASK(0, 1)

/* definitions for field: Select Receiver Input in reg: Channel 9 Control */
#define WB_TRIG_MUX_CH9_CTL_RCV_IN_SEL_MASK   WBGEN2_GEN_MASK(8, 8)
#define WB_TRIG_MUX_CH9_CTL_RCV_IN_SEL_SHIFT  8
#define WB_TRIG_MUX_CH9_CTL_RCV_IN_SEL_W(value) WBGEN2_GEN_WRITE(value, 8, 8)
#define WB_TRIG_MUX_CH9_CTL_RCV_IN_SEL_R(reg) WBGEN2_GEN_READ(reg, 8, 8)

/* definitions for field: Transmitter Source in reg: Channel 9 Control */
#define WB_TRIG_MUX_CH9_CTL_TRANSM_SRC        WBGEN2_GEN_MASK(16, 1)

/* definitions for field: Select Transmitter Output in reg: Channel 9 Control */
#define WB_TRIG_MUX_CH9_CTL_TRANSM_OUT_SEL_MASK WBGEN2_GEN_MASK(24, 8)
#define WB_TRIG_MUX_CH9_CTL_TRANSM_OUT_SEL_SHIFT 24
#define WB_TRIG_MUX_CH9_CTL_TRANSM_OUT_SEL_W(value) WBGEN2_GEN_WRITE(value, 24, 8)
#define WB_TRIG_MUX_CH9_CTL_TRANSM_OUT_SEL_R(reg) WBGEN2_GEN_READ(reg, 24, 8)

/* definitions for register: Channel 9 Dummy Register */

/* definitions for register: Channel 10 Control */

/* definitions for field: Receiver Source in reg: Channel 10 Control */
#define WB_TRIG_MUX_CH10_CTL_RCV_SRC          WBGEN2_GEN_MASK(0, 1)

/* definitions for field: Select Receiver Input in reg: Channel 10 Control */
#define WB_TRIG_MUX_CH10_CTL_RCV_IN_SEL_MASK  WBGEN2_GEN_MASK(8, 8)
#define WB_TRIG_MUX_CH10_CTL_RCV_IN_SEL_SHIFT 8
#define WB_TRIG_MUX_CH10_CTL_RCV_IN_SEL_W(value) WBGEN2_GEN_WRITE(value, 8, 8)
#define WB_TRIG_MUX_CH10_CTL_RCV_IN_SEL_R(reg) WBGEN2_GEN_READ(reg, 8, 8)

/* definitions for field: Transmitter Source in reg: Channel 10 Control */
#define WB_TRIG_MUX_CH10_CTL_TRANSM_SRC       WBGEN2_GEN_MASK(16, 1)

/* definitions for field: Select Transmitter Output in reg: Channel 10 Control */
#define WB_TRIG_MUX_CH10_CTL_TRANSM_OUT_SEL_MASK WBGEN2_GEN_MASK(24, 8)
#define WB_TRIG_MUX_CH10_CTL_TRANSM_OUT_SEL_SHIFT 24
#define WB_TRIG_MUX_CH10_CTL_TRANSM_OUT_SEL_W(value) WBGEN2_GEN_WRITE(value, 24, 8)
#define WB_TRIG_MUX_CH10_CTL_TRANSM_OUT_SEL_R(reg) WBGEN2_GEN_READ(reg, 24, 8)

/* definitions for register: Channel 10 Dummy Register */

/* definitions for register: Channel 11 Control */

/* definitions for field: Receiver Source in reg: Channel 11 Control */
#define WB_TRIG_MUX_CH11_CTL_RCV_SRC          WBGEN2_GEN_MASK(0, 1)

/* definitions for field: Select Receiver Input in reg: Channel 11 Control */
#define WB_TRIG_MUX_CH11_CTL_RCV_IN_SEL_MASK  WBGEN2_GEN_MASK(8, 8)
#define WB_TRIG_MUX_CH11_CTL_RCV_IN_SEL_SHIFT 8
#define WB_TRIG_MUX_CH11_CTL_RCV_IN_SEL_W(value) WBGEN2_GEN_WRITE(value, 8, 8)
#define WB_TRIG_MUX_CH11_CTL_RCV_IN_SEL_R(reg) WBGEN2_GEN_READ(reg, 8, 8)

/* definitions for field: Transmitter Source in reg: Channel 11 Control */
#define WB_TRIG_MUX_CH11_CTL_TRANSM_SRC       WBGEN2_GEN_MASK(16, 1)

/* definitions for field: Select Transmitter Output in reg: Channel 11 Control */
#define WB_TRIG_MUX_CH11_CTL_TRANSM_OUT_SEL_MASK WBGEN2_GEN_MASK(24, 8)
#define WB_TRIG_MUX_CH11_CTL_TRANSM_OUT_SEL_SHIFT 24
#define WB_TRIG_MUX_CH11_CTL_TRANSM_OUT_SEL_W(value) WBGEN2_GEN_WRITE(value, 24, 8)
#define WB_TRIG_MUX_CH11_CTL_TRANSM_OUT_SEL_R(reg) WBGEN2_GEN_READ(reg, 24, 8)

/* definitions for register: Channel 11 Dummy Register */

/* definitions for register: Channel 12 Control */

/* definitions for field: Receiver Source in reg: Channel 12 Control */
#define WB_TRIG_MUX_CH12_CTL_RCV_SRC          WBGEN2_GEN_MASK(0, 1)

/* definitions for field: Select Receiver Input in reg: Channel 12 Control */
#define WB_TRIG_MUX_CH12_CTL_RCV_IN_SEL_MASK  WBGEN2_GEN_MASK(8, 8)
#define WB_TRIG_MUX_CH12_CTL_RCV_IN_SEL_SHIFT 8
#define WB_TRIG_MUX_CH12_CTL_RCV_IN_SEL_W(value) WBGEN2_GEN_WRITE(value, 8, 8)
#define WB_TRIG_MUX_CH12_CTL_RCV_IN_SEL_R(reg) WBGEN2_GEN_READ(reg, 8, 8)

/* definitions for field: Transmitter Source in reg: Channel 12 Control */
#define WB_TRIG_MUX_CH12_CTL_TRANSM_SRC       WBGEN2_GEN_MASK(16, 1)

/* definitions for field: Select Transmitter Output in reg: Channel 12 Control */
#define WB_TRIG_MUX_CH12_CTL_TRANSM_OUT_SEL_MASK WBGEN2_GEN_MASK(24, 8)
#define WB_TRIG_MUX_CH12_CTL_TRANSM_OUT_SEL_SHIFT 24
#define WB_TRIG_MUX_CH12_CTL_TRANSM_OUT_SEL_W(value) WBGEN2_GEN_WRITE(value, 24, 8)
#define WB_TRIG_MUX_CH12_CTL_TRANSM_OUT_SEL_R(reg) WBGEN2_GEN_READ(reg, 24, 8)

/* definitions for register: Channel 12 Dummy Register */

/* definitions for register: Channel 13 Control */

/* definitions for field: Receiver Source in reg: Channel 13 Control */
#define WB_TRIG_MUX_CH13_CTL_RCV_SRC          WBGEN2_GEN_MASK(0, 1)

/* definitions for field: Select Receiver Input in reg: Channel 13 Control */
#define WB_TRIG_MUX_CH13_CTL_RCV_IN_SEL_MASK  WBGEN2_GEN_MASK(8, 8)
#define WB_TRIG_MUX_CH13_CTL_RCV_IN_SEL_SHIFT 8
#define WB_TRIG_MUX_CH13_CTL_RCV_IN_SEL_W(value) WBGEN2_GEN_WRITE(value, 8, 8)
#define WB_TRIG_MUX_CH13_CTL_RCV_IN_SEL_R(reg) WBGEN2_GEN_READ(reg, 8, 8)

/* definitions for field: Transmitter Source in reg: Channel 13 Control */
#define WB_TRIG_MUX_CH13_CTL_TRANSM_SRC       WBGEN2_GEN_MASK(16, 1)

/* definitions for field: Select Transmitter Output in reg: Channel 13 Control */
#define WB_TRIG_MUX_CH13_CTL_TRANSM_OUT_SEL_MASK WBGEN2_GEN_MASK(24, 8)
#define WB_TRIG_MUX_CH13_CTL_TRANSM_OUT_SEL_SHIFT 24
#define WB_TRIG_MUX_CH13_CTL_TRANSM_OUT_SEL_W(value) WBGEN2_GEN_WRITE(value, 24, 8)
#define WB_TRIG_MUX_CH13_CTL_TRANSM_OUT_SEL_R(reg) WBGEN2_GEN_READ(reg, 24, 8)

/* definitions for register: Channel 13 Dummy Register */

/* definitions for register: Channel 14 Control */

/* definitions for field: Receiver Source in reg: Channel 14 Control */
#define WB_TRIG_MUX_CH14_CTL_RCV_SRC          WBGEN2_GEN_MASK(0, 1)

/* definitions for field: Select Receiver Input in reg: Channel 14 Control */
#define WB_TRIG_MUX_CH14_CTL_RCV_IN_SEL_MASK  WBGEN2_GEN_MASK(8, 8)
#define WB_TRIG_MUX_CH14_CTL_RCV_IN_SEL_SHIFT 8
#define WB_TRIG_MUX_CH14_CTL_RCV_IN_SEL_W(value) WBGEN2_GEN_WRITE(value, 8, 8)
#define WB_TRIG_MUX_CH14_CTL_RCV_IN_SEL_R(reg) WBGEN2_GEN_READ(reg, 8, 8)

/* definitions for field: Transmitter Source in reg: Channel 14 Control */
#define WB_TRIG_MUX_CH14_CTL_TRANSM_SRC       WBGEN2_GEN_MASK(16, 1)

/* definitions for field: Select Transmitter Output in reg: Channel 14 Control */
#define WB_TRIG_MUX_CH14_CTL_TRANSM_OUT_SEL_MASK WBGEN2_GEN_MASK(24, 8)
#define WB_TRIG_MUX_CH14_CTL_TRANSM_OUT_SEL_SHIFT 24
#define WB_TRIG_MUX_CH14_CTL_TRANSM_OUT_SEL_W(value) WBGEN2_GEN_WRITE(value, 24, 8)
#define WB_TRIG_MUX_CH14_CTL_TRANSM_OUT_SEL_R(reg) WBGEN2_GEN_READ(reg, 24, 8)

/* definitions for register: Channel 14 Dummy Register */

/* definitions for register: Channel 15 Control */

/* definitions for field: Receiver Source in reg: Channel 15 Control */
#define WB_TRIG_MUX_CH15_CTL_RCV_SRC          WBGEN2_GEN_MASK(0, 1)

/* definitions for field: Select Receiver Input in reg: Channel 15 Control */
#define WB_TRIG_MUX_CH15_CTL_RCV_IN_SEL_MASK  WBGEN2_GEN_MASK(8, 8)
#define WB_TRIG_MUX_CH15_CTL_RCV_IN_SEL_SHIFT 8
#define WB_TRIG_MUX_CH15_CTL_RCV_IN_SEL_W(value) WBGEN2_GEN_WRITE(value, 8, 8)
#define WB_TRIG_MUX_CH15_CTL_RCV_IN_SEL_R(reg) WBGEN2_GEN_READ(reg, 8, 8)

/* definitions for field: Transmitter Source in reg: Channel 15 Control */
#define WB_TRIG_MUX_CH15_CTL_TRANSM_SRC       WBGEN2_GEN_MASK(16, 1)

/* definitions for field: Select Transmitter Output in reg: Channel 15 Control */
#define WB_TRIG_MUX_CH15_CTL_TRANSM_OUT_SEL_MASK WBGEN2_GEN_MASK(24, 8)
#define WB_TRIG_MUX_CH15_CTL_TRANSM_OUT_SEL_SHIFT 24
#define WB_TRIG_MUX_CH15_CTL_TRANSM_OUT_SEL_W(value) WBGEN2_GEN_WRITE(value, 24, 8)
#define WB_TRIG_MUX_CH15_CTL_TRANSM_OUT_SEL_R(reg) WBGEN2_GEN_READ(reg, 24, 8)

/* definitions for register: Channel 15 Dummy Register */

/* definitions for register: Channel 16 Control */

/* definitions for field: Receiver Source in reg: Channel 16 Control */
#define WB_TRIG_MUX_CH16_CTL_RCV_SRC          WBGEN2_GEN_MASK(0, 1)

/* definitions for field: Select Receiver Input in reg: Channel 16 Control */
#define WB_TRIG_MUX_CH16_CTL_RCV_IN_SEL_MASK  WBGEN2_GEN_MASK(8, 8)
#define WB_TRIG_MUX_CH16_CTL_RCV_IN_SEL_SHIFT 8
#define WB_TRIG_MUX_CH16_CTL_RCV_IN_SEL_W(value) WBGEN2_GEN_WRITE(value, 8, 8)
#define WB_TRIG_MUX_CH16_CTL_RCV_IN_SEL_R(reg) WBGEN2_GEN_READ(reg, 8, 8)

/* definitions for field: Transmitter Source in reg: Channel 16 Control */
#define WB_TRIG_MUX_CH16_CTL_TRANSM_SRC       WBGEN2_GEN_MASK(16, 1)

/* definitions for field: Select Transmitter Output in reg: Channel 16 Control */
#define WB_TRIG_MUX_CH16_CTL_TRANSM_OUT_SEL_MASK WBGEN2_GEN_MASK(24, 8)
#define WB_TRIG_MUX_CH16_CTL_TRANSM_OUT_SEL_SHIFT 24
#define WB_TRIG_MUX_CH16_CTL_TRANSM_OUT_SEL_W(value) WBGEN2_GEN_WRITE(value, 24, 8)
#define WB_TRIG_MUX_CH16_CTL_TRANSM_OUT_SEL_R(reg) WBGEN2_GEN_READ(reg, 24, 8)

/* definitions for register: Channel 16 Dummy Register */

/* definitions for register: Channel 17 Control */

/* definitions for field: Receiver Source in reg: Channel 17 Control */
#define WB_TRIG_MUX_CH17_CTL_RCV_SRC          WBGEN2_GEN_MASK(0, 1)

/* definitions for field: Select Receiver Input in reg: Channel 17 Control */
#define WB_TRIG_MUX_CH17_CTL_RCV_IN_SEL_MASK  WBGEN2_GEN_MASK(8, 8)
#define WB_TRIG_MUX_CH17_CTL_RCV_IN_SEL_SHIFT 8
#define WB_TRIG_MUX_CH17_CTL_RCV_IN_SEL_W(value) WBGEN2_GEN_WRITE(value, 8, 8)
#define WB_TRIG_MUX_CH17_CTL_RCV_IN_SEL_R(reg) WBGEN2_GEN_READ(reg, 8, 8)

/* definitions for field: Transmitter Source in reg: Channel 17 Control */
#define WB_TRIG_MUX_CH17_CTL_TRANSM_SRC       WBGEN2_GEN_MASK(16, 1)

/* definitions for field: Select Transmitter Output in reg: Channel 17 Control */
#define WB_TRIG_MUX_CH17_CTL_TRANSM_OUT_SEL_MASK WBGEN2_GEN_MASK(24, 8)
#define WB_TRIG_MUX_CH17_CTL_TRANSM_OUT_SEL_SHIFT 24
#define WB_TRIG_MUX_CH17_CTL_TRANSM_OUT_SEL_W(value) WBGEN2_GEN_WRITE(value, 24, 8)
#define WB_TRIG_MUX_CH17_CTL_TRANSM_OUT_SEL_R(reg) WBGEN2_GEN_READ(reg, 24, 8)

/* definitions for register: Channel 17 Dummy Register */

/* definitions for register: Channel 18 Control */

/* definitions for field: Receiver Source in reg: Channel 18 Control */
#define WB_TRIG_MUX_CH18_CTL_RCV_SRC          WBGEN2_GEN_MASK(0, 1)

/* definitions for field: Select Receiver Input in reg: Channel 18 Control */
#define WB_TRIG_MUX_CH18_CTL_RCV_IN_SEL_MASK  WBGEN2_GEN_MASK(8, 8)
#define WB_TRIG_MUX_CH18_CTL_RCV_IN_SEL_SHIFT 8
#define WB_TRIG_MUX_CH18_CTL_RCV_IN_SEL_W(value) WBGEN2_GEN_WRITE(value, 8, 8)
#define WB_TRIG_MUX_CH18_CTL_RCV_IN_SEL_R(reg) WBGEN2_GEN_READ(reg, 8, 8)

/* definitions for field: Transmitter Source in reg: Channel 18 Control */
#define WB_TRIG_MUX_CH18_CTL_TRANSM_SRC       WBGEN2_GEN_MASK(16, 1)

/* definitions for field: Select Transmitter Output in reg: Channel 18 Control */
#define WB_TRIG_MUX_CH18_CTL_TRANSM_OUT_SEL_MASK WBGEN2_GEN_MASK(24, 8)
#define WB_TRIG_MUX_CH18_CTL_TRANSM_OUT_SEL_SHIFT 24
#define WB_TRIG_MUX_CH18_CTL_TRANSM_OUT_SEL_W(value) WBGEN2_GEN_WRITE(value, 24, 8)
#define WB_TRIG_MUX_CH18_CTL_TRANSM_OUT_SEL_R(reg) WBGEN2_GEN_READ(reg, 24, 8)

/* definitions for register: Channel 18 Dummy Register */

/* definitions for register: Channel 19 Control */

/* definitions for field: Receiver Source in reg: Channel 19 Control */
#define WB_TRIG_MUX_CH19_CTL_RCV_SRC          WBGEN2_GEN_MASK(0, 1)

/* definitions for field: Select Receiver Input in reg: Channel 19 Control */
#define WB_TRIG_MUX_CH19_CTL_RCV_IN_SEL_MASK  WBGEN2_GEN_MASK(8, 8)
#define WB_TRIG_MUX_CH19_CTL_RCV_IN_SEL_SHIFT 8
#define WB_TRIG_MUX_CH19_CTL_RCV_IN_SEL_W(value) WBGEN2_GEN_WRITE(value, 8, 8)
#define WB_TRIG_MUX_CH19_CTL_RCV_IN_SEL_R(reg) WBGEN2_GEN_READ(reg, 8, 8)

/* definitions for field: Transmitter Source in reg: Channel 19 Control */
#define WB_TRIG_MUX_CH19_CTL_TRANSM_SRC       WBGEN2_GEN_MASK(16, 1)

/* definitions for field: Select Transmitter Output in reg: Channel 19 Control */
#define WB_TRIG_MUX_CH19_CTL_TRANSM_OUT_SEL_MASK WBGEN2_GEN_MASK(24, 8)
#define WB_TRIG_MUX_CH19_CTL_TRANSM_OUT_SEL_SHIFT 24
#define WB_TRIG_MUX_CH19_CTL_TRANSM_OUT_SEL_W(value) WBGEN2_GEN_WRITE(value, 24, 8)
#define WB_TRIG_MUX_CH19_CTL_TRANSM_OUT_SEL_R(reg) WBGEN2_GEN_READ(reg, 24, 8)

/* definitions for register: Channel 19 Dummy Register */

/* definitions for register: Channel 20 Control */

/* definitions for field: Receiver Source in reg: Channel 20 Control */
#define WB_TRIG_MUX_CH20_CTL_RCV_SRC          WBGEN2_GEN_MASK(0, 1)

/* definitions for field: Select Receiver Input in reg: Channel 20 Control */
#define WB_TRIG_MUX_CH20_CTL_RCV_IN_SEL_MASK  WBGEN2_GEN_MASK(8, 8)
#define WB_TRIG_MUX_CH20_CTL_RCV_IN_SEL_SHIFT 8
#define WB_TRIG_MUX_CH20_CTL_RCV_IN_SEL_W(value) WBGEN2_GEN_WRITE(value, 8, 8)
#define WB_TRIG_MUX_CH20_CTL_RCV_IN_SEL_R(reg) WBGEN2_GEN_READ(reg, 8, 8)

/* definitions for field: Transmitter Source in reg: Channel 20 Control */
#define WB_TRIG_MUX_CH20_CTL_TRANSM_SRC       WBGEN2_GEN_MASK(16, 1)

/* definitions for field: Select Transmitter Output in reg: Channel 20 Control */
#define WB_TRIG_MUX_CH20_CTL_TRANSM_OUT_SEL_MASK WBGEN2_GEN_MASK(24, 8)
#define WB_TRIG_MUX_CH20_CTL_TRANSM_OUT_SEL_SHIFT 24
#define WB_TRIG_MUX_CH20_CTL_TRANSM_OUT_SEL_W(value) WBGEN2_GEN_WRITE(value, 24, 8)
#define WB_TRIG_MUX_CH20_CTL_TRANSM_OUT_SEL_R(reg) WBGEN2_GEN_READ(reg, 24, 8)

/* definitions for register: Channel 20 Dummy Register */

/* definitions for register: Channel 21 Control */

/* definitions for field: Receiver Source in reg: Channel 21 Control */
#define WB_TRIG_MUX_CH21_CTL_RCV_SRC          WBGEN2_GEN_MASK(0, 1)

/* definitions for field: Select Receiver Input in reg: Channel 21 Control */
#define WB_TRIG_MUX_CH21_CTL_RCV_IN_SEL_MASK  WBGEN2_GEN_MASK(8, 8)
#define WB_TRIG_MUX_CH21_CTL_RCV_IN_SEL_SHIFT 8
#define WB_TRIG_MUX_CH21_CTL_RCV_IN_SEL_W(value) WBGEN2_GEN_WRITE(value, 8, 8)
#define WB_TRIG_MUX_CH21_CTL_RCV_IN_SEL_R(reg) WBGEN2_GEN_READ(reg, 8, 8)

/* definitions for field: Transmitter Source in reg: Channel 21 Control */
#define WB_TRIG_MUX_CH21_CTL_TRANSM_SRC       WBGEN2_GEN_MASK(16, 1)

/* definitions for field: Select Transmitter Output in reg: Channel 21 Control */
#define WB_TRIG_MUX_CH21_CTL_TRANSM_OUT_SEL_MASK WBGEN2_GEN_MASK(24, 8)
#define WB_TRIG_MUX_CH21_CTL_TRANSM_OUT_SEL_SHIFT 24
#define WB_TRIG_MUX_CH21_CTL_TRANSM_OUT_SEL_W(value) WBGEN2_GEN_WRITE(value, 24, 8)
#define WB_TRIG_MUX_CH21_CTL_TRANSM_OUT_SEL_R(reg) WBGEN2_GEN_READ(reg, 24, 8)

/* definitions for register: Channel 21 Dummy Register */

/* definitions for register: Channel 22 Control */

/* definitions for field: Receiver Source in reg: Channel 22 Control */
#define WB_TRIG_MUX_CH22_CTL_RCV_SRC          WBGEN2_GEN_MASK(0, 1)

/* definitions for field: Select Receiver Input in reg: Channel 22 Control */
#define WB_TRIG_MUX_CH22_CTL_RCV_IN_SEL_MASK  WBGEN2_GEN_MASK(8, 8)
#define WB_TRIG_MUX_CH22_CTL_RCV_IN_SEL_SHIFT 8
#define WB_TRIG_MUX_CH22_CTL_RCV_IN_SEL_W(value) WBGEN2_GEN_WRITE(value, 8, 8)
#define WB_TRIG_MUX_CH22_CTL_RCV_IN_SEL_R(reg) WBGEN2_GEN_READ(reg, 8, 8)

/* definitions for field: Transmitter Source in reg: Channel 22 Control */
#define WB_TRIG_MUX_CH22_CTL_TRANSM_SRC       WBGEN2_GEN_MASK(16, 1)

/* definitions for field: Select Transmitter Output in reg: Channel 22 Control */
#define WB_TRIG_MUX_CH22_CTL_TRANSM_OUT_SEL_MASK WBGEN2_GEN_MASK(24, 8)
#define WB_TRIG_MUX_CH22_CTL_TRANSM_OUT_SEL_SHIFT 24
#define WB_TRIG_MUX_CH22_CTL_TRANSM_OUT_SEL_W(value) WBGEN2_GEN_WRITE(value, 24, 8)
#define WB_TRIG_MUX_CH22_CTL_TRANSM_OUT_SEL_R(reg) WBGEN2_GEN_READ(reg, 24, 8)

/* definitions for register: Channel 22 Dummy Register */

/* definitions for register: Channel 23 Control */

/* definitions for field: Receiver Source in reg: Channel 23 Control */
#define WB_TRIG_MUX_CH23_CTL_RCV_SRC          WBGEN2_GEN_MASK(0, 1)

/* definitions for field: Select Receiver Input in reg: Channel 23 Control */
#define WB_TRIG_MUX_CH23_CTL_RCV_IN_SEL_MASK  WBGEN2_GEN_MASK(8, 8)
#define WB_TRIG_MUX_CH23_CTL_RCV_IN_SEL_SHIFT 8
#define WB_TRIG_MUX_CH23_CTL_RCV_IN_SEL_W(value) WBGEN2_GEN_WRITE(value, 8, 8)
#define WB_TRIG_MUX_CH23_CTL_RCV_IN_SEL_R(reg) WBGEN2_GEN_READ(reg, 8, 8)

/* definitions for field: Transmitter Source in reg: Channel 23 Control */
#define WB_TRIG_MUX_CH23_CTL_TRANSM_SRC       WBGEN2_GEN_MASK(16, 1)

/* definitions for field: Select Transmitter Output in reg: Channel 23 Control */
#define WB_TRIG_MUX_CH23_CTL_TRANSM_OUT_SEL_MASK WBGEN2_GEN_MASK(24, 8)
#define WB_TRIG_MUX_CH23_CTL_TRANSM_OUT_SEL_SHIFT 24
#define WB_TRIG_MUX_CH23_CTL_TRANSM_OUT_SEL_W(value) WBGEN2_GEN_WRITE(value, 24, 8)
#define WB_TRIG_MUX_CH23_CTL_TRANSM_OUT_SEL_R(reg) WBGEN2_GEN_READ(reg, 24, 8)

/* definitions for register: Channel 23 Dummy Register */
/* [0x0]: REG Channel 0 Control */
#define WB_TRIG_MUX_REG_CH0_CTL 0x00000000
/* [0x4]: REG Channel 0 Dummy Register */
#define WB_TRIG_MUX_REG_CH0_DUMMY 0x00000004
/* [0x8]: REG Channel 1 Control */
#define WB_TRIG_MUX_REG_CH1_CTL 0x00000008
/* [0xc]: REG Channel 1 Dummy Register */
#define WB_TRIG_MUX_REG_CH1_DUMMY 0x0000000c
/* [0x10]: REG Channel 2 Control */
#define WB_TRIG_MUX_REG_CH2_CTL 0x00000010
/* [0x14]: REG Channel 2 Dummy Register */
#define WB_TRIG_MUX_REG_CH2_DUMMY 0x00000014
/* [0x18]: REG Channel 3 Control */
#define WB_TRIG_MUX_REG_CH3_CTL 0x00000018
/* [0x1c]: REG Channel 3 Dummy Register */
#define WB_TRIG_MUX_REG_CH3_DUMMY 0x0000001c
/* [0x20]: REG Channel 4 Control */
#define WB_TRIG_MUX_REG_CH4_CTL 0x00000020
/* [0x24]: REG Channel 4 Dummy Register */
#define WB_TRIG_MUX_REG_CH4_DUMMY 0x00000024
/* [0x28]: REG Channel 5 Control */
#define WB_TRIG_MUX_REG_CH5_CTL 0x00000028
/* [0x2c]: REG Channel 5 Dummy Register */
#define WB_TRIG_MUX_REG_CH5_DUMMY 0x0000002c
/* [0x30]: REG Channel 6 Control */
#define WB_TRIG_MUX_REG_CH6_CTL 0x00000030
/* [0x34]: REG Channel 6 Dummy Register */
#define WB_TRIG_MUX_REG_CH6_DUMMY 0x00000034
/* [0x38]: REG Channel 7 Control */
#define WB_TRIG_MUX_REG_CH7_CTL 0x00000038
/* [0x3c]: REG Channel 7 Dummy Register */
#define WB_TRIG_MUX_REG_CH7_DUMMY 0x0000003c
/* [0x40]: REG Channel 8 Control */
#define WB_TRIG_MUX_REG_CH8_CTL 0x00000040
/* [0x44]: REG Channel 8 Dummy Register */
#define WB_TRIG_MUX_REG_CH8_DUMMY 0x00000044
/* [0x48]: REG Channel 9 Control */
#define WB_TRIG_MUX_REG_CH9_CTL 0x00000048
/* [0x4c]: REG Channel 9 Dummy Register */
#define WB_TRIG_MUX_REG_CH9_DUMMY 0x0000004c
/* [0x50]: REG Channel 10 Control */
#define WB_TRIG_MUX_REG_CH10_CTL 0x00000050
/* [0x54]: REG Channel 10 Dummy Register */
#define WB_TRIG_MUX_REG_CH10_DUMMY 0x00000054
/* [0x58]: REG Channel 11 Control */
#define WB_TRIG_MUX_REG_CH11_CTL 0x00000058
/* [0x5c]: REG Channel 11 Dummy Register */
#define WB_TRIG_MUX_REG_CH11_DUMMY 0x0000005c
/* [0x60]: REG Channel 12 Control */
#define WB_TRIG_MUX_REG_CH12_CTL 0x00000060
/* [0x64]: REG Channel 12 Dummy Register */
#define WB_TRIG_MUX_REG_CH12_DUMMY 0x00000064
/* [0x68]: REG Channel 13 Control */
#define WB_TRIG_MUX_REG_CH13_CTL 0x00000068
/* [0x6c]: REG Channel 13 Dummy Register */
#define WB_TRIG_MUX_REG_CH13_DUMMY 0x0000006c
/* [0x70]: REG Channel 14 Control */
#define WB_TRIG_MUX_REG_CH14_CTL 0x00000070
/* [0x74]: REG Channel 14 Dummy Register */
#define WB_TRIG_MUX_REG_CH14_DUMMY 0x00000074
/* [0x78]: REG Channel 15 Control */
#define WB_TRIG_MUX_REG_CH15_CTL 0x00000078
/* [0x7c]: REG Channel 15 Dummy Register */
#define WB_TRIG_MUX_REG_CH15_DUMMY 0x0000007c
/* [0x80]: REG Channel 16 Control */
#define WB_TRIG_MUX_REG_CH16_CTL 0x00000080
/* [0x84]: REG Channel 16 Dummy Register */
#define WB_TRIG_MUX_REG_CH16_DUMMY 0x00000084
/* [0x88]: REG Channel 17 Control */
#define WB_TRIG_MUX_REG_CH17_CTL 0x00000088
/* [0x8c]: REG Channel 17 Dummy Register */
#define WB_TRIG_MUX_REG_CH17_DUMMY 0x0000008c
/* [0x90]: REG Channel 18 Control */
#define WB_TRIG_MUX_REG_CH18_CTL 0x00000090
/* [0x94]: REG Channel 18 Dummy Register */
#define WB_TRIG_MUX_REG_CH18_DUMMY 0x00000094
/* [0x98]: REG Channel 19 Control */
#define WB_TRIG_MUX_REG_CH19_CTL 0x00000098
/* [0x9c]: REG Channel 19 Dummy Register */
#define WB_TRIG_MUX_REG_CH19_DUMMY 0x0000009c
/* [0xa0]: REG Channel 20 Control */
#define WB_TRIG_MUX_REG_CH20_CTL 0x000000a0
/* [0xa4]: REG Channel 20 Dummy Register */
#define WB_TRIG_MUX_REG_CH20_DUMMY 0x000000a4
/* [0xa8]: REG Channel 21 Control */
#define WB_TRIG_MUX_REG_CH21_CTL 0x000000a8
/* [0xac]: REG Channel 21 Dummy Register */
#define WB_TRIG_MUX_REG_CH21_DUMMY 0x000000ac
/* [0xb0]: REG Channel 22 Control */
#define WB_TRIG_MUX_REG_CH22_CTL 0x000000b0
/* [0xb4]: REG Channel 22 Dummy Register */
#define WB_TRIG_MUX_REG_CH22_DUMMY 0x000000b4
/* [0xb8]: REG Channel 23 Control */
#define WB_TRIG_MUX_REG_CH23_CTL 0x000000b8
/* [0xbc]: REG Channel 23 Dummy Register */
#define WB_TRIG_MUX_REG_CH23_DUMMY 0x000000bc
#endif
