#--------------------------------
#       Virtex6 Board ML605
#--------------------------------

NET "sys_clk_n_i"                             LOC = H9   | IOSTANDARD = LVDS_25; # 5 on U11, 5 on U89 (DNP)
NET "sys_clk_p_i"                             LOC = J9   | IOSTANDARD = LVDS_25; # 4 on U11, 4 on U89 (DNP)

NET "rs232_rxd_i"                             LOC = J24  | IOSTANDARD = LVCMOS25; # 25 on U34
NET "rs232_txd_o"                             LOC = J25  | IOSTANDARD = LVCMOS25; # 24 on U34

NET "sys_rst_button_i"                        LOC = H10 | IOSTANDARD = "SSTL15" | TIG;

# MMCM Status
NET "fmc_mmcm_lock_led_o"                     LOC = "AP24"  |  IOSTANDARD = "LVCMOS25"; # GPIO_LED_C, DS16

# LMK clock distribution Status
NET "fmc_pll_status_led_o"                    LOC = "AD21"  |  IOSTANDARD = "LVCMOS25"; # GPIO_LED_W, DS17

#NET "led_south_o"                            LOC = "AH28"  |  IOSTANDARD = "LVCMOS25"; # GPIO_LED_S, DS18
#NET "led_east_o"                             LOC = "AE21"  |  IOSTANDARD = "LVCMOS25"; # GPIO_LED_E, DS19
#NET "led_north_o"                            LOC = "AH27"  |  IOSTANDARD = "LVCMOS25"; # GPIO_LED_N, DS20

#NET "board_led1_o"                           LOC = AC22 | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = SLOW; // User led 0
#NET "board_led2_o"                           LOC = AC24 | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = SLOW; // User led 1
#NET "board_led3_o"                           LOC = AE22 | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = SLOW; // User led 2

#--------------------------------
#      Button/LEDs Contraints
#--------------------------------

NET "buttons_i[0]"                            LOC = D22 | IOSTANDARD = LVCMOS25;
NET "buttons_i[1]"                            LOC = C22 | IOSTANDARD = LVCMOS25;
NET "buttons_i[2]"                            LOC = L21 | IOSTANDARD = LVCMOS25;
NET "buttons_i[3]"                            LOC = L20 | IOSTANDARD = LVCMOS25;
NET "buttons_i[4]"                            LOC = C18 | IOSTANDARD = LVCMOS25;
NET "buttons_i[5]"                            LOC = B18 | IOSTANDARD = LVCMOS25;
NET "buttons_i[6]"                            LOC = K22 | IOSTANDARD = LVCMOS25;
NET "buttons_i[7]"                            LOC = K21 | IOSTANDARD = LVCMOS25;
NET "leds_o[0]"                               LOC = AC22 | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = SLOW;
NET "leds_o[1]"                               LOC = AC24 | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = SLOW;
NET "leds_o[2]"                               LOC = AE22 | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = SLOW;
NET "leds_o[3]"                               LOC = AE23 | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = SLOW;
NET "leds_o[4]"                               LOC = AB23 | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = SLOW;
NET "leds_o[5]"                               LOC = AG23 | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = SLOW;
NET "leds_o[6]"                               LOC = AE24 | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = SLOW;
NET "leds_o[7]"                               LOC = AD24 | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = SLOW;

#--------------------------------
#       FMC Connector HPC
#--------------------------------

NET  "fmc_prsnt_i"                            LOC = AP25 | IOSTANDARD = "LVCMOS25";
NET  "fmc_pg_m2c_i"                           LOC = AK29 | IOSTANDARD = "LVCMOS25"; // LA31_N

// Trigger
NET "fmc_trig_dir_o"                          LOC = AK27 | IOSTANDARD = "LVCMOS25"; // LA28_P
NET "fmc_trig_term_o"                         LOC = AL25 | IOSTANDARD = "LVCMOS25"; // LA26_N
NET "fmc_trig_val_p_b"                        LOC = AG25 | IOSTANDARD = "BLVDS_25"; // LA32_P
NET "fmc_trig_val_n_b"                        LOC = AG26 | IOSTANDARD = "BLVDS_25"; // LA32_N

// Si571 clock gen
NET "si571_scl_pad_b"                         LOC = AE32 | IOSTANDARD = "LVCMOS25"; // HA12_N
NET "si571_sda_pad_b"                         LOC = AE31 | IOSTANDARD = "LVCMOS25"; // HA13_P
NET "fmc_si571_oe_o"                          LOC = AD32 | IOSTANDARD = "LVCMOS25"; // HA12_P

// AD9510 clock distribution PLL
NET "spi_ad9510_cs_o"                         LOC = AN18 | IOSTANDARD = "LVCMOS25";  // LA13_N
NET "spi_ad9510_sclk_o"                       LOC = AP19 | IOSTANDARD = "LVCMOS25"; // LA13_P
NET "spi_ad9510_mosi_o"                       LOC = AL18 | IOSTANDARD = "LVCMOS25"; // LA09_N
NET "spi_ad9510_miso_i"                       LOC = AN19 | IOSTANDARD = "LVCMOS25"; // LA14_P
NET "fmc_pll_function_o"                      LOC = AN20 | IOSTANDARD = "LVCMOS25"; // LA14_N
NET "fmc_pll_status_i"                        LOC = AM18 | IOSTANDARD = "LVCMOS25"; // LA09_P

#NET "fmc_fpga_clk_p_i"                       LOC = K24  | IOSTANDARD = "LVDS_25"; // CLK0_M2C_P
#NET "fmc_fpga_clk_n_i"                       LOC = K23  | IOSTANDARD = "LVDS_25"; // CLK0_M2C_N

// Clock reference selection (TS3USB221)
NET "fmc_clk_sel_o"                           LOC = AL29 | IOSTANDARD = "LVCMOS25"; // LA31_P

// EEPROM (multiplexer PCA9548)
NET "eeprom_scl_pad_b"                        LOC = AK9  | IOSTANDARD ="LVCMOS25"; # SCL C30
NET "eeprom_sda_pad_b"                        LOC = AE9  | IOSTANDARD ="LVCMOS25"; # SDA C31

// LM75 temperature monitor (can be used without multiplexer on KC705 board)
NET "lm75_scl_pad_b"                          LOC = AP30 | IOSTANDARD = "LVCMOS25"; // LA27_P
NET "lm75_sda_pad_b"                          LOC = AP31 | IOSTANDARD = "LVCMOS25"; // LA27_N
NET "fmc_lm75_temp_alarm_i"                   LOC = AJ27 | IOSTANDARD = "LVCMOS25"; // LA28_N

// LTC ADC control pins
NET "fmc_adc_pga_o"                           LOC = AG20 | IOSTANDARD = "LVCMOS25"; // LA06_P
NET "fmc_adc_shdn_o"                          LOC = AL20 | IOSTANDARD = "LVCMOS25"; // LA10_N
NET "fmc_adc_dith_o"                          LOC = AM20 | IOSTANDARD = "LVCMOS25"; // LA10_P
NET "fmc_adc_rand_o"                          LOC = AG21 | IOSTANDARD = "LVCMOS25"; // LA06_N

// LEDs
NET "fmc_led1_o"                              LOC = AN23 | IOSTANDARD = "LVCMOS25"; // LA16_N
NET "fmc_led2_o"                              LOC = AP22 | IOSTANDARD = "LVCMOS25"; // LA16_P
NET "fmc_led3_o"                              LOC = AM25 | IOSTANDARD = "LVCMOS25";  // LA26_P

#--------------------------------
#       FMC Connector HPC
#         LTC ADC lines
#--------------------------------

// ADC0
NET "fmc_adc0_clk_i"                          LOC = AN27  | IOSTANDARD = "LVCMOS25"; // LA17_CC_P

NET "fmc_adc0_data_i[0]"                      LOC = AN30  | IOSTANDARD = "LVCMOS25"; // LA24_P
NET "fmc_adc0_data_i[1]"                      LOC = AM30  | IOSTANDARD = "LVCMOS25"; // LA24_N
NET "fmc_adc0_data_i[2]"                      LOC = AN28  | IOSTANDARD = "LVCMOS25"; // LA25_P
NET "fmc_adc0_data_i[3]"                      LOC = AM28  | IOSTANDARD = "LVCMOS25"; // LA25_N
NET "fmc_adc0_data_i[4]"                      LOC = AN29  | IOSTANDARD = "LVCMOS25"; // LA21_P
NET "fmc_adc0_data_i[5]"                      LOC = AP29  | IOSTANDARD = "LVCMOS25"; // LA21_N
NET "fmc_adc0_data_i[6]"                      LOC = AP27  | IOSTANDARD = "LVCMOS25"; // LA22_P
NET "fmc_adc0_data_i[7]"                      LOC = AP26  | IOSTANDARD = "LVCMOS25"; // LA22_N
NET "fmc_adc0_data_i[8]"                      LOC = AM26  | IOSTANDARD = "LVCMOS25"; // LA23_N
NET "fmc_adc0_data_i[9]"                      LOC = AN24  | IOSTANDARD = "LVCMOS25"; // LA19_N
NET "fmc_adc0_data_i[10]"                     LOC = AJ25  | IOSTANDARD = "LVCMOS25"; // LA18_CC_N
NET "fmc_adc0_data_i[11]"                     LOC = AL26  | IOSTANDARD = "LVCMOS25"; // LA23_P
NET "fmc_adc0_data_i[12]"                     LOC = AL24  | IOSTANDARD = "LVCMOS25"; // LA20_N
NET "fmc_adc0_data_i[13]"                     LOC = AN25  | IOSTANDARD = "LVCMOS25"; // LA19_P
NET "fmc_adc0_data_i[14]"                     LOC = AH25  | IOSTANDARD = "LVCMOS25"; // LA18_CC_P
NET "fmc_adc0_data_i[15]"                     LOC = AK23  | IOSTANDARD = "LVCMOS25"; // LA20_P
NET "fmc_adc0_of_i"                           LOC = AL28  | IOSTANDARD = "LVCMOS25"; // LA29_P

// ADC1
NET "fmc_adc1_clk_i"                          LOC = V30   | IOSTANDARD = "LVCMOS25"; // HA17_CC_P

NET "fmc_adc1_data_i[15]"                     LOC = AD34  | IOSTANDARD = "LVCMOS25"; // HA10_P
NET "fmc_adc1_data_i[14]"                     LOC = AG33  | IOSTANDARD = "LVCMOS25"; // HA11_P
NET "fmc_adc1_data_i[13]"                     LOC = AC34  | IOSTANDARD = "LVCMOS25"; // HA10_N
NET "fmc_adc1_data_i[12]"                     LOC = AG32  | IOSTANDARD = "LVCMOS25"; // HA11_N
NET "fmc_adc1_data_i[11]"                     LOC = AB32  | IOSTANDARD = "LVCMOS25"; // HA15_P
NET "fmc_adc1_data_i[10]"                     LOC = AA30  | IOSTANDARD = "LVCMOS25"; // HA14_P
NET "fmc_adc1_data_i[9]"                      LOC = AC32  | IOSTANDARD = "LVCMOS25"; // HA15_N
NET "fmc_adc1_data_i[8]"                      LOC = AA31  | IOSTANDARD = "LVCMOS25"; // HA14_N
NET "fmc_adc1_data_i[7]"                      LOC = T34   | IOSTANDARD = "LVCMOS25"; // HA18_N
NET "fmc_adc1_data_i[6]"                      LOC = T33   | IOSTANDARD = "LVCMOS25"; // HA18_P
NET "fmc_adc1_data_i[5]"                      LOC = U32   | IOSTANDARD = "LVCMOS25"; // HA19_N
NET "fmc_adc1_data_i[4]"                      LOC = U31   | IOSTANDARD = "LVCMOS25"; // HA21_P
NET "fmc_adc1_data_i[3]"                      LOC = U28   | IOSTANDARD = "LVCMOS25"; // HA22_P
NET "fmc_adc1_data_i[2]"                      LOC = U30   | IOSTANDARD = "LVCMOS25"; // HA21_N
NET "fmc_adc1_data_i[1]"                      LOC = U26   | IOSTANDARD = "LVCMOS25"; // HA23_P
NET "fmc_adc1_data_i[0]"                      LOC = V29   | IOSTANDARD = "LVCMOS25"; // HA22_N
NET "fmc_adc1_of_i"                           LOC = U27   | IOSTANDARD = "LVCMOS25"; // HA23_N

// ADC2
NET "fmc_adc2_clk_i"                          LOC = AF20  | IOSTANDARD = "LVCMOS25"; // LA00_CC_P

NET "fmc_adc2_data_i[15]"                     LOC = AK19  | IOSTANDARD = "LVCMOS25"; // LA01_CC_P
NET "fmc_adc2_data_i[14]"                     LOC = AC20  | IOSTANDARD = "LVCMOS25"; // LA02_P
NET "fmc_adc2_data_i[13]"                     LOC = AL19  | IOSTANDARD = "LVCMOS25"; // LA01_CC_N
NET "fmc_adc2_data_i[12]"                     LOC = AD20  | IOSTANDARD = "LVCMOS25"; // LA02_N
NET "fmc_adc2_data_i[11]"                     LOC = AD19  | IOSTANDARD = "LVCMOS25"; // LA03_N
NET "fmc_adc2_data_i[10]"                     LOC = AC19  | IOSTANDARD = "LVCMOS25"; // LA03_P
NET "fmc_adc2_data_i[9]"                      LOC = AE19  | IOSTANDARD = "LVCMOS25"; // LA04_N
NET "fmc_adc2_data_i[8]"                      LOC = AF19  | IOSTANDARD = "LVCMOS25"; // LA04_P
NET "fmc_adc2_data_i[7]"                      LOC = AH22  | IOSTANDARD = "LVCMOS25"; // LA05_N
NET "fmc_adc2_data_i[6]"                      LOC = AG22  | IOSTANDARD = "LVCMOS25"; // LA05_P
NET "fmc_adc2_data_i[5]"                      LOC = AJ22  | IOSTANDARD = "LVCMOS25"; // LA08_N
NET "fmc_adc2_data_i[4]"                      LOC = AK22  | IOSTANDARD = "LVCMOS25"; // LA08_P
NET "fmc_adc2_data_i[3]"                      LOC = AJ21  | IOSTANDARD = "LVCMOS25"; // LA07_N
NET "fmc_adc2_data_i[2]"                      LOC = AK21  | IOSTANDARD = "LVCMOS25"; // LA07_P
NET "fmc_adc2_data_i[1]"                      LOC = AL21  | IOSTANDARD = "LVCMOS25"; // LA12_N
NET "fmc_adc2_data_i[0]"                      LOC = AM21  | IOSTANDARD = "LVCMOS25"; // LA12_P
NET "fmc_adc2_of_i"                           LOC = AM22  | IOSTANDARD = "LVCMOS25"; // LA11_P

// ADC3
NET "fmc_adc3_clk_i"                          LOC = AD29  | IOSTANDARD = "LVCMOS25"; // HA01_CC_P

NET "fmc_adc3_data_i[15]"                     LOC = AF33  | IOSTANDARD = "LVCMOS25"; // HA00_CC_N
NET "fmc_adc3_data_i[14]"                     LOC = AE33  | IOSTANDARD = "LVCMOS25"; // HA00_CC_P
NET "fmc_adc3_data_i[13]"                     LOC = AC27  | IOSTANDARD = "LVCMOS25"; // HA05_N
NET "fmc_adc3_data_i[12]"                     LOC = AB27  | IOSTANDARD = "LVCMOS25"; // HA05_P
NET "fmc_adc3_data_i[11]"                     LOC = AC28  | IOSTANDARD = "LVCMOS25"; // HA04_N
NET "fmc_adc3_data_i[10]"                     LOC = AB28  | IOSTANDARD = "LVCMOS25"; // HA04_P
NET "fmc_adc3_data_i[9]"                      LOC = AB31  | IOSTANDARD = "LVCMOS25"; // HA09_N
NET "fmc_adc3_data_i[8]"                      LOC = AB30  | IOSTANDARD = "LVCMOS25"; // HA09_P
NET "fmc_adc3_data_i[7]"                      LOC = Y26   | IOSTANDARD = "LVCMOS25"; // HA03_N
NET "fmc_adc3_data_i[6]"                      LOC = AA25  | IOSTANDARD = "LVCMOS25"; // HA03_P
NET "fmc_adc3_data_i[5]"                      LOC = AG31  | IOSTANDARD = "LVCMOS25"; // HA08_P
NET "fmc_adc3_data_i[4]"                      LOC = AB25  | IOSTANDARD = "LVCMOS25"; // HA02_P
NET "fmc_adc3_data_i[3]"                      LOC = AA26  | IOSTANDARD = "LVCMOS25"; // HA07_P
NET "fmc_adc3_data_i[2]"                      LOC = AC25  | IOSTANDARD = "LVCMOS25"; // HA02_N
NET "fmc_adc3_data_i[1]"                      LOC = AA28  | IOSTANDARD = "LVCMOS25"; // HA06_P
NET "fmc_adc3_data_i[0]"                      LOC = AB26  | IOSTANDARD = "LVCMOS25"; // HA07_N
NET "fmc_adc3_of_i"                           LOC = AA29  | IOSTANDARD = "LVCMOS25"; // HA06_N

#--------------------------------
#            Ethernet Contraints.
#              MII 10/100 Mode
#--------------------------------

NET "mrstn_o"                                 LOC = AH13;
NET "mcoll_pad_i"                             LOC = AK13;   ## 114 on U80
NET "mcrs_pad_i"                              LOC = AL13;   ## 115 on U80
# NET "PHY_INT"                               LOC = AH14;   ## 32  on U80
NET "mdc_pad_o"                               LOC = AP14;   ## 35  on U80
NET "md_pad_b"                                LOC = AN14;   ## 33  on U80
# NET "PHY_RESET"                             LOC = AH13;   ## 36  on U80
NET "mrx_clk_pad_i"                           LOC = AP11;   ## 7   on U80
NET "mrxdv_pad_i"                             LOC = AM13;   ## 4   on U80
NET "mrxd_pad_i[0]"                           LOC = AN13;   ## 3   on U80
NET "mrxd_pad_i[1]"                           LOC = AF14;   ## 128 on U80
NET "mrxd_pad_i[2]"                           LOC = AE14;   ## 126 on U80
NET "mrxd_pad_i[3]"                           LOC = AN12;   ## 125 on U80
# NET "PHY_RXD4"                              LOC = AM12;   ## 124 on U80
# NET "PHY_RXD5"                              LOC = AD11;   ## 123 on U80
# NET "PHY_RXD6"                              LOC = AC12;   ## 121 on U80
# NET "PHY_RXD7"                              LOC = AC13;   ## 120 on U80
NET "mrxerr_pad_i"                            LOC = AG12;   ## 9   on U80
NET "mtx_clk_pad_i"                           LOC = AD12;   ## 10  on U80
NET "mtxen_pad_o"                             LOC = AJ10;   ## 16  on U80
# NET "PHY_TXC_GTXCLK"                        LOC = AH12;   ## 14  on U80
NET "mtxd_pad_o[0]"                           LOC = AM11;   ## 18  on U80
NET "mtxd_pad_o[1]"                           LOC = AL11;   ## 19  on U80
NET "mtxd_pad_o[2]"                           LOC = AG10;   ## 20  on U80
NET "mtxd_pad_o[3]"                           LOC = AG11;   ## 24  on U80
# NET "PHY_TXD4"                              LOC = AL10;   ## 25  on U80
# NET "PHY_TXD5"                              LOC = AM10;   ## 26  on U80
# NET "PHY_TXD6"                              LOC = AE11;   ## 28  on U80
# NET "PHY_TXD7"                              LOC = AF11;   ## 29  on U80
NET "mtxerr_pad_o"                            LOC = AH10;   ## 13  on U80

#--------------------------------
#     Pinout and Related I/O Constraints
#--------------------------------

# On ML605 kit, all clock pins are assigned to MRCC pins. However, two of them
# (fmc_adc1_clk and fmc_adc3_clk) are located in the outer left/right column
# I/Os. These locations cannot connect to BUFG primitives, only inner (center)
# left/right column I/Os on the same half top/bottom can!
#
# For 7-series FPGAs there is no such impediment, apparently.

#--------------------------------
#       DIFF TERM
#--------------------------------
NET "sys_clk_p_i" DIFF_TERM = TRUE;
NET "sys_clk_n_i" DIFF_TERM = TRUE;

NET "fmc_trig_val_p_b" DIFF_TERM = TRUE;
NET "fmc_trig_val_n_b" DIFF_TERM = TRUE;

#NET "fmc_fpga_clk_p_i" DIFF_TERM = TRUE;
#NET "fmc_fpga_clk_n_i" DIFF_TERM = TRUE;

#--------------------------------
#       Timing constraints
#--------------------------------
#--------------------------------
#             Clocks
#--------------------------------
NET "sys_clk_p_i" TNM_NET = sys_clk_p_i;
TIMESPEC TS_sys_clk_p_i = PERIOD "sys_clk_p_i" 200 MHz HIGH 50% INPUT_JITTER 50 ps;

// real jitter is about 22ps peak-to-peak
NET "fmc_adc0_clk_i" TNM_NET = fmc_adc0_clk_i;
// TIMESPEC TS_fmc_adc0_clk_i = PERIOD "fmc_adc0_clk_i" 130 MHz HIGH 50% INPUT_JITTER 50 ps;
TIMESPEC TS_fmc_adc0_clk_i = PERIOD "fmc_adc0_clk_i" 112.583 MHz HIGH 50% INPUT_JITTER 50 ps;

NET "fmc_adc1_clk_i" TNM_NET = fmc_adc1_clk_i;
// TIMESPEC TS_fmc_adc1_clk_i = PERIOD "fmc_adc1_clk_i" 130 MHz HIGH 50% INPUT_JITTER 50 ps;
TIMESPEC TS_fmc_adc1_clk_i = PERIOD "fmc_adc1_clk_i" 112.583 MHz HIGH 50% INPUT_JITTER 50 ps;

NET "fmc_adc2_clk_i" TNM_NET = fmc_adc2_clk_i;
// TIMESPEC TS_fmc_adc2_clk_i = PERIOD "fmc_adc2_clk_i" 130 MHz HIGH 50% INPUT_JITTER 50 ps;
TIMESPEC TS_fmc_adc2_clk_i = PERIOD "fmc_adc2_clk_i" 112.583 MHz HIGH 50% INPUT_JITTER 50 ps;

NET "fmc_adc3_clk_i" TNM_NET = fmc_adc3_clk_i;
// TIMESPEC TS_fmc_adc3_clk_i = PERIOD "fmc_adc3_clk_i" 130 MHz HIGH 50% INPUT_JITTER 50 ps;
TIMESPEC TS_fmc_adc3_clk_i = PERIOD "fmc_adc3_clk_i" 112.583 MHz HIGH 50% INPUT_JITTER 50 ps;

//NET "fmc_fpga_clk_p" TNM_NET = fmc_fpga_clk_p;
//TIMESPEC TS_fmc_fpga_clk_p = PERIOD "fmc_fpga_clk_p" 130 MHz HIGH 50% INPUT_JITTER 40 ps;

#--------------------------------
#             Data
#--------------------------------
#INST "fmc_adc_130m_4ch_i/ltcInterface_adc0_i/IDELAYCTRL_adc0_inst" LOC = IDELAYCTRL_X0Y1;
#INST "fmc_adc_130m_4ch_i/ltcInterface_adc1_i/IDELAYCTRL_adc0_inst" LOC = IDELAYCTRL_X0Y2;
#INST "fmc_adc_130m_4ch_i/ltcInterface_adc2_i/IDELAYCTRL_adc0_inst" LOC = IDELAYCTRL_X0Y0;
#INST "fmc_adc_130m_4ch_i/ltcInterface_adc3_i/IDELAYCTRL_adc0_inst" LOC = IDELAYCTRL_X0Y1; // same as ADC1

// including 50ps jitter, for 130MHz clock
// since design uses copy of input ADC clock
// there is additional delay for clock/ data (tC)

INST "fmc_adc0_data_i<*>" TNM = fmc_adc0_data_i;
INST "fmc_adc1_data_i<*>" TNM = fmc_adc1_data_i;
INST "fmc_adc2_data_i<*>" TNM = fmc_adc2_data_i;
INST "fmc_adc3_data_i<*>" TNM = fmc_adc3_data_i;

TIMEGRP "fmc_adc0_data_i" OFFSET = IN -0.7 ns VALID 7.6 ns BEFORE "fmc_adc0_clk_i";
TIMEGRP "fmc_adc1_data_i" OFFSET = IN -0.7 ns VALID 7.6 ns BEFORE "fmc_adc1_clk_i";
TIMEGRP "fmc_adc2_data_i" OFFSET = IN -0.7 ns VALID 7.6 ns BEFORE "fmc_adc2_clk_i";
TIMEGRP "fmc_adc3_data_i" OFFSET = IN -0.7 ns VALID 7.6 ns BEFORE "fmc_adc3_clk_i";
