echo "project open dbe_bpm_ebone.xise" > run.tcl
echo "process run {Generate Programming File} -force rerun_all" >> run.tcl
xtclsh run.tcl

Started : "Synthesize - XST".
Running xst...
Command Line: xst -intstyle ise -ifn "/home/lerwys/Repos/bpm-sw/hdl/syn/dbe_bpm_ebone/dbe_bpm_ebone.xst" -ofn "/home/lerwys/Repos/bpm-sw/hdl/syn/dbe_bpm_ebone/dbe_bpm_ebone.syr"
Reading design: dbe_bpm_ebone.prj
INFO:Xst - Part-select index evaluated to out of bound value may lead to incorrect synthesis results; it is recommended not to use them in RTL

=========================================================================
*                          HDL Parsing                                  *
=========================================================================
Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/timescale.v" into library work
Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_txcounters.v" into library work
Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/timescale.v" included at line 85.
Parsing module <eth_txcounters>.
Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_clockgen.v" into library work
Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/timescale.v" included at line 69.
Parsing module <eth_clockgen>.
Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_receivecontrol.v" into library work
Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/timescale.v" included at line 77.
Parsing module <eth_receivecontrol>.
Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_txethmac.v" into library work
Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/timescale.v" included at line 94.
Parsing module <eth_txethmac>.
Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_cop.v" into library work
Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_defines.v" included at line 64.
Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/timescale.v" included at line 65.
Parsing module <eth_cop>.
Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_registers.v" into library work
Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/ethmac_defines.v" included at line 165.
WARNING:HDLCompiler:572 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/ethmac_defines.v" Line 198: Macro <ETH_TX_FIFO_CNT_WIDTH> is redefined.
WARNING:HDLCompiler:572 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/ethmac_defines.v" Line 199: Macro <ETH_TX_FIFO_DEPTH> is redefined.
WARNING:HDLCompiler:572 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/ethmac_defines.v" Line 220: Macro <ETH_RX_FIFO_CNT_WIDTH> is redefined.
WARNING:HDLCompiler:572 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/ethmac_defines.v" Line 221: Macro <ETH_RX_FIFO_DEPTH> is redefined.
Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/timescale.v" included at line 166.
Parsing module <eth_registers>.
Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_txstatem.v" into library work
Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/timescale.v" included at line 87.
Parsing module <eth_txstatem>.
Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_crc.v" into library work
Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/timescale.v" included at line 77.
Parsing module <eth_crc>.
Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_register.v" into library work
Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/timescale.v" included at line 74.
Parsing module <eth_register>.
Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_wishbone.v" into library work
Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/ethmac_defines.v" included at line 41.
Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/timescale.v" included at line 42.
Parsing module <eth_wishbone>.
Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_defines.v" into library work
WARNING:HDLCompiler:572 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_defines.v" Line 317: Macro <ETH_TX_FIFO_CNT_WIDTH> is redefined.
WARNING:HDLCompiler:572 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_defines.v" Line 318: Macro <ETH_TX_FIFO_DEPTH> is redefined.
WARNING:HDLCompiler:572 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_defines.v" Line 322: Macro <ETH_RX_FIFO_CNT_WIDTH> is redefined.
WARNING:HDLCompiler:572 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_defines.v" Line 323: Macro <ETH_RX_FIFO_DEPTH> is redefined.
Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_rxaddrcheck.v" into library work
Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/timescale.v" included at line 67.
Parsing module <eth_rxaddrcheck>.
Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_fifo.v" into library work
Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/ethmac_defines.v" included at line 42.
WARNING:HDLCompiler:572 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/ethmac_defines.v" Line 198: Macro <ETH_TX_FIFO_CNT_WIDTH> is redefined.
WARNING:HDLCompiler:572 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/ethmac_defines.v" Line 199: Macro <ETH_TX_FIFO_DEPTH> is redefined.
WARNING:HDLCompiler:572 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/ethmac_defines.v" Line 220: Macro <ETH_RX_FIFO_CNT_WIDTH> is redefined.
WARNING:HDLCompiler:572 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/ethmac_defines.v" Line 221: Macro <ETH_RX_FIFO_DEPTH> is redefined.
Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/timescale.v" included at line 43.
Parsing module <eth_fifo>.
Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_rxcounters.v" into library work
Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/timescale.v" included at line 43.
Parsing module <eth_rxcounters>.
Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_random.v" into library work
Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/timescale.v" included at line 80.
Parsing module <eth_random>.
Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_maccontrol.v" into library work
Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/timescale.v" included at line 85.
Parsing module <eth_maccontrol>.
Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_rxethmac.v" into library work
Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/timescale.v" included at line 43.
Parsing module <eth_rxethmac>.
Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/ethmac_defines.v" into library work
Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_rxstatem.v" into library work
Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/timescale.v" included at line 85.
Parsing module <eth_rxstatem>.
Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_macstatus.v" into library work
Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/timescale.v" included at line 112.
Parsing module <eth_macstatus>.
Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_shiftreg.v" into library work
Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/timescale.v" included at line 75.
Parsing module <eth_shiftreg>.
Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/xilinx_dist_ram_16x32.v" into library work
Parsing module <xilinx_dist_ram_16x32>.
Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/ethmac.v" into library work
Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/ethmac_defines.v" included at line 43.
Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/timescale.v" included at line 44.
Parsing module <ethmac>.
Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_spram_256x32.v" into library work
Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/ethmac_defines.v" included at line 74.
Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/timescale.v" included at line 75.
Parsing module <eth_spram_256x32>.
Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_miim.v" into library work
Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/timescale.v" included at line 83.
Parsing module <eth_miim>.
Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_top.v" into library work
Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/ethmac_defines.v" included at line 240.
Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/timescale.v" included at line 241.
Parsing module <eth_top>.
Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_outputcontrol.v" into library work
Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/timescale.v" included at line 69.
Parsing module <eth_outputcontrol>.
Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_transmitcontrol.v" into library work
Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/timescale.v" included at line 82.
Parsing module <eth_transmitcontrol>.
Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v" into library work
Parsing module <sockit_owm>.
Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v" into library work
Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v" included at line 41.
Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/timescale.v" included at line 42.
Parsing module <spi_clgen>.
Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v" into library work
Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v" included at line 44.
Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/timescale.v" included at line 45.
Parsing module <spi_shift>.
Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v" into library work
Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v" included at line 44.
Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/timescale.v" included at line 45.
Parsing module <spi_top>.
Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" into library work
Parsing module <lm32_top_full_debug>.
Parsing module <lm32_mc_arithmetic_full_debug>.
Parsing module <lm32_cpu_full_debug>.
Parsing module <lm32_load_store_unit_full_debug>.
Parsing module <lm32_decoder_full_debug>.
Parsing module <lm32_icache_full_debug>.
Parsing module <lm32_dcache_full_debug>.
Parsing module <lm32_debug_full_debug>.
Parsing module <lm32_instruction_unit_full_debug>.
Parsing module <lm32_jtag_full_debug>.
Parsing module <lm32_interrupt_full_debug>.
Parsing module <lm32_top_full>.
Parsing module <lm32_mc_arithmetic_full>.
Parsing module <lm32_cpu_full>.
Parsing module <lm32_load_store_unit_full>.
Parsing module <lm32_decoder_full>.
Parsing module <lm32_icache_full>.
Parsing module <lm32_dcache_full>.
Parsing module <lm32_instruction_unit_full>.
Parsing module <lm32_interrupt_full>.
Parsing module <lm32_top_medium_debug>.
Parsing module <lm32_mc_arithmetic_medium_debug>.
Parsing module <lm32_cpu_medium_debug>.
Parsing module <lm32_load_store_unit_medium_debug>.
Parsing module <lm32_decoder_medium_debug>.
Parsing module <lm32_icache_medium_debug>.
Parsing module <lm32_debug_medium_debug>.
Parsing module <lm32_instruction_unit_medium_debug>.
Parsing module <lm32_jtag_medium_debug>.
Parsing module <lm32_interrupt_medium_debug>.
Parsing module <lm32_top_medium_icache_debug>.
Parsing module <lm32_mc_arithmetic_medium_icache_debug>.
Parsing module <lm32_cpu_medium_icache_debug>.
Parsing module <lm32_load_store_unit_medium_icache_debug>.
Parsing module <lm32_decoder_medium_icache_debug>.
Parsing module <lm32_icache_medium_icache_debug>.
Parsing module <lm32_debug_medium_icache_debug>.
Parsing module <lm32_instruction_unit_medium_icache_debug>.
Parsing module <lm32_jtag_medium_icache_debug>.
Parsing module <lm32_interrupt_medium_icache_debug>.
Parsing module <lm32_top_medium_icache>.
Parsing module <lm32_mc_arithmetic_medium_icache>.
Parsing module <lm32_cpu_medium_icache>.
Parsing module <lm32_load_store_unit_medium_icache>.
Parsing module <lm32_decoder_medium_icache>.
Parsing module <lm32_icache_medium_icache>.
Parsing module <lm32_instruction_unit_medium_icache>.
Parsing module <lm32_interrupt_medium_icache>.
Parsing module <lm32_top_medium>.
Parsing module <lm32_mc_arithmetic_medium>.
Parsing module <lm32_cpu_medium>.
Parsing module <lm32_load_store_unit_medium>.
Parsing module <lm32_decoder_medium>.
Parsing module <lm32_instruction_unit_medium>.
Parsing module <lm32_interrupt_medium>.
Parsing module <lm32_top_minimal>.
Parsing module <lm32_mc_arithmetic_minimal>.
Parsing module <lm32_cpu_minimal>.
Parsing module <lm32_load_store_unit_minimal>.
Parsing module <lm32_decoder_minimal>.
Parsing module <lm32_instruction_unit_minimal>.
Parsing module <lm32_interrupt_minimal>.
Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_mc_arithmetic.v" into library work
Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v" included at line 29.
Parsing module <lm32_mc_arithmetic>.
Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v" into library work
Parsing module <jtag_cores>.
Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v" into library work
Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v" included at line 29.
Parsing module <lm32_adder>.
Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v" into library work
Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v" included at line 28.
Parsing module <lm32_addsub>.
Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.v" into library work
Parsing module <lm32_dp_ram>.
Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v" into library work
Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v" included at line 29.
Parsing module <lm32_logic_op>.
Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.v" into library work
Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v" included at line 34.
Parsing module <lm32_ram>.
Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v" into library work
Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v" included at line 29.
Parsing module <lm32_shifter>.
Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic/lm32_multiplier.v" into library work
Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic/../../src/lm32_include.v" included at line 29.
Parsing module <lm32_multiplier>.
Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/virtex6/jtag_tap.v" into library work
Parsing module <jtag_tap>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/genram_pkg.vhd" into library work
Parsing package <genram_pkg>.
Parsing package body <genram_pkg>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd" into library work
Parsing package <wishbone_pkg>.
Parsing package body <wishbone_pkg>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gencores_pkg.vhd" into library work
Parsing package <gencores_pkg>.
Parsing package body <gencores_pkg>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_stream/wb_stream_pkg.vhd" into library work
Parsing package <wb_stream_pkg>.
Parsing package body <wb_stream_pkg>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_stream/generic/wb_stream_generic_pkg.vhd" into library work
Parsing package <wb_stream_generic_pkg>.
Parsing package body <wb_stream_generic_pkg>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc516/fmc516_pkg.vhd" into library work
Parsing package <fmc516_pkg>.
Parsing package body <fmc516_pkg>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/fabric/wr_fabric_pkg.vhd" into library work
Parsing package <wr_fabric_pkg>.
Parsing package body <wr_fabric_pkg>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/dbe_wishbone_pkg.vhd" into library work
Parsing package <dbe_wishbone_pkg>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/ethmac_pkg.vhd" into library work
Parsing package <ethmac_pkg>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/etherbone_pkg.vhd" into library work
Parsing package <etherbone_pkg>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_ebone/dbe_bpm_ebone.vhd" into library work
Parsing entity <dbe_bpm_ebone>.
Parsing architecture <rtl> of entity <dbe_bpm_ebone>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_ebone/sys_pll.vhd" into library work
Parsing entity <sys_pll>.
Parsing architecture <syn> of entity <sys_pll>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_ebone/clk_gen.vhd" into library work
Parsing entity <clk_gen>.
Parsing architecture <syn> of entity <clk_gen>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_common/dbe_common_pkg.vhd" into library work
Parsing package <dbe_common_pkg>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/wb_ethmac.vhd" into library work
Parsing entity <wb_ethmac>.
Parsing architecture <rtl> of entity <wb_ethmac>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/xwb_ethmac.vhd" into library work
Parsing entity <xwb_ethmac>.
Parsing architecture <rtl> of entity <xwb_ethmac>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/fabric/xwb_fabric_sink.vhd" into library work
Parsing entity <xwb_fabric_sink>.
Parsing architecture <rtl> of entity <xwb_fabric_sink>.
Parsing entity <wb_fabric_sink>.
Parsing architecture <wrapper> of entity <wb_fabric_sink>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/fabric/xwb_fabric_source.vhd" into library work
Parsing entity <xwb_fabric_source>.
Parsing architecture <rtl> of entity <xwb_fabric_source>.
Parsing entity <wb_fabric_source>.
Parsing architecture <wrapper> of entity <wb_fabric_source>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_stream/xwb_stream_sink.vhd" into library work
Parsing entity <xwb_stream_sink>.
Parsing architecture <rtl> of entity <xwb_stream_sink>.
Parsing entity <wb_stream_sink>.
Parsing architecture <wrapper> of entity <wb_stream_sink>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_stream/xwb_stream_source.vhd" into library work
Parsing entity <xwb_stream_source>.
Parsing architecture <rtl> of entity <xwb_stream_source>.
Parsing entity <wb_stream_source>.
Parsing architecture <wrapper> of entity <wb_stream_source>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/xfmc150_regs_pkg.vhd" into library work
Parsing package <fmc150_wbgen2_pkg>.
Parsing package body <fmc150_wbgen2_pkg>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/wb_fmc150.vhd" into library work
Parsing entity <wb_fmc150>.
Parsing architecture <rtl> of entity <wb_fmc150>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/xwb_fmc150.vhd" into library work
Parsing entity <xwb_fmc150>.
Parsing architecture <rtl> of entity <xwb_fmc150>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/wb_fmc150_port.vhd" into library work
Parsing entity <wb_fmc150_port>.
Parsing architecture <syn> of entity <wb_fmc150_port>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc516/wbgen/wb_fmc516_regs_pkg.vhd" into library work
Parsing package <fmc516_wbgen2_pkg>.
Parsing package body <fmc516_wbgen2_pkg>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc516/wb_fmc516.vhd" into library work
Parsing entity <wb_fmc516>.
Parsing architecture <rtl> of entity <wb_fmc516>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc516/xwb_fmc516.vhd" into library work
Parsing entity <xwb_fmc516>.
Parsing architecture <rtl> of entity <xwb_fmc516>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc516/fmc516_adc_clk.vhd" into library work
Parsing entity <fmc516_adc_clk>.
Parsing architecture <rtl> of entity <fmc516_adc_clk>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc516/fmc516_adc_data.vhd" into library work
Parsing entity <fmc516_adc_data>.
Parsing architecture <rtl> of entity <fmc516_adc_data>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc516/fmc516_adc_buf.vhd" into library work
Parsing entity <fmc516_adc_buf>.
Parsing architecture <rtl> of entity <fmc516_adc_buf>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc516/fmc516_adc_iface.vhd" into library work
Parsing entity <fmc516_adc_iface>.
Parsing architecture <rtl> of entity <fmc516_adc_iface>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc516/wbgen/wb_fmc516_regs.vhd" into library work
Parsing entity <wb_fmc516_regs>.
Parsing architecture <syn> of entity <wb_fmc516_regs>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac_adapter/xwb_ethmac_adapter.vhd" into library work
Parsing entity <xwb_ethmac_adapter>.
Parsing architecture <behavioral> of entity <xwb_ethmac_adapter>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_stream/generic/wb_stream_sink_gen.vhd" into library work
Parsing entity <wb_stream_sink_gen>.
Parsing architecture <rtl> of entity <wb_stream_sink_gen>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_stream/generic/wb_stream_source_gen.vhd" into library work
Parsing entity <wb_stream_source_gen>.
Parsing architecture <rtl> of entity <wb_stream_source_gen>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_stream/generic/xwb_stream_sink_gen.vhd" into library work
Parsing entity <xwb_stream_sink_gen>.
Parsing architecture <rtl> of entity <xwb_stream_sink_gen>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_stream/generic/xwb_stream_source_gen.vhd" into library work
Parsing entity <xwb_stream_source_gen>.
Parsing architecture <rtl> of entity <xwb_stream_source_gen>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/adc/adc_channel_lvds_ddr.vhd" into library work
Parsing entity <adc_channel_lvds_ddr>.
Parsing architecture <rtl> of entity <adc_channel_lvds_ddr>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/adc/adc_pkg.vhd" into library work
Parsing package <adc_pkg>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/adc/strobe_lvds.vhd" into library work
Parsing entity <strobe_lvds>.
Parsing architecture <rtl> of entity <strobe_lvds>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/fmc150/ads62p49_ctrl.vhd" into library work
Parsing entity <ads62p49_ctrl>.
Parsing architecture <ads62p49_ctrl_syn> of entity <ads62p49_ctrl>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/fmc150/amc7823_ctrl.vhd" into library work
Parsing entity <amc7823_ctrl>.
Parsing architecture <amc7823_ctrl_syn> of entity <amc7823_ctrl>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/fmc150/cdce72010_ctrl.vhd" into library work
Parsing entity <cdce72010_ctrl>.
Parsing architecture <cdce72010_ctrl_syn> of entity <cdce72010_ctrl>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/fmc150/dac3283_ctrl.vhd" into library work
Parsing entity <dac3283_ctrl>.
Parsing architecture <dac3283_ctrl_syn> of entity <dac3283_ctrl>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/fmc150/fmc150_adc_if.vhd" into library work
Parsing entity <fmc150_adc_if>.
Parsing architecture <rtl> of entity <fmc150_adc_if>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/fmc150/fmc150_dac_if.vhd" into library work
Parsing entity <fmc150_dac_if>.
Parsing architecture <rtl> of entity <fmc150_dac_if>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/fmc150/fmc150_pkg.vhd" into library work
Parsing package <fmc150_pkg>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/fmc150/fmc150_spi_ctrl.vhd" into library work
Parsing entity <fmc150_spi_ctrl>.
Parsing architecture <fmc150_spi_ctrl_syn> of entity <fmc150_spi_ctrl>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/fmc150/fmc150_stellar_cmd.vhd" into library work
Parsing entity <fmc150_stellar_cmd>.
Parsing architecture <arch_fmc150_stellar_cmd> of entity <fmc150_stellar_cmd>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/fmc150/fmc150_testbench.vhd" into library work
Parsing entity <fmc150_testbench>.
Parsing architecture <rtl> of entity <fmc150_testbench>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/fmc150/pulse2pulse.vhd" into library work
Parsing entity <pulse2pulse>.
Parsing architecture <syn> of entity <pulse2pulse>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_common/reset_synch/reset_synch.vhd" into library work
Parsing entity <reset_synch>.
Parsing architecture <rtl> of entity <reset_synch>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/rffe_top/bpm_swap_ctrl/rf_ch_swap.vhd" into library work
Parsing entity <rf_ch_swap>.
Parsing architecture <rtl> of entity <rf_ch_swap>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/rffe_top/bpm_gain_ctrl/utilities_package.vhd" into library work
Parsing package <utilities_pkg>.
Parsing package body <utilities_pkg>.
Parsing entity <data_generator>.
Parsing architecture <rtl> of entity <data_generator>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/rffe_top/bpm_gain_ctrl/mc_serial_ctrl.vhd" into library work
Parsing entity <mc_serial_ctrl>.
Parsing architecture <rtl> of entity <mc_serial_ctrl>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_crc_gen.vhd" into library work
Parsing entity <gc_crc_gen>.
Parsing architecture <rtl> of entity <gc_crc_gen>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_moving_average.vhd" into library work
Parsing entity <gc_moving_average>.
Parsing architecture <rtl> of entity <gc_moving_average>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_extend_pulse.vhd" into library work
Parsing entity <gc_extend_pulse>.
Parsing architecture <rtl> of entity <gc_extend_pulse>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_ext_pulse_sync.vhd" into library work
Parsing entity <gc_ext_pulse_sync>.
Parsing architecture <rtl> of entity <gc_ext_pulse_sync>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_delay_gen.vhd" into library work
Parsing entity <gc_delay_gen>.
Parsing architecture <behavioral> of entity <gc_delay_gen>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_dual_pi_controller.vhd" into library work
Parsing entity <gc_dual_pi_controller>.
Parsing architecture <behavioral> of entity <gc_dual_pi_controller>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_reset.vhd" into library work
Parsing entity <gc_reset>.
Parsing architecture <rtl> of entity <gc_reset>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_serial_dac.vhd" into library work
Parsing entity <gc_serial_dac>.
Parsing architecture <syn> of entity <gc_serial_dac>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_sync_ffs.vhd" into library work
Parsing entity <gc_sync_ffs>.
Parsing architecture <behavioral> of entity <gc_sync_ffs>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_arbitrated_mux.vhd" into library work
Parsing entity <gc_arbitrated_mux>.
Parsing architecture <rtl> of entity <gc_arbitrated_mux>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd" into library work
Parsing entity <gc_pulse_synchronizer>.
Parsing architecture <rtl> of entity <gc_pulse_synchronizer>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_frequency_meter.vhd" into library work
Parsing entity <gc_frequency_meter>.
Parsing architecture <behavioral> of entity <gc_frequency_meter>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_dual_clock_ram.vhd" into library work
Parsing entity <gc_dual_clock_ram>.
Parsing architecture <rtl> of entity <gc_dual_clock_ram>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_wfifo.vhd" into library work
Parsing entity <gc_wfifo>.
Parsing architecture <rtl> of entity <gc_wfifo>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd" into library work
Parsing package <memory_loader_pkg>.
Parsing package body <memory_loader_pkg>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/generic_shiftreg_fifo.vhd" into library work
Parsing entity <generic_shiftreg_fifo>.
Parsing architecture <rtl> of entity <generic_shiftreg_fifo>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/inferred_sync_fifo.vhd" into library work
Parsing entity <inferred_sync_fifo>.
Parsing architecture <syn> of entity <inferred_sync_fifo>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/inferred_async_fifo.vhd" into library work
Parsing entity <inferred_async_fifo>.
Parsing architecture <syn> of entity <inferred_async_fifo>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd" into library work
Parsing entity <generic_dpram>.
Parsing architecture <syn> of entity <generic_dpram>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd" into library work
Parsing entity <generic_dpram_sameclock>.
Parsing architecture <syn> of entity <generic_dpram_sameclock>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd" into library work
Parsing entity <generic_dpram_dualclock>.
Parsing architecture <syn> of entity <generic_dpram_dualclock>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_spram.vhd" into library work
Parsing entity <generic_spram>.
Parsing architecture <syn> of entity <generic_spram>.
WARNING:HDLCompiler:443 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_spram.vhd" Line 58: Function f_bitstring_2_slv does not always return a value.
WARNING:HDLCompiler:443 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_spram.vhd" Line 63: Function f_load_from_file does not always return a value.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_v6_1_pkg.vhd" into library fifo_generator_v6_1
Parsing package <fifo_generator_v6_1_pkg>.
Parsing package body <fifo_generator_v6_1_pkg>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_v6_1_defaults.vhd" into library fifo_generator_v6_1
Parsing package <fifo_generator_v6_1_defaults>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_v6_1_xst_comp.vhd" into library fifo_generator_v6_1
Parsing package <fifo_generator_v6_1_xst_comp>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/input_blk.vhd" into library fifo_generator_v6_1
Parsing entity <input_blk>.
Parsing architecture <xilinx> of entity <input_blk>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/output_blk.vhd" into library fifo_generator_v6_1
Parsing entity <output_blk>.
Parsing architecture <xilinx> of entity <output_blk>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/shft_wrapper.vhd" into library fifo_generator_v6_1
Parsing entity <shft_wrapper>.
Parsing architecture <xilinx> of entity <shft_wrapper>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/shft_ram.vhd" into library fifo_generator_v6_1
Parsing entity <shft_ram>.
Parsing architecture <xilinx> of entity <shft_ram>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/dmem.vhd" into library fifo_generator_v6_1
Parsing entity <dmem>.
Parsing architecture <Xilinx> of entity <dmem>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_v4_1_xst_comp.vhd" into library blk_mem_gen_v4_1
Parsing package <blk_mem_gen_v4_1_xst_comp>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/memory.vhd" into library fifo_generator_v6_1
Parsing entity <memory>.
Parsing architecture <xilinx> of entity <memory>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/compare.vhd" into library fifo_generator_v6_1
Parsing entity <compare>.
Parsing architecture <Xilinx> of entity <compare>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_bin_cntr.vhd" into library fifo_generator_v6_1
Parsing entity <wr_bin_cntr>.
Parsing architecture <xilinx> of entity <wr_bin_cntr>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_bin_cntr.vhd" into library fifo_generator_v6_1
Parsing entity <rd_bin_cntr>.
Parsing architecture <xilinx> of entity <rd_bin_cntr>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/updn_cntr.vhd" into library fifo_generator_v6_1
Parsing entity <updn_cntr>.
Parsing architecture <xilinx> of entity <updn_cntr>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_status_flags_as.vhd" into library fifo_generator_v6_1
Parsing entity <rd_status_flags_as>.
Parsing architecture <xilinx> of entity <rd_status_flags_as>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_status_flags_ss.vhd" into library fifo_generator_v6_1
Parsing entity <rd_status_flags_ss>.
Parsing architecture <xilinx> of entity <rd_status_flags_ss>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_pe_as.vhd" into library fifo_generator_v6_1
Parsing entity <rd_pe_as>.
Parsing architecture <xilinx> of entity <rd_pe_as>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_pe_ss.vhd" into library fifo_generator_v6_1
Parsing entity <rd_pe_ss>.
Parsing architecture <xilinx> of entity <rd_pe_ss>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_handshaking_flags.vhd" into library fifo_generator_v6_1
Parsing entity <rd_handshaking_flags>.
Parsing architecture <xilinx> of entity <rd_handshaking_flags>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_dc_as.vhd" into library fifo_generator_v6_1
Parsing entity <rd_dc_as>.
Parsing architecture <xilinx> of entity <rd_dc_as>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_dc_fwft_ext_as.vhd" into library fifo_generator_v6_1
Parsing entity <rd_dc_fwft_ext_as>.
Parsing architecture <xilinx> of entity <rd_dc_fwft_ext_as>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/dc_ss.vhd" into library fifo_generator_v6_1
Parsing entity <dc_ss>.
Parsing architecture <xilinx> of entity <dc_ss>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/dc_ss_fwft.vhd" into library fifo_generator_v6_1
Parsing entity <dc_ss_fwft>.
Parsing architecture <xilinx> of entity <dc_ss_fwft>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_fwft.vhd" into library fifo_generator_v6_1
Parsing entity <rd_fwft>.
Parsing architecture <xilinx> of entity <rd_fwft>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_logic.vhd" into library fifo_generator_v6_1
Parsing entity <rd_logic>.
Parsing architecture <xilinx> of entity <rd_logic>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/reset_blk_ramfifo.vhd" into library fifo_generator_v6_1
Parsing entity <reset_blk_ramfifo>.
Parsing architecture <xilinx> of entity <reset_blk_ramfifo>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/clk_x_pntrs.vhd" into library fifo_generator_v6_1
Parsing entity <clk_x_pntrs>.
Parsing architecture <xilinx> of entity <clk_x_pntrs>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_status_flags_as.vhd" into library fifo_generator_v6_1
Parsing entity <wr_status_flags_as>.
Parsing architecture <xilinx> of entity <wr_status_flags_as>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_status_flags_ss.vhd" into library fifo_generator_v6_1
Parsing entity <wr_status_flags_ss>.
Parsing architecture <xilinx> of entity <wr_status_flags_ss>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_pf_as.vhd" into library fifo_generator_v6_1
Parsing entity <wr_pf_as>.
Parsing architecture <xilinx> of entity <wr_pf_as>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_pf_ss.vhd" into library fifo_generator_v6_1
Parsing entity <wr_pf_ss>.
Parsing architecture <xilinx> of entity <wr_pf_ss>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_handshaking_flags.vhd" into library fifo_generator_v6_1
Parsing entity <wr_handshaking_flags>.
Parsing architecture <xilinx> of entity <wr_handshaking_flags>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_dc_as.vhd" into library fifo_generator_v6_1
Parsing entity <wr_dc_as>.
Parsing architecture <xilinx> of entity <wr_dc_as>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_dc_fwft_ext_as.vhd" into library fifo_generator_v6_1
Parsing entity <wr_dc_fwft_ext_as>.
Parsing architecture <xilinx> of entity <wr_dc_fwft_ext_as>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_logic.vhd" into library fifo_generator_v6_1
Parsing entity <wr_logic>.
Parsing architecture <xilinx> of entity <wr_logic>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_status_flags_sshft.vhd" into library fifo_generator_v6_1
Parsing entity <wr_status_flags_sshft>.
Parsing architecture <xilinx> of entity <wr_status_flags_sshft>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_status_flags_sshft.vhd" into library fifo_generator_v6_1
Parsing entity <rd_status_flags_sshft>.
Parsing architecture <xilinx> of entity <rd_status_flags_sshft>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_pf_sshft.vhd" into library fifo_generator_v6_1
Parsing entity <wr_pf_sshft>.
Parsing architecture <xilinx> of entity <wr_pf_sshft>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_pe_sshft.vhd" into library fifo_generator_v6_1
Parsing entity <rd_pe_sshft>.
Parsing architecture <xilinx> of entity <rd_pe_sshft>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/logic_sshft.vhd" into library fifo_generator_v6_1
Parsing entity <logic_sshft>.
Parsing architecture <xilinx> of entity <logic_sshft>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_ramfifo.vhd" into library fifo_generator_v6_1
Parsing entity <fifo_generator_ramfifo>.
Parsing architecture <xilinx> of entity <fifo_generator_ramfifo>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_v6_1_comps_builtin.vhd" into library fifo_generator_v6_1
Parsing package <fifo_generator_v6_1_comps_builtin>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/delay.vhd" into library fifo_generator_v6_1
Parsing entity <delay>.
Parsing architecture <xilinx> of entity <delay>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/clk_x_pntrs_builtin.vhd" into library fifo_generator_v6_1
Parsing entity <clk_x_pntrs_builtin>.
Parsing architecture <xilinx> of entity <clk_x_pntrs_builtin>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/bin_cntr.vhd" into library fifo_generator_v6_1
Parsing entity <bin_cntr>.
Parsing architecture <xilinx> of entity <bin_cntr>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/logic_builtin.vhd" into library fifo_generator_v6_1
Parsing entity <logic_builtin>.
Parsing architecture <xilinx> of entity <logic_builtin>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/reset_builtin.vhd" into library fifo_generator_v6_1
Parsing entity <reset_builtin>.
Parsing architecture <xilinx> of entity <reset_builtin>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/builtin_prim.vhd" into library fifo_generator_v6_1
Parsing entity <builtin_prim>.
Parsing architecture <xilinx> of entity <builtin_prim>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/builtin_extdepth.vhd" into library fifo_generator_v6_1
Parsing entity <builtin_extdepth>.
Parsing architecture <xilinx> of entity <builtin_extdepth>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/builtin_top.vhd" into library fifo_generator_v6_1
Parsing entity <builtin_top>.
Parsing architecture <xilinx> of entity <builtin_top>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/builtin_prim_v6.vhd" into library fifo_generator_v6_1
Parsing entity <builtin_prim_v6>.
Parsing architecture <xilinx> of entity <builtin_prim_v6>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/builtin_extdepth_v6.vhd" into library fifo_generator_v6_1
Parsing entity <builtin_extdepth_v6>.
Parsing architecture <xilinx> of entity <builtin_extdepth_v6>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/builtin_top_v6.vhd" into library fifo_generator_v6_1
Parsing entity <builtin_top_v6>.
Parsing architecture <xilinx> of entity <builtin_top_v6>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_v6_1_builtin.vhd" into library fifo_generator_v6_1
Parsing entity <fifo_generator_v6_1_builtin>.
Parsing architecture <xilinx> of entity <fifo_generator_v6_1_builtin>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rgtw.vhd" into library fifo_generator_v6_1
Parsing entity <rgtw>.
Parsing architecture <xilinx> of entity <rgtw>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wgtr.vhd" into library fifo_generator_v6_1
Parsing entity <wgtr>.
Parsing architecture <xilinx> of entity <wgtr>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/input_block_fifo16_patch.vhd" into library fifo_generator_v6_1
Parsing entity <input_block_fifo16_patch>.
Parsing architecture <xilinx> of entity <input_block_fifo16_patch>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/output_block_fifo16_patch.vhd" into library fifo_generator_v6_1
Parsing entity <output_block_fifo16_patch>.
Parsing architecture <xilinx> of entity <output_block_fifo16_patch>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo16_patch_top.vhd" into library fifo_generator_v6_1
Parsing entity <fifo16_patch_top>.
Parsing architecture <xilinx> of entity <fifo16_patch_top>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_v6_1_fifo16_patch.vhd" into library fifo_generator_v6_1
Parsing entity <fifo_generator_v6_1_fifo16_patch>.
Parsing architecture <xilinx> of entity <fifo_generator_v6_1_fifo16_patch>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_v6_1_xst.vhd" into library fifo_generator_v6_1
Parsing entity <fifo_generator_v6_1_xst>.
Parsing architecture <xilinx> of entity <fifo_generator_v6_1_xst>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_async_fifo.vhd" into library work
Parsing entity <generic_async_fifo>.
Parsing architecture <syn> of entity <generic_async_fifo>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_sync_fifo.vhd" into library work
Parsing entity <generic_sync_fifo>.
Parsing architecture <syn> of entity <generic_sync_fifo>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd" into library work
Parsing entity <wb_async_bridge>.
Parsing architecture <behavioral> of entity <wb_async_bridge>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_async_bridge/xwb_async_bridge.vhd" into library work
Parsing entity <xwb_async_bridge>.
Parsing architecture <wrapper> of entity <xwb_async_bridge>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd" into library work
Parsing entity <wb_onewire_master>.
Parsing architecture <rtl> of entity <wb_onewire_master>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd" into library work
Parsing entity <xwb_onewire_master>.
Parsing architecture <rtl> of entity <xwb_onewire_master>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd" into library work
Parsing entity <i2c_master_bit_ctrl>.
Parsing architecture <structural> of entity <i2c_master_bit_ctrl>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd" into library work
Parsing entity <i2c_master_byte_ctrl>.
Parsing architecture <structural> of entity <i2c_master_byte_ctrl>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd" into library work
Parsing entity <i2c_master_top>.
Parsing architecture <structural> of entity <i2c_master_top>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" into library work
Parsing entity <wb_i2c_master>.
Parsing architecture <rtl> of entity <wb_i2c_master>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd" into library work
Parsing entity <xwb_i2c_master>.
Parsing architecture <rtl> of entity <xwb_i2c_master>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_bus_fanout/xwb_bus_fanout.vhd" into library work
Parsing entity <xwb_bus_fanout>.
Parsing architecture <rtl> of entity <xwb_bus_fanout>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" into library work
Parsing entity <xwb_dpram>.
Parsing architecture <struct> of entity <xwb_dpram>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" into library work
Parsing entity <wb_gpio_port>.
Parsing architecture <behavioral> of entity <wb_gpio_port>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd" into library work
Parsing entity <xwb_gpio_port>.
Parsing architecture <rtl> of entity <xwb_gpio_port>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd" into library work
Parsing entity <wb_tics>.
Parsing architecture <behaviour> of entity <wb_tics>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_simple_timer/xwb_tics.vhd" into library work
Parsing entity <xwb_tics>.
Parsing architecture <rtl> of entity <xwb_tics>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd" into library work
Parsing entity <uart_async_rx>.
Parsing architecture <behavioral> of entity <uart_async_rx>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd" into library work
Parsing entity <uart_async_tx>.
Parsing architecture <behavioral> of entity <uart_async_tx>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd" into library work
Parsing entity <uart_baud_gen>.
Parsing architecture <behavioral> of entity <uart_baud_gen>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd" into library work
Parsing package <uart_wbgen2_pkg>.
Parsing package body <uart_wbgen2_pkg>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd" into library work
Parsing entity <simple_uart_wb>.
Parsing architecture <syn> of entity <simple_uart_wb>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" into library work
Parsing entity <wb_simple_uart>.
Parsing architecture <syn> of entity <wb_simple_uart>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd" into library work
Parsing entity <xwb_simple_uart>.
Parsing architecture <rtl> of entity <xwb_simple_uart>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_vic/vic_prio_enc.vhd" into library work
Parsing entity <vic_prio_enc>.
Parsing architecture <syn> of entity <vic_prio_enc>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd" into library work
Parsing package <wbgen2_pkg>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd" into library work
Parsing entity <wb_slave_vic>.
Parsing architecture <syn> of entity <wb_slave_vic>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd" into library work
Parsing entity <wb_vic>.
Parsing architecture <syn> of entity <wb_vic>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_vic/xwb_vic.vhd" into library work
Parsing entity <xwb_vic>.
Parsing architecture <wrapper> of entity <xwb_vic>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd" into library work
Parsing entity <wb_spi>.
Parsing architecture <rtl> of entity <wb_spi>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd" into library work
Parsing entity <xwb_spi>.
Parsing architecture <rtl> of entity <xwb_spi>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd" into library work
Parsing entity <sdb_rom>.
Parsing architecture <rtl> of entity <sdb_rom>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd" into library work
Parsing entity <xwb_crossbar>.
Parsing architecture <rtl> of entity <xwb_crossbar>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd" into library work
Parsing entity <xwb_sdb_crossbar>.
Parsing architecture <rtl> of entity <xwb_sdb_crossbar>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" into library work
Parsing entity <xwb_lm32>.
Parsing architecture <rtl> of entity <xwb_lm32>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd" into library work
Parsing entity <wb_slave_adapter>.
Parsing architecture <rtl> of entity <wb_slave_adapter>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd" into library work
Parsing package <xldr_wbgen2_pkg>.
Parsing package body <xldr_wbgen2_pkg>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/wb_xilinx_fpga_loader.vhd" into library work
Parsing entity <wb_xilinx_fpga_loader>.
Parsing architecture <behavioral> of entity <wb_xilinx_fpga_loader>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/xwb_xilinx_fpga_loader.vhd" into library work
Parsing entity <xwb_xilinx_fpga_loader>.
Parsing architecture <rtl> of entity <xwb_xilinx_fpga_loader>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/xloader_wb.vhd" into library work
Parsing entity <xloader_wb>.
Parsing architecture <syn> of entity <xloader_wb>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd" into library work
Parsing entity <xwb_clock_crossing>.
Parsing architecture <rtl> of entity <xwb_clock_crossing>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dma/xwb_dma.vhd" into library work
Parsing entity <xwb_dma>.
Parsing architecture <rtl> of entity <xwb_dma>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd" into library work
Parsing entity <wbgen2_dpssram>.
Parsing architecture <syn> of entity <wbgen2_dpssram>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd" into library work
Parsing entity <wbgen2_eic>.
Parsing architecture <syn> of entity <wbgen2_eic>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd" into library work
Parsing entity <wbgen2_fifo_async>.
Parsing architecture <rtl> of entity <wbgen2_fifo_async>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd" into library work
Parsing entity <wbgen2_fifo_sync>.
Parsing architecture <rtl> of entity <wbgen2_fifo_sync>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_hdr_pkg.vhd" into library work
Parsing package <EB_HDR_PKG>.
Parsing package body <EB_HDR_PKG>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_main_fsm.vhd" into library work
Parsing entity <eb_main_fsm>.
Parsing architecture <behavioral> of entity <eb_main_fsm>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_checksum.vhd" into library work
Parsing entity <EB_checksum>.
Parsing architecture <behavioral> of entity <eb_checksum>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_config.vhd" into library work
Parsing entity <eb_config>.
Parsing architecture <behavioral> of entity <eb_config>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_core.vhd" into library work
Parsing entity <eb_slave_core>.
Parsing architecture <behavioral> of entity <eb_slave_core>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_rx_ctrl.vhd" into library work
Parsing entity <EB_RX_CTRL>.
Parsing architecture <behavioral> of entity <eb_rx_ctrl>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_ctrl.vhd" into library work
Parsing entity <EB_TX_CTRL>.
Parsing architecture <behavioral> of entity <eb_tx_ctrl>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/piso_flag.vhd" into library work
Parsing entity <piso_flag>.
Parsing architecture <behavioral> of entity <piso_flag>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/vhdl_2008_workaround_pkg.vhd" into library work
Parsing package <vhdl_2008_workaround_pkg>.
Parsing package body <vhdl_2008_workaround_pkg>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/sipo_flag.vhd" into library work
Parsing entity <sipo_flag>.
Parsing architecture <behavioral> of entity <sipo_flag>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/WB_bus_adapter_streaming_sg.vhd" into library work
Parsing entity <WB_bus_adapter_streaming_sg>.
Parsing architecture <behavioral> of entity <wb_bus_adapter_streaming_sg>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/xetherbone_core.vhd" into library work
Parsing entity <xetherbone_core>.
Parsing architecture <wrapper> of entity <xetherbone_core>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_v4_1_defaults.vhd" into library blk_mem_gen_v4_1
Parsing package <blk_mem_gen_v4_1_defaults>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_v4_1_pkg.vhd" into library blk_mem_gen_v4_1
Parsing package <blk_mem_gen_pkg>.
Parsing package body <blk_mem_gen_pkg>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_getinit_pkg.vhd" into library blk_mem_gen_v4_1
Parsing package <blk_mem_gen_getinit_pkg>.
Parsing package body <blk_mem_gen_getinit_pkg>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_min_area_pkg.vhd" into library blk_mem_gen_v4_1
Parsing package <blk_mem_min_area_pkg>.
Parsing package body <blk_mem_min_area_pkg>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_bindec.vhd" into library blk_mem_gen_v4_1
Parsing entity <bindec>.
Parsing architecture <xilinx> of entity <bindec>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_mux.vhd" into library blk_mem_gen_v4_1
Parsing entity <blk_mem_gen_mux>.
Parsing architecture <xilinx> of entity <blk_mem_gen_mux>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s6.vhd" into library blk_mem_gen_v4_1
Parsing entity <blk_mem_gen_prim_wrapper_s6>.
Parsing architecture <xilinx> of entity <blk_mem_gen_prim_wrapper_s6>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s6_init.vhd" into library blk_mem_gen_v4_1
Parsing entity <blk_mem_gen_prim_wrapper_s6_init>.
Parsing architecture <xilinx> of entity <blk_mem_gen_prim_wrapper_s6_init>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3adsp.vhd" into library blk_mem_gen_v4_1
Parsing entity <blk_mem_gen_prim_wrapper_s3adsp>.
Parsing architecture <xilinx> of entity <blk_mem_gen_prim_wrapper_s3adsp>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3adsp_init.vhd" into library blk_mem_gen_v4_1
Parsing entity <blk_mem_gen_prim_wrapper_s3adsp_init>.
Parsing architecture <xilinx> of entity <blk_mem_gen_prim_wrapper_s3adsp_init>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3a.vhd" into library blk_mem_gen_v4_1
Parsing entity <blk_mem_gen_prim_wrapper_s3a>.
Parsing architecture <xilinx> of entity <blk_mem_gen_prim_wrapper_s3a>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3a_init.vhd" into library blk_mem_gen_v4_1
Parsing entity <blk_mem_gen_prim_wrapper_s3a_init>.
Parsing architecture <xilinx> of entity <blk_mem_gen_prim_wrapper_s3a_init>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v6.vhd" into library blk_mem_gen_v4_1
Parsing entity <blk_mem_gen_prim_wrapper_v6>.
Parsing architecture <xilinx> of entity <blk_mem_gen_prim_wrapper_v6>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v6_init.vhd" into library blk_mem_gen_v4_1
Parsing entity <blk_mem_gen_prim_wrapper_v6_init>.
Parsing architecture <xilinx> of entity <blk_mem_gen_prim_wrapper_v6_init>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v5.vhd" into library blk_mem_gen_v4_1
Parsing entity <blk_mem_gen_prim_wrapper_v5>.
Parsing architecture <xilinx> of entity <blk_mem_gen_prim_wrapper_v5>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v5_init.vhd" into library blk_mem_gen_v4_1
Parsing entity <blk_mem_gen_prim_wrapper_v5_init>.
Parsing architecture <xilinx> of entity <blk_mem_gen_prim_wrapper_v5_init>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v4.vhd" into library blk_mem_gen_v4_1
Parsing entity <blk_mem_gen_prim_wrapper_v4>.
Parsing architecture <xilinx> of entity <blk_mem_gen_prim_wrapper_v4>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v4_init.vhd" into library blk_mem_gen_v4_1
Parsing entity <blk_mem_gen_prim_wrapper_v4_init>.
Parsing architecture <xilinx> of entity <blk_mem_gen_prim_wrapper_v4_init>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3.vhd" into library blk_mem_gen_v4_1
Parsing entity <blk_mem_gen_prim_wrapper_s3>.
Parsing architecture <xilinx> of entity <blk_mem_gen_prim_wrapper_s3>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3_init.vhd" into library blk_mem_gen_v4_1
Parsing entity <blk_mem_gen_prim_wrapper_s3_init>.
Parsing architecture <xilinx> of entity <blk_mem_gen_prim_wrapper_s3_init>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_width.vhd" into library blk_mem_gen_v4_1
Parsing entity <blk_mem_gen_prim_width>.
Parsing architecture <xilinx> of entity <blk_mem_gen_prim_width>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_generic_cstr.vhd" into library blk_mem_gen_v4_1
Parsing entity <blk_mem_gen_generic_cstr>.
Parsing architecture <xilinx> of entity <blk_mem_gen_generic_cstr>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_ecc_encoder.vhd" into library blk_mem_gen_v4_1
Parsing entity <blk_mem_gen_ecc_encoder>.
Parsing architecture <xilinx> of entity <blk_mem_gen_ecc_encoder>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_ecc_decoder.vhd" into library blk_mem_gen_v4_1
Parsing entity <blk_mem_gen_ecc_decoder>.
Parsing architecture <xilinx> of entity <blk_mem_gen_ecc_decoder>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_input_block.vhd" into library blk_mem_gen_v4_1
Parsing entity <blk_mem_input_block>.
Parsing architecture <xilinx> of entity <blk_mem_input_block>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_output_block.vhd" into library blk_mem_gen_v4_1
Parsing entity <blk_mem_output_block>.
Parsing architecture <xilinx> of entity <blk_mem_output_block>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_top.vhd" into library blk_mem_gen_v4_1
Parsing entity <blk_mem_gen_top>.
Parsing architecture <xilinx> of entity <blk_mem_gen_top>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_v4_1_xst.vhd" into library blk_mem_gen_v4_1
Parsing entity <blk_mem_gen_v4_1_xst>.
Parsing architecture <xilinx> of entity <blk_mem_gen_v4_1_xst>.

=========================================================================
*                            HDL Elaboration                            *
=========================================================================
WARNING:HDLCompiler:746 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/genram_pkg.vhd" Line 50: Range is empty (null range)

Elaborating entity <dbe_bpm_ebone> (architecture <rtl>) from library <work>.

Elaborating entity <clk_gen> (architecture <syn>) from library <work>.

Elaborating entity <sys_pll> (architecture <syn>) with generics from library <work>.

Elaborating entity <gc_reset> (architecture <rtl>) with generics from library <work>.

Elaborating entity <gc_sync_ffs> (architecture <behavioral>) with generics from library <work>.

Elaborating entity <gc_extend_pulse> (architecture <rtl>) with generics from library <work>.

Elaborating entity <xwb_sdb_crossbar> (architecture <rtl>) with generics from library <work>.

Elaborating entity <sdb_rom> (architecture <rtl>) with generics from library <work>.

Elaborating entity <xwb_crossbar> (architecture <rtl>) with generics from library <work>.
Note: "Mapping slave #0[0x0/0xfffe0000]"
Note: "Mapping slave #1[0x10000000/0xfffe0000]"
Note: "Mapping slave #2[0x20000000/0xffff0000]"
Note: "Mapping slave #3[0x60000000/0xffffffe0]"
Note: "Mapping slave #4[0x70000000/0xff000000]"
Note: "Mapping slave #5[0x80000000/0xffffff00]"
Note: "Mapping slave #6[0x90000000/0xffffff00]"
Note: "Mapping slave #7[0xa0000000/0xffffff00]"
Note: "Mapping slave #8[0xb0000000/0xffffff00]"
Note: "Mapping slave #9[0xc0000000/0xffffff00]"
Note: "Mapping slave #10[0x30000000/0xfffffc00]"

Elaborating entity <xwb_lm32> (architecture <rtl>) with generics from library <work>.
WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" Line 31: Comparison between arrays of unequal length always returns FALSE.
WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" Line 32: Comparison between arrays of unequal length always returns FALSE.
WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" Line 33: Comparison between arrays of unequal length always returns FALSE.
WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" Line 34: Comparison between arrays of unequal length always returns FALSE.
WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" Line 20: Comparison between arrays of unequal length always returns FALSE.
WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" Line 21: Comparison between arrays of unequal length always returns FALSE.
WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" Line 22: Comparison between arrays of unequal length always returns FALSE.
WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" Line 23: Comparison between arrays of unequal length always returns FALSE.
WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" Line 326: Comparison between arrays of unequal length always returns FALSE.
WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" Line 367: Comparison between arrays of unequal length always returns FALSE.
WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" Line 408: Comparison between arrays of unequal length always returns FALSE.
WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" Line 449: Comparison between arrays of unequal length always returns FALSE.
Going to verilog side to elaborate module lm32_top_medium_icache_debug

Elaborating module <lm32_top_medium_icache_debug>.

Elaborating module <lm32_cpu_medium_icache_debug>.

Elaborating module <lm32_instruction_unit_medium_icache_debug(associativity=1,sets=256,bytes_per_line=16,base_address=32'b0,limit=32'b01111111111111111111111111111111)>.

Elaborating module <lm32_icache_medium_icache_debug(associativity=1,sets=256,bytes_per_line=16,base_address=32'b0,limit=32'b01111111111111111111111111111111)>.

Elaborating module <lm32_ram(data_width=32,address_width=32'sb01010)>.

Elaborating module <lm32_ram(data_width=32'sb010100,address_width=32'sb01000)>.
WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" Line 49056: Result of 30-bit expression is truncated to fit in 29-bit target.
WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" Line 41108: Assignment to pc_w ignored, since the identifier is never used

Elaborating module <lm32_decoder_medium_icache_debug>.
WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" Line 45380: Assignment to op_user ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" Line 45414: Assignment to multiply ignored, since the identifier is never used
WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" Line 45624: Result of 32-bit expression is truncated to fit in 29-bit target.

Elaborating module <lm32_load_store_unit_medium_icache_debug(associativity=1,sets=512,bytes_per_line=16,base_address=0,limit=0)>.
"/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" Line 44387. $display Data bus error. Address: 0
"/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" Line 44535. $display Warning: Non-aligned halfword access. Address: 0x0 Time:  $time .
"/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" Line 44537. $display Warning: Non-aligned word access. Address: 0x0 Time:  $time .

Elaborating module <lm32_adder>.

Elaborating module <lm32_addsub>.

Elaborating module <lm32_logic_op>.

Elaborating module <lm32_shifter>.
WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v" Line 128: Result of 64-bit expression is truncated to fit in 32-bit target.

Elaborating module <lm32_multiplier>.

Elaborating module <lm32_interrupt_medium_icache_debug>.
WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" Line 50707: Result of 3-bit expression is truncated to fit in 1-bit target.
WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" Line 50707: Assignment to ie_csr_read_data ignored, since the identifier is never used
WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" Line 50718: Result of 32-bit expression is truncated to fit in 1-bit target.
WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" Line 50718: Assignment to ip_csr_read_data ignored, since the identifier is never used
WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" Line 50719: Result of 32-bit expression is truncated to fit in 1-bit target.
WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" Line 50719: Assignment to im_csr_read_data ignored, since the identifier is never used

Elaborating module <lm32_jtag_medium_icache_debug>.

Elaborating module <lm32_debug_medium_icache_debug(breakpoints=0,watchpoints=32'b0100)>.
WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" Line 47797: Net <wp_match_n[4]> does not have a driver.

Elaborating module <lm32_dp_ram(addr_depth=32'sb0100000,addr_width=5,data_width=32)>.
WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" Line 42753: Assignment to x_result_sel_logic_x ignored, since the identifier is never used

Elaborating module <jtag_cores>.

Elaborating module <jtag_tap>.

Elaborating module <BSCAN_VIRTEX6(JTAG_CHAIN=2)>.
WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" Line 39170: Assignment to jrstn ignored, since the identifier is never used
Back to vhdl to continue elaboration
WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" Line 531: Comparison between arrays of unequal length always returns FALSE.
WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" Line 572: Comparison between arrays of unequal length always returns FALSE.

Elaborating entity <xwb_dma> (architecture <rtl>) with generics from library <work>.

Elaborating entity <xwb_dpram> (architecture <struct>) with generics from library <work>.

Elaborating entity <wb_slave_adapter> (architecture <rtl>) with generics from library <work>.

Elaborating entity <generic_dpram> (architecture <syn>) with generics from library <work>.

Elaborating entity <generic_dpram_sameclock> (architecture <syn>) with generics from library <work>.
WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd" Line 150: Comparison between arrays of unequal length always returns FALSE.
WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" Line 72: Net <slave1_out_int> does not have a driver.
WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" Line 74: Net <slave2_out_int> does not have a driver.

Elaborating entity <xwb_dpram> (architecture <struct>) with generics from library <work>.

Elaborating entity <wb_slave_adapter> (architecture <rtl>) with generics from library <work>.

Elaborating entity <wb_slave_adapter> (architecture <rtl>) with generics from library <work>.

Elaborating entity <generic_dpram> (architecture <syn>) with generics from library <work>.

Elaborating entity <generic_dpram_sameclock> (architecture <syn>) with generics from library <work>.

Elaborating entity <xwb_ethmac> (architecture <rtl>) with generics from library <work>.

Elaborating entity <wb_ethmac> (architecture <rtl>) with generics from library <work>.

Elaborating entity <wb_slave_adapter> (architecture <rtl>) with generics from library <work>.
Going to verilog side to elaborate module ethmac

Elaborating module <ethmac>.

Elaborating module <eth_miim>.
WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_miim.v" Line 409: Result of 8-bit expression is truncated to fit in 7-bit target.

Elaborating module <eth_clockgen>.

Elaborating module <eth_shiftreg>.
WARNING:HDLCompiler:1308 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_shiftreg.v" Line 122: Found full_case directive in module eth_shiftreg. Use of full_case directives may cause differences between RTL and post-synthesis simulation

Elaborating module <eth_outputcontrol>.

Elaborating module <eth_registers>.

Elaborating module <eth_register(WIDTH=8,RESET_VALUE=8'b0)>.

Elaborating module <eth_register(WIDTH=8,RESET_VALUE=8'b10100000)>.

Elaborating module <eth_register(WIDTH=1,RESET_VALUE=1'b0)>.

Elaborating module <eth_register(WIDTH=7,RESET_VALUE=7'b0)>.

Elaborating module <eth_register(WIDTH=7,RESET_VALUE=7'b010010)>.

Elaborating module <eth_register(WIDTH=7,RESET_VALUE=7'b01100)>.

Elaborating module <eth_register(WIDTH=8,RESET_VALUE=8'b0110)>.

Elaborating module <eth_register(WIDTH=8,RESET_VALUE=8'b01000000)>.

Elaborating module <eth_register(WIDTH=6,RESET_VALUE=6'b111111)>.

Elaborating module <eth_register(WIDTH=4,RESET_VALUE=4'b1111)>.

Elaborating module <eth_register(WIDTH=3,RESET_VALUE=3'b0)>.

Elaborating module <eth_register(WIDTH=8,RESET_VALUE=8'b01100100)>.

Elaborating module <eth_register(WIDTH=1,RESET_VALUE=0)>.

Elaborating module <eth_register(WIDTH=5,RESET_VALUE=5'b0)>.

Elaborating module <eth_register(WIDTH=16,RESET_VALUE=16'b0)>.
WARNING:HDLCompiler:91 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_registers.v" Line 883: Signal <dbg_dat> missing in the sensitivity list is added for synthesis purposes. HDL and post-synthesis simulations may differ as a result.
WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_registers.v" Line 1000: Assignment to ResetTxCIrq_sync1 ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/ethmac.v" Line 399: Assignment to r_NoPre ignored, since the identifier is never used

Elaborating module <eth_maccontrol>.

Elaborating module <eth_receivecontrol>.

Elaborating module <eth_transmitcontrol>.

Elaborating module <eth_txethmac>.
WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_txethmac.v" Line 344: Result of 5-bit expression is truncated to fit in 4-bit target.

Elaborating module <eth_txcounters>.
WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_txcounters.v" Line 172: Assignment to ExcessiveDeferCnt ignored, since the identifier is never used

Elaborating module <eth_txstatem>.

Elaborating module <eth_crc>.
WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_txethmac.v" Line 481: Assignment to CrcError ignored, since the identifier is never used

Elaborating module <eth_random>.

Elaborating module <eth_rxethmac>.

Elaborating module <eth_rxstatem>.

Elaborating module <eth_rxcounters>.

Elaborating module <eth_rxaddrcheck>.

Elaborating module <eth_wishbone>.

Elaborating module <eth_spram_256x32(we_width=1)>.
WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_wishbone.v" Line 821: Result of 31-bit expression is truncated to fit in 30-bit target.
WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_wishbone.v" Line 964: Result of 31-bit expression is truncated to fit in 30-bit target.
WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_wishbone.v" Line 1001: Result of 31-bit expression is truncated to fit in 30-bit target.

Elaborating module <eth_fifo(DATA_WIDTH=32,DEPTH=256,CNT_WIDTH=8)>.
WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_fifo.v" Line 81: Result of 32-bit expression is truncated to fit in 8-bit target.
WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_fifo.v" Line 83: Result of 9-bit expression is truncated to fit in 8-bit target.
WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_fifo.v" Line 114: Result of 9-bit expression is truncated to fit in 8-bit target.
WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_fifo.v" Line 122: Result of 9-bit expression is truncated to fit in 8-bit target.
WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_wishbone.v" Line 1395: Result of 32-bit expression is truncated to fit in 7-bit target.
WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_wishbone.v" Line 1397: Result of 32-bit expression is truncated to fit in 7-bit target.
WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_wishbone.v" Line 2001: Result of 31-bit expression is truncated to fit in 30-bit target.
WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_wishbone.v" Line 2098: Result of 3-bit expression is truncated to fit in 2-bit target.
WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_wishbone.v" Line 2117: Result of 3-bit expression is truncated to fit in 2-bit target.
WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_wishbone.v" Line 2399: Assignment to RxBufferAlmostEmpty ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_wishbone.v" Line 2418: Assignment to enough_data_in_rxfifo_for_burst_plus1 ignored, since the identifier is never used
"/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_wishbone.v" Line 2774. $display ( $time )(eth_wishbone) Ethernet MAC BUSY signal asserted

Elaborating module <eth_macstatus>.
Back to vhdl to continue elaboration

Elaborating entity <xwb_ethmac_adapter> (architecture <behavioral>) from library <work>.

Elaborating entity <WB_bus_adapter_streaming_sg> (architecture <behavioral>) with generics from library <work>.

Elaborating entity <sipo_flag> (architecture <behavioral>) with generics from library <work>.
WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/WB_bus_adapter_streaming_sg.vhd" Line 104: Net <sipo_clr> does not have a driver.
WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac_adapter/xwb_ethmac_adapter.vhd" Line 274: Assignment to rx_ram_dat_reg ignored, since the identifier is never used

Elaborating entity <WB_bus_adapter_streaming_sg> (architecture <behavioral>) with generics from library <work>.

Elaborating entity <piso_flag> (architecture <behavioral>) with generics from library <work>.

Elaborating entity <eb_slave_core> (architecture <behavioral>) with generics from library <work>.

Elaborating entity <EB_TX_CTRL> (architecture <behavioral>) from library <work>.

Elaborating entity <piso_flag> (architecture <behavioral>) with generics from library <work>.

Elaborating entity <EB_checksum> (architecture <behavioral>) from library <work>.
INFO:HDLCompiler:679 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_checksum.vhd" Line 109. Case statement is complete. others clause is never selected

Elaborating entity <piso_flag> (architecture <behavioral>) with generics from library <work>.
INFO:HDLCompiler:679 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_ctrl.vhd" Line 509. Case statement is complete. others clause is never selected
WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_ctrl.vhd" Line 357: Assignment to sh_hdr_en ignored, since the identifier is never used

Elaborating entity <EB_RX_CTRL> (architecture <behavioral>) from library <work>.

Elaborating entity <sipo_flag> (architecture <behavioral>) with generics from library <work>.
INFO:HDLCompiler:679 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_rx_ctrl.vhd" Line 473. Case statement is complete. others clause is never selected
INFO:HDLCompiler:679 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_rx_ctrl.vhd" Line 560. Case statement is complete. others clause is never selected
WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_rx_ctrl.vhd" Line 129: Net <snk_hdr_fsm_rty> does not have a driver.

Elaborating entity <eb_main_fsm> (architecture <behavioral>) from library <work>.

Elaborating entity <generic_sync_fifo> (architecture <syn>) with generics from library <work>.

Elaborating entity <fifo_generator_v6_1_xst> (architecture <xilinx>) with generics from library <fifo_generator_v6_1>.

Elaborating entity <fifo_generator_ramfifo> (architecture <xilinx>) with generics from library <fifo_generator_v6_1>.
Warning: "WARNING : Virtex-6 has a potential collision issue. For more information, please refer xyz."

Elaborating entity <reset_blk_ramfifo> (architecture <xilinx>) with generics from library <fifo_generator_v6_1>.

Elaborating entity <input_blk> (architecture <xilinx>) with generics from library <fifo_generator_v6_1>.

Elaborating entity <memory> (architecture <xilinx>) with generics from library <fifo_generator_v6_1>.
WARNING:HDLCompiler:871 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/memory.vhd" Line 248: Using initial value "00000000000000000000000000000000" for zero_din_width since it is never assigned

Elaborating entity <blk_mem_gen_v4_1_xst> (architecture <xilinx>) with generics from library <blk_mem_gen_v4_1>.

Elaborating entity <blk_mem_gen_top> (architecture <xilinx>) with generics from library <blk_mem_gen_v4_1>.
library is /opt/Xilinx/13.4/ISE_DS/ISE/lib/lin64/libIp_Xst.so
Function name : Ip_Xst:Ip_blk_mem_gen_v4_1_placement_algo_num_prims
WARNING:UtilitiesC:159 - Message file "usenglish/ip.msg" wasn't found.
INFO:ip - 0: (0,0) 	: 36x1024 	u:32
library is /opt/Xilinx/13.4/ISE_DS/ISE/lib/lin64/libIp_Xst.so
Function name : Ip_Xst:Ip_blk_mem_gen_v4_1_placement_algo
INFO:ip - 0: (0,0) 	: 36x1024 	u:32

Elaborating entity <blk_mem_input_block> (architecture <xilinx>) with generics from library <blk_mem_gen_v4_1>.

Elaborating entity <blk_mem_gen_generic_cstr> (architecture <xilinx>) with generics from library <blk_mem_gen_v4_1>.

Elaborating entity <blk_mem_gen_prim_width> (architecture <xilinx>) with generics from library <blk_mem_gen_v4_1>.

Elaborating entity <blk_mem_gen_prim_wrapper_v6> (architecture <xilinx>) with generics from library <blk_mem_gen_v4_1>.
WARNING:HDLCompiler:746 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v6.vhd" Line 3234: Range is empty (null range)
WARNING:HDLCompiler:220 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v6.vhd" Line 3234: Assignment ignored
WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v6.vhd" Line 509: Net <douta_i[35]> does not have a driver.
WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_width.vhd" Line 428: Net <dina_pad[35]> does not have a driver.
WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_width.vhd" Line 432: Net <dinb_pad[35]> does not have a driver.

Elaborating entity <blk_mem_output_block> (architecture <xilinx>) with generics from library <blk_mem_gen_v4_1>.

Elaborating entity <rd_logic> (architecture <xilinx>) with generics from library <fifo_generator_v6_1>.

Elaborating entity <rd_bin_cntr> (architecture <xilinx>) with generics from library <fifo_generator_v6_1>.

Elaborating entity <rd_status_flags_ss> (architecture <xilinx>) with generics from library <fifo_generator_v6_1>.

Elaborating entity <compare> (architecture <Xilinx>) with generics from library <fifo_generator_v6_1>.

Elaborating entity <rd_pe_ss> (architecture <xilinx>) with generics from library <fifo_generator_v6_1>.

Elaborating entity <dc_ss> (architecture <xilinx>) with generics from library <fifo_generator_v6_1>.

Elaborating entity <updn_cntr> (architecture <xilinx>) with generics from library <fifo_generator_v6_1>.

Elaborating entity <wr_logic> (architecture <xilinx>) with generics from library <fifo_generator_v6_1>.

Elaborating entity <wr_bin_cntr> (architecture <xilinx>) with generics from library <fifo_generator_v6_1>.

Elaborating entity <wr_status_flags_ss> (architecture <xilinx>) with generics from library <fifo_generator_v6_1>.
WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_status_flags_ss.vhd" Line 168: Net <ram_afull_i> does not have a driver.
WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_status_flags_ss.vhd" Line 169: Net <ram_afull_fb> does not have a driver.

Elaborating entity <wr_pf_ss> (architecture <xilinx>) with generics from library <fifo_generator_v6_1>.

Elaborating entity <wr_handshaking_flags> (architecture <xilinx>) with generics from library <fifo_generator_v6_1>.

Elaborating entity <output_blk> (architecture <xilinx>) with generics from library <fifo_generator_v6_1>.
INFO:HDLCompiler:679 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_main_fsm.vhd" Line 689. Case statement is complete. others clause is never selected
WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_main_fsm.vhd" Line 753: Assignment to s_eb_rx_stall ignored, since the identifier is never used

Elaborating entity <eb_config> (architecture <behavioral>) with generics from library <work>.
WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_core.vhd" Line 80: Net <WB_master_i_rty> does not have a driver.

Elaborating entity <xwb_simple_uart> (architecture <rtl>) with generics from library <work>.

Elaborating entity <wb_simple_uart> (architecture <syn>) with generics from library <work>.

Elaborating entity <wb_slave_adapter> (architecture <rtl>) with generics from library <work>.

Elaborating entity <simple_uart_wb> (architecture <syn>) from library <work>.
WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd" Line 56: Assignment to bwsel_reg ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd" Line 57: Assignment to rd_int ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd" Line 58: Assignment to wr_int ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd" Line 59: Assignment to allones ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd" Line 60: Assignment to allzeros ignored, since the identifier is never used

Elaborating entity <uart_baud_gen> (architecture <behavioral>) with generics from library <work>.

Elaborating entity <uart_async_tx> (architecture <behavioral>) from library <work>.
INFO:HDLCompiler:679 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd" Line 139. Case statement is complete. others clause is never selected

Elaborating entity <uart_async_rx> (architecture <behavioral>) from library <work>.
WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" Line 132: Net <wb_out_err> does not have a driver.
WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" Line 134: Net <regs_in_host_tdr_rdy_i> does not have a driver.

Elaborating entity <xwb_gpio_port> (architecture <rtl>) with generics from library <work>.

Elaborating entity <wb_gpio_port> (architecture <behavioral>) with generics from library <work>.

Elaborating entity <wb_slave_adapter> (architecture <rtl>) with generics from library <work>.
INFO:HDLCompiler:679 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" Line 146. Case statement is complete. others clause is never selected
WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" Line 78: Net <gpio_in_synced[31]> does not have a driver.
WARNING:HDLCompiler:89 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_ebone/dbe_bpm_ebone.vhd" Line 325: <chipscope_icon_4_port> remains a black-box since it has no binding entity.
WARNING:HDLCompiler:89 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_ebone/dbe_bpm_ebone.vhd" Line 335: <chipscope_ila> remains a black-box since it has no binding entity.
WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_ebone/dbe_bpm_ebone.vhd" Line 281: Net <TRIG_ILA3_0[5]> does not have a driver.

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <dbe_bpm_ebone>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_ebone/dbe_bpm_ebone.vhd".
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_ebone/dbe_bpm_ebone.vhd" line 365: Output port <clk1_o> of the instance <cmp_sys_pll_inst> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_ebone/dbe_bpm_ebone.vhd" line 393: Output port <synced_o> of the instance <cmp_button_sys_ffs> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_ebone/dbe_bpm_ebone.vhd" line 393: Output port <npulse_o> of the instance <cmp_button_sys_ffs> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_ebone/dbe_bpm_ebone.vhd" line 502: Output port <slave2_o_dat> of the instance <cmp_ethmac_buf_ram> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_ebone/dbe_bpm_ebone.vhd" line 502: Output port <slave2_o_ack> of the instance <cmp_ethmac_buf_ram> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_ebone/dbe_bpm_ebone.vhd" line 502: Output port <slave2_o_err> of the instance <cmp_ethmac_buf_ram> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_ebone/dbe_bpm_ebone.vhd" line 502: Output port <slave2_o_rty> of the instance <cmp_ethmac_buf_ram> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_ebone/dbe_bpm_ebone.vhd" line 502: Output port <slave2_o_stall> of the instance <cmp_ethmac_buf_ram> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_ebone/dbe_bpm_ebone.vhd" line 502: Output port <slave2_o_int> of the instance <cmp_ethmac_buf_ram> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_ebone/dbe_bpm_ebone.vhd" line 641: Output port <desc_o> of the instance <cmp_uart> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_ebone/dbe_bpm_ebone.vhd" line 656: Output port <desc_o> of the instance <cmp_leds> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_ebone/dbe_bpm_ebone.vhd" line 656: Output port <gpio_oen_o> of the instance <cmp_leds> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_ebone/dbe_bpm_ebone.vhd" line 682: Output port <desc_o> of the instance <cmp_buttons> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_ebone/dbe_bpm_ebone.vhd" line 682: Output port <gpio_out_o> of the instance <cmp_buttons> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_ebone/dbe_bpm_ebone.vhd" line 682: Output port <gpio_oen_o> of the instance <cmp_buttons> is unconnected or connected to loadless signal.
WARNING:Xst:653 - Signal <TRIG_ILA3_0<5>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
    Found 1-bit tristate buffer for signal <md_pad_b> created at line 577
    Summary:
	inferred   1 Tristate(s).
Unit <dbe_bpm_ebone> synthesized.

Synthesizing Unit <clk_gen>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_ebone/clk_gen.vhd".
    Summary:
	no macro.
Unit <clk_gen> synthesized.

Synthesizing Unit <sys_pll>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_ebone/sys_pll.vhd".
        g_clkin_period = 5.0
        g_clkbout_mult_f = 5.0
        g_clk0_divide_f = 10.0
        g_clk1_divide = 5
    Summary:
	no macro.
Unit <sys_pll> synthesized.

Synthesizing Unit <gc_reset>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_reset.vhd".
        g_clocks = 1
        g_logdelay = 10
        g_syncdepth = 3
    Found 1-bit register for signal <master_rstn>.
    Found 10-bit register for signal <locked_count>.
    Found 3-bit register for signal <shifters<0>>.
    Found 10-bit adder for signal <locked_count[9]_GND_50_o_add_1_OUT> created at line 1241.
    Summary:
	inferred   1 Adder/Subtractor(s).
	inferred  14 D-type flip-flop(s).
Unit <gc_reset> synthesized.

Synthesizing Unit <gc_sync_ffs>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_sync_ffs.vhd".
        g_sync_edge = "positive"
    Register <synced_o> equivalent to <sync2> has been removed
    Found 1-bit register for signal <sync1>.
    Found 1-bit register for signal <sync2>.
    Found 1-bit register for signal <npulse_o>.
    Found 1-bit register for signal <ppulse_o>.
    Found 1-bit register for signal <sync0>.
    Summary:
	inferred   5 D-type flip-flop(s).
Unit <gc_sync_ffs> synthesized.

Synthesizing Unit <gc_extend_pulse>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_extend_pulse.vhd".
        g_width = 255
    Found 32-bit register for signal <cntr>.
    Found 1-bit register for signal <extended_int>.
    Found 32-bit subtractor for signal <GND_52_o_GND_52_o_sub_2_OUT<31:0>> created at line 1308.
    Summary:
	inferred   1 Adder/Subtractor(s).
	inferred  33 D-type flip-flop(s).
Unit <gc_extend_pulse> synthesized.

Synthesizing Unit <xwb_sdb_crossbar>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd".
        g_num_masters = 8
        g_num_slaves = 10
        g_registered = true
        g_wraparound = false
        g_layout =
("00000000000000000000000100000000000000000000000000000000000001110000000000000000000000000000000011000000000000000000000000000000000000000000000000000000000000001100000000000000000000001111111100000000000000000000000000000000000000000000000000000110010100010011010110101010011010111001010100000000000000000000000000000001001000000001001000000011000001010100011101010011010010010101111101000111010100000100100101001111010111110011001100110010001000000010000000100000001000000010000000100000001000000010000000000001","000000000000000000000001000000000000000000000000000000000000011100000000000000000000000000000000101100000000000000000000000000000000000000000000000000000000000010110000000000000000000011111111000000000000000000000000000000000000000000000000000001100101000100110101101010100110101110010101000000000000000000000000000000010010000000010010000000110000010101000111010100110100100101011111010001110101000001001001010011110101111100110011001100100010000000100000001000000010000000100000001000000010000000100000000
00001","00000000000000000000000100000000000000000000000000000000000000010000000000000000000000000000000010100000000000000000000000000000000000000000000000000000000000001010000000000000000000001111111100000000000000000000000000000000000000000000000011001110010000101000101001010111000110011010111000000000000000000000000000000001001000000001001000010000000100010100001101000101010100100100111001011111010100110100100101001101010100000100110001000101010111110101010101000001010100100101010000100000001000000010000000000001","000000000000000000000001000000010000000000000000000000000000010000000000000000000000000000000000100100000000000000000000000000000000000000000000000000000000000010010000000000000000000011111111000000000000000000000000000000000000000000000000000001100101000101101000001000000010101100100010000000000000000000000000000000010010000000010010000010010001001001000111010100110100100101011111010001010101010001001000010001010101001001000010010011110100111001000101010111110100001101000110010001110010000000100
00000000001","00000000000000000000000100000001000000000000000000000000000001000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000001000000000000000000000001111111100010000000000000000000000000000000000000000000000010010000101010010111111111001101000101000111000000000000000000000000000000001001000000001001100000111000000010100010101010100010010000100110101000001010000110101111101000001010001000100000101010000010101000100010101010010001000000010000000100000001000000010000000000001","000000000000000000000001000000000000000000000000000000000000010000000000000000000000000000000000011100000000000000000000000000000000000000000000000000000000000001110000111111111111111111111111000100000000000000000000000000000100111000101100000001011110010111111000110011111110101100010110000000000000000000000000000000010010000000010010000100100001001001001111010000110100111101010010010001010101001101011111010001010101010001001000010011010100000101000011001000000010000000100000001000000010000
00010000000000001","00000000000000000000000100000000000000000000000000000000000001110000000000000000000000000000000001100000000000000000000000000000000000000000000000000000000000000110000000000000000000000001111100000000000000000000000000000000000000000000000000000110010100011100101010111010101110100101011000000000000000000000000000000001001000000001001000000101000110000101011101000010001101000010110101010011011101000111001001100101011000010110110101101001011011100110011100101101010001000100110101000001010111110011000000000001","000000000000000100000001000000000000000000000000000000000000011100000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000100000000000001111111111111111000000000000000000000000000000000000000000000000110011100100001001100110110011111110101101010010000000000000000000000000000000010010000000010010000000110000010101010111010000100011010000101101010000100110110001101111011000110110101101010010010000010100110100100000001000000010000000100000001000000
01000000010000000000001","00000000000000010000000100000000000000000000000000000000000001110000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000001000000000001111111111111111100000000000000000000000000000000000000000000000011001110010000100110011011001111111010110101001000000000000000000000000000000001001000000001001000000011000001010101011101000010001101000010110101000010011011000110111101100011011010110101001001000001010011010010000000100000001000000010000000100000001000000010000000000001","000000000000000100000001000000000000000000000000000000000000011100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011111111111111111000000000000000000000000000000000000000000000000110011100100001001100110110011111110101101010010000000000000000000000000000000010010000000010010000000110000010101010111010000100011010000101101010000100110110001101111011000110110101101010010010000010100110100100000001000000010000000100000001
00000001000000010000000000001")
        g_sdb_addr = "00110000000000000000000000000000"
    Summary:
	no macro.
Unit <xwb_sdb_crossbar> synthesized.

Synthesizing Unit <sdb_rom>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd".
        g_layout =
("00000000000000000000000100000000000000000000000000000000000001110000000000000000000000000000000011000000000000000000000000000000000000000000000000000000000000001100000000000000000000001111111100000000000000000000000000000000000000000000000000000110010100010011010110101010011010111001010100000000000000000000000000000001001000000001001000000011000001010100011101010011010010010101111101000111010100000100100101001111010111110011001100110010001000000010000000100000001000000010000000100000001000000010000000000001","000000000000000000000001000000000000000000000000000000000000011100000000000000000000000000000000101100000000000000000000000000000000000000000000000000000000000010110000000000000000000011111111000000000000000000000000000000000000000000000000000001100101000100110101101010100110101110010101000000000000000000000000000000010010000000010010000000110000010101000111010100110100100101011111010001110101000001001001010011110101111100110011001100100010000000100000001000000010000000100000001000000010000000100000000
00001","00000000000000000000000100000000000000000000000000000000000000010000000000000000000000000000000010100000000000000000000000000000000000000000000000000000000000001010000000000000000000001111111100000000000000000000000000000000000000000000000011001110010000101000101001010111000110011010111000000000000000000000000000000001001000000001001000010000000100010100001101000101010100100100111001011111010100110100100101001101010100000100110001000101010111110101010101000001010100100101010000100000001000000010000000000001","000000000000000000000001000000010000000000000000000000000000010000000000000000000000000000000000100100000000000000000000000000000000000000000000000000000000000010010000000000000000000011111111000000000000000000000000000000000000000000000000000001100101000101101000001000000010101100100010000000000000000000000000000000010010000000010010000010010001001001000111010100110100100101011111010001010101010001001000010001010101001001000010010011110100111001000101010111110100001101000110010001110010000000100
00000000001","00000000000000000000000100000001000000000000000000000000000001000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000001000000000000000000000001111111100010000000000000000000000000000000000000000000000010010000101010010111111111001101000101000111000000000000000000000000000000001001000000001001100000111000000010100010101010100010010000100110101000001010000110101111101000001010001000100000101010000010101000100010101010010001000000010000000100000001000000010000000000001","000000000000000000000001000000000000000000000000000000000000010000000000000000000000000000000000011100000000000000000000000000000000000000000000000000000000000001110000111111111111111111111111000100000000000000000000000000000100111000101100000001011110010111111000110011111110101100010110000000000000000000000000000000010010000000010010000100100001001001001111010000110100111101010010010001010101001101011111010001010101010001001000010011010100000101000011001000000010000000100000001000000010000
00010000000000001","00000000000000000000000100000000000000000000000000000000000001110000000000000000000000000000000001100000000000000000000000000000000000000000000000000000000000000110000000000000000000000001111100000000000000000000000000000000000000000000000000000110010100011100101010111010101110100101011000000000000000000000000000000001001000000001001000000101000110000101011101000010001101000010110101010011011101000111001001100101011000010110110101101001011011100110011100101101010001000100110101000001010111110011000000000001","000000000000000100000001000000000000000000000000000000000000011100000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000100000000000001111111111111111000000000000000000000000000000000000000000000000110011100100001001100110110011111110101101010010000000000000000000000000000000010010000000010010000000110000010101010111010000100011010000101101010000100110110001101111011000110110101101010010010000010100110100100000001000000010000000100000001000000
01000000010000000000001","00000000000000010000000100000000000000000000000000000000000001110000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000001000000000001111111111111111100000000000000000000000000000000000000000000000011001110010000100110011011001111111010110101001000000000000000000000000000000001001000000001001000000011000001010101011101000010001101000010110101000010011011000110111101100011011010110101001001000001010011010010000000100000001000000010000000100000001000000010000000000001","000000000000000100000001000000000000000000000000000000000000011100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011111111111111111000000000000000000000000000000000000000000000000110011100100001001100110110011111110101101010010000000000000000000000000000000010010000000010010000000110000010101010111010000100011010000101101010000100110110001101111011000110110101101010010010000010100110100100000001000000010000000100000001
00000001000000010000000000001")
        g_bus_end = "0000000000000000000000000000000011111111111111111111111111111111"
WARNING:Xst:647 - Input <slave_i_adr<31:10>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <slave_i_adr<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <slave_i_sel<3:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <slave_i_dat<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <slave_i_we> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:2999 - Signal 'rom', unconnected in block 'sdb_rom', is tied to its initial value.
    Found 256x32-bit single-port Read Only RAM <Mram_rom> for signal <rom>.
    Found 1-bit register for signal <slave_o_ack>.
    Found 8-bit register for signal <adr_reg>.
    Summary:
	inferred   1 RAM(s).
	inferred   9 D-type flip-flop(s).
Unit <sdb_rom> synthesized.

Synthesizing Unit <xwb_crossbar>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd".
        g_num_masters = 8
        g_num_slaves = 11
        g_registered = true
        g_address = ("00110000000000000000000000000000","11000000000000000000000000000000","10110000000000000000000000000000","10100000000000000000000000000000","10010000000000000000000000000000","10000000000000000000000000000000","01110000000000000000000000000000","01100000000000000000000000000000","00100000000000000000000000000000","00010000000000000000000000000000","00000000000000000000000000000000")
        g_mask = ("11111111111111111111110000000000","11111111111111111111111100000000","11111111111111111111111100000000","11111111111111111111111100000000","11111111111111111111111100000000","11111111111111111111111100000000","11111111000000000000000000000000","11111111111111111111111111100000","11111111111111110000000000000000","11111111111111100000000000000000","11111111111111100000000000000000")
WARNING:Xst:647 - Input <master_i[10]_int> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <master_i[9]_int> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <master_i[8]_int> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <master_i[7]_int> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <master_i[6]_int> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <master_i[5]_int> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <master_i[4]_int> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <master_i[3]_int> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <master_i[2]_int> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <master_i[1]_int> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <master_i[0]_int> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 12-bit register for signal <matrix_old<7>>.
    Found 12-bit register for signal <matrix_old<6>>.
    Found 12-bit register for signal <matrix_old<5>>.
    Found 12-bit register for signal <matrix_old<4>>.
    Found 12-bit register for signal <matrix_old<3>>.
    Found 12-bit register for signal <matrix_old<2>>.
    Found 12-bit register for signal <matrix_old<1>>.
    Found 12-bit register for signal <matrix_old<0>>.
    Found 1-bit register for signal <virtual_ERR>.
    Summary:
	inferred  97 D-type flip-flop(s).
	inferred  96 Multiplexer(s).
Unit <xwb_crossbar> synthesized.

Synthesizing Unit <xwb_lm32>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd".
        g_profile = "medium_icache_debug"
WARNING:Xst:647 - Input <dwb_i_int> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <iwb_i_int> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" line 491: Output port <I_BTE_O> of the instance <gen_profile_medium_icache_debug.U_Wrapped_LM32> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" line 491: Output port <D_CTI_O> of the instance <gen_profile_medium_icache_debug.U_Wrapped_LM32> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" line 491: Output port <D_BTE_O> of the instance <gen_profile_medium_icache_debug.U_Wrapped_LM32> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" line 491: Output port <I_STB_O> of the instance <gen_profile_medium_icache_debug.U_Wrapped_LM32> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" line 491: Output port <I_LOCK_O> of the instance <gen_profile_medium_icache_debug.U_Wrapped_LM32> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" line 491: Output port <D_STB_O> of the instance <gen_profile_medium_icache_debug.U_Wrapped_LM32> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" line 491: Output port <D_LOCK_O> of the instance <gen_profile_medium_icache_debug.U_Wrapped_LM32> is unconnected or connected to loadless signal.
    Found 3-bit register for signal <inst_remaining>.
    Found 32-bit register for signal <inst_addr_reg>.
    Found 1-bit register for signal <data_was_busy>.
    Found 1-bit register for signal <data_remaining>.
    Found 32-bit register for signal <data_addr_reg>.
    Found 1-bit register for signal <inst_was_busy>.
    Found 2-bit subtractor for signal <n0267> created at line 688.
    Found 32-bit adder for signal <inst_addr_reg[31]_GND_56_o_add_9_OUT> created at line 1241.
    Found 32-bit adder for signal <data_addr_reg[31]_GND_56_o_add_20_OUT> created at line 1241.
    Found 3-bit subtractor for signal <GND_56_o_GND_56_o_sub_11_OUT<2:0>> created at line 650.
    Summary:
	inferred   4 Adder/Subtractor(s).
	inferred  70 D-type flip-flop(s).
	inferred  74 Multiplexer(s).
Unit <xwb_lm32> synthesized.

Synthesizing Unit <lm32_top_medium_icache_debug>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v".
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" line 39161: Output port <jrstn> of the instance <jtag_cores> is unconnected or connected to loadless signal.
    Summary:
	no macro.
Unit <lm32_top_medium_icache_debug> synthesized.

Synthesizing Unit <lm32_cpu_medium_icache_debug>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v".
        eba_reset = 32'b00000000000000000000000000000000
        deba_reset = 32'b00010000000000000000000000000000
        icache_associativity = 1
        icache_sets = 256
        icache_bytes_per_line = 16
        icache_base_address = 32'b00000000000000000000000000000000
        icache_limit = 32'b01111111111111111111111111111111
        dcache_associativity = 1
        dcache_sets = 512
        dcache_bytes_per_line = 16
        dcache_base_address = 0
        dcache_limit = 0
        watchpoints = 32'b00000000000000000000000000000100
        breakpoints = 0
        interrupts = 32
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" line 41044: Output port <pc_w> of the instance <instruction_unit> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" line 41154: Output port <x_result_sel_logic> of the instance <decoder> is unconnected or connected to loadless signal.
    Found 1-bit register for signal <regfile_raw_1>.
    Found 32-bit register for signal <w_result_d>.
    Found 23-bit register for signal <eba>.
    Found 23-bit register for signal <deba>.
    Found 1-bit register for signal <valid_f>.
    Found 1-bit register for signal <valid_d>.
    Found 1-bit register for signal <valid_x>.
    Found 1-bit register for signal <valid_m>.
    Found 1-bit register for signal <valid_w>.
    Found 32-bit register for signal <operand_0_x>.
    Found 32-bit register for signal <operand_1_x>.
    Found 32-bit register for signal <store_operand_x>.
    Found 29-bit register for signal <branch_target_x>.
    Found 1-bit register for signal <x_result_sel_csr_x>.
    Found 1-bit register for signal <x_result_sel_sext_x>.
    Found 1-bit register for signal <x_result_sel_add_x>.
    Found 1-bit register for signal <m_result_sel_compare_x>.
    Found 1-bit register for signal <m_result_sel_shift_x>.
    Found 1-bit register for signal <w_result_sel_load_x>.
    Found 1-bit register for signal <w_result_sel_mul_x>.
    Found 1-bit register for signal <x_bypass_enable_x>.
    Found 1-bit register for signal <m_bypass_enable_x>.
    Found 1-bit register for signal <write_enable_x>.
    Found 5-bit register for signal <write_idx_x>.
    Found 5-bit register for signal <csr_x>.
    Found 1-bit register for signal <load_x>.
    Found 1-bit register for signal <store_x>.
    Found 2-bit register for signal <size_x>.
    Found 1-bit register for signal <sign_extend_x>.
    Found 1-bit register for signal <adder_op_x>.
    Found 1-bit register for signal <adder_op_x_n>.
    Found 4-bit register for signal <logic_op_x>.
    Found 1-bit register for signal <direction_x>.
    Found 1-bit register for signal <branch_x>.
    Found 1-bit register for signal <branch_predict_x>.
    Found 1-bit register for signal <branch_predict_taken_x>.
    Found 3-bit register for signal <condition_x>.
    Found 1-bit register for signal <break_x>.
    Found 1-bit register for signal <system_call_exception>.
    Found 1-bit register for signal <eret_x>.
    Found 1-bit register for signal <bret_x>.
    Found 1-bit register for signal <csr_write_enable_x>.
    Found 32-bit register for signal <operand_m>.
    Found 29-bit register for signal <branch_target_m>.
    Found 1-bit register for signal <m_result_sel_compare_m>.
    Found 1-bit register for signal <m_result_sel_shift_m>.
    Found 1-bit register for signal <w_result_sel_load_m>.
    Found 1-bit register for signal <w_result_sel_mul_m>.
    Found 1-bit register for signal <m_bypass_enable_m>.
    Found 1-bit register for signal <branch_m>.
    Found 1-bit register for signal <branch_predict_m>.
    Found 1-bit register for signal <branch_predict_taken_m>.
    Found 1-bit register for signal <exception_m>.
    Found 1-bit register for signal <load_m>.
    Found 1-bit register for signal <store_m>.
    Found 1-bit register for signal <write_enable_m>.
    Found 5-bit register for signal <write_idx_m>.
    Found 1-bit register for signal <condition_met_m>.
    Found 1-bit register for signal <debug_exception_m>.
    Found 1-bit register for signal <non_debug_exception_m>.
    Found 32-bit register for signal <operand_w>.
    Found 1-bit register for signal <w_result_sel_load_w>.
    Found 1-bit register for signal <w_result_sel_mul_w>.
    Found 5-bit register for signal <write_idx_w>.
    Found 1-bit register for signal <write_enable_w>.
    Found 1-bit register for signal <debug_exception_w>.
    Found 1-bit register for signal <non_debug_exception_w>.
    Found 1-bit register for signal <use_buf>.
    Found 32-bit register for signal <reg_data_buf_0>.
    Found 32-bit register for signal <reg_data_buf_1>.
    Found 1-bit register for signal <regfile_raw_0>.
    Found 29-bit adder for signal <branch_target_d> created at line 41841.
    Found 32-bit 3-to-1 multiplexer for signal <d_result_1> created at line 41852.
    Found 1-bit 8-to-1 multiplexer for signal <condition_met_x> created at line 41889.
    Found 5-bit comparator equal for signal <write_idx_w[4]_instruction_f[25]_equal_1_o> created at line 41592
    Found 5-bit comparator equal for signal <write_idx_w[4]_instruction_f[20]_equal_2_o> created at line 41598
    Found 5-bit comparator equal for signal <write_idx_x[4]_read_idx_0_d[4]_equal_11_o> created at line 41779
    Found 5-bit comparator equal for signal <write_idx_m[4]_read_idx_0_d[4]_equal_13_o> created at line 41780
    Found 5-bit comparator equal for signal <write_idx_w[4]_read_idx_0_d[4]_equal_15_o> created at line 41781
    Found 5-bit comparator equal for signal <write_idx_x[4]_read_idx_1_d[4]_equal_17_o> created at line 41782
    Found 5-bit comparator equal for signal <write_idx_m[4]_read_idx_1_d[4]_equal_19_o> created at line 41783
    Found 5-bit comparator equal for signal <write_idx_w[4]_read_idx_1_d[4]_equal_21_o> created at line 41784
    Found 32-bit comparator equal for signal <cmp_zero> created at line 41883
    Found 1-bit comparator equal for signal <cmp_negative_cmp_overflow_equal_55_o> created at line 41896
    Summary:
	inferred   1 Adder/Subtractor(s).
	inferred 441 D-type flip-flop(s).
	inferred  10 Comparator(s).
	inferred  74 Multiplexer(s).
Unit <lm32_cpu_medium_icache_debug> synthesized.

Synthesizing Unit <lm32_instruction_unit_medium_icache_debug>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v".
        associativity = 1
        sets = 256
        bytes_per_line = 16
        base_address = 32'b00000000000000000000000000000000
        limit = 32'b01111111111111111111111111111111
WARNING:Xst:647 - Input <i_rty_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 29-bit register for signal <pc_d>.
    Found 29-bit register for signal <pc_x>.
    Found 29-bit register for signal <pc_m>.
    Found 29-bit register for signal <pc_w>.
    Found 29-bit register for signal <restart_address>.
    Found 1-bit register for signal <i_cyc_o>.
    Found 1-bit register for signal <i_stb_o>.
    Found 32-bit register for signal <i_adr_o>.
    Found 3-bit register for signal <i_cti_o>.
    Found 1-bit register for signal <i_lock_o>.
    Found 32-bit register for signal <icache_refill_data>.
    Found 1-bit register for signal <icache_refill_ready>.
    Found 1-bit register for signal <i_we_o>.
    Found 4-bit register for signal <i_sel_o>.
    Found 1-bit register for signal <jtag_access>.
    Found 32-bit register for signal <i_dat_o>.
    Found 32-bit register for signal <instruction_d>.
    Found 29-bit register for signal <pc_f>.
    Found 29-bit adder for signal <pc_f[30]_GND_60_o_add_9_OUT> created at line 48969.
    Found 2-bit adder for signal <i_adr_o[3]_GND_60_o_add_58_OUT> created at line 49199.
    Found 8-bit 4-to-1 multiplexer for signal <jtag_read_data> created at line 49131.
    Summary:
	inferred   2 Adder/Subtractor(s).
	inferred 314 D-type flip-flop(s).
	inferred  17 Multiplexer(s).
Unit <lm32_instruction_unit_medium_icache_debug> synthesized.

Synthesizing Unit <lm32_icache_medium_icache_debug>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v".
        associativity = 1
        sets = 256
        bytes_per_line = 16
        base_address = 32'b00000000000000000000000000000000
        limit = 32'b01111111111111111111111111111111
WARNING:Xst:647 - Input <address_a<30:12>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 4-bit register for signal <state>.
    Found 8-bit register for signal <flush_set>.
    Found 29-bit register for signal <refill_address>.
    Found 1-bit register for signal <restart_request>.
    Found 2-bit register for signal <refill_offset>.
    Found 1-bit register for signal <refilling>.
    Found finite state machine <FSM_0> for signal <state>.
    -----------------------------------------------------------------------
    | States             | 4                                              |
    | Transitions        | 18                                             |
    | Inputs             | 11                                             |
    | Outputs            | 8                                              |
    | Clock              | clk_i (rising_edge)                            |
    | Reset              | rst_i (positive)                               |
    | Reset type         | synchronous                                    |
    | Reset State        | 0001                                           |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 8-bit subtractor for signal <flush_set[7]_GND_61_o_sub_22_OUT> created at line 46392.
    Found 2-bit adder for signal <refill_offset[3]_GND_61_o_add_59_OUT> created at line 46469.
    Found 20-bit comparator equal for signal <way_match> created at line 46274
    Summary:
	inferred   2 Adder/Subtractor(s).
	inferred  41 D-type flip-flop(s).
	inferred   1 Comparator(s).
	inferred   8 Multiplexer(s).
	inferred   1 Finite State Machine(s).
Unit <lm32_icache_medium_icache_debug> synthesized.

Synthesizing Unit <lm32_ram_1>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.v".
        data_width = 32
        address_width = 10
WARNING:Xst:647 - Input <reset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 1024x32-bit dual-port RAM <Mram_mem> for signal <mem>.
    Found 10-bit register for signal <ra>.
    Summary:
	inferred   1 RAM(s).
	inferred  10 D-type flip-flop(s).
Unit <lm32_ram_1> synthesized.

Synthesizing Unit <lm32_ram_2>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.v".
        data_width = 20
        address_width = 8
WARNING:Xst:647 - Input <reset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 256x20-bit dual-port RAM <Mram_mem> for signal <mem>.
    Found 8-bit register for signal <ra>.
    Summary:
	inferred   1 RAM(s).
	inferred   8 D-type flip-flop(s).
Unit <lm32_ram_2> synthesized.

Synthesizing Unit <lm32_decoder_medium_icache_debug>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v".
WARNING:Xst:647 - Input <instruction<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Summary:
	inferred  10 Multiplexer(s).
Unit <lm32_decoder_medium_icache_debug> synthesized.

Synthesizing Unit <lm32_load_store_unit_medium_icache_debug>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v".
        associativity = 1
        sets = 512
        bytes_per_line = 16
        base_address = 0
        limit = 0
WARNING:Xst:647 - Input <load_store_address_x<31:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <stall_a> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <kill_x> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <load_x> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <store_x> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <store_q_x> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <d_rty_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 1-bit register for signal <d_stb_o>.
    Found 32-bit register for signal <d_dat_o>.
    Found 32-bit register for signal <d_adr_o>.
    Found 4-bit register for signal <d_sel_o>.
    Found 1-bit register for signal <d_we_o>.
    Found 1-bit register for signal <d_lock_o>.
    Found 32-bit register for signal <wb_data_m>.
    Found 1-bit register for signal <wb_load_complete>.
    Found 1-bit register for signal <stall_wb_load>.
    Found 1-bit register for signal <sign_extend_m>.
    Found 2-bit register for signal <size_m>.
    Found 4-bit register for signal <byte_enable_m>.
    Found 32-bit register for signal <store_data_m>.
    Found 1-bit register for signal <wb_select_m>.
    Found 2-bit register for signal <size_w>.
    Found 32-bit register for signal <data_w>.
    Found 1-bit register for signal <sign_extend_w>.
    Found 1-bit register for signal <d_cyc_o>.
    Found 32-bit 3-to-1 multiplexer for signal <store_data_x> created at line 44142.
    Summary:
	inferred 180 D-type flip-flop(s).
	inferred   2 Multiplexer(s).
Unit <lm32_load_store_unit_medium_icache_debug> synthesized.

Synthesizing Unit <lm32_adder>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v".
    Summary:
	no macro.
Unit <lm32_adder> synthesized.

Synthesizing Unit <lm32_addsub>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v".
    Found 33-bit subtractor for signal <GND_67_o_GND_67_o_sub_3_OUT> created at line 69.
    Found 33-bit subtractor for signal <tmp_subResult> created at line 69.
    Found 33-bit adder for signal <n0025> created at line 68.
    Found 33-bit adder for signal <tmp_addResult> created at line 68.
    Summary:
	inferred   4 Adder/Subtractor(s).
	inferred   2 Multiplexer(s).
Unit <lm32_addsub> synthesized.

Synthesizing Unit <lm32_logic_op>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v".
    Found 1-bit 4-to-1 multiplexer for signal <logic_result_x<0>> created at line 72.
    Found 1-bit 4-to-1 multiplexer for signal <logic_result_x<1>> created at line 72.
    Found 1-bit 4-to-1 multiplexer for signal <logic_result_x<2>> created at line 72.
    Found 1-bit 4-to-1 multiplexer for signal <logic_result_x<3>> created at line 72.
    Found 1-bit 4-to-1 multiplexer for signal <logic_result_x<4>> created at line 72.
    Found 1-bit 4-to-1 multiplexer for signal <logic_result_x<5>> created at line 72.
    Found 1-bit 4-to-1 multiplexer for signal <logic_result_x<6>> created at line 72.
    Found 1-bit 4-to-1 multiplexer for signal <logic_result_x<7>> created at line 72.
    Found 1-bit 4-to-1 multiplexer for signal <logic_result_x<8>> created at line 72.
    Found 1-bit 4-to-1 multiplexer for signal <logic_result_x<9>> created at line 72.
    Found 1-bit 4-to-1 multiplexer for signal <logic_result_x<10>> created at line 72.
    Found 1-bit 4-to-1 multiplexer for signal <logic_result_x<11>> created at line 72.
    Found 1-bit 4-to-1 multiplexer for signal <logic_result_x<12>> created at line 72.
    Found 1-bit 4-to-1 multiplexer for signal <logic_result_x<13>> created at line 72.
    Found 1-bit 4-to-1 multiplexer for signal <logic_result_x<14>> created at line 72.
    Found 1-bit 4-to-1 multiplexer for signal <logic_result_x<15>> created at line 72.
    Found 1-bit 4-to-1 multiplexer for signal <logic_result_x<16>> created at line 72.
    Found 1-bit 4-to-1 multiplexer for signal <logic_result_x<17>> created at line 72.
    Found 1-bit 4-to-1 multiplexer for signal <logic_result_x<18>> created at line 72.
    Found 1-bit 4-to-1 multiplexer for signal <logic_result_x<19>> created at line 72.
    Found 1-bit 4-to-1 multiplexer for signal <logic_result_x<20>> created at line 72.
    Found 1-bit 4-to-1 multiplexer for signal <logic_result_x<21>> created at line 72.
    Found 1-bit 4-to-1 multiplexer for signal <logic_result_x<22>> created at line 72.
    Found 1-bit 4-to-1 multiplexer for signal <logic_result_x<23>> created at line 72.
    Found 1-bit 4-to-1 multiplexer for signal <logic_result_x<24>> created at line 72.
    Found 1-bit 4-to-1 multiplexer for signal <logic_result_x<25>> created at line 72.
    Found 1-bit 4-to-1 multiplexer for signal <logic_result_x<26>> created at line 72.
    Found 1-bit 4-to-1 multiplexer for signal <logic_result_x<27>> created at line 72.
    Found 1-bit 4-to-1 multiplexer for signal <logic_result_x<28>> created at line 72.
    Found 1-bit 4-to-1 multiplexer for signal <logic_result_x<29>> created at line 72.
    Found 1-bit 4-to-1 multiplexer for signal <logic_result_x<30>> created at line 72.
    Found 1-bit 4-to-1 multiplexer for signal <logic_result_x<31>> created at line 72.
    Summary:
	inferred  32 Multiplexer(s).
Unit <lm32_logic_op> synthesized.

Synthesizing Unit <lm32_shifter>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v".
WARNING:Xst:647 - Input <operand_1_x<31:5>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 1-bit register for signal <direction_m>.
    Found 32-bit register for signal <right_shift_result>.
    Found 64-bit shifter logical right for signal <n0028> created at line 128
    Summary:
	inferred  33 D-type flip-flop(s).
	inferred   3 Multiplexer(s).
	inferred   1 Combinational logic shifter(s).
Unit <lm32_shifter> synthesized.

Synthesizing Unit <lm32_multiplier>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic/lm32_multiplier.v".
    Found 16-bit register for signal <a1>.
    Found 16-bit register for signal <b0>.
    Found 16-bit register for signal <b1>.
    Found 16-bit register for signal <c0>.
    Found 16-bit register for signal <c1>.
    Found 16-bit register for signal <d1>.
    Found 16-bit register for signal <e1>.
    Found 16-bit register for signal <result0>.
    Found 16-bit register for signal <result1>.
    Found 16-bit register for signal <a0>.
    Found 16-bit adder for signal <n0077> created at line 115.
    Found 16-bit adder for signal <c1[15]_e1[15]_add_17_OUT> created at line 115.
    Found 16x16-bit multiplier for signal <a0[15]_b0[15]_MuLt_9_OUT> created at line 109.
    Found 16x16-bit multiplier for signal <n0055> created at line 110.
    Found 16x16-bit multiplier for signal <n0056> created at line 111.
    Summary:
	inferred   3 Multiplier(s).
	inferred   2 Adder/Subtractor(s).
	inferred 160 D-type flip-flop(s).
Unit <lm32_multiplier> synthesized.

Synthesizing Unit <lm32_interrupt_medium_icache_debug>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v".
        interrupts = 32
WARNING:Xst:647 - Input <csr_write_data<3:31>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 1-bit register for signal <eie>.
    Found 1-bit register for signal <bie>.
    Found 32-bit register for signal <im>.
    Found 32-bit register for signal <ip>.
    Found 11-bit register for signal <eie_delay>.
    Found 1-bit register for signal <ie>.
    Found 32-bit 3-to-1 multiplexer for signal <csr_read_data> created at line 50671.
    Summary:
	inferred  78 D-type flip-flop(s).
	inferred  17 Multiplexer(s).
Unit <lm32_interrupt_medium_icache_debug> synthesized.

Synthesizing Unit <lm32_jtag_medium_icache_debug>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v".
WARNING:Xst:647 - Input <csr_write_data<31:8>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <jtag_clk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 1-bit register for signal <rx_update_r>.
    Found 1-bit register for signal <rx_update_r_r>.
    Found 1-bit register for signal <rx_update_r_r_r>.
    Found 4-bit register for signal <state>.
    Found 4-bit register for signal <command>.
    Found 8-bit register for signal <jtag_reg_d>.
    Found 1-bit register for signal <processing>.
    Found 1-bit register for signal <jtag_csr_write_enable>.
    Found 1-bit register for signal <jtag_read_enable>.
    Found 1-bit register for signal <jtag_write_enable>.
    Found 1-bit register for signal <jtag_break>.
    Found 1-bit register for signal <jtag_reset>.
    Found 8-bit register for signal <uart_tx_byte>.
    Found 1-bit register for signal <uart_tx_valid>.
    Found 8-bit register for signal <uart_rx_byte>.
    Found 1-bit register for signal <uart_rx_valid>.
    Found 8-bit register for signal <jtag_byte_4>.
    Found 8-bit register for signal <jtag_byte_3>.
    Found 8-bit register for signal <jtag_byte_2>.
    Found 8-bit register for signal <jtag_byte_1>.
    Found 8-bit register for signal <jtag_byte_0>.
    Found 1-bit register for signal <rx_update>.
    Found finite state machine <FSM_1> for signal <state>.
    -----------------------------------------------------------------------
    | States             | 9                                              |
    | Transitions        | 36                                             |
    | Inputs             | 13                                             |
    | Outputs            | 8                                              |
    | Clock              | clk_i (rising_edge)                            |
    | Reset              | rst_i (positive)                               |
    | Reset type         | synchronous                                    |
    | Reset State        | 0000                                           |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 16-bit adder for signal <jtag_byte_2[7]_GND_73_o_add_22_OUT> created at line 50090.
    Summary:
	inferred   1 Adder/Subtractor(s).
	inferred  80 D-type flip-flop(s).
	inferred  13 Multiplexer(s).
	inferred   1 Finite State Machine(s).
Unit <lm32_jtag_medium_icache_debug> synthesized.

Synthesizing Unit <lm32_debug_medium_icache_debug>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v".
        breakpoints = 0
        watchpoints = 32'b00000000000000000000000000000100
WARNING:Xst:647 - Input <pc_x<30:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:653 - Signal <wp_match_n<4>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
    Found 1-bit register for signal <wp<0><30>>.
    Found 1-bit register for signal <wp<0><29>>.
    Found 1-bit register for signal <wp<0><28>>.
    Found 1-bit register for signal <wp<0><27>>.
    Found 1-bit register for signal <wp<0><26>>.
    Found 1-bit register for signal <wp<0><25>>.
    Found 1-bit register for signal <wp<0><24>>.
    Found 1-bit register for signal <wp<0><23>>.
    Found 1-bit register for signal <wp<0><22>>.
    Found 1-bit register for signal <wp<0><21>>.
    Found 1-bit register for signal <wp<0><20>>.
    Found 1-bit register for signal <wp<0><19>>.
    Found 1-bit register for signal <wp<0><18>>.
    Found 1-bit register for signal <wp<0><17>>.
    Found 1-bit register for signal <wp<0><16>>.
    Found 1-bit register for signal <wp<0><15>>.
    Found 1-bit register for signal <wp<0><14>>.
    Found 1-bit register for signal <wp<0><13>>.
    Found 1-bit register for signal <wp<0><12>>.
    Found 1-bit register for signal <wp<0><11>>.
    Found 1-bit register for signal <wp<0><10>>.
    Found 1-bit register for signal <wp<0><9>>.
    Found 1-bit register for signal <wp<0><8>>.
    Found 1-bit register for signal <wp<0><7>>.
    Found 1-bit register for signal <wp<0><6>>.
    Found 1-bit register for signal <wp<0><5>>.
    Found 1-bit register for signal <wp<0><4>>.
    Found 1-bit register for signal <wp<0><3>>.
    Found 1-bit register for signal <wp<0><2>>.
    Found 1-bit register for signal <wp<0><1>>.
    Found 1-bit register for signal <wp<0><0>>.
    Found 1-bit register for signal <wpc_c<0><1>>.
    Found 1-bit register for signal <wpc_c<0><0>>.
    Found 1-bit register for signal <wp<1><31>>.
    Found 1-bit register for signal <wp<1><30>>.
    Found 1-bit register for signal <wp<1><29>>.
    Found 1-bit register for signal <wp<1><28>>.
    Found 1-bit register for signal <wp<1><27>>.
    Found 1-bit register for signal <wp<1><26>>.
    Found 1-bit register for signal <wp<1><25>>.
    Found 1-bit register for signal <wp<1><24>>.
    Found 1-bit register for signal <wp<1><23>>.
    Found 1-bit register for signal <wp<1><22>>.
    Found 1-bit register for signal <wp<1><21>>.
    Found 1-bit register for signal <wp<1><20>>.
    Found 1-bit register for signal <wp<1><19>>.
    Found 1-bit register for signal <wp<1><18>>.
    Found 1-bit register for signal <wp<1><17>>.
    Found 1-bit register for signal <wp<1><16>>.
    Found 1-bit register for signal <wp<1><15>>.
    Found 1-bit register for signal <wp<1><14>>.
    Found 1-bit register for signal <wp<1><13>>.
    Found 1-bit register for signal <wp<1><12>>.
    Found 1-bit register for signal <wp<1><11>>.
    Found 1-bit register for signal <wp<1><10>>.
    Found 1-bit register for signal <wp<1><9>>.
    Found 1-bit register for signal <wp<1><8>>.
    Found 1-bit register for signal <wp<1><7>>.
    Found 1-bit register for signal <wp<1><6>>.
    Found 1-bit register for signal <wp<1><5>>.
    Found 1-bit register for signal <wp<1><4>>.
    Found 1-bit register for signal <wp<1><3>>.
    Found 1-bit register for signal <wp<1><2>>.
    Found 1-bit register for signal <wp<1><1>>.
    Found 1-bit register for signal <wp<1><0>>.
    Found 1-bit register for signal <wpc_c<1><1>>.
    Found 1-bit register for signal <wpc_c<1><0>>.
    Found 1-bit register for signal <wp<2><31>>.
    Found 1-bit register for signal <wp<2><30>>.
    Found 1-bit register for signal <wp<2><29>>.
    Found 1-bit register for signal <wp<2><28>>.
    Found 1-bit register for signal <wp<2><27>>.
    Found 1-bit register for signal <wp<2><26>>.
    Found 1-bit register for signal <wp<2><25>>.
    Found 1-bit register for signal <wp<2><24>>.
    Found 1-bit register for signal <wp<2><23>>.
    Found 1-bit register for signal <wp<2><22>>.
    Found 1-bit register for signal <wp<2><21>>.
    Found 1-bit register for signal <wp<2><20>>.
    Found 1-bit register for signal <wp<2><19>>.
    Found 1-bit register for signal <wp<2><18>>.
    Found 1-bit register for signal <wp<2><17>>.
    Found 1-bit register for signal <wp<2><16>>.
    Found 1-bit register for signal <wp<2><15>>.
    Found 1-bit register for signal <wp<2><14>>.
    Found 1-bit register for signal <wp<2><13>>.
    Found 1-bit register for signal <wp<2><12>>.
    Found 1-bit register for signal <wp<2><11>>.
    Found 1-bit register for signal <wp<2><10>>.
    Found 1-bit register for signal <wp<2><9>>.
    Found 1-bit register for signal <wp<2><8>>.
    Found 1-bit register for signal <wp<2><7>>.
    Found 1-bit register for signal <wp<2><6>>.
    Found 1-bit register for signal <wp<2><5>>.
    Found 1-bit register for signal <wp<2><4>>.
    Found 1-bit register for signal <wp<2><3>>.
    Found 1-bit register for signal <wp<2><2>>.
    Found 1-bit register for signal <wp<2><1>>.
    Found 1-bit register for signal <wp<2><0>>.
    Found 1-bit register for signal <wpc_c<2><1>>.
    Found 1-bit register for signal <wpc_c<2><0>>.
    Found 1-bit register for signal <wp<3><31>>.
    Found 1-bit register for signal <wp<3><30>>.
    Found 1-bit register for signal <wp<3><29>>.
    Found 1-bit register for signal <wp<3><28>>.
    Found 1-bit register for signal <wp<3><27>>.
    Found 1-bit register for signal <wp<3><26>>.
    Found 1-bit register for signal <wp<3><25>>.
    Found 1-bit register for signal <wp<3><24>>.
    Found 1-bit register for signal <wp<3><23>>.
    Found 1-bit register for signal <wp<3><22>>.
    Found 1-bit register for signal <wp<3><21>>.
    Found 1-bit register for signal <wp<3><20>>.
    Found 1-bit register for signal <wp<3><19>>.
    Found 1-bit register for signal <wp<3><18>>.
    Found 1-bit register for signal <wp<3><17>>.
    Found 1-bit register for signal <wp<3><16>>.
    Found 1-bit register for signal <wp<3><15>>.
    Found 1-bit register for signal <wp<3><14>>.
    Found 1-bit register for signal <wp<3><13>>.
    Found 1-bit register for signal <wp<3><12>>.
    Found 1-bit register for signal <wp<3><11>>.
    Found 1-bit register for signal <wp<3><10>>.
    Found 1-bit register for signal <wp<3><9>>.
    Found 1-bit register for signal <wp<3><8>>.
    Found 1-bit register for signal <wp<3><7>>.
    Found 1-bit register for signal <wp<3><6>>.
    Found 1-bit register for signal <wp<3><5>>.
    Found 1-bit register for signal <wp<3><4>>.
    Found 1-bit register for signal <wp<3><3>>.
    Found 1-bit register for signal <wp<3><2>>.
    Found 1-bit register for signal <wp<3><1>>.
    Found 1-bit register for signal <wp<3><0>>.
    Found 1-bit register for signal <wpc_c<3><1>>.
    Found 1-bit register for signal <wpc_c<3><0>>.
    Found 1-bit register for signal <dc_re>.
    Found 3-bit register for signal <state>.
    Found 1-bit register for signal <dc_ss>.
    Found 1-bit register for signal <wp<0><31>>.
    Found finite state machine <FSM_2> for signal <state>.
    -----------------------------------------------------------------------
    | States             | 5                                              |
    | Transitions        | 36                                             |
    | Inputs             | 8                                              |
    | Outputs            | 4                                              |
    | Clock              | clk_i (rising_edge)                            |
    | Reset              | rst_i (positive)                               |
    | Reset type         | synchronous                                    |
    | Reset State        | 000                                            |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 32-bit comparator equal for signal <wp[0][31]_load_store_address_x[31]_equal_2_o> created at line 47900
    Found 32-bit comparator equal for signal <wp[1][31]_load_store_address_x[31]_equal_3_o> created at line 47900
    Found 32-bit comparator equal for signal <wp[2][31]_load_store_address_x[31]_equal_4_o> created at line 47900
    Found 32-bit comparator equal for signal <wp[3][31]_load_store_address_x[31]_equal_5_o> created at line 47900
    Summary:
	inferred 138 D-type flip-flop(s).
	inferred   4 Comparator(s).
	inferred  35 Multiplexer(s).
	inferred   1 Finite State Machine(s).
Unit <lm32_debug_medium_icache_debug> synthesized.

Synthesizing Unit <lm32_dp_ram>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.v".
        addr_width = 5
        addr_depth = 32
        data_width = 32
WARNING:Xst:647 - Input <rst_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 32x32-bit dual-port RAM <Mram_ram> for signal <ram>.
    Found 5-bit register for signal <raddr_r>.
    Summary:
	inferred   1 RAM(s).
	inferred   5 D-type flip-flop(s).
Unit <lm32_dp_ram> synthesized.

Synthesizing Unit <jtag_cores>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v".
    Found 11-bit register for signal <jtag_latched>.
    Found 11-bit register for signal <jtag_shift>.
    Summary:
	inferred  22 D-type flip-flop(s).
	inferred   1 Multiplexer(s).
Unit <jtag_cores> synthesized.

Synthesizing Unit <jtag_tap>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/virtex6/jtag_tap.v".
    Found 1-bit register for signal <update_delay>.
    Summary:
	inferred   1 D-type flip-flop(s).
Unit <jtag_tap> synthesized.

Synthesizing Unit <xwb_dma>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dma/xwb_dma.vhd".
        logRingLen = 4
WARNING:Xst:647 - Input <slave_i_adr<31:5>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <slave_i_adr<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <w_master_i_dat<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <r_master_i_int> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <w_master_i_int> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:653 - Signal <slave_o_int> is used but never assigned. This sourceless signal will be automatically connected to value GND.
    Found 16x32-bit dual-port RAM <Mram_ring> for signal <ring>.
    Found 5-bit register for signal <read_result_offset>.
    Found 5-bit register for signal <write_issue_offset>.
    Found 5-bit register for signal <write_result_offset>.
    Found 32-bit register for signal <read_issue_address>.
    Found 32-bit register for signal <write_issue_address>.
    Found 32-bit register for signal <read_stride>.
    Found 32-bit register for signal <write_stride>.
    Found 32-bit register for signal <transfer_count>.
    Found 1-bit register for signal <r_master_o_CYC>.
    Found 1-bit register for signal <w_master_o_CYC>.
    Found 1-bit register for signal <r_master_o_STB>.
    Found 1-bit register for signal <w_master_o_STB>.
    Found 1-bit register for signal <slave_o_ACK>.
    Found 32-bit register for signal <slave_o_DAT>.
    Found 1-bit register for signal <interrupt_o>.
    Found 5-bit register for signal <read_issue_offset>.
    Found 32-bit adder for signal <read_issue_address[31]_read_stride[31]_add_8_OUT> created at line 197.
    Found 5-bit adder for signal <read_issue_offset[4]_GND_79_o_add_9_OUT> created at line 1241.
    Found 5-bit adder for signal <read_result_offset[4]_GND_79_o_add_15_OUT> created at line 1241.
    Found 32-bit adder for signal <write_issue_address[31]_write_stride[31]_add_17_OUT> created at line 213.
    Found 5-bit adder for signal <write_issue_offset[4]_GND_79_o_add_18_OUT> created at line 1241.
    Found 5-bit adder for signal <write_result_offset[4]_GND_79_o_add_21_OUT> created at line 1241.
    Found 32-bit subtractor for signal <GND_79_o_GND_79_o_sub_11_OUT<31:0>> created at line 1308.
    Found 32-bit 7-to-1 multiplexer for signal <slave_i_adr[4]_GND_79_o_wide_mux_7_OUT> created at line 180.
    Found 4-bit comparator equal for signal <write_result_offset[4]_read_issue_offset[4]_equal_24_o> created at line 224
    Found 5-bit comparator not equal for signal <n0052> created at line 236
    Found 5-bit comparator not equal for signal <n0055> created at line 237
    Found 5-bit comparator not equal for signal <n0057> created at line 238
    Summary:
	inferred   1 RAM(s).
	inferred   7 Adder/Subtractor(s).
	inferred 218 D-type flip-flop(s).
	inferred   4 Comparator(s).
	inferred 175 Multiplexer(s).
Unit <xwb_dma> synthesized.

Synthesizing Unit <xwb_dpram_1>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd".
        g_size = 32768
        g_init_file = "../../../embedded-sw/dbe.ram"
        g_init_value = ""
        g_must_have_init_file = true
        g_slave1_interface_mode = pipelined
        g_slave2_interface_mode = pipelined
        g_slave1_granularity = byte
        g_slave2_granularity = byte
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 80: Output port <sl_dat_o> of the instance <U_Adapter1> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 80: Output port <ma_adr_o> of the instance <U_Adapter1> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 80: Output port <ma_dat_o> of the instance <U_Adapter1> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 80: Output port <ma_sel_o> of the instance <U_Adapter1> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 80: Output port <sl_err_o> of the instance <U_Adapter1> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 80: Output port <sl_rty_o> of the instance <U_Adapter1> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 80: Output port <sl_ack_o> of the instance <U_Adapter1> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 80: Output port <sl_stall_o> of the instance <U_Adapter1> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 80: Output port <sl_int_o> of the instance <U_Adapter1> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 80: Output port <ma_cyc_o> of the instance <U_Adapter1> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 80: Output port <ma_stb_o> of the instance <U_Adapter1> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 80: Output port <ma_we_o> of the instance <U_Adapter1> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 96: Output port <sl_dat_o> of the instance <U_Adapter2> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 96: Output port <ma_adr_o> of the instance <U_Adapter2> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 96: Output port <ma_dat_o> of the instance <U_Adapter2> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 96: Output port <ma_sel_o> of the instance <U_Adapter2> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 96: Output port <sl_err_o> of the instance <U_Adapter2> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 96: Output port <sl_rty_o> of the instance <U_Adapter2> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 96: Output port <sl_ack_o> of the instance <U_Adapter2> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 96: Output port <sl_stall_o> of the instance <U_Adapter2> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 96: Output port <sl_int_o> of the instance <U_Adapter2> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 96: Output port <ma_cyc_o> of the instance <U_Adapter2> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 96: Output port <ma_stb_o> of the instance <U_Adapter2> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 96: Output port <ma_we_o> of the instance <U_Adapter2> is unconnected or connected to loadless signal.
WARNING:Xst:653 - Signal <slave1_out_int> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <slave2_out_int> is used but never assigned. This sourceless signal will be automatically connected to value GND.
    Found 1-bit register for signal <slave2_out_ack>.
    Found 1-bit register for signal <slave1_out_ack>.
    Summary:
	inferred   2 D-type flip-flop(s).
	inferred   2 Multiplexer(s).
Unit <xwb_dpram_1> synthesized.

Synthesizing Unit <wb_slave_adapter_1>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd".
        g_master_use_struct = true
        g_master_mode = pipelined
        g_master_granularity = word
        g_slave_use_struct = true
        g_slave_mode = pipelined
        g_slave_granularity = byte
WARNING:Xst:647 - Input <sl_adr_i<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <sl_dat_i<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <sl_sel_i<3:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ma_dat_i<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clk_sys_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <rst_n_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <sl_cyc_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <sl_stb_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <sl_we_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ma_err_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ma_rty_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ma_ack_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ma_stall_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ma_int_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:653 - Signal <ma_adr_o> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <ma_dat_o> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <ma_sel_o> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <ma_cyc_o> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <ma_stb_o> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <ma_we_o> is used but never assigned. This sourceless signal will be automatically connected to value GND.
    Summary:
	no macro.
Unit <wb_slave_adapter_1> synthesized.

Synthesizing Unit <generic_dpram_1>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd".
        g_data_width = 32
        g_size = 32768
        g_with_byte_enable = true
        g_addr_conflict_resolution = "read_first"
        g_init_file = "../../../embedded-sw/dbe.ram"
        g_init_value = ""
        g_dual_clock = false
        g_fail_if_file_not_found = true
WARNING:Xst:647 - Input <clkb_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Summary:
	no macro.
Unit <generic_dpram_1> synthesized.

Synthesizing Unit <generic_dpram_sameclock_1>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd".
        g_data_width = 32
        g_size = 32768
        g_with_byte_enable = true
        g_addr_conflict_resolution = "read_first"
        g_init_file = "../../../embedded-sw/dbe.ram"
        g_init_value = ""
        g_fail_if_file_not_found = true
WARNING:Xst:647 - Input <rst_n_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 32768x32-bit dual-port RAM <Mram_ram> for signal <ram>.
    Found 32-bit register for signal <qb_o>.
    Found 32-bit register for signal <qa_o>.
    Summary:
	inferred   1 RAM(s).
	inferred  64 D-type flip-flop(s).
	inferred   8 Multiplexer(s).
Unit <generic_dpram_sameclock_1> synthesized.

Synthesizing Unit <xwb_dpram_2>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd".
        g_size = 16384
        g_init_file = ""
        g_init_value = ""
        g_must_have_init_file = false
        g_slave1_interface_mode = classic
        g_slave2_interface_mode = classic
        g_slave1_granularity = byte
        g_slave2_granularity = word
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 80: Output port <sl_dat_o> of the instance <U_Adapter1> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 80: Output port <ma_adr_o> of the instance <U_Adapter1> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 80: Output port <ma_dat_o> of the instance <U_Adapter1> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 80: Output port <ma_sel_o> of the instance <U_Adapter1> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 80: Output port <sl_err_o> of the instance <U_Adapter1> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 80: Output port <sl_rty_o> of the instance <U_Adapter1> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 80: Output port <sl_ack_o> of the instance <U_Adapter1> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 80: Output port <sl_stall_o> of the instance <U_Adapter1> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 80: Output port <sl_int_o> of the instance <U_Adapter1> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 80: Output port <ma_cyc_o> of the instance <U_Adapter1> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 80: Output port <ma_stb_o> of the instance <U_Adapter1> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 80: Output port <ma_we_o> of the instance <U_Adapter1> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 96: Output port <sl_dat_o> of the instance <U_Adapter2> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 96: Output port <ma_adr_o> of the instance <U_Adapter2> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 96: Output port <ma_dat_o> of the instance <U_Adapter2> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 96: Output port <ma_sel_o> of the instance <U_Adapter2> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 96: Output port <sl_err_o> of the instance <U_Adapter2> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 96: Output port <sl_rty_o> of the instance <U_Adapter2> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 96: Output port <sl_ack_o> of the instance <U_Adapter2> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 96: Output port <sl_stall_o> of the instance <U_Adapter2> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 96: Output port <sl_int_o> of the instance <U_Adapter2> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 96: Output port <ma_cyc_o> of the instance <U_Adapter2> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 96: Output port <ma_stb_o> of the instance <U_Adapter2> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 96: Output port <ma_we_o> of the instance <U_Adapter2> is unconnected or connected to loadless signal.
WARNING:Xst:653 - Signal <slave1_out_int> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <slave2_out_int> is used but never assigned. This sourceless signal will be automatically connected to value GND.
    Found 1-bit register for signal <slave2_out_ack>.
    Found 1-bit register for signal <slave1_out_ack>.
    Summary:
	inferred   2 D-type flip-flop(s).
	inferred   4 Multiplexer(s).
Unit <xwb_dpram_2> synthesized.

Synthesizing Unit <wb_slave_adapter_2>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd".
        g_master_use_struct = true
        g_master_mode = classic
        g_master_granularity = word
        g_slave_use_struct = true
        g_slave_mode = classic
        g_slave_granularity = byte
WARNING:Xst:647 - Input <sl_adr_i<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <sl_dat_i<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <sl_sel_i<3:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ma_dat_i<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clk_sys_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <rst_n_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <sl_cyc_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <sl_stb_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <sl_we_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ma_err_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ma_rty_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ma_ack_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ma_stall_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ma_int_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:653 - Signal <ma_adr_o> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <ma_dat_o> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <ma_sel_o> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <ma_cyc_o> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <ma_stb_o> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <ma_we_o> is used but never assigned. This sourceless signal will be automatically connected to value GND.
    Summary:
	no macro.
Unit <wb_slave_adapter_2> synthesized.

Synthesizing Unit <wb_slave_adapter_3>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd".
        g_master_use_struct = true
        g_master_mode = classic
        g_master_granularity = word
        g_slave_use_struct = true
        g_slave_mode = classic
        g_slave_granularity = word
WARNING:Xst:647 - Input <sl_adr_i<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <sl_dat_i<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <sl_sel_i<3:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ma_dat_i<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clk_sys_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <rst_n_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <sl_cyc_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <sl_stb_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <sl_we_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ma_err_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ma_rty_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ma_ack_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ma_stall_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ma_int_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:653 - Signal <ma_adr_o> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <ma_dat_o> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <ma_sel_o> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <ma_cyc_o> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <ma_stb_o> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <ma_we_o> is used but never assigned. This sourceless signal will be automatically connected to value GND.
    Summary:
	no macro.
Unit <wb_slave_adapter_3> synthesized.

Synthesizing Unit <generic_dpram_2>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd".
        g_data_width = 32
        g_size = 16384
        g_with_byte_enable = true
        g_addr_conflict_resolution = "read_first"
        g_init_file = ""
        g_init_value = ""
        g_dual_clock = false
        g_fail_if_file_not_found = true
WARNING:Xst:647 - Input <clkb_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Summary:
	no macro.
Unit <generic_dpram_2> synthesized.

Synthesizing Unit <generic_dpram_sameclock_2>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd".
        g_data_width = 32
        g_size = 16384
        g_with_byte_enable = true
        g_addr_conflict_resolution = "read_first"
        g_init_file = ""
        g_init_value = ""
        g_fail_if_file_not_found = true
WARNING:Xst:647 - Input <rst_n_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 16384x32-bit dual-port RAM <Mram_ram> for signal <ram>.
    Found 32-bit register for signal <qb_o>.
    Found 32-bit register for signal <qa_o>.
    Summary:
	inferred   1 RAM(s).
	inferred  64 D-type flip-flop(s).
	inferred   8 Multiplexer(s).
Unit <generic_dpram_sameclock_2> synthesized.

Synthesizing Unit <xwb_ethmac>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/xwb_ethmac.vhd".
        g_ma_interface_mode = classic
        g_ma_address_granularity = byte
        g_sl_interface_mode = pipelined
        g_sl_address_granularity = byte
WARNING:Xst:647 - Input <wb_slave_in_adr<31:12>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <wb_master_in_int> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:653 - Signal <wb_slave_out_int> is used but never assigned. This sourceless signal will be automatically connected to value GND.
    Summary:
	no macro.
Unit <xwb_ethmac> synthesized.

Synthesizing Unit <wb_ethmac>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/wb_ethmac.vhd".
        g_ma_interface_mode = classic
        g_ma_address_granularity = byte
        g_sl_interface_mode = pipelined
        g_sl_address_granularity = byte
WARNING:Xst:647 - Input <m_wb_stall_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <m_wb_rty_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/wb_ethmac.vhd" line 167: Output port <slave_o_dat> of the instance <cmp_sl_iface_slave_adapter> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/wb_ethmac.vhd" line 167: Output port <ma_adr_o> of the instance <cmp_sl_iface_slave_adapter> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/wb_ethmac.vhd" line 167: Output port <ma_dat_o> of the instance <cmp_sl_iface_slave_adapter> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/wb_ethmac.vhd" line 167: Output port <ma_sel_o> of the instance <cmp_sl_iface_slave_adapter> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/wb_ethmac.vhd" line 167: Output port <sl_int_o> of the instance <cmp_sl_iface_slave_adapter> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/wb_ethmac.vhd" line 167: Output port <slave_o_ack> of the instance <cmp_sl_iface_slave_adapter> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/wb_ethmac.vhd" line 167: Output port <slave_o_err> of the instance <cmp_sl_iface_slave_adapter> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/wb_ethmac.vhd" line 167: Output port <slave_o_rty> of the instance <cmp_sl_iface_slave_adapter> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/wb_ethmac.vhd" line 167: Output port <slave_o_stall> of the instance <cmp_sl_iface_slave_adapter> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/wb_ethmac.vhd" line 167: Output port <slave_o_int> of the instance <cmp_sl_iface_slave_adapter> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/wb_ethmac.vhd" line 167: Output port <ma_cyc_o> of the instance <cmp_sl_iface_slave_adapter> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/wb_ethmac.vhd" line 167: Output port <ma_stb_o> of the instance <cmp_sl_iface_slave_adapter> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/wb_ethmac.vhd" line 167: Output port <ma_we_o> of the instance <cmp_sl_iface_slave_adapter> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/wb_ethmac.vhd" line 239: Output port <m_wb_cti_o> of the instance <cmp_wrapper_ethmac> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/wb_ethmac.vhd" line 239: Output port <m_wb_bte_o> of the instance <cmp_wrapper_ethmac> is unconnected or connected to loadless signal.
    Summary:
	no macro.
Unit <wb_ethmac> synthesized.

Synthesizing Unit <wb_slave_adapter_4>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd".
        g_master_use_struct = true
        g_master_mode = classic
        g_master_granularity = byte
        g_slave_use_struct = false
        g_slave_mode = pipelined
        g_slave_granularity = byte
WARNING:Xst:647 - Input <slave_i_adr<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <slave_i_sel<3:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <slave_i_dat<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ma_dat_i<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clk_sys_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <rst_n_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <slave_i_cyc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <slave_i_stb> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <slave_i_we> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ma_err_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ma_rty_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ma_ack_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ma_stall_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ma_int_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <master_i_stall> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:653 - Signal <ma_adr_o> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <ma_dat_o> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <ma_sel_o> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <ma_cyc_o> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <ma_stb_o> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <ma_we_o> is used but never assigned. This sourceless signal will be automatically connected to value GND.
    Summary:
	no macro.
Unit <wb_slave_adapter_4> synthesized.

Synthesizing Unit <ethmac>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/ethmac.v".
WARNING:Xst:647 - Input <wb_adr_i<2:8>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/ethmac.v" line 370: Output port <r_Iam> of the instance <ethreg1> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/ethmac.v" line 370: Output port <r_NoPre> of the instance <ethreg1> is unconnected or connected to loadless signal.
    Found 32-bit register for signal <temp_wb_dat_o_reg>.
    Found 1-bit register for signal <temp_wb_err_o_reg>.
    Found 1-bit register for signal <CarrierSense_Tx1>.
    Found 1-bit register for signal <CarrierSense_Tx2>.
    Found 1-bit register for signal <Collision_Tx1>.
    Found 1-bit register for signal <Collision_Tx2>.
    Found 1-bit register for signal <RxEnSync>.
    Found 1-bit register for signal <WillSendControlFrame_sync1>.
    Found 1-bit register for signal <WillSendControlFrame_sync2>.
    Found 1-bit register for signal <WillSendControlFrame_sync3>.
    Found 1-bit register for signal <RstTxPauseRq>.
    Found 1-bit register for signal <TxPauseRq_sync1>.
    Found 1-bit register for signal <TxPauseRq_sync2>.
    Found 1-bit register for signal <TxPauseRq_sync3>.
    Found 1-bit register for signal <TPauseRq>.
    Found 1-bit register for signal <RxAbort_latch>.
    Found 1-bit register for signal <RxAbort_sync1>.
    Found 1-bit register for signal <RxAbort_wb>.
    Found 1-bit register for signal <RxAbortRst_sync1>.
    Found 1-bit register for signal <RxAbortRst>.
    Found 1-bit register for signal <temp_wb_ack_o_reg>.
    Found 1-bit register for signal <WillTransmit_q>.
    Found 1-bit register for signal <WillTransmit_q2>.
    Summary:
	inferred  54 D-type flip-flop(s).
	inferred   4 Multiplexer(s).
Unit <ethmac> synthesized.

Synthesizing Unit <eth_miim>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_miim.v".
        Tp = 1
    Found 1-bit register for signal <EndBusy>.
    Found 1-bit register for signal <UpdateMIIRX_DATAReg>.
    Found 1-bit register for signal <WCtrlData_q1>.
    Found 1-bit register for signal <WCtrlData_q2>.
    Found 1-bit register for signal <WCtrlData_q3>.
    Found 1-bit register for signal <RStat_q1>.
    Found 1-bit register for signal <RStat_q2>.
    Found 1-bit register for signal <RStat_q3>.
    Found 1-bit register for signal <ScanStat_q1>.
    Found 1-bit register for signal <ScanStat_q2>.
    Found 1-bit register for signal <SyncStatMdcEn>.
    Found 1-bit register for signal <WCtrlDataStart>.
    Found 1-bit register for signal <WCtrlDataStart_q>.
    Found 1-bit register for signal <RStatStart>.
    Found 1-bit register for signal <Nvalid>.
    Found 1-bit register for signal <WCtrlDataStart_q1>.
    Found 1-bit register for signal <WCtrlDataStart_q2>.
    Found 1-bit register for signal <RStatStart_q1>.
    Found 1-bit register for signal <RStatStart_q2>.
    Found 1-bit register for signal <InProgress_q1>.
    Found 1-bit register for signal <InProgress_q2>.
    Found 1-bit register for signal <InProgress_q3>.
    Found 1-bit register for signal <LatchByte0_d>.
    Found 1-bit register for signal <LatchByte1_d>.
    Found 1-bit register for signal <InProgress>.
    Found 1-bit register for signal <WriteOp>.
    Found 1-bit register for signal <EndBusy_d>.
    Found 2-bit register for signal <LatchByte>.
    Found 7-bit register for signal <BitCounter>.
    Found 7-bit adder for signal <BitCounter[6]_GND_134_o_add_3_OUT> created at line 409.
    Summary:
	inferred   1 Adder/Subtractor(s).
	inferred  36 D-type flip-flop(s).
	inferred   3 Multiplexer(s).
Unit <eth_miim> synthesized.

Synthesizing Unit <eth_clockgen>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_clockgen.v".
        Tp = 1
    Found 1-bit register for signal <Mdc>.
    Found 8-bit register for signal <Counter>.
    Found 8-bit subtractor for signal <CounterPreset> created at line 92.
    Found 8-bit subtractor for signal <Counter[7]_GND_135_o_sub_4_OUT> created at line 107.
    Found 8-bit comparator greater for signal <Divider[7]_GND_135_o_LessThan_1_o> created at line 91
    Summary:
	inferred   1 Adder/Subtractor(s).
	inferred   9 D-type flip-flop(s).
	inferred   1 Comparator(s).
	inferred   2 Multiplexer(s).
Unit <eth_clockgen> synthesized.

Synthesizing Unit <eth_shiftreg>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_shiftreg.v".
        Tp = 1
    Found 1-bit register for signal <LinkFail>.
    Found 16-bit register for signal <Prsd>.
    Found 8-bit register for signal <ShiftReg>.
    Summary:
	inferred  25 D-type flip-flop(s).
	inferred  10 Multiplexer(s).
Unit <eth_shiftreg> synthesized.

Synthesizing Unit <eth_outputcontrol>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_outputcontrol.v".
        Tp = 1
    Found 1-bit register for signal <MdoEn_d>.
    Found 1-bit register for signal <MdoEn>.
    Found 1-bit register for signal <Mdo_2d>.
    Found 1-bit register for signal <Mdo_d>.
    Found 1-bit register for signal <Mdo>.
    Found 1-bit register for signal <MdoEn_2d>.
    Found 7-bit comparator greater for signal <GND_138_o_BitCounter[6]_LessThan_1_o> created at line 100
    Found 7-bit comparator greater for signal <BitCounter[6]_GND_138_o_LessThan_4_o> created at line 101
    Found 7-bit comparator greater for signal <BitCounter[6]_GND_138_o_LessThan_7_o> created at line 138
    Summary:
	inferred   6 D-type flip-flop(s).
	inferred   3 Comparator(s).
Unit <eth_outputcontrol> synthesized.

Synthesizing Unit <eth_registers>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_registers.v".
        Tp = 1
    Found 1-bit register for signal <SetTxCIrq_sync1>.
    Found 1-bit register for signal <SetTxCIrq_sync2>.
    Found 1-bit register for signal <SetTxCIrq_sync3>.
    Found 1-bit register for signal <SetTxCIrq>.
    Found 1-bit register for signal <ResetTxCIrq_sync2>.
    Found 1-bit register for signal <SetRxCIrq_rxclk>.
    Found 1-bit register for signal <SetRxCIrq_sync1>.
    Found 1-bit register for signal <SetRxCIrq_sync2>.
    Found 1-bit register for signal <SetRxCIrq_sync3>.
    Found 1-bit register for signal <SetRxCIrq>.
    Found 1-bit register for signal <ResetRxCIrq_sync1>.
    Found 1-bit register for signal <ResetRxCIrq_sync2>.
    Found 1-bit register for signal <ResetRxCIrq_sync3>.
    Found 1-bit register for signal <irq_txb>.
    Found 1-bit register for signal <irq_txe>.
    Found 1-bit register for signal <irq_rxb>.
    Found 1-bit register for signal <irq_rxe>.
    Found 1-bit register for signal <irq_busy>.
    Found 1-bit register for signal <irq_txc>.
    Found 1-bit register for signal <irq_rxc>.
    Found 1-bit register for signal <SetTxCIrq_txclk>.
    Found 32-bit 25-to-1 multiplexer for signal <_n0358> created at line 861.
    Found 32-bit comparator lessequal for signal <n0045> created at line 388
    Found 32-bit comparator greater for signal <GND_139_o_TX_BD_NUMOut[31]_LessThan_67_o> created at line 907
    Found 32-bit comparator greater for signal <TX_BD_NUMOut[31]_GND_139_o_LessThan_68_o> created at line 908
    Summary:
	inferred  21 D-type flip-flop(s).
	inferred   3 Comparator(s).
	inferred   3 Multiplexer(s).
Unit <eth_registers> synthesized.

Synthesizing Unit <eth_register_1>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_register.v".
        WIDTH = 8
        RESET_VALUE = 8'b00000000
    Found 8-bit register for signal <DataOut>.
    Summary:
	inferred   8 D-type flip-flop(s).
	inferred   1 Multiplexer(s).
Unit <eth_register_1> synthesized.

Synthesizing Unit <eth_register_2>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_register.v".
        WIDTH = 8
        RESET_VALUE = 8'b10100000
    Found 8-bit register for signal <DataOut>.
    Summary:
	inferred   8 D-type flip-flop(s).
Unit <eth_register_2> synthesized.

Synthesizing Unit <eth_register_3>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_register.v".
        WIDTH = 1
        RESET_VALUE = 1'b0
    Found 1-bit register for signal <DataOut>.
    Summary:
	inferred   1 D-type flip-flop(s).
	inferred   1 Multiplexer(s).
Unit <eth_register_3> synthesized.

Synthesizing Unit <eth_register_4>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_register.v".
        WIDTH = 7
        RESET_VALUE = 7'b0000000
    Found 7-bit register for signal <DataOut>.
    Summary:
	inferred   7 D-type flip-flop(s).
Unit <eth_register_4> synthesized.

Synthesizing Unit <eth_register_5>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_register.v".
        WIDTH = 7
        RESET_VALUE = 7'b0010010
    Found 7-bit register for signal <DataOut>.
    Summary:
	inferred   7 D-type flip-flop(s).
	inferred   1 Multiplexer(s).
Unit <eth_register_5> synthesized.

Synthesizing Unit <eth_register_6>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_register.v".
        WIDTH = 7
        RESET_VALUE = 7'b0001100
    Found 7-bit register for signal <DataOut>.
    Summary:
	inferred   7 D-type flip-flop(s).
Unit <eth_register_6> synthesized.

Synthesizing Unit <eth_register_7>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_register.v".
        WIDTH = 8
        RESET_VALUE = 8'b00000110
    Found 8-bit register for signal <DataOut>.
    Summary:
	inferred   8 D-type flip-flop(s).
Unit <eth_register_7> synthesized.

Synthesizing Unit <eth_register_8>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_register.v".
        WIDTH = 8
        RESET_VALUE = 8'b01000000
    Found 8-bit register for signal <DataOut>.
    Summary:
	inferred   8 D-type flip-flop(s).
	inferred   1 Multiplexer(s).
Unit <eth_register_8> synthesized.

Synthesizing Unit <eth_register_9>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_register.v".
        WIDTH = 6
        RESET_VALUE = 6'b111111
    Found 6-bit register for signal <DataOut>.
    Summary:
	inferred   6 D-type flip-flop(s).
Unit <eth_register_9> synthesized.

Synthesizing Unit <eth_register_10>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_register.v".
        WIDTH = 4
        RESET_VALUE = 4'b1111
    Found 4-bit register for signal <DataOut>.
    Summary:
	inferred   4 D-type flip-flop(s).
Unit <eth_register_10> synthesized.

Synthesizing Unit <eth_register_11>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_register.v".
        WIDTH = 3
        RESET_VALUE = 3'b000
    Found 3-bit register for signal <DataOut>.
    Summary:
	inferred   3 D-type flip-flop(s).
Unit <eth_register_11> synthesized.

Synthesizing Unit <eth_register_12>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_register.v".
        WIDTH = 8
        RESET_VALUE = 8'b01100100
    Found 8-bit register for signal <DataOut>.
    Summary:
	inferred   8 D-type flip-flop(s).
Unit <eth_register_12> synthesized.

Synthesizing Unit <eth_register_13>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_register.v".
        WIDTH = 1
        RESET_VALUE = 0
    Found 1-bit register for signal <DataOut>.
    Summary:
	inferred   1 D-type flip-flop(s).
	inferred   1 Multiplexer(s).
Unit <eth_register_13> synthesized.

Synthesizing Unit <eth_register_14>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_register.v".
        WIDTH = 5
        RESET_VALUE = 5'b00000
    Found 5-bit register for signal <DataOut>.
    Summary:
	inferred   5 D-type flip-flop(s).
	inferred   1 Multiplexer(s).
Unit <eth_register_14> synthesized.

Synthesizing Unit <eth_register_15>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_register.v".
        WIDTH = 16
        RESET_VALUE = 16'b0000000000000000
    Found 16-bit register for signal <DataOut>.
    Summary:
	inferred  16 D-type flip-flop(s).
Unit <eth_register_15> synthesized.

Synthesizing Unit <eth_maccontrol>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_maccontrol.v".
        Tp = 1
    Found 1-bit register for signal <TxAbortInLatched>.
    Found 1-bit register for signal <TxDoneInLatched>.
    Found 1-bit register for signal <MuxedAbort>.
    Found 1-bit register for signal <MuxedDone>.
    Found 1-bit register for signal <TxUsedDataOutDetected>.
    Summary:
	inferred   5 D-type flip-flop(s).
	inferred   5 Multiplexer(s).
Unit <eth_maccontrol> synthesized.

Synthesizing Unit <eth_receivecontrol>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_receivecontrol.v".
        Tp = 1
    Found 1-bit register for signal <DetectionWindow>.
    Found 1-bit register for signal <PauseTimerEq0_sync1>.
    Found 1-bit register for signal <PauseTimerEq0_sync2>.
    Found 1-bit register for signal <TypeLengthOK>.
    Found 1-bit register for signal <OpCodeOK>.
    Found 1-bit register for signal <ReceivedPauseFrmWAddr>.
    Found 1-bit register for signal <AssembledTimerValue<15>>.
    Found 1-bit register for signal <AssembledTimerValue<14>>.
    Found 1-bit register for signal <AssembledTimerValue<13>>.
    Found 1-bit register for signal <AssembledTimerValue<12>>.
    Found 1-bit register for signal <AssembledTimerValue<11>>.
    Found 1-bit register for signal <AssembledTimerValue<10>>.
    Found 1-bit register for signal <AssembledTimerValue<9>>.
    Found 1-bit register for signal <AssembledTimerValue<8>>.
    Found 1-bit register for signal <AssembledTimerValue<7>>.
    Found 1-bit register for signal <AssembledTimerValue<6>>.
    Found 1-bit register for signal <AssembledTimerValue<5>>.
    Found 1-bit register for signal <AssembledTimerValue<4>>.
    Found 1-bit register for signal <AssembledTimerValue<3>>.
    Found 1-bit register for signal <AssembledTimerValue<2>>.
    Found 1-bit register for signal <AssembledTimerValue<1>>.
    Found 1-bit register for signal <AssembledTimerValue<0>>.
    Found 1-bit register for signal <Divider2>.
    Found 1-bit register for signal <ReceivedPauseFrm>.
    Found 1-bit register for signal <AddressOK>.
    Found 1-bit register for signal <Pause>.
    Found 16-bit register for signal <LatchedTimerValue>.
    Found 16-bit register for signal <PauseTimer>.
    Found 3-bit register for signal <DlyCrcCnt>.
    Found 5-bit register for signal <ByteCnt>.
    Found 6-bit register for signal <SlotTimer>.
    Found 16-bit subtractor for signal <PauseTimer[15]_GND_164_o_sub_45_OUT> created at line 356.
    Found 3-bit adder for signal <DlyCrcCnt[2]_GND_164_o_add_22_OUT> created at line 304.
    Found 5-bit adder for signal <ByteCnt[4]_GND_164_o_add_26_OUT> created at line 323.
    Found 6-bit adder for signal <SlotTimer[5]_GND_164_o_add_50_OUT> created at line 417.
    Found 8-bit comparator equal for signal <RxData[7]_MAC[47]_equal_4_o> created at line 171
    Found 8-bit comparator equal for signal <RxData[7]_MAC[39]_equal_6_o> created at line 174
    Found 8-bit comparator equal for signal <RxData[7]_MAC[31]_equal_8_o> created at line 177
    Found 8-bit comparator equal for signal <RxData[7]_MAC[23]_equal_10_o> created at line 180
    Found 8-bit comparator equal for signal <RxData[7]_MAC[15]_equal_12_o> created at line 183
    Found 8-bit comparator equal for signal <RxData[7]_MAC[7]_equal_14_o> created at line 186
    Summary:
	inferred   4 Adder/Subtractor(s).
	inferred  72 D-type flip-flop(s).
	inferred   6 Comparator(s).
	inferred  32 Multiplexer(s).
Unit <eth_receivecontrol> synthesized.

Synthesizing Unit <eth_transmitcontrol>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_transmitcontrol.v".
        Tp = 1
    Found 1-bit register for signal <TxCtrlStartFrm>.
    Found 1-bit register for signal <TxCtrlEndFrm>.
    Found 1-bit register for signal <CtrlMux>.
    Found 1-bit register for signal <SendingCtrlFrm>.
    Found 1-bit register for signal <TxUsedDataIn_q>.
    Found 1-bit register for signal <BlockTxDone>.
    Found 1-bit register for signal <WillSendControlFrame>.
    Found 4-bit register for signal <DlyCrcCnt>.
    Found 6-bit register for signal <ByteCnt>.
    Found 8-bit register for signal <ControlData>.
    Found 1-bit register for signal <ControlEnd_q>.
    Found 1-bit register for signal <TxCtrlStartFrm_q>.
    Found 4-bit adder for signal <DlyCrcCnt[3]_GND_166_o_add_1_OUT> created at line 255.
    Found 6-bit adder for signal <ByteCnt[5]_GND_166_o_add_6_OUT> created at line 274.
    Found 6-bit adder for signal <ByteCnt[5]_GND_166_o_add_7_OUT> created at line 277.
    Summary:
	inferred   2 Adder/Subtractor(s).
	inferred  27 D-type flip-flop(s).
	inferred  20 Multiplexer(s).
Unit <eth_transmitcontrol> synthesized.

Synthesizing Unit <eth_txethmac>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_txethmac.v".
        Tp = 1
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_txethmac.v" line 480: Output port <CrcError> of the instance <txcrc> is unconnected or connected to loadless signal.
    Found 1-bit register for signal <ColWindow>.
    Found 1-bit register for signal <StatusLatch>.
    Found 1-bit register for signal <TxUsedData>.
    Found 1-bit register for signal <TxDone>.
    Found 1-bit register for signal <TxRetry>.
    Found 1-bit register for signal <TxAbort>.
    Found 1-bit register for signal <MTxEn>.
    Found 1-bit register for signal <MTxErr>.
    Found 1-bit register for signal <WillTransmit>.
    Found 1-bit register for signal <PacketFinished>.
    Found 1-bit register for signal <PacketFinished_q>.
    Found 1-bit register for signal <StopExcessiveDeferOccured>.
    Found 4-bit register for signal <RetryCnt>.
    Found 4-bit register for signal <MTxD>.
    Found 4-bit adder for signal <RetryCnt[3]_GND_167_o_add_3_OUT> created at line 344.
    Found 6-bit comparator equal for signal <ByteCnt[5]_CollValid[5]_equal_2_o> created at line 249
    Found 4-bit comparator equal for signal <RetryMax> created at line 349
    Summary:
	inferred   1 Adder/Subtractor(s).
	inferred  20 D-type flip-flop(s).
	inferred   2 Comparator(s).
	inferred   8 Multiplexer(s).
Unit <eth_txethmac> synthesized.

Synthesizing Unit <eth_txcounters>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_txcounters.v".
        Tp = 1
    Found 16-bit register for signal <ByteCnt>.
    Found 16-bit register for signal <NibCnt>.
    Found 3-bit register for signal <DlyCrcCnt>.
    Found 17-bit subtractor for signal <GND_168_o_GND_168_o_sub_8_OUT> created at line 170.
    Found 32-bit subtractor for signal <GND_168_o_GND_168_o_sub_9_OUT> created at line 170.
    Found 16-bit adder for signal <NibCnt[15]_GND_168_o_add_1_OUT> created at line 162.
    Found 16-bit adder for signal <ByteCnt[15]_GND_168_o_add_13_OUT> created at line 194.
    Found 3-bit adder for signal <DlyCrcCnt[2]_GND_168_o_add_21_OUT> created at line 215.
    Found 32-bit comparator lessequal for signal <n0031> created at line 170
    Found 16-bit comparator equal for signal <ByteCnt[15]_MaxFL[15]_equal_18_o> created at line 199
    Summary:
	inferred   5 Adder/Subtractor(s).
	inferred  35 D-type flip-flop(s).
	inferred   2 Comparator(s).
	inferred   3 Multiplexer(s).
Unit <eth_txcounters> synthesized.

Synthesizing Unit <eth_txstatem>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_txstatem.v".
        Tp = 1
    Found 1-bit register for signal <StateDefer>.
    Found 1-bit register for signal <StateIdle>.
    Found 1-bit register for signal <StatePreamble>.
    Found 1-bit register for signal <StatePAD>.
    Found 1-bit register for signal <StateFCS>.
    Found 1-bit register for signal <StateJam>.
    Found 1-bit register for signal <StateJam_q>.
    Found 1-bit register for signal <StateBackOff>.
    Found 1-bit register for signal <Rule1>.
    Found 1-bit register for signal <StateIPG>.
    Found 2-bit register for signal <StateData>.
    Found 7-bit comparator lessequal for signal <n0003> created at line 170
    Found 7-bit comparator lessequal for signal <n0007> created at line 170
    Found 7-bit comparator lessequal for signal <n0056> created at line 187
    Found 7-bit comparator not equal for signal <n0059> created at line 187
    Summary:
	inferred  12 D-type flip-flop(s).
	inferred   4 Comparator(s).
Unit <eth_txstatem> synthesized.

Synthesizing Unit <eth_crc>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_crc.v".
        Tp = 1
    Found 32-bit register for signal <Crc>.
    Summary:
	inferred  32 D-type flip-flop(s).
	inferred   1 Multiplexer(s).
Unit <eth_crc> synthesized.

Synthesizing Unit <eth_random>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_random.v".
        Tp = 1
WARNING:Xst:647 - Input <NibCnt<15:7>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 10-bit register for signal <RandomLatched>.
    Found 10-bit register for signal <x>.
    Found 4-bit comparator greater for signal <GND_173_o_RetryCnt[3]_LessThan_2_o> created at line 114
    Found 4-bit comparator greater for signal <GND_173_o_RetryCnt[3]_LessThan_3_o> created at line 115
    Found 4-bit comparator greater for signal <GND_173_o_RetryCnt[3]_LessThan_4_o> created at line 116
    Found 4-bit comparator greater for signal <GND_173_o_RetryCnt[3]_LessThan_5_o> created at line 117
    Found 4-bit comparator greater for signal <GND_173_o_RetryCnt[3]_LessThan_6_o> created at line 118
    Found 4-bit comparator greater for signal <GND_173_o_RetryCnt[3]_LessThan_7_o> created at line 119
    Found 4-bit comparator greater for signal <GND_173_o_RetryCnt[3]_LessThan_8_o> created at line 120
    Found 4-bit comparator greater for signal <PWR_99_o_RetryCnt[3]_LessThan_9_o> created at line 121
    Found 4-bit comparator greater for signal <PWR_99_o_RetryCnt[3]_LessThan_10_o> created at line 122
    Found 10-bit comparator equal for signal <ByteCnt[9]_RandomLatched[9]_equal_14_o> created at line 139
    Summary:
	inferred  20 D-type flip-flop(s).
	inferred  10 Comparator(s).
	inferred   9 Multiplexer(s).
Unit <eth_random> synthesized.

Synthesizing Unit <eth_rxethmac>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_rxethmac.v".
    Found 1-bit register for signal <DelayData>.
    Found 1-bit register for signal <Broadcast>.
    Found 1-bit register for signal <Multicast>.
    Found 1-bit register for signal <RxValid_d>.
    Found 1-bit register for signal <RxValid>.
    Found 1-bit register for signal <RxStartFrm_d>.
    Found 1-bit register for signal <RxStartFrm>.
    Found 1-bit register for signal <RxEndFrm_d>.
    Found 1-bit register for signal <RxEndFrm>.
    Found 8-bit register for signal <RxData_d>.
    Found 8-bit register for signal <LatchedByte>.
    Found 8-bit register for signal <RxData>.
    Found 6-bit register for signal <CrcHash>.
    Found 1-bit register for signal <CrcHashGood>.
    Found 4-bit comparator greater for signal <DlyCrcCnt[3]_PWR_100_o_LessThan_5_o> created at line 213
    Found 4-bit comparator lessequal for signal <n0046> created at line 314
    Summary:
	inferred  40 D-type flip-flop(s).
	inferred   2 Comparator(s).
	inferred   2 Multiplexer(s).
Unit <eth_rxethmac> synthesized.

Synthesizing Unit <eth_rxstatem>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_rxstatem.v".
        Tp = 1
WARNING:Xst:647 - Input <ByteCntEq0> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ByteCntGreat2> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 1-bit register for signal <StateDrop>.
    Found 1-bit register for signal <StatePreamble>.
    Found 1-bit register for signal <StateSFD>.
    Found 1-bit register for signal <StateData0>.
    Found 1-bit register for signal <StateData1>.
    Found 1-bit register for signal <StateIdle>.
    Summary:
	inferred   6 D-type flip-flop(s).
Unit <eth_rxstatem> synthesized.

Synthesizing Unit <eth_rxcounters>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_rxcounters.v".
    Found 5-bit register for signal <IFGCounter>.
    Found 4-bit register for signal <DlyCrcCnt>.
    Found 16-bit register for signal <ByteCnt>.
    Found 16-bit adder for signal <ByteCnt[15]_GND_178_o_add_1_OUT> created at line 116.
    Found 16-bit adder for signal <ByteCntDelayed> created at line 120.
    Found 5-bit adder for signal <IFGCounter[4]_GND_178_o_add_19_OUT> created at line 151.
    Found 4-bit adder for signal <DlyCrcCnt[3]_GND_178_o_add_26_OUT> created at line 173.
    Found 16-bit comparator greater for signal <ByteCntGreat2> created at line 131
    Found 16-bit comparator greater for signal <ByteCntSmall7> created at line 132
    Found 16-bit comparator equal for signal <ByteCnt[15]_MaxFL[15]_equal_19_o> created at line 134
    Summary:
	inferred   4 Adder/Subtractor(s).
	inferred  25 D-type flip-flop(s).
	inferred   3 Comparator(s).
	inferred   5 Multiplexer(s).
Unit <eth_rxcounters> synthesized.

Synthesizing Unit <eth_rxaddrcheck>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_rxaddrcheck.v".
        Tp = 1
    Found 1-bit register for signal <AddressMiss>.
    Found 1-bit register for signal <MulticastOK>.
    Found 1-bit register for signal <UnicastOK>.
    Found 1-bit register for signal <RxAbort>.
    Found 1-bit 8-to-1 multiplexer for signal <HashBit> created at line 204.
    Found 1-bit 4-to-1 multiplexer for signal <ByteHash<7>> created at line 204.
    Found 1-bit 4-to-1 multiplexer for signal <ByteHash<6>> created at line 204.
    Found 1-bit 4-to-1 multiplexer for signal <ByteHash<5>> created at line 204.
    Found 1-bit 4-to-1 multiplexer for signal <ByteHash<4>> created at line 204.
    Found 1-bit 4-to-1 multiplexer for signal <ByteHash<3>> created at line 204.
    Found 1-bit 4-to-1 multiplexer for signal <ByteHash<2>> created at line 204.
    Found 1-bit 4-to-1 multiplexer for signal <ByteHash<1>> created at line 204.
    Found 1-bit 4-to-1 multiplexer for signal <ByteHash<0>> created at line 204.
    Found 8-bit comparator equal for signal <RxData[7]_MAC[47]_equal_2_o> created at line 171
    Found 8-bit comparator equal for signal <RxData[7]_MAC[39]_equal_3_o> created at line 174
    Found 8-bit comparator equal for signal <RxData[7]_MAC[31]_equal_4_o> created at line 177
    Found 8-bit comparator equal for signal <RxData[7]_MAC[23]_equal_5_o> created at line 180
    Found 8-bit comparator equal for signal <RxData[7]_MAC[15]_equal_6_o> created at line 183
    Found 8-bit comparator equal for signal <RxData[7]_MAC[7]_equal_7_o> created at line 186
    Summary:
	inferred   4 D-type flip-flop(s).
	inferred   6 Comparator(s).
	inferred  48 Multiplexer(s).
Unit <eth_rxaddrcheck> synthesized.

Synthesizing Unit <eth_wishbone>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_wishbone.v".
WARNING:Xst:3149 - Value "0" of property "syn_allow_retiming" is not applicable.
WARNING:Xst:3149 - Value "0" of property "syn_allow_retiming" is not applicable.
WARNING:Xst:3149 - Value "0" of property "syn_allow_retiming" is not applicable.
WARNING:Xst:3149 - Value "0" of property "syn_allow_retiming" is not applicable.
WARNING:Xst:3149 - Value "0" of property "syn_allow_retiming" is not applicable.
WARNING:Xst:3149 - Value "0" of property "syn_allow_retiming" is not applicable.
WARNING:Xst:3149 - Value "0" of property "syn_allow_retiming" is not applicable.
WARNING:Xst:3149 - Value "0" of property "syn_allow_retiming" is not applicable.
WARNING:Xst:3149 - Value "0" of property "syn_allow_retiming" is not applicable.
WARNING:Xst:3149 - Value "0" of property "syn_allow_retiming" is not applicable.
WARNING:Xst:647 - Input <r_TxBDNum<7:7>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_wishbone.v" line 2355: Output port <almost_full> of the instance <rx_fifo0> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_wishbone.v" line 2355: Output port <almost_empty> of the instance <rx_fifo0> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_wishbone.v" line 2377: Output port <almost_full> of the instance <rx_fifo1> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_wishbone.v" line 2377: Output port <almost_empty> of the instance <rx_fifo1> is unconnected or connected to loadless signal.
    Found 1-bit register for signal <TxBDRead>.
    Found 1-bit register for signal <tx_burst_en>.
    Found 1-bit register for signal <WbEn>.
    Found 1-bit register for signal <TxEn_needed>.
    Found 1-bit register for signal <RxEn>.
    Found 1-bit register for signal <TxEn>.
    Found 1-bit register for signal <BDRead>.
    Found 1-bit register for signal <WbEn_q>.
    Found 1-bit register for signal <RxEn_q>.
    Found 1-bit register for signal <TxEn_q>.
    Found 1-bit register for signal <r_TxEn_q>.
    Found 1-bit register for signal <r_RxEn_q>.
    Found 1-bit register for signal <Flop>.
    Found 1-bit register for signal <TxBDReady>.
    Found 1-bit register for signal <TxPointerRead>.
    Found 1-bit register for signal <BlockingTxStatusWrite>.
    Found 1-bit register for signal <BlockingTxStatusWrite_sync1>.
    Found 1-bit register for signal <BlockingTxStatusWrite_sync2>.
    Found 1-bit register for signal <BlockingTxStatusWrite_sync3>.
    Found 1-bit register for signal <BlockingTxBDRead>.
    Found 1-bit register for signal <WriteRxDataToMemory_r>.
    Found 1-bit register for signal <BlockingIncrementTxPointer>.
    Found 1-bit register for signal <ReadTxDataFromMemory>.
    Found 1-bit register for signal <BlockReadTxDataFromMemory>.
    Found 1-bit register for signal <MasterWbTX>.
    Found 1-bit register for signal <MasterWbRX>.
    Found 1-bit register for signal <m_wb_cyc_o>.
    Found 1-bit register for signal <m_wb_we_o>.
    Found 1-bit register for signal <cyc_cleared>.
    Found 1-bit register for signal <IncrTxPointer>.
    Found 1-bit register for signal <rx_burst_en>.
    Found 1-bit register for signal <TxStartFrm_wb>.
    Found 1-bit register for signal <StartOccured>.
    Found 1-bit register for signal <TxStartFrm_sync1>.
    Found 1-bit register for signal <TxStartFrm_sync2>.
    Found 1-bit register for signal <TxStartFrm_syncb1>.
    Found 1-bit register for signal <TxStartFrm_syncb2>.
    Found 1-bit register for signal <TxStartFrm>.
    Found 1-bit register for signal <TxEndFrm_wb>.
    Found 1-bit register for signal <LatchValidBytes>.
    Found 1-bit register for signal <LatchValidBytes_q>.
    Found 1-bit register for signal <TxAbort_q>.
    Found 1-bit register for signal <TxRetry_q>.
    Found 1-bit register for signal <TxUsedData_q>.
    Found 1-bit register for signal <TxDone_wb_q>.
    Found 1-bit register for signal <TxAbort_wb_q>.
    Found 1-bit register for signal <TxRetry_wb_q>.
    Found 1-bit register for signal <TxAbortPacket>.
    Found 1-bit register for signal <TxAbortPacket_NotCleared>.
    Found 1-bit register for signal <TxAbortPacketBlocked>.
    Found 1-bit register for signal <TxRetryPacket>.
    Found 1-bit register for signal <TxRetryPacket_NotCleared>.
    Found 1-bit register for signal <TxRetryPacketBlocked>.
    Found 1-bit register for signal <TxDonePacket>.
    Found 1-bit register for signal <TxDonePacket_NotCleared>.
    Found 1-bit register for signal <TxDonePacketBlocked>.
    Found 1-bit register for signal <LastWord>.
    Found 1-bit register for signal <TxEndFrm>.
    Found 1-bit register for signal <TxUnderRun_wb>.
    Found 1-bit register for signal <TxUnderRun_sync1>.
    Found 1-bit register for signal <TxUnderRun>.
    Found 1-bit register for signal <ReadTxDataFromFifo_tck>.
    Found 1-bit register for signal <ReadTxDataFromFifo_sync1>.
    Found 1-bit register for signal <ReadTxDataFromFifo_sync2>.
    Found 1-bit register for signal <ReadTxDataFromFifo_syncb1>.
    Found 1-bit register for signal <ReadTxDataFromFifo_syncb2>.
    Found 1-bit register for signal <ReadTxDataFromFifo_syncb3>.
    Found 1-bit register for signal <ReadTxDataFromFifo_sync3>.
    Found 1-bit register for signal <TxRetrySync1>.
    Found 1-bit register for signal <TxRetry_wb>.
    Found 1-bit register for signal <TxDoneSync1>.
    Found 1-bit register for signal <TxDone_wb>.
    Found 1-bit register for signal <TxAbortSync1>.
    Found 1-bit register for signal <TxAbort_wb>.
    Found 1-bit register for signal <RxBDRead>.
    Found 1-bit register for signal <RxBDReady>.
    Found 1-bit register for signal <rx_just_read_bd>.
    Found 1-bit register for signal <rx_waiting_for_bd_to_become_free>.
    Found 1-bit register for signal <RxBDOK>.
    Found 1-bit register for signal <RxPointerRead>.
    Found 1-bit register for signal <RxEn_needed>.
    Found 1-bit register for signal <LastByteIn>.
    Found 1-bit register for signal <ShiftWillEnd>.
    Found 1-bit register for signal <WriteRxDataToFifo>.
    Found 1-bit register for signal <WriteRxDataToFifoSync1>.
    Found 1-bit register for signal <WriteRxDataToFifoSync2>.
    Found 1-bit register for signal <WriteRxDataToFifoSync3>.
    Found 1-bit register for signal <rx_ethside_fifo_sel>.
    Found 1-bit register for signal <rx_wbside_fifo_sel>.
    Found 1-bit register for signal <LatchedRxStartFrm>.
    Found 1-bit register for signal <SyncRxStartFrm>.
    Found 1-bit register for signal <SyncRxStartFrm_q>.
    Found 1-bit register for signal <SyncRxStartFrm_q2>.
    Found 1-bit register for signal <ShiftEnded_rck>.
    Found 1-bit register for signal <ShiftEndedSync1>.
    Found 1-bit register for signal <ShiftEndedSync2>.
    Found 1-bit register for signal <rx_wb_last_writes>.
    Found 1-bit register for signal <rx_wb_writeback_finished>.
    Found 1-bit register for signal <ShiftEndedSync_c1>.
    Found 1-bit register for signal <ShiftEndedSync_c2>.
    Found 1-bit register for signal <RxEnableWindow>.
    Found 1-bit register for signal <RxAbortSync1>.
    Found 1-bit register for signal <RxAbortSync2>.
    Found 1-bit register for signal <RxAbortSync3>.
    Found 1-bit register for signal <RxAbortSync4>.
    Found 1-bit register for signal <RxAbortSyncb1>.
    Found 1-bit register for signal <RxAbortSyncb2>.
    Found 1-bit register for signal <RxAbortLatched>.
    Found 1-bit register for signal <RxOverrun>.
    Found 1-bit register for signal <RxStatusWriteLatched>.
    Found 1-bit register for signal <RxStatusWriteLatched_sync1>.
    Found 1-bit register for signal <RxStatusWriteLatched_sync2>.
    Found 1-bit register for signal <RxStatusWriteLatched_syncb1>.
    Found 1-bit register for signal <RxStatusWriteLatched_syncb2>.
    Found 1-bit register for signal <TxB_IRQ>.
    Found 1-bit register for signal <TxE_IRQ>.
    Found 1-bit register for signal <RxB_IRQ>.
    Found 1-bit register for signal <RxE_IRQ>.
    Found 1-bit register for signal <busy_wb>.
    Found 8-bit register for signal <ram_addr>.
    Found 8-bit register for signal <TxData>.
    Found 32-bit register for signal <ram_di>.
    Found 32-bit register for signal <TxDataLatched>.
    Found 32-bit register for signal <RxDataLatched2>.
    Found 4-bit register for signal <BDWrite>.
    Found 4-bit register for signal <TxStatus>.
    Found 4-bit register for signal <m_wb_sel_o>.
    Found 16-bit register for signal <TxLength>.
    Found 16-bit register for signal <LatchedTxLength>.
    Found 16-bit register for signal <LatchedRxLength>.
    Found 30-bit register for signal <TxPointerMSB>.
    Found 30-bit register for signal <m_wb_adr_o>.
    Found 30-bit register for signal <RxPointerMSB>.
    Found 2-bit register for signal <TxPointerLSB>.
    Found 2-bit register for signal <TxPointerLSB_rst>.
    Found 2-bit register for signal <m_wb_bte_o>.
    Found 2-bit register for signal <TxValidBytesLatched>.
    Found 2-bit register for signal <TxByteCnt>.
    Found 2-bit register for signal <RxStatus>.
    Found 2-bit register for signal <RxPointerLSB_rst>.
    Found 2-bit register for signal <RxByteCnt>.
    Found 3-bit register for signal <tx_burst_cnt>.
    Found 3-bit register for signal <rx_burst_cnt>.
    Found 3-bit register for signal <m_wb_cti_o>.
    Found 7-bit register for signal <TxBDAddress>.
    Found 7-bit register for signal <RxBDAddress>.
    Found 2-bit register for signal <RxValidBytes>.
    Found 24-bit register for signal <RxDataLatched1>.
    Found 9-bit register for signal <RxStatusInLatched>.
    Found 4-bit register for signal <rx_shift_ended_wb_shr>.
    Found 1-bit register for signal <rxstartfrm_occurred>.
    Found 1-bit register for signal <WB_ACK_O>.
    Found 16-bit subtractor for signal <TxLength[15]_GND_180_o_sub_47_OUT> created at line 773.
    Found 16-bit subtractor for signal <TxLength[15]_GND_180_o_sub_49_OUT> created at line 777.
    Found 16-bit subtractor for signal <TxLength[15]_GND_180_o_sub_51_OUT> created at line 781.
    Found 16-bit subtractor for signal <TxLength[15]_GND_180_o_sub_53_OUT> created at line 785.
    Found 30-bit adder for signal <TxPointerMSB[31]_GND_180_o_add_65_OUT> created at line 821.
    Found 3-bit adder for signal <tx_burst_cnt[2]_GND_180_o_add_76_OUT> created at line 960.
    Found 30-bit adder for signal <m_wb_adr_o[29]_GND_180_o_add_78_OUT> created at line 964.
    Found 3-bit adder for signal <rx_burst_cnt[2]_GND_180_o_add_83_OUT> created at line 996.
    Found 8-bit adder for signal <n1113[7:0]> created at line 1395.
    Found 8-bit adder for signal <n1115[7:0]> created at line 1398.
    Found 2-bit adder for signal <TxByteCnt[1]_GND_180_o_add_214_OUT> created at line 1745.
    Found 30-bit adder for signal <RxPointerMSB[31]_GND_180_o_add_223_OUT> created at line 2001.
    Found 2-bit adder for signal <RxByteCnt[1]_GND_180_o_add_235_OUT> created at line 2098.
    Found 2-bit adder for signal <RxValidBytes[1]_GND_180_o_add_241_OUT> created at line 2117.
    Found 4x2-bit Read Only RAM for signal <TxPointerLSB[1]_GND_180_o_wide_mux_213_OUT>
    Found 4x6-bit Read Only RAM for signal <_n1569>
    Found 1-bit 4-to-1 multiplexer for signal <TxValidBytesLatched[1]_TxByteCnt[1]_Mux_201_o> created at line 1630.
    Found 8-bit 4-to-1 multiplexer for signal <TxPointerLSB[1]_TxData_wb[7]_wide_mux_202_OUT> created at line 1648.
    Found 8-bit 4-to-1 multiplexer for signal <TxByteCnt[1]_TxDataLatched[7]_wide_mux_204_OUT> created at line 1660.
    Found 16-bit 4-to-1 multiplexer for signal <TxLength[15]_TxLength[15]_mux_56_OUT> created at line 776.
    Found 16-bit comparator greater for signal <GND_180_o_ram_do[31]_LessThan_43_o> created at line 627
    Found 16-bit comparator greater for signal <TxLengthLt4> created at line 803
    Found 16-bit comparator lessequal for signal <n0175> created at line 898
    Found 8-bit comparator greater for signal <txfifo_cnt[7]_PWR_104_o_LessThan_96_o> created at line 1062
    Found 16-bit comparator greater for signal <GND_180_o_TxLength[15]_LessThan_97_o> created at line 1062
    Found 8-bit comparator lessequal for signal <n0705> created at line 2417
    Found 1-bit comparator equal for signal <rx_wbside_fifo_sel_rx_ethside_fifo_sel_equal_288_o> created at line 2422
    Found 8-bit comparator greater for signal <GND_180_o_rxfifo_cnt[7]_LessThan_289_o> created at line 2423
    Summary:
	inferred   2 RAM(s).
	inferred  11 Adder/Subtractor(s).
	inferred 461 D-type flip-flop(s).
	inferred   8 Comparator(s).
	inferred 104 Multiplexer(s).
Unit <eth_wishbone> synthesized.

Synthesizing Unit <eth_spram_256x32>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_spram_256x32.v".
        we_width = 1
    Found 256x32-bit dual-port RAM <Mram_mem> for signal <mem>.
    Found 8-bit register for signal <raddr>.
    Summary:
	inferred   1 RAM(s).
	inferred   8 D-type flip-flop(s).
	inferred   1 Multiplexer(s).
Unit <eth_spram_256x32> synthesized.

Synthesizing Unit <eth_fifo>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_fifo.v".
        DATA_WIDTH = 32
        DEPTH = 256
        CNT_WIDTH = 8
    Set property "syn_ramstyle = no_rw_check" for signal <fifo>.
    Found 256x32-bit dual-port RAM <Mram_fifo> for signal <fifo>.
    Found 8-bit register for signal <cnt>.
    Found 1-bit register for signal <fallthrough_read>.
    Found 8-bit register for signal <fallthrough_read_addr>.
    Found 8-bit register for signal <waddr>.
    Found 8-bit register for signal <raddr>.
    Found 1-bit register for signal <clear_reg>.
    Found 8-bit register for signal <raddr_reg>.
    Found 8-bit adder for signal <cnt[7]_GND_182_o_add_1_OUT> created at line 83.
    Found 8-bit adder for signal <waddr[7]_GND_182_o_add_11_OUT> created at line 114.
    Found 8-bit adder for signal <raddr[7]_GND_182_o_add_16_OUT> created at line 122.
    Found 8-bit subtractor for signal <GND_182_o_GND_182_o_sub_1_OUT<7:0>> created at line 81.
    Summary:
	inferred   1 RAM(s).
	inferred   3 Adder/Subtractor(s).
	inferred  42 D-type flip-flop(s).
	inferred   3 Multiplexer(s).
Unit <eth_fifo> synthesized.

Synthesizing Unit <eth_macstatus>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/ethmac/eth_macstatus.v".
        Tp = 1
WARNING:Xst:647 - Input <RxByteCntGreat2> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <TxUsedData> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 1-bit register for signal <RxColWindow>.
    Found 1-bit register for signal <LatchedMRxErr>.
    Found 1-bit register for signal <LoadRxStatus>.
    Found 1-bit register for signal <ReceiveEnd>.
    Found 1-bit register for signal <InvalidSymbol>.
    Found 1-bit register for signal <RxLateCollision>.
    Found 1-bit register for signal <ShortFrame>.
    Found 1-bit register for signal <DribbleNibble>.
    Found 1-bit register for signal <ReceivedPacketTooBig>.
    Found 1-bit register for signal <RetryLimit>.
    Found 1-bit register for signal <LateCollLatched>.
    Found 1-bit register for signal <DeferLatched>.
    Found 1-bit register for signal <CarrierSenseLost>.
    Found 1-bit register for signal <LatchedCrcError>.
    Found 4-bit register for signal <RetryCntLatched>.
    Found 16-bit comparator greater for signal <n0013> created at line 236
    Found 16-bit comparator greater for signal <n0015> created at line 236
    Found 6-bit comparator equal for signal <RxByteCnt[5]_CollValid[5]_equal_6_o> created at line 310
    Summary:
	inferred  18 D-type flip-flop(s).
	inferred   3 Comparator(s).
	inferred   3 Multiplexer(s).
Unit <eth_macstatus> synthesized.

Synthesizing Unit <xwb_ethmac_adapter>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac_adapter/xwb_ethmac_adapter.vhd".
WARNING:Xst:647 - Input <wb_slave_i_sel<3:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <tx_ram_i_dat<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <tx_ram_i_err> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <tx_ram_i_rty> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <tx_ram_i_int> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <rx_ram_i_err> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <rx_ram_i_rty> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <rx_ram_i_int> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac_adapter/xwb_ethmac_adapter.vhd" line 237: Output port <A_DAT_o> of the instance <cmp_tx_adapter_16_to_32> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac_adapter/xwb_ethmac_adapter.vhd" line 237: Output port <B_ADR_o> of the instance <cmp_tx_adapter_16_to_32> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac_adapter/xwb_ethmac_adapter.vhd" line 237: Output port <B_SEL_o> of the instance <cmp_tx_adapter_16_to_32> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac_adapter/xwb_ethmac_adapter.vhd" line 237: Output port <B_WE_o> of the instance <cmp_tx_adapter_16_to_32> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac_adapter/xwb_ethmac_adapter.vhd" line 335: Output port <A_DAT_o> of the instance <cmp_rx_adapter_32_to_16> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac_adapter/xwb_ethmac_adapter.vhd" line 335: Output port <A_ACK_o> of the instance <cmp_rx_adapter_32_to_16> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac_adapter/xwb_ethmac_adapter.vhd" line 335: Output port <A_ERR_o> of the instance <cmp_rx_adapter_32_to_16> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_ethmac_adapter/xwb_ethmac_adapter.vhd" line 335: Output port <A_RTY_o> of the instance <cmp_rx_adapter_32_to_16> is unconnected or connected to loadless signal.
    Found 32-bit register for signal <base_adr_tx>.
    Found 32-bit register for signal <base_adr_rx>.
    Found 32-bit register for signal <length_rx>.
    Found 1-bit register for signal <wb_slave_o_ack>.
    Found 1-bit register for signal <wb_slave_o_err>.
    Found 1-bit register for signal <wb_slave_o_rty>.
    Found 1-bit register for signal <wb_slave_o_stall>.
    Found 1-bit register for signal <wb_slave_o_int>.
    Found 32-bit register for signal <wb_slave_o_dat>.
    Found 1-bit register for signal <tx_eb32_o_err>.
    Found 1-bit register for signal <tx_eb32_o_rty>.
    Found 1-bit register for signal <irq_tx_done>.
    Found 32-bit register for signal <tx_counter>.
    Found 3-bit register for signal <state_tx>.
    Found 3-bit register for signal <state_rx>.
    Found 1-bit register for signal <irq_rx_done>.
    Found 16-bit register for signal <rx_counter>.
    Found 1-bit register for signal <rx_ram_o_cyc>.
    Found 1-bit register for signal <rx_ram_o_we>.
    Found 32-bit register for signal <rx_ram_o_dat>.
    Found 1-bit register for signal <rx_eb32_o_cyc>.
    Found 32-bit register for signal <rx_eb32_o_adr>.
    Found 1-bit register for signal <eb_stall>.
    Found 1-bit register for signal <ctrl<0>>.
INFO:Xst:1799 - State waiting is never reached in FSM <state_tx>.
    Found finite state machine <FSM_3> for signal <state_tx>.
    -----------------------------------------------------------------------
    | States             | 5                                              |
    | Transitions        | 7                                              |
    | Inputs             | 3                                              |
    | Outputs            | 4                                              |
    | Clock              | clk_i (rising_edge)                            |
    | Reset              | rstn_i_INV_862_o (positive)                    |
    | Reset type         | synchronous                                    |
    | Reset State        | idle                                           |
    | Power Up State     | idle                                           |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
INFO:Xst:1799 - State waiting is never reached in FSM <state_rx>.
    Found finite state machine <FSM_4> for signal <state_rx>.
    -----------------------------------------------------------------------
    | States             | 5                                              |
    | Transitions        | 6                                              |
    | Inputs             | 2                                              |
    | Outputs            | 6                                              |
    | Clock              | clk_i (rising_edge)                            |
    | Reset              | rstn_i_INV_862_o (positive)                    |
    | Reset type         | synchronous                                    |
    | Reset State        | idle                                           |
    | Power Up State     | idle                                           |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 32-bit adder for signal <length_rx[31]_base_adr_tx[31]_add_38_OUT> created at line 299.
    Found 32-bit adder for signal <tx_counter[31]_GND_187_o_add_40_OUT> created at line 1241.
    Found 16-bit adder for signal <length_rx[15]_base_adr_rx[15]_add_53_OUT> created at line 320.
    Found 16-bit adder for signal <rx_counter[15]_GND_187_o_add_59_OUT> created at line 1241.
    Found 32-bit 7-to-1 multiplexer for signal <_n0442> created at line 206.
    Found 32-bit comparator greater for signal <tx_counter[31]_length_rx[31]_LessThan_40_o> created at line 299
    Found 16-bit comparator greater for signal <rx_counter[15]_length_rx[15]_LessThan_55_o> created at line 320
    Summary:
	inferred   4 Adder/Subtractor(s).
	inferred 254 D-type flip-flop(s).
	inferred   2 Comparator(s).
	inferred   7 Multiplexer(s).
	inferred   2 Finite State Machine(s).
Unit <xwb_ethmac_adapter> synthesized.

Synthesizing Unit <WB_bus_adapter_streaming_sg_1>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/WB_bus_adapter_streaming_sg.vhd".
        g_adr_width_A = 2
        g_adr_width_B = 32
        g_dat_width_A = 16
        g_dat_width_B = 32
        g_pipeline = 3
WARNING:Xst:647 - Input <A_ADR_i<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <A_SEL_i<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <B_DAT_i<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <B_ACK_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/WB_bus_adapter_streaming_sg.vhd" line 163: Output port <empty_o> of the instance <PIPELINED.A_LESSER_B.gather> is unconnected or connected to loadless signal.
WARNING:Xst:653 - Signal <B_ADR_o> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <B_SEL_o> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <sipo_clr> is used but never assigned. This sourceless signal will be automatically connected to value GND.
    Found 1-bit register for signal <ALLRDY_STROBED>.
    Found 1-bit register for signal <A_ACK_o>.
    Summary:
	inferred   2 D-type flip-flop(s).
Unit <WB_bus_adapter_streaming_sg_1> synthesized.

Synthesizing Unit <sipo_flag_1>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/sipo_flag.vhd".
        g_width_IN = 16
        g_width_OUT = 32
    Found 1-bit register for signal <full>.
    Found 1-bit register for signal <empty>.
    Found 2-bit register for signal <cnt>.
    Found 32-bit register for signal <sh_reg>.
    Found 2-bit adder for signal <cnt[1]_GND_190_o_add_1_OUT> created at line 1241.
    Summary:
	inferred   1 Adder/Subtractor(s).
	inferred  36 D-type flip-flop(s).
	inferred   1 Multiplexer(s).
Unit <sipo_flag_1> synthesized.

Synthesizing Unit <WB_bus_adapter_streaming_sg_2>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/WB_bus_adapter_streaming_sg.vhd".
        g_adr_width_A = 32
        g_adr_width_B = 2
        g_dat_width_A = 32
        g_dat_width_B = 16
        g_pipeline = 3
WARNING:Xst:647 - Input <A_ADR_i<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <A_SEL_i<3:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <B_DAT_i<15:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <B_ACK_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/WB_bus_adapter_streaming_sg.vhd" line 239: Output port <full_o> of the instance <PIPELINED.A_GREATER_B.scatter> is unconnected or connected to loadless signal.
WARNING:Xst:653 - Signal <B_ADR_o> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <B_SEL_o> is used but never assigned. This sourceless signal will be automatically connected to value GND.
    Found 1-bit register for signal <A_ACK_o>.
    Summary:
	inferred   1 D-type flip-flop(s).
Unit <WB_bus_adapter_streaming_sg_2> synthesized.

Synthesizing Unit <piso_flag_1>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/piso_flag.vhd".
        g_width_IN = 32
        g_width_OUT = 16
        g_protected = 1
    Found 9-bit register for signal <sh_cnt>.
    Found 32-bit register for signal <sh_reg>.
    Found 1-bit register for signal <full>.
    Found 9-bit subtractor for signal <GND_224_o_GND_224_o_sub_3_OUT<8:0>> created at line 1308.
    Summary:
	inferred   1 Adder/Subtractor(s).
	inferred  42 D-type flip-flop(s).
	inferred   2 Multiplexer(s).
Unit <piso_flag_1> synthesized.

Synthesizing Unit <eb_slave_core>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_core.vhd".
        g_sdb_address = "0000000000000000000000000000000000110000000000000000000000000000"
WARNING:Xst:647 - Input <master_i_rty> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <master_i_int> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_core.vhd" line 372: Output port <local_slave_o_rty> of the instance <cfg_space> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_core.vhd" line 372: Output port <local_slave_o_int> of the instance <cfg_space> is unconnected or connected to loadless signal.
WARNING:Xst:653 - Signal <cfg_slave_o_rty> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <cfg_slave_o_int> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <WB_master_i_rty> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <WB_master_i_int> is used but never assigned. This sourceless signal will be automatically connected to value GND.
    Summary:
	no macro.
Unit <eb_slave_core> synthesized.

Synthesizing Unit <EB_TX_CTRL>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_ctrl.vhd".
WARNING:Xst:647 - Input <my_vlan_i<15:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_ctrl.vhd" line 267: Output port <full_o> of the instance <shift_hdr_chk_sum> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_ctrl.vhd" line 267: Output port <almost_empty_o> of the instance <shift_hdr_chk_sum> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_ctrl.vhd" line 292: Output port <full_o> of the instance <Shift_out> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_ctrl.vhd" line 292: Output port <almost_empty_o> of the instance <Shift_out> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_ctrl.vhd" line 292: Output port <empty_o> of the instance <Shift_out> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_ctrl.vhd" line 309: Output port <A_DAT_o> of the instance <uut> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_ctrl.vhd" line 309: Output port <B_ADR_o> of the instance <uut> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_ctrl.vhd" line 309: Output port <B_SEL_o> of the instance <uut> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_ctrl.vhd" line 309: Output port <A_RTY_o> of the instance <uut> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_ctrl.vhd" line 309: Output port <B_WE_o> of the instance <uut> is unconnected or connected to loadless signal.
WARNING:Xst:653 - Signal <wb_slave_o_int> is used but never assigned. This sourceless signal will be automatically connected to value GND.
    Found 15-bit register for signal <s_timeout_cnt>.
    Found 48-bit register for signal <ETH_TX_DST>.
    Found 48-bit register for signal <ETH_TX_SRC>.
    Found 16-bit register for signal <ETH_TX_TYP>.
    Found 4-bit register for signal <IPV4_TX_VER>.
    Found 4-bit register for signal <IPV4_TX_IHL>.
    Found 8-bit register for signal <IPV4_TX_TOS>.
    Found 16-bit register for signal <IPV4_TX_TOL>.
    Found 16-bit register for signal <IPV4_TX_ID>.
    Found 3-bit register for signal <IPV4_TX_FLG>.
    Found 13-bit register for signal <IPV4_TX_FRO>.
    Found 8-bit register for signal <IPV4_TX_TTL>.
    Found 8-bit register for signal <IPV4_TX_PRO>.
    Found 16-bit register for signal <IPV4_TX_SUM>.
    Found 32-bit register for signal <IPV4_TX_SRC>.
    Found 32-bit register for signal <IPV4_TX_DST>.
    Found 16-bit register for signal <UDP_TX_SRC_PORT>.
    Found 16-bit register for signal <UDP_TX_DST_PORT>.
    Found 16-bit register for signal <UDP_TX_MLEN>.
    Found 16-bit register for signal <UDP_TX_SUM>.
    Found 2-bit register for signal <state_mux>.
    Found 1-bit register for signal <ld_hdr>.
    Found 1-bit register for signal <ld_p_chk_vals>.
    Found 1-bit register for signal <sh_chk_en>.
    Found 1-bit register for signal <calc_chk_en>.
    Found 16-bit register for signal <s_src_padding_o_dat>.
    Found 1-bit register for signal <s_src_padding_o_stb>.
    Found 1-bit register for signal <s_src_hdr_o_stb>.
    Found 160-bit register for signal <TX_HDR_slv>.
    Found 5-bit register for signal <s_ETH_end>.
    Found 1-bit register for signal <conv_reset>.
    Found 4-bit register for signal <state>.
    Found 11-bit register for signal <byte_count>.
    Found finite state machine <FSM_5> for signal <state>.
    -----------------------------------------------------------------------
    | States             | 12                                             |
    | Transitions        | 41                                             |
    | Inputs             | 13                                             |
    | Outputs            | 8                                              |
    | Clock              | clk_i (rising_edge)                            |
    | Reset              | _n0498 (positive)                              |
    | Reset type         | synchronous                                    |
    | Reset State        | idle                                           |
    | Power Up State     | idle                                           |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 11-bit adder for signal <byte_count[10]_GND_243_o_add_1_OUT> created at line 222.
    Found 6-bit adder for signal <n0466[5:0]> created at line 464.
    Found 7-bit adder for signal <n0468[6:0]> created at line 472.
    Found 16-bit adder for signal <IPV4_TX_TOL[15]_GND_243_o_add_66_OUT> created at line 1241.
    Found 15-bit subtractor for signal <GND_243_o_GND_243_o_sub_21_OUT<14:0>> created at line 1308.
    Found 16-bit 3-to-1 multiplexer for signal <s_src_o_dat> created at line 242.
    Found 1-bit 3-to-1 multiplexer for signal <s_src_o_stb> created at line 242.
    Found 11-bit comparator equal for signal <GND_243_o_byte_count[10]_equal_56_o> created at line 456
    Found 11-bit comparator equal for signal <GND_243_o_byte_count[10]_equal_60_o> created at line 464
    Found 11-bit comparator equal for signal <GND_243_o_byte_count[10]_equal_64_o> created at line 472
    Found 11-bit comparator greater for signal <byte_count[10]_GND_243_o_LessThan_66_o> created at line 482
    Found 16-bit comparator equal for signal <n0149> created at line 485
    Summary:
	inferred   5 Adder/Subtractor(s).
	inferred 499 D-type flip-flop(s).
	inferred   5 Comparator(s).
	inferred  86 Multiplexer(s).
	inferred   1 Finite State Machine(s).
Unit <EB_TX_CTRL> synthesized.

Synthesizing Unit <piso_flag_2>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/piso_flag.vhd".
        g_width_IN = 96
        g_width_OUT = 16
        g_protected = 1
    Found 9-bit register for signal <sh_cnt>.
    Found 96-bit register for signal <sh_reg>.
    Found 1-bit register for signal <full>.
    Found 9-bit subtractor for signal <GND_244_o_GND_244_o_sub_3_OUT<8:0>> created at line 1308.
    Summary:
	inferred   1 Adder/Subtractor(s).
	inferred 106 D-type flip-flop(s).
	inferred   2 Multiplexer(s).
Unit <piso_flag_2> synthesized.

Synthesizing Unit <EB_checksum>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_checksum.vhd".
    Found 28-bit register for signal <sum>.
    Found 3-bit register for signal <state>.
    Found 16-bit register for signal <data>.
    Found 16-bit register for signal <sum_o>.
    Found 1-bit register for signal <done_o>.
    Found finite state machine <FSM_6> for signal <state>.
    -----------------------------------------------------------------------
    | States             | 5                                              |
    | Transitions        | 7                                              |
    | Inputs             | 1                                              |
    | Outputs            | 4                                              |
    | Clock              | clk_i (rising_edge)                            |
    | Reset              | nRst_i_INV_878_o (positive)                    |
    | Reset type         | synchronous                                    |
    | Reset State        | idle                                           |
    | Power Up State     | idle                                           |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 28-bit adder for signal <sum[27]_GND_245_o_add_2_OUT> created at line 91.
    Found 28-bit adder for signal <GND_245_o_GND_245_o_add_5_OUT> created at line 102.
    Summary:
	inferred   1 Adder/Subtractor(s).
	inferred  61 D-type flip-flop(s).
	inferred   4 Multiplexer(s).
	inferred   1 Finite State Machine(s).
Unit <EB_checksum> synthesized.

Synthesizing Unit <piso_flag_3>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/piso_flag.vhd".
        g_width_IN = 160
        g_width_OUT = 16
        g_protected = 0
    Found 9-bit register for signal <sh_cnt>.
    Found 160-bit register for signal <sh_reg>.
    Found 1-bit register for signal <full>.
    Found 9-bit subtractor for signal <GND_246_o_GND_246_o_sub_3_OUT<8:0>> created at line 1308.
    Summary:
	inferred   1 Adder/Subtractor(s).
	inferred 170 D-type flip-flop(s).
	inferred   1 Multiplexer(s).
Unit <piso_flag_3> synthesized.

Synthesizing Unit <EB_RX_CTRL>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_rx_ctrl.vhd".
WARNING:Xst:647 - Input <my_mac_i<47:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <my_vlan_i<15:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <my_ip_i<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <wb_master_i_int> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_rx_ctrl.vhd" line 193: Output port <A_DAT_o> of the instance <uut> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_rx_ctrl.vhd" line 258: Output port <full_o> of the instance <Shift_in> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_rx_ctrl.vhd" line 258: Output port <empty_o> of the instance <Shift_in> is unconnected or connected to loadless signal.
WARNING:Xst:653 - Signal <snk_hdr_fsm_rty> is used but never assigned. This sourceless signal will be automatically connected to value GND.
    Found 1-bit register for signal <sipo_clr>.
    Found 11-bit register for signal <byte_count>.
    Found 1-bit register for signal <snk_hdr_fsm_ACK>.
    Found 16-bit register for signal <snk_buffer>.
    Found 15-bit register for signal <s_timeout_cnt>.
    Found 1-bit register for signal <parser_wait>.
    Found 1-bit register for signal <get_last_element>.
    Found 4-bit register for signal <parse>.
    Found 1-bit register for signal <valid_o>.
    Found 11-bit register for signal <counter_comp>.
    Found 48-bit register for signal <ETH_RX_SRC>.
    Found 16-bit register for signal <ETH_RX_TYP>.
    Found 4-bit register for signal <IPV4_RX_IHL>.
    Found 16-bit register for signal <IPV4_RX_TOL>.
    Found 8-bit register for signal <IPV4_RX_PRO>.
    Found 32-bit register for signal <IPV4_RX_SRC>.
    Found 16-bit register for signal <UDP_RX_SRC_PORT>.
    Found 16-bit register for signal <UDP_RX_DST_PORT>.
    Found 16-bit register for signal <UDP_RX_MLEN>.
    Found 3-bit register for signal <state>.
    Found 1-bit register for signal <snk_hdr_fsm_stall_0001>.
    Found 1-bit register for signal <parser_reset>.
    Found 11-bit register for signal <eop>.
    Found 1-bit register for signal <snk_buffer_empty>.
    Found finite state machine <FSM_8> for signal <state>.
    -----------------------------------------------------------------------
    | States             | 6                                              |
    | Transitions        | 29                                             |
    | Inputs             | 10                                             |
    | Outputs            | 5                                              |
    | Clock              | clk_i (rising_edge)                            |
    | Reset              | nRst_i_INV_938_o (positive)                    |
    | Reset type         | synchronous                                    |
    | Reset State        | idle                                           |
    | Power Up State     | idle                                           |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
INFO:Xst:1799 - State ipv4_chksum is never reached in FSM <parse>.
    Found finite state machine <FSM_7> for signal <parse>.
    -----------------------------------------------------------------------
    | States             | 15                                             |
    | Transitions        | 34                                             |
    | Inputs             | 13                                             |
    | Outputs            | 12                                             |
    | Clock              | clk_i (rising_edge)                            |
    | Reset              | nRst_i_parser_reset_OR_13374_o (positive)       |
    | Reset type         | synchronous                                    |
    | Reset State        | idle                                           |
    | Power Up State     | eth                                            |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 14-bit subtractor for signal <GND_279_o_GND_279_o_sub_65_OUT> created at line 426.
    Found 11-bit adder for signal <byte_count[10]_GND_279_o_add_13_OUT> created at line 291.
    Found 12-bit adder for signal <n0296> created at line 405.
    Found 12-bit adder for signal <n0298> created at line 426.
    Found 13-bit adder for signal <n0314[12:0]> created at line 426.
    Found 17-bit adder for signal <n0317> created at line 504.
    Found 15-bit subtractor for signal <GND_279_o_GND_279_o_sub_24_OUT<14:0>> created at line 1308.
    Found 11-bit subtractor for signal <GND_279_o_GND_279_o_sub_154_OUT<10:0>> created at line 504.
    Found 11-bit comparator equal for signal <counter_comp[10]_byte_count[10]_equal_29_o> created at line 347
    Found 12-bit comparator equal for signal <BUS_0003_GND_279_o_equal_45_o> created at line 405
    Found 12-bit comparator greater for signal <n0074> created at line 420
    Found 14-bit comparator equal for signal <GND_279_o_GND_279_o_equal_66_o> created at line 426
    Found 16-bit comparator equal for signal <my_port_i[15]_UDP_RX_DST_PORT[15]_equal_69_o> created at line 447
    Found 11-bit comparator greater for signal <byte_count[10]_GND_279_o_LessThan_162_o> created at line 520
    Found 11-bit comparator equal for signal <eop[10]_byte_count[10]_equal_166_o> created at line 529
    Summary:
	inferred   8 Adder/Subtractor(s).
	inferred 244 D-type flip-flop(s).
	inferred   7 Comparator(s).
	inferred  14 Multiplexer(s).
	inferred   2 Finite State Machine(s).
Unit <EB_RX_CTRL> synthesized.

Synthesizing Unit <sipo_flag_2>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/sipo_flag.vhd".
        g_width_IN = 16
        g_width_OUT = 160
    Found 1-bit register for signal <full>.
    Found 1-bit register for signal <empty>.
    Found 4-bit register for signal <cnt>.
    Found 160-bit register for signal <sh_reg>.
    Found 4-bit adder for signal <cnt[3]_GND_280_o_add_1_OUT> created at line 1241.
    Summary:
	inferred   1 Adder/Subtractor(s).
	inferred 166 D-type flip-flop(s).
	inferred   1 Multiplexer(s).
Unit <sipo_flag_2> synthesized.

Synthesizing Unit <eb_main_fsm>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_main_fsm.vhd".
WARNING:Xst:647 - Input <EB_RX_i_adr<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <EB_RX_i_sel<3:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <EB_TX_i_dat<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <EB_RX_i_we> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <EB_TX_i_ack> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <EB_TX_i_err> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <EB_TX_i_rty> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <EB_TX_i_int> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <config_master_i_rty> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <config_master_i_int> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <WB_master_i_rty> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <WB_master_i_int> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_main_fsm.vhd" line 265: Output port <count_o> of the instance <TX_FIFO> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_main_fsm.vhd" line 265: Output port <almost_empty_o> of the instance <TX_FIFO> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_main_fsm.vhd" line 315: Output port <full_o> of the instance <RX_FIFO> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_main_fsm.vhd" line 315: Output port <almost_empty_o> of the instance <RX_FIFO> is unconnected or connected to loadless signal.
WARNING:Xst:653 - Signal <EB_RX_o_dat> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <EB_RX_o_rty> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <EB_RX_o_int> is used but never assigned. This sourceless signal will be automatically connected to value GND.
    Found 9-bit register for signal <s_WB_wr_ack_cnt>.
    Found 9-bit register for signal <s_WB_rd_ack_cnt>.
    Found 15-bit register for signal <s_timeout_cnt>.
    Found 4-bit register for signal <s_EB_probe_wait_cnt>.
    Found 1-bit register for signal <s_EB_RX_byte_cnt_idle_rst>.
    Found 4-bit register for signal <s_state_TX>.
    Found 5-bit register for signal <s_state_RX>.
    Found 1-bit register for signal <rx_stall>.
    Found 16-bit register for signal <s_EB_TX_HDR_EB_MAGIC>.
    Found 4-bit register for signal <s_EB_TX_HDR_VER>.
    Found 1-bit register for signal <s_EB_TX_HDR_RESERVED1>.
    Found 1-bit register for signal <s_EB_TX_HDR_PROBE_RES>.
    Found 1-bit register for signal <s_EB_TX_HDR_PROBE>.
    Found 4-bit register for signal <s_EB_TX_HDR_ADDR_SIZE>.
    Found 4-bit register for signal <s_EB_TX_HDR_PORT_SIZE>.
    Found 32-bit register for signal <PROBE_ID>.
    Found 1-bit register for signal <s_EB_TX_CUR_CYCLE_BCA_CFG>.
    Found 1-bit register for signal <s_EB_TX_CUR_CYCLE_RCA_CFG>.
    Found 1-bit register for signal <s_EB_TX_CUR_CYCLE_RD_FIFO>.
    Found 1-bit register for signal <s_EB_TX_CUR_CYCLE_RESERVED1>.
    Found 1-bit register for signal <s_EB_TX_CUR_CYCLE_WCA_CFG>.
    Found 1-bit register for signal <s_EB_TX_CUR_CYCLE_WR_FIFO>.
    Found 1-bit register for signal <s_EB_TX_CUR_CYCLE_RESERVED2>.
    Found 4-bit register for signal <s_EB_TX_CUR_CYCLE_UNUSED>.
    Found 4-bit register for signal <s_EB_TX_CUR_CYCLE_SEL>.
    Found 8-bit register for signal <s_EB_TX_CUR_CYCLE_WR_CNT>.
    Found 8-bit register for signal <s_EB_TX_CUR_CYCLE_RD_CNT>.
    Found 1-bit register for signal <s_EB_RX_CUR_CYCLE_BCA_CFG>.
    Found 1-bit register for signal <s_EB_RX_CUR_CYCLE_RCA_CFG>.
    Found 1-bit register for signal <s_EB_RX_CUR_CYCLE_RD_FIFO>.
    Found 1-bit register for signal <s_EB_RX_CUR_CYCLE_DROP_CYC>.
    Found 1-bit register for signal <s_EB_RX_CUR_CYCLE_WCA_CFG>.
    Found 1-bit register for signal <s_EB_RX_CUR_CYCLE_WR_FIFO>.
    Found 4-bit register for signal <s_EB_RX_CUR_CYCLE_SEL>.
    Found 8-bit register for signal <s_EB_RX_CUR_CYCLE_WR_CNT>.
    Found 8-bit register for signal <s_EB_RX_CUR_CYCLE_RD_CNT>.
    Found 32-bit register for signal <s_EB_TX_base_wr_adr>.
    Found 1-bit register for signal <s_WB_CYC>.
    Found 1-bit register for signal <s_EB_RX_ACK>.
    Found 1-bit register for signal <EB_TX_o_cyc>.
    Found 32-bit register for signal <EB_TX_o_adr>.
    Found 1-bit register for signal <TX_silent_o>.
    Found 16-bit register for signal <s_EB_packet_length>.
    Found 1-bit register for signal <s_ADR_CONFIG>.
    Found 1-bit register for signal <s_WB_STB>.
    Found 1-bit register for signal <s_WB_WE>.
    Found 4-bit register for signal <s_WB_SEL>.
    Found 32-bit register for signal <s_WB_ADR>.
    Found 8-bit register for signal <s_EB_TX_zeropad_cnt>.
    Found 1-bit register for signal <s_fifo_rx_pop>.
    Found 1-bit register for signal <s_EB_TX_STB>.
    Found 16-bit register for signal <s_EB_RX_HDR_EB_MAGIC>.
    Found 4-bit register for signal <s_EB_RX_HDR_VER>.
    Found 1-bit register for signal <s_EB_RX_HDR_NO_RESPONSE>.
    Found 1-bit register for signal <s_EB_RX_HDR_PROBE>.
    Found 4-bit register for signal <s_EB_RX_HDR_ADDR_SIZE>.
    Found 4-bit register for signal <s_EB_RX_HDR_PORT_SIZE>.
    Found 32-bit register for signal <s_fifo_tx_data>.
    Found 16-bit register for signal <s_EB_RX_byte_cnt>.
INFO:Xst:1799 - State zero_pad_wait is never reached in FSM <s_state_TX>.
INFO:Xst:1799 - State error is never reached in FSM <s_state_TX>.
    Found finite state machine <FSM_9> for signal <s_state_TX>.
    -----------------------------------------------------------------------
    | States             | 14                                             |
    | Transitions        | 716                                            |
    | Inputs             | 23                                             |
    | Outputs            | 9                                              |
    | Clock              | clk_i (rising_edge)                            |
    | Reset              | nRst_i_INV_1025_o (positive)                   |
    | Reset type         | synchronous                                    |
    | Reset State        | idle                                           |
    | Power Up State     | idle                                           |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found finite state machine <FSM_10> for signal <s_state_RX>.
    -----------------------------------------------------------------------
    | States             | 19                                             |
    | Transitions        | 145                                            |
    | Inputs             | 19                                             |
    | Outputs            | 16                                             |
    | Clock              | clk_i (rising_edge)                            |
    | Reset              | nRst_i_INV_1025_o (positive)                   |
    | Reset type         | synchronous                                    |
    | Reset State        | idle                                           |
    | Power Up State     | idle                                           |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 16-bit adder for signal <s_EB_RX_byte_cnt[15]_GND_297_o_add_17_OUT> created at line 1241.
    Found 4-bit adder for signal <s_EB_probe_wait_cnt[3]_GND_297_o_add_43_OUT> created at line 1241.
    Found 8-bit adder for signal <s_EB_RX_CUR_CYCLE_WR_CNT[7]_GND_297_o_add_158_OUT> created at line 1241.
    Found 8-bit adder for signal <s_EB_RX_CUR_CYCLE_WR_CNT[7]_GND_297_o_add_159_OUT> created at line 1241.
    Found 32-bit adder for signal <s_WB_ADR[31]_GND_297_o_add_166_OUT> created at line 1241.
    Found 9-bit subtractor for signal <GND_297_o_GND_297_o_sub_30_OUT<8:0>> created at line 1308.
    Found 9-bit subtractor for signal <GND_297_o_GND_297_o_sub_34_OUT<8:0>> created at line 1308.
    Found 15-bit subtractor for signal <GND_297_o_GND_297_o_sub_48_OUT<14:0>> created at line 1308.
    Found 16-bit subtractor for signal <GND_297_o_GND_297_o_sub_155_OUT<15:0>> created at line 1308.
    Found 8-bit subtractor for signal <GND_297_o_GND_297_o_sub_172_OUT<7:0>> created at line 1308.
    Found 8-bit subtractor for signal <GND_297_o_GND_297_o_sub_185_OUT<7:0>> created at line 1308.
    Found 8-bit subtractor for signal <GND_297_o_GND_297_o_sub_225_OUT<7:0>> created at line 1308.
    Found 8-bit subtractor for signal <GND_297_o_GND_297_o_sub_228_OUT<7:0>> created at line 1308.
    Found 4-bit comparator greater for signal <s_fifo_rx_am_empty_INV_1030_o> created at line 363
    Found 16-bit comparator greater for signal <s_EB_RX_byte_cnt[15]_s_EB_packet_length[15]_LessThan_65_o> created at line 504
    Found 8-bit comparator greater for signal <GND_297_o_s_EB_RX_CUR_CYCLE_WR_CNT[7]_LessThan_94_o> created at line 584
    Found 8-bit comparator greater for signal <GND_297_o_s_EB_RX_CUR_CYCLE_RD_CNT[7]_LessThan_106_o> created at line 619
    Found 16-bit comparator equal for signal <s_EB_RX_byte_cnt[15]_s_EB_packet_length[15]_equal_123_o> created at line 659
    Found 4-bit comparator greater for signal <GND_297_o_s_EB_probe_wait_cnt[3]_LessThan_138_o> created at line 716
    Found 8-bit comparator greater for signal <GND_297_o_s_EB_TX_zeropad_cnt[7]_LessThan_227_o> created at line 986
    Summary:
	inferred  13 Adder/Subtractor(s).
	inferred 359 D-type flip-flop(s).
	inferred   7 Comparator(s).
	inferred  65 Multiplexer(s).
	inferred   2 Finite State Machine(s).
Unit <eb_main_fsm> synthesized.

Synthesizing Unit <generic_sync_fifo>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_sync_fifo.vhd".
        g_data_width = 32
        g_size = 16
        g_show_ahead = true
        g_with_empty = true
        g_with_full = true
        g_with_almost_empty = true
        g_with_almost_full = true
        g_with_count = true
        g_almost_empty_threshold = 1
        g_almost_full_threshold = 11
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_sync_fifo.vhd" line 213: Output port <RD_DATA_COUNT> of the instance <wrapped_gen> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_sync_fifo.vhd" line 213: Output port <WR_DATA_COUNT> of the instance <wrapped_gen> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_sync_fifo.vhd" line 213: Output port <ALMOST_FULL> of the instance <wrapped_gen> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_sync_fifo.vhd" line 213: Output port <WR_ACK> of the instance <wrapped_gen> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_sync_fifo.vhd" line 213: Output port <OVERFLOW> of the instance <wrapped_gen> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_sync_fifo.vhd" line 213: Output port <ALMOST_EMPTY> of the instance <wrapped_gen> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_sync_fifo.vhd" line 213: Output port <VALID> of the instance <wrapped_gen> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_sync_fifo.vhd" line 213: Output port <UNDERFLOW> of the instance <wrapped_gen> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_sync_fifo.vhd" line 213: Output port <SBITERR> of the instance <wrapped_gen> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_sync_fifo.vhd" line 213: Output port <DBITERR> of the instance <wrapped_gen> is unconnected or connected to loadless signal.
    Summary:
	no macro.
Unit <generic_sync_fifo> synthesized.

Synthesizing Unit <fifo_generator_v6_1_xst>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_v6_1_xst.vhd".
        C_COMMON_CLOCK = 1
        C_COUNT_TYPE = 0
        C_DATA_COUNT_WIDTH = 4
        C_DEFAULT_VALUE = "BlankString"
        C_DIN_WIDTH = 32
        C_DOUT_RST_VAL = "0"
        C_DOUT_WIDTH = 32
        C_ENABLE_RLOCS = 0
        C_FAMILY = "virtex6"
        C_FULL_FLAGS_RST_VAL = 1
        C_HAS_ALMOST_EMPTY = 0
        C_HAS_ALMOST_FULL = 0
        C_HAS_BACKUP = 0
        C_HAS_DATA_COUNT = 1
        C_HAS_INT_CLK = 0
        C_HAS_MEMINIT_FILE = 0
        C_HAS_OVERFLOW = 1
        C_HAS_RD_DATA_COUNT = 0
        C_HAS_RD_RST = 0
        C_HAS_RST = 1
        C_HAS_SRST = 0
        C_HAS_UNDERFLOW = 0
        C_HAS_VALID = 0
        C_HAS_WR_ACK = 0
        C_HAS_WR_DATA_COUNT = 0
        C_HAS_WR_RST = 0
        C_IMPLEMENTATION_TYPE = 0
        C_INIT_WR_PNTR_VAL = 0
        C_MEMORY_TYPE = 1
        C_MIF_FILE_NAME = "BlankString"
        C_OPTIMIZATION_MODE = 0
        C_OVERFLOW_LOW = 0
        C_PRELOAD_LATENCY = 1
        C_PRELOAD_REGS = 0
        C_PRIM_FIFO_TYPE = "1kx18"
        C_PROG_EMPTY_THRESH_ASSERT_VAL = 1
        C_PROG_EMPTY_THRESH_NEGATE_VAL = 2
        C_PROG_EMPTY_TYPE = 1
        C_PROG_FULL_THRESH_ASSERT_VAL = 11
        C_PROG_FULL_THRESH_NEGATE_VAL = 10
        C_PROG_FULL_TYPE = 1
        C_RD_DATA_COUNT_WIDTH = 4
        C_RD_DEPTH = 16
        C_RD_FREQ = 1
        C_RD_PNTR_WIDTH = 4
        C_UNDERFLOW_LOW = 0
        C_USE_DOUT_RST = 1
        C_USE_ECC = 0
        C_USE_EMBEDDED_REG = 0
        C_USE_FIFO16_FLAGS = 0
        C_USE_FWFT_DATA_COUNT = 0
        C_VALID_LOW = 0
        C_WR_ACK_LOW = 0
        C_WR_DATA_COUNT_WIDTH = 4
        C_WR_DEPTH = 16
        C_WR_FREQ = 1
        C_WR_PNTR_WIDTH = 4
        C_WR_RESPONSE_LATENCY = 1
        C_MSGON_VAL = 1
        C_ENABLE_RST_SYNC = 1
        C_ERROR_INJECTION_TYPE = 0
WARNING:Xst:647 - Input <BACKUP> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <BACKUP_MARKER> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <INT_CLK> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Summary:
	no macro.
Unit <fifo_generator_v6_1_xst> synthesized.

Synthesizing Unit <fifo_generator_ramfifo>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_ramfifo.vhd".
        C_FAMILY = "virtex6"
        C_COMMON_CLOCK = 1
        C_MEMORY_TYPE = 1
        C_PRELOAD_REGS = 0
        C_PRELOAD_LATENCY = 1
        C_HAS_RST = 1
        C_HAS_SRST = 0
        C_DIN_WIDTH = 32
        C_DOUT_WIDTH = 32
        C_DOUT_RST_VAL = "0"
        C_RD_DEPTH = 16
        C_RD_PNTR_WIDTH = 4
        C_WR_DEPTH = 16
        C_WR_PNTR_WIDTH = 4
        C_DEPTH_RATIO_WR = 1
        C_DEPTH_RATIO_RD = 1
        C_FULL_FLAGS_RST_VAL = 1
        C_USE_EMBEDDED_REG = 0
        C_MSGON_VAL = 1
        C_HAS_ALMOST_EMPTY = 0
        C_PROG_EMPTY_TYPE = 1
        C_PROG_EMPTY_THRESH_ASSERT_VAL = 1
        C_PROG_EMPTY_THRESH_NEGATE_VAL = 2
        C_HAS_ALMOST_FULL = 0
        C_PROG_FULL_TYPE = 1
        C_PROG_FULL_THRESH_ASSERT_VAL = 11
        C_PROG_FULL_THRESH_NEGATE_VAL = 10
        C_HAS_VALID = 0
        C_VALID_LOW = 0
        C_HAS_UNDERFLOW = 0
        C_UNDERFLOW_LOW = 0
        C_HAS_WR_ACK = 0
        C_WR_ACK_LOW = 0
        C_HAS_OVERFLOW = 1
        C_OVERFLOW_LOW = 0
        C_HAS_DATA_COUNT = 1
        C_DATA_COUNT_WIDTH = 4
        C_HAS_RD_DATA_COUNT = 0
        C_RD_DATA_COUNT_WIDTH = 4
        C_HAS_WR_DATA_COUNT = 0
        C_USE_FWFT_DATA_COUNT = 0
        C_WR_DATA_COUNT_WIDTH = 4
        C_USE_ECC = 0
        C_USE_DOUT_RST = 1
        C_ENABLE_RST_SYNC = 1
        C_ERROR_INJECTION_TYPE = 0
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_ramfifo.vhd" line 358: Output port <INT_CLK_I> of the instance <inblk> is unconnected or connected to loadless signal.
    Summary:
	no macro.
Unit <fifo_generator_ramfifo> synthesized.

Synthesizing Unit <reset_blk_ramfifo>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/reset_blk_ramfifo.vhd".
        C_HAS_RST = 1
        C_HAS_SRST = 0
        C_WR_RST_MAXFAN = 2
        C_RD_RST_MAXFAN = 3
        C_MSGON_VAL = 1
        C_ENABLE_RST_SYNC = 1
        C_FULL_FLAGS_RST_VAL = 1
    Set property "equivalent_register_removal = no" for signal <ngwrdrst.grst.wr_rst_reg>.
    Set property "equivalent_register_removal = no" for signal <ngwrdrst.grst.rd_rst_reg>.
    Set property "ASYNC_REG = TRUE" for signal <wr_rst_asreg>.
    Set property "MSGON = TRUE" for signal <wr_rst_asreg>.
    Set property "ASYNC_REG = TRUE" for signal <rd_rst_asreg>.
    Set property "MSGON = TRUE" for signal <rd_rst_asreg>.
    Set property "ASYNC_REG = TRUE" for signal <wr_rst_asreg_d1>.
    Set property "MSGON = TRUE" for signal <wr_rst_asreg_d1>.
    Set property "ASYNC_REG = TRUE" for signal <rd_rst_asreg_d1>.
    Set property "MSGON = TRUE" for signal <rd_rst_asreg_d1>.
    Set property "ASYNC_REG = TRUE" for signal <wr_rst_asreg_d2>.
    Set property "MSGON = TRUE" for signal <wr_rst_asreg_d2>.
    Set property "ASYNC_REG = TRUE" for signal <rd_rst_asreg_d2>.
    Set property "MSGON = TRUE" for signal <rd_rst_asreg_d2>.
    Set property "ASYNC_REG = TRUE" for signal <grstd1.grst_full.rst_d1>.
    Set property "MSGON = TRUE" for signal <grstd1.grst_full.rst_d1>.
    Set property "ASYNC_REG = TRUE" for signal <grstd1.grst_full.rst_d2>.
    Set property "MSGON = TRUE" for signal <grstd1.grst_full.rst_d2>.
    Set property "ASYNC_REG = TRUE" for signal <grstd1.grst_full.rst_d3>.
    Set property "MSGON = TRUE" for signal <grstd1.grst_full.rst_d3>.
WARNING:Xst:647 - Input <WR_RST> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <RD_RST> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <SRST> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 1-bit register for signal <RST_FULL_GEN>.
    Found 1-bit register for signal <rd_rst_asreg>.
    Found 1-bit register for signal <grstd1.grst_full.rst_d1>.
    Found 1-bit register for signal <grstd1.grst_full.rst_d2>.
    Found 1-bit register for signal <grstd1.grst_full.rst_d3>.
    Found 1-bit register for signal <wr_rst_asreg>.
    Found 1-bit register for signal <wr_rst_asreg_d1>.
    Found 1-bit register for signal <wr_rst_asreg_d2>.
    Found 2-bit register for signal <ngwrdrst.grst.wr_rst_reg>.
    Found 1-bit register for signal <rd_rst_asreg_d1>.
    Found 1-bit register for signal <rd_rst_asreg_d2>.
    Found 3-bit register for signal <ngwrdrst.grst.rd_rst_reg>.
    Summary:
	inferred  15 D-type flip-flop(s).
Unit <reset_blk_ramfifo> synthesized.

Synthesizing Unit <input_blk>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/input_blk.vhd".
        C_COMMON_CLOCK = 1
        C_IMPLEMENTATION_TYPE = 0
        C_DIN_WIDTH = 32
        C_DOUT_WIDTH = 32
        C_HAS_INT_CLK = 0
        C_PROG_EMPTY_TYPE = 1
        C_PROG_FULL_TYPE = 1
        C_DEPTH_RATIO_RD = 1
        C_RD_PNTR_WIDTH = 4
        C_WR_PNTR_WIDTH = 4
        C_USE_EMBEDDED_REG = 1
        C_ERROR_INJECTION_TYPE = 0
WARNING:Xst:647 - Input <PROG_EMPTY_THRESH<3:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <PROG_EMPTY_THRESH_ASSERT<3:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <PROG_EMPTY_THRESH_NEGATE<3:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <PROG_FULL_THRESH<3:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <PROG_FULL_THRESH_ASSERT<3:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <PROG_FULL_THRESH_NEGATE<3:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <RD_CLK> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <WR_CLK> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <INT_CLK> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <INJECTDBITERR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <INJECTSBITERR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Summary:
	no macro.
Unit <input_blk> synthesized.

Synthesizing Unit <memory>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/memory.vhd".
        C_FAMILY = "virtex6"
        C_COMMON_CLOCK = 1
        C_HAS_SRST = 0
        C_DIN_WIDTH = 32
        C_DOUT_WIDTH = 32
        C_USE_DOUT_RST = 1
        C_DOUT_RST_VAL = "0"
        C_MEMORY_TYPE = 1
        C_PRELOAD_LATENCY = 1
        C_PRELOAD_REGS = 0
        C_LARGER_DEPTH = 16
        C_RD_DEPTH = 16
        C_WR_DEPTH = 16
        C_SMALLER_DATA_WIDTH = 32
        C_RD_PNTR_WIDTH = 4
        C_WR_PNTR_WIDTH = 4
        C_DEPTH_RATIO_RD = 1
        C_DEPTH_RATIO_WR = 1
        C_USE_ECC = 0
        C_USE_EMBEDDED_REG = 0
        C_ERROR_INJECTION_TYPE = 0
WARNING:Xst:647 - Input <RAM_REGOUT_EN> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <SRST> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/memory.vhd" line 470: Output port <DOUTA> of the instance <gbm.gbmg.gbmga.ngecc.bmg> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/memory.vhd" line 470: Output port <RDADDRECC> of the instance <gbm.gbmg.gbmga.ngecc.bmg> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/memory.vhd" line 470: Output port <SBITERR> of the instance <gbm.gbmg.gbmga.ngecc.bmg> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/memory.vhd" line 470: Output port <DBITERR> of the instance <gbm.gbmg.gbmga.ngecc.bmg> is unconnected or connected to loadless signal.
    Summary:
	no macro.
Unit <memory> synthesized.

Synthesizing Unit <blk_mem_gen_v4_1_xst>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_v4_1_xst.vhd".
        C_FAMILY = "virtex6"
        C_XDEVICEFAMILY = "virtex6"
        C_ELABORATION_DIR = ""
        C_MEM_TYPE = 1
        C_BYTE_SIZE = 9
        C_ALGORITHM = 1
        C_PRIM_TYPE = 3
        C_LOAD_INIT_FILE = 0
        C_INIT_FILE_NAME = "no_coe_file_loaded"
        C_USE_DEFAULT_DATA = 0
        C_DEFAULT_DATA = "0"
        C_RST_TYPE = "SYNC"
        C_HAS_RSTA = 0
        C_RST_PRIORITY_A = "CE"
        C_RSTRAM_A = 0
        C_INITA_VAL = "0"
        C_HAS_ENA = 1
        C_HAS_REGCEA = 0
        C_USE_BYTE_WEA = 0
        C_WEA_WIDTH = 1
        C_WRITE_MODE_A = "READ_FIRST"
        C_WRITE_WIDTH_A = 32
        C_READ_WIDTH_A = 32
        C_WRITE_DEPTH_A = 16
        C_READ_DEPTH_A = 16
        C_ADDRA_WIDTH = 4
        C_HAS_RSTB = 1
        C_RST_PRIORITY_B = "CE"
        C_RSTRAM_B = 0
        C_INITB_VAL = "00000000"
        C_HAS_ENB = 1
        C_HAS_REGCEB = 0
        C_USE_BYTE_WEB = 0
        C_WEB_WIDTH = 1
        C_WRITE_MODE_B = "READ_FIRST"
        C_WRITE_WIDTH_B = 32
        C_READ_WIDTH_B = 32
        C_WRITE_DEPTH_B = 16
        C_READ_DEPTH_B = 16
        C_ADDRB_WIDTH = 4
        C_HAS_MEM_OUTPUT_REGS_A = 0
        C_HAS_MEM_OUTPUT_REGS_B = 0
        C_HAS_MUX_OUTPUT_REGS_A = 0
        C_HAS_MUX_OUTPUT_REGS_B = 0
        C_MUX_PIPELINE_STAGES = 0
        C_HAS_SOFTECC_INPUT_REGS_A = 0
        C_HAS_SOFTECC_INPUT_REGS_B = 0
        C_HAS_SOFTECC_OUTPUT_REGS_A = 0
        C_HAS_SOFTECC_OUTPUT_REGS_B = 0
        C_USE_ECC = 0
        C_USE_SOFTECC = 0
        C_HAS_INJECTERR = 0
        C_SIM_COLLISION_CHECK = "ALL"
        C_COMMON_CLK = 0
        C_DISABLE_WARN_BHV_COLL = 0
        C_DISABLE_WARN_BHV_RANGE = 0
    Summary:
	no macro.
Unit <blk_mem_gen_v4_1_xst> synthesized.

Synthesizing Unit <blk_mem_gen_top>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_top.vhd".
        C_FAMILY = "virtex6"
        C_XDEVICEFAMILY = "virtex6"
        C_ELABORATION_DIR = ""
        C_MEM_TYPE = 1
        C_BYTE_SIZE = 9
        C_ALGORITHM = 1
        C_PRIM_TYPE = 3
        C_LOAD_INIT_FILE = 0
        C_INIT_FILE_NAME = "no_coe_file_loaded"
        C_USE_DEFAULT_DATA = 0
        C_DEFAULT_DATA = "0"
        C_RST_TYPE = "SYNC"
        C_HAS_RSTA = 0
        C_RST_PRIORITY_A = "CE"
        C_RSTRAM_A = 0
        C_INITA_VAL = "0"
        C_HAS_ENA = 1
        C_HAS_REGCEA = 0
        C_USE_BYTE_WEA = 0
        C_WEA_WIDTH = 1
        C_WRITE_MODE_A = "WRITE_FIRST"
        C_WRITE_WIDTH_A = 32
        C_READ_WIDTH_A = 32
        C_WRITE_DEPTH_A = 16
        C_READ_DEPTH_A = 16
        C_ADDRA_WIDTH = 4
        C_HAS_RSTB = 1
        C_RST_PRIORITY_B = "CE"
        C_RSTRAM_B = 0
        C_INITB_VAL = "00000000"
        C_HAS_ENB = 1
        C_HAS_REGCEB = 0
        C_USE_BYTE_WEB = 0
        C_WEB_WIDTH = 1
        C_WRITE_MODE_B = "WRITE_FIRST"
        C_WRITE_WIDTH_B = 32
        C_READ_WIDTH_B = 32
        C_WRITE_DEPTH_B = 16
        C_READ_DEPTH_B = 16
        C_ADDRB_WIDTH = 4
        C_HAS_MEM_OUTPUT_REGS_A = 0
        C_HAS_MEM_OUTPUT_REGS_B = 0
        C_HAS_MUX_OUTPUT_REGS_A = 0
        C_HAS_MUX_OUTPUT_REGS_B = 0
        C_MUX_PIPELINE_STAGES = 0
        C_HAS_SOFTECC_INPUT_REGS_A = 0
        C_HAS_SOFTECC_INPUT_REGS_B = 0
        C_HAS_SOFTECC_OUTPUT_REGS_A = 0
        C_HAS_SOFTECC_OUTPUT_REGS_B = 0
        C_USE_SOFTECC = 0
        C_USE_ECC = 0
        C_HAS_INJECTERR = 0
        C_SIM_COLLISION_CHECK = "ALL"
        C_COMMON_CLK = 0
        C_DISABLE_WARN_BHV_COLL = 0
        C_DISABLE_WARN_BHV_RANGE = 0
    Summary:
	no macro.
Unit <blk_mem_gen_top> synthesized.

Synthesizing Unit <blk_mem_input_block>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_input_block.vhd".
        C_FAMILY = "virtex6"
        C_MEM_TYPE = 1
        C_HAS_RSTA = 0
        C_RSTA_WIDTH = 1
        C_HAS_ENA = 1
        C_HAS_REGCEA = 0
        C_REGCEA_WIDTH = 1
        C_USE_BYTE_WEA = 0
        C_WEA_WIDTH = 1
        C_WEA_I_WIDTH = 4
        C_WRITE_WIDTH_A = 32
        C_WRITE_WIDTH_A_CORE = 32
        C_ADDRA_WIDTH = 4
        C_ADDRA_WIDTH_CORE = 4
        C_HAS_RSTB = 1
        C_RSTB_WIDTH = 1
        C_HAS_ENB = 1
        C_HAS_REGCEB = 0
        C_REGCEB_WIDTH = 1
        C_USE_BYTE_WEB = 0
        C_WEB_WIDTH = 1
        C_WEB_I_WIDTH = 4
        C_WRITE_WIDTH_B = 32
        C_WRITE_WIDTH_B_CORE = 32
        C_ADDRB_WIDTH = 4
        C_ADDRB_WIDTH_CORE = 4
        C_HAS_MEM_OUTPUT_REGS_A = 0
        C_HAS_MEM_OUTPUT_REGS_B = 0
        C_HAS_MUX_OUTPUT_REGS_A = 0
        C_HAS_MUX_OUTPUT_REGS_B = 0
        C_MUX_PIPELINE_STAGES_A = 0
        C_MUX_PIPELINE_STAGES_B = 0
        C_HAS_SOFTECC_INPUT_REGS_A = 0
        C_HAS_SOFTECC_INPUT_REGS_B = 0
        C_USE_SOFTECC = 0
        C_HAS_INJECTERR = 0
WARNING:Xst:647 - Input <WEB<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DINB<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <RSTA> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <REGCEA> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <REGCEB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <INJECTDBITERR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <INJECTSBITERR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Summary:
	no macro.
Unit <blk_mem_input_block> synthesized.

Synthesizing Unit <blk_mem_gen_generic_cstr>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_generic_cstr.vhd".
        C_FAMILY = "virtex6"
        C_XDEVICEFAMILY = "virtex6"
        C_ELABORATION_DIR = ""
        C_MEM_TYPE = 1
        C_BYTE_SIZE = 9
        C_USER_WIDTH = 32
        C_USER_DEPTH = 16
        C_TOTAL_PRIMS = 1
        C_DEPTH_RESOLUTION = 1024
        C_START_WIDTH =
(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0)
        C_START_DEPTH =
(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0)
        C_PRIM_WIDTH =
(36,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0)
        C_PRIM_DEPTH =
(1024,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0)
        C_USED_WIDTH =
(32,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0)
        C_LOAD_INIT_FILE = 0
        C_INIT_FILE_NAME = "no_coe_file_loaded"
        C_USE_DEFAULT_DATA = 0
        C_DEFAULT_DATA = "0"
        C_RST_TYPE = "SYNC"
        C_HAS_RSTA = 0
        C_RSTA_WIDTH = 1
        C_RST_PRIORITY_A = "CE"
        C_RSTRAM_A = 0
        C_INITA_VAL = "0"
        C_HAS_REGCEA = 0
        C_REGCEA_WIDTH = 1
        C_USE_BYTE_WEA = 0
        C_WE_WIDTH_A = 4
        C_WRITE_MODE_A = "WRITE_FIRST"
        C_WRITE_WIDTH_A = 32
        C_RATIO_WA = 1
        C_READ_WIDTH_A = 32
        C_RATIO_RA = 1
        C_ADDR_WIDTH_A = 4
        C_HAS_RSTB = 1
        C_RSTB_WIDTH = 1
        C_RST_PRIORITY_B = "CE"
        C_RSTRAM_B = 0
        C_INITB_VAL = "00000000"
        C_HAS_REGCEB = 0
        C_REGCEB_WIDTH = 1
        C_USE_BYTE_WEB = 0
        C_WE_WIDTH_B = 4
        C_WRITE_MODE_B = "WRITE_FIRST"
        C_WRITE_WIDTH_B = 32
        C_RATIO_WB = 1
        C_READ_WIDTH_B = 32
        C_RATIO_RB = 1
        C_ADDR_WIDTH_B = 4
        C_HAS_MEM_OUTPUT_REGS_A = 0
        C_HAS_MEM_OUTPUT_REGS_B = 0
        C_HAS_MUX_OUTPUT_REGS_A = 0
        C_HAS_MUX_OUTPUT_REGS_B = 0
        C_MUX_PIPELINE_STAGES_A = 0
        C_MUX_PIPELINE_STAGES_B = 0
        C_USE_SOFTECC = 0
        C_EN_ECC_READ = false
        C_EN_ECC_WRITE = false
        C_SIM_COLLISION_CHECK = "ALL"
WARNING:Xst:647 - Input <REGCEA<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <WEA<3:1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <REGCEB<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <WEB<3:1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_generic_cstr.vhd" line 1324: Output port <SBITERR> of the instance <ramloop[0].ram.r> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_generic_cstr.vhd" line 1324: Output port <DBITERR> of the instance <ramloop[0].ram.r> is unconnected or connected to loadless signal.
WARNING:Xst:653 - Signal <RDADDRECC> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <SBITERR> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <DBITERR> is used but never assigned. This sourceless signal will be automatically connected to value GND.
    Summary:
	no macro.
Unit <blk_mem_gen_generic_cstr> synthesized.

Synthesizing Unit <blk_mem_gen_prim_width>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_width.vhd".
        C_FAMILY = "virtex6"
        C_XDEVICEFAMILY = "virtex6"
        C_ELABORATION_DIR = ""
        C_MEM_TYPE = 1
        C_BYTE_SIZE = 9
        C_USER_WIDTH = 32
        C_USER_DEPTH = 16
        C_START_WIDTH = 0
        C_START_DEPTH = 0
        C_PRIM_WIDTH = 36
        C_PRIM_DEPTH = 1024
        C_USED_WIDTH = 32
        C_LOAD_INIT_FILE = 0
        C_INIT_FILE_NAME = "no_coe_file_loaded"
        C_USE_DEFAULT_DATA = 0
        C_DEFAULT_DATA = "0"
        C_RST_TYPE = "SYNC"
        C_HAS_RSTA = 0
        C_RST_PRIORITY_A = "CE"
        C_RSTRAM_A = 0
        C_INITA_VAL = "00000000000000000000000000000000"
        C_USE_BYTE_WEA = 0
        C_WEA_WIDTH = 1
        C_WRITE_MODE_A = "WRITE_FIRST"
        C_RATIO_WA = 1
        C_RATIO_RA = 1
        C_ADDR_WIDTH_A = 4
        C_HAS_RSTB = 1
        C_RST_PRIORITY_B = "CE"
        C_RSTRAM_B = 0
        C_INITB_VAL = "00000000000000000000000000000000"
        C_USE_BYTE_WEB = 0
        C_WEB_WIDTH = 1
        C_WRITE_MODE_B = "WRITE_FIRST"
        C_RATIO_WB = 1
        C_RATIO_RB = 1
        C_ADDR_WIDTH_B = 4
        C_HAS_MEM_OUTPUT_REGS_A = 0
        C_HAS_MEM_OUTPUT_REGS_B = 0
        C_HAS_MUX_OUTPUT_REGS_A = 0
        C_HAS_MUX_OUTPUT_REGS_B = 0
        C_EN_ECC_READ = false
        C_EN_ECC_WRITE = false
        C_COMMON_CLK = 0
        C_SIM_COLLISION_CHECK = "ALL"
WARNING:Xst:2935 - Signal 'dina_pad<35>', unconnected in block 'blk_mem_gen_prim_width', is tied to its initial value (0).
WARNING:Xst:2935 - Signal 'dina_pad<26>', unconnected in block 'blk_mem_gen_prim_width', is tied to its initial value (0).
WARNING:Xst:2935 - Signal 'dina_pad<17>', unconnected in block 'blk_mem_gen_prim_width', is tied to its initial value (0).
WARNING:Xst:2935 - Signal 'dina_pad<8>', unconnected in block 'blk_mem_gen_prim_width', is tied to its initial value (0).
WARNING:Xst:2935 - Signal 'dinb_pad<35>', unconnected in block 'blk_mem_gen_prim_width', is tied to its initial value (0).
WARNING:Xst:2935 - Signal 'dinb_pad<26>', unconnected in block 'blk_mem_gen_prim_width', is tied to its initial value (0).
WARNING:Xst:2935 - Signal 'dinb_pad<17>', unconnected in block 'blk_mem_gen_prim_width', is tied to its initial value (0).
WARNING:Xst:2935 - Signal 'dinb_pad<8>', unconnected in block 'blk_mem_gen_prim_width', is tied to its initial value (0).
    Summary:
	no macro.
Unit <blk_mem_gen_prim_width> synthesized.

Synthesizing Unit <blk_mem_gen_prim_wrapper_v6>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v6.vhd".
        C_ELABORATION_DIR = ""
        C_MEM_TYPE = 1
        C_BYTE_SIZE = 9
        C_USER_WIDTH = 32
        C_USER_DEPTH = 16
        C_START_WIDTH = 0
        C_START_DEPTH = 0
        C_PRIM_WIDTH = 36
        C_PRIM_DEPTH = 1024
        C_USED_WIDTH = 32
        C_LOAD_INIT_FILE = 0
        C_INIT_FILE_NAME = "no_coe_file_loaded"
        C_USE_DEFAULT_DATA = 0
        C_DEFAULT_DATA = "0"
        C_USE_BYTE_WE = 0
        C_WEA_WIDTH = 1
        C_WEB_WIDTH = 1
        C_HAS_SSRA = 0
        C_RST_PRIORITY_A = "CE"
        C_RSTRAM_A = 0
        C_SINITA_VAL = "000000000000000000000000000000000000"
        C_WRITE_MODE_A = "WRITE_FIRST"
        C_WRITE_WIDTH_A = 36
        C_RATIO_WA = 1
        C_READ_WIDTH_A = 36
        C_RATIO_RA = 1
        C_ADDR_WIDTH_A = 10
        C_HAS_SSRB = 1
        C_RST_PRIORITY_B = "CE"
        C_RSTRAM_B = 0
        C_SINITB_VAL = "000000000000000000000000000000000000"
        C_WRITE_MODE_B = "WRITE_FIRST"
        C_WRITE_WIDTH_B = 36
        C_RATIO_WB = 1
        C_READ_WIDTH_B = 36
        C_RATIO_RB = 1
        C_ADDR_WIDTH_B = 10
        C_HAS_MEM_OUTPUT_REGS_A = 0
        C_HAS_MEM_OUTPUT_REGS_B = 0
        C_HAS_MUX_OUTPUT_REGS_A = 0
        C_HAS_MUX_OUTPUT_REGS_B = 0
        C_EN_ECC_READ = false
        C_EN_ECC_WRITE = false
        C_COMMON_CLK = 0
        C_SIM_COLLISION_CHECK = "ALL"
WARNING:Xst:647 - Input <WEB<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DINB<35:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <SSRA> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <REGCEA> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:2935 - Signal 'douta_i', unconnected in block 'blk_mem_gen_prim_wrapper_v6', is tied to its initial value (000000000000000000000000000000000000).
WARNING:Xst:653 - Signal <SBITERR> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <DBITERR> is used but never assigned. This sourceless signal will be automatically connected to value GND.
    Summary:
	no macro.
Unit <blk_mem_gen_prim_wrapper_v6> synthesized.

Synthesizing Unit <blk_mem_output_block>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_output_block.vhd".
        C_MEM_TYPE = 1
        C_WRITE_WIDTH_A = 32
        C_READ_WIDTH_A = 32
        C_READ_WIDTH_B = 32
        C_READ_WIDTH_A_CORE = 32
        C_READ_WIDTH_B_CORE = 32
        C_ADDRB_WIDTH = 4
        C_HAS_SOFTECC_OUTPUT_REGS_A = 0
        C_HAS_SOFTECC_OUTPUT_REGS_B = 0
        C_USE_SOFTECC = 0
        C_USE_ECC = 0
WARNING:Xst:647 - Input <DOUTA_I<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <RDADDRECC_I<3:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <CLKB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <SBITERR_I> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DBITERR_I> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:653 - Signal <RDADDRECC> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <SBITERR> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <DBITERR> is used but never assigned. This sourceless signal will be automatically connected to value GND.
    Summary:
	no macro.
Unit <blk_mem_output_block> synthesized.

Synthesizing Unit <rd_logic>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_logic.vhd".
        C_COMMON_CLOCK = 1
        C_HAS_ALMOST_EMPTY = 0
        C_HAS_RD_DATA_COUNT = 0
        C_USE_FWFT_DATA_COUNT = 0
        C_HAS_DATA_COUNT = 1
        C_HAS_RST = 1
        C_HAS_SRST = 0
        C_HAS_VALID = 0
        C_VALID_LOW = 0
        C_HAS_UNDERFLOW = 0
        C_UNDERFLOW_LOW = 0
        C_PRELOAD_LATENCY = 1
        C_PRELOAD_REGS = 0
        C_RD_DEPTH = 16
        C_RD_PNTR_WIDTH = 4
        C_WR_DEPTH = 16
        C_WR_PNTR_WIDTH = 4
        C_PROG_EMPTY_TYPE = 1
        C_PROG_EMPTY_THRESH_ASSERT_VAL = 1
        C_PROG_EMPTY_THRESH_NEGATE_VAL = 2
        C_USE_EMBEDDED_REG = 0
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_logic.vhd" line 362: Output port <RAM_ALMOST_EMPTY> of the instance <grss.rsts> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_logic.vhd" line 362: Output port <RAM_ALMOST_EMPTY_FB> of the instance <grss.rsts> is unconnected or connected to loadless signal.
WARNING:Xst:2935 - Signal 'RD_DATA_COUNT', unconnected in block 'rd_logic', is tied to its initial value (00000).
WARNING:Xst:2935 - Signal 'RAM_REGOUT_EN', unconnected in block 'rd_logic', is tied to its initial value (0).
    Summary:
	no macro.
Unit <rd_logic> synthesized.

Synthesizing Unit <rd_bin_cntr>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_bin_cntr.vhd".
        C_HAS_ALMOST_EMPTY = 0
        C_PNTR_WIDTH = 4
    Found 4-bit register for signal <gc0.count_d1>.
    Found 4-bit register for signal <gc0.count>.
    Found 4-bit adder for signal <gc0.count[3]_GND_409_o_add_0_OUT> created at line 128.
    Summary:
	inferred   1 Adder/Subtractor(s).
	inferred   8 D-type flip-flop(s).
	inferred   2 Multiplexer(s).
Unit <rd_bin_cntr> synthesized.

Synthesizing Unit <rd_status_flags_ss>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_status_flags_ss.vhd".
        C_RD_PNTR_WIDTH = 4
        C_WR_PNTR_WIDTH = 4
        C_HAS_ALMOST_EMPTY = 0
    Set property "equivalent_register_removal = no" for signal <ram_empty_i>.
    Set property "equivalent_register_removal = no" for signal <ram_empty_fb_i>.
WARNING:Xst:647 - Input <RD_PNTR_PLUS2<3:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:2935 - Signal 'RAM_ALMOST_EMPTY_FB', unconnected in block 'rd_status_flags_ss', is tied to its initial value (0).
    Found 1-bit register for signal <ram_empty_fb_i>.
    Found 1-bit register for signal <ram_empty_i>.
    Summary:
	inferred   2 D-type flip-flop(s).
	inferred   1 Multiplexer(s).
Unit <rd_status_flags_ss> synthesized.

Synthesizing Unit <compare>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/compare.vhd".
        C_WIDTH = 4
    Summary:
Unit <compare> synthesized.

Synthesizing Unit <rd_pe_ss>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_pe_ss.vhd".
        C_PROG_EMPTY_TYPE = 1
        C_PROG_EMPTY_THRESH_ASSERT_VAL = 1
        C_PROG_EMPTY_THRESH_NEGATE_VAL = 2
        C_RD_PNTR_WIDTH = 4
        C_WR_PNTR_WIDTH = 4
        C_PRELOAD_LATENCY = 1
        C_PRELOAD_REGS = 0
WARNING:Xst:647 - Input <PROG_EMPTY_THRESH<3:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <PROG_EMPTY_THRESH_ASSERT<3:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <PROG_EMPTY_THRESH_NEGATE<3:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ALMOST_FULL_FB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 1-bit register for signal <prog_empty_i>.
    Found 1-bit register for signal <ram_rd_en_i>.
    Found 1-bit register for signal <ram_wr_en_i>.
    Found 4-bit register for signal <diff_pntr_pad<4:1>>.
    Found 5-bit adder for signal <wr_pntr_rd_pad[4]_rd_pntr_inv_pad[4]_add_2_OUT> created at line 210.
    Summary:
	inferred   1 Adder/Subtractor(s).
	inferred   7 D-type flip-flop(s).
	inferred   4 Multiplexer(s).
Unit <rd_pe_ss> synthesized.

Synthesizing Unit <dc_ss>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/dc_ss.vhd".
        C_RD_PNTR_WIDTH = 4
    Summary:
Unit <dc_ss> synthesized.

Synthesizing Unit <updn_cntr>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/updn_cntr.vhd".
        C_COUNTER_RESET_VAL = 0
        C_PNTR_WIDTH = 4
    Found 4-bit register for signal <count>.
    Found 4-bit adder for signal <count[3]_one[3]_add_1_OUT> created at line 126.
    Found 4-bit subtractor for signal <GND_417_o_GND_417_o_sub_3_OUT<3:0>> created at line 128.
    Summary:
	inferred   1 Adder/Subtractor(s).
	inferred   4 D-type flip-flop(s).
	inferred   1 Multiplexer(s).
Unit <updn_cntr> synthesized.

Synthesizing Unit <wr_logic>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_logic.vhd".
        C_COMMON_CLOCK = 1
        C_HAS_ALMOST_FULL = 0
        C_HAS_WR_DATA_COUNT = 0
        C_HAS_RST = 1
        C_HAS_WR_ACK = 0
        C_WR_ACK_LOW = 0
        C_HAS_OVERFLOW = 1
        C_OVERFLOW_LOW = 0
        C_PRELOAD_LATENCY = 1
        C_PRELOAD_REGS = 0
        C_DEPTH_RATIO_RD = 1
        C_DEPTH_RATIO_WR = 1
        C_RD_PNTR_WIDTH = 4
        C_WR_PNTR_WIDTH = 4
        C_USE_FWFT_DATA_COUNT = 0
        C_PROG_EMPTY_TYPE = 1
        C_PROG_FULL_TYPE = 1
        C_PROG_FULL_THRESH_ASSERT_VAL = 11
        C_PROG_FULL_THRESH_NEGATE_VAL = 10
        C_FULL_FLAGS_RST_VAL = 1
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_logic.vhd" line 214: Output port <PNTR_PLUS3> of the instance <wpntr> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_logic.vhd" line 381: Output port <RAM_ALMOST_FULL> of the instance <gwss.wsts> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_logic.vhd" line 476: Output port <WR_ACK> of the instance <gwhf.whf> is unconnected or connected to loadless signal.
    Summary:
	no macro.
Unit <wr_logic> synthesized.

Synthesizing Unit <wr_bin_cntr>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_bin_cntr.vhd".
        C_HAS_ALMOST_FULL = 0
        C_PROG_EMPTY_TYPE = 1
        C_PROG_FULL_TYPE = 1
        C_PNTR_WIDTH = 4
        C_COMMON_CLOCK = 1
    Found 4-bit register for signal <gcc0.gc0.count_d1>.
    Found 4-bit register for signal <gcc0.gc0.count>.
    Found 4-bit adder for signal <gcc0.gc0.count[3]_GND_419_o_add_0_OUT> created at line 151.
    Summary:
	inferred   1 Adder/Subtractor(s).
	inferred   8 D-type flip-flop(s).
	inferred   2 Multiplexer(s).
Unit <wr_bin_cntr> synthesized.

Synthesizing Unit <wr_status_flags_ss>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_status_flags_ss.vhd".
        C_RD_PNTR_WIDTH = 4
        C_WR_PNTR_WIDTH = 4
        C_HAS_RST = 1
        C_HAS_ALMOST_FULL = 0
        C_PROG_FULL_TYPE = 1
        C_PROG_EMPTY_TYPE = 1
        C_FULL_FLAGS_RST_VAL = 1
    Set property "equivalent_register_removal = no" for signal <ram_full_i>.
    Set property "equivalent_register_removal = no" for signal <ram_full_fb_i>.
    Set property "equivalent_register_removal = no" for signal <ram_afull_i>.
    Set property "equivalent_register_removal = no" for signal <ram_afull_fb>.
WARNING:Xst:647 - Input <WR_PNTR_PLUS2<3:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <WR_RST> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <SRST> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:2935 - Signal 'ram_afull_i', unconnected in block 'wr_status_flags_ss', is tied to its initial value (1).
WARNING:Xst:2935 - Signal 'ram_afull_fb', unconnected in block 'wr_status_flags_ss', is tied to its initial value (1).
    Found 1-bit register for signal <ram_full_fb_i>.
    Found 1-bit register for signal <ram_full_i>.
    Summary:
	inferred   2 D-type flip-flop(s).
	inferred   1 Multiplexer(s).
Unit <wr_status_flags_ss> synthesized.

Synthesizing Unit <wr_pf_ss>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_pf_ss.vhd".
        C_HAS_RST = 1
        C_PROG_FULL_TYPE = 1
        C_PROG_FULL_THRESH_ASSERT_VAL = 11
        C_PROG_FULL_THRESH_NEGATE_VAL = 10
        C_RD_PNTR_WIDTH = 4
        C_WR_PNTR_WIDTH = 4
        C_FULL_FLAGS_RST_VAL = 1
        C_PRELOAD_LATENCY = 1
        C_PRELOAD_REGS = 0
WARNING:Xst:647 - Input <PROG_FULL_THRESH<3:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <PROG_FULL_THRESH_ASSERT<3:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <PROG_FULL_THRESH_NEGATE<3:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <RAM_ALMOST_FULL> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 1-bit register for signal <prog_full_i>.
    Found 1-bit register for signal <ram_wr_en_i>.
    Found 1-bit register for signal <ram_rd_en_i>.
    Found 4-bit register for signal <diff_pntr_pad<4:1>>.
    Found 5-bit adder for signal <wr_pntr_plus1_pad[4]_rd_pntr_wr_inv_pad[4]_add_2_OUT> created at line 243.
    Summary:
	inferred   1 Adder/Subtractor(s).
	inferred   7 D-type flip-flop(s).
	inferred   5 Multiplexer(s).
Unit <wr_pf_ss> synthesized.

Synthesizing Unit <wr_handshaking_flags>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_handshaking_flags.vhd".
        C_HAS_WR_ACK = 0
        C_WR_ACK_LOW = 0
        C_HAS_OVERFLOW = 1
        C_OVERFLOW_LOW = 0
WARNING:Xst:647 - Input <WR_RST> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <SRST> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:653 - Signal <WR_ACK> is used but never assigned. This sourceless signal will be automatically connected to value GND.
    Found 1-bit register for signal <OVERFLOW>.
    Summary:
	inferred   1 D-type flip-flop(s).
Unit <wr_handshaking_flags> synthesized.

Synthesizing Unit <output_blk>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/output_blk.vhd".
        C_COMMON_CLOCK = 1
        C_DATA_COUNT_WIDTH = 4
        C_DIN_WIDTH = 32
        C_DOUT_WIDTH = 32
        C_HAS_ALMOST_EMPTY = 0
        C_HAS_ALMOST_FULL = 0
        C_HAS_DATA_COUNT = 1
        C_HAS_OVERFLOW = 1
        C_HAS_RD_DATA_COUNT = 0
        C_HAS_UNDERFLOW = 0
        C_HAS_VALID = 0
        C_HAS_WR_ACK = 0
        C_HAS_WR_DATA_COUNT = 0
        C_PROG_EMPTY_TYPE = 1
        C_PROG_FULL_TYPE = 1
        C_DEPTH_RATIO_WR = 1
        C_RD_DATA_COUNT_WIDTH = 4
        C_RD_PNTR_WIDTH = 4
        C_WR_PNTR_WIDTH = 4
        C_WR_DATA_COUNT_WIDTH = 4
        C_USE_FWFT_DATA_COUNT = 0
        C_USE_ECC = 0
WARNING:Xst:647 - Input <DATA_COUNT_I<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <WR_DATA_COUNT_I<4:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <RD_DATA_COUNT_I<4:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ALMOST_FULL_I> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ALMOST_EMPTY_I> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <WR_ACK_I> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <VALID_I> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <UNDERFLOW_I> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <SBITERR_I> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DBITERR_I> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Summary:
	no macro.
Unit <output_blk> synthesized.

Synthesizing Unit <eb_config>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/etherbone-core/hdl/eb_slave_core/eb_config.vhd".
        g_sdb_address = "0000000000000000000000000000000000110000000000000000000000000000"
WARNING:Xst:647 - Input <local_slave_i_adr<31:8>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <local_slave_i_adr<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <local_slave_i_sel<3:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <eb_slave_i_adr<31:8>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <eb_slave_i_adr<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <eb_slave_i_sel<3:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:653 - Signal <local_slave_o_int> is used but never assigned. This sourceless signal will be automatically connected to value GND.
    Found 1-bit register for signal <eb_slave_o_err>.
    Found 1-bit register for signal <eb_slave_o_rty>.
    Found 1-bit register for signal <eb_slave_o_stall>.
    Found 1-bit register for signal <eb_slave_o_int>.
    Found 32-bit register for signal <eb_slave_o_dat>.
    Found 1-bit register for signal <local_slave_o_ack>.
    Found 1-bit register for signal <local_slave_o_err>.
    Found 1-bit register for signal <local_slave_o_rty>.
    Found 32-bit register for signal <local_slave_o_dat>.
    Found 32-bit register for signal <my_ip>.
    Found 48-bit register for signal <my_mac>.
    Found 16-bit register for signal <my_port>.
    Found 64-bit register for signal <p_auto_cfg>.
    Found 32-bit register for signal <local_write_reg>.
    Found 64-bit register for signal <status_reg>.
    Found 1-bit register for signal <eb_slave_o_ack>.
    Found 32-bit 8-to-1 multiplexer for signal <_n0259> created at line 137.
    Found 32-bit 8-to-1 multiplexer for signal <_n0277> created at line 168.
    Summary:
	inferred 328 D-type flip-flop(s).
	inferred  22 Multiplexer(s).
Unit <eb_config> synthesized.

Synthesizing Unit <xwb_simple_uart>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd".
        g_with_virtual_uart = false
        g_with_physical_uart = true
        g_interface_mode = pipelined
        g_address_granularity = byte
WARNING:Xst:647 - Input <slave_i_adr<31:5>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:653 - Signal <desc_o> is used but never assigned. This sourceless signal will be automatically connected to value GND.
    Summary:
	no macro.
Unit <xwb_simple_uart> synthesized.

Synthesizing Unit <wb_simple_uart>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd".
        g_with_virtual_uart = false
        g_with_physical_uart = true
        g_interface_mode = pipelined
        g_address_granularity = byte
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 154: Output port <slave_o_dat> of the instance <U_Adapter> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 154: Output port <ma_adr_o> of the instance <U_Adapter> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 154: Output port <ma_dat_o> of the instance <U_Adapter> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 154: Output port <ma_sel_o> of the instance <U_Adapter> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 154: Output port <sl_err_o> of the instance <U_Adapter> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 154: Output port <sl_rty_o> of the instance <U_Adapter> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 154: Output port <sl_int_o> of the instance <U_Adapter> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 154: Output port <slave_o_ack> of the instance <U_Adapter> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 154: Output port <slave_o_err> of the instance <U_Adapter> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 154: Output port <slave_o_rty> of the instance <U_Adapter> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 154: Output port <slave_o_stall> of the instance <U_Adapter> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 154: Output port <slave_o_int> of the instance <U_Adapter> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 154: Output port <ma_cyc_o> of the instance <U_Adapter> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 154: Output port <ma_stb_o> of the instance <U_Adapter> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 154: Output port <ma_we_o> of the instance <U_Adapter> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 177: Output port <regs_o_host_tdr_data_o> of the instance <U_WB_SLAVE> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 177: Output port <host_rack_o> of the instance <U_WB_SLAVE> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 229: Output port <rx_error_o> of the instance <gen_phys_uart.U_RX> is unconnected or connected to loadless signal.
WARNING:Xst:653 - Signal <regs_in_host_rdr_data_i> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <regs_in_host_rdr_count_i> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <wb_out_err> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <wb_out_rty> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <wb_out_int> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <regs_in_host_tdr_rdy_i> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <regs_in_host_rdr_rdy_i> is used but never assigned. This sourceless signal will be automatically connected to value GND.
    Found 1-bit register for signal <regs_in_sr_rx_rdy_i>.
    Found 8-bit register for signal <regs_in_rdr_rx_data_i>.
    Found 32-bit register for signal <uart_bcr>.
    Summary:
	inferred  41 D-type flip-flop(s).
Unit <wb_simple_uart> synthesized.

Synthesizing Unit <wb_slave_adapter_5>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd".
        g_master_use_struct = true
        g_master_mode = classic
        g_master_granularity = word
        g_slave_use_struct = false
        g_slave_mode = pipelined
        g_slave_granularity = byte
WARNING:Xst:647 - Input <slave_i_adr<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <slave_i_sel<3:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <slave_i_dat<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ma_dat_i<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clk_sys_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <rst_n_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <slave_i_cyc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <slave_i_stb> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <slave_i_we> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ma_err_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ma_rty_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ma_ack_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ma_stall_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ma_int_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <master_i_stall> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:653 - Signal <ma_adr_o> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <ma_dat_o> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <ma_sel_o> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <ma_cyc_o> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <ma_stb_o> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <ma_we_o> is used but never assigned. This sourceless signal will be automatically connected to value GND.
    Summary:
	no macro.
Unit <wb_slave_adapter_5> synthesized.

Synthesizing Unit <simple_uart_wb>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd".
WARNING:Xst:647 - Input <wb_sel_i<3:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 9-bit register for signal <ack_sreg>.
    Found 32-bit register for signal <rddata_reg>.
    Found 1-bit register for signal <ack_in_progress>.
    Found 1-bit register for signal <regs_o_bcr_wr_o>.
    Found 1-bit register for signal <regs_o_tdr_tx_data_wr_o>.
    Found 1-bit register for signal <regs_o_host_tdr_data_wr_o>.
    Found 1-bit register for signal <rdr_rack_o>.
    Found 1-bit register for signal <host_rack_o>.
    WARNING:Xst:2404 -  FFs/Latches <ack_sreg<9:9>> (without init value) have a constant value of 0 in block <simple_uart_wb>.
    Summary:
	inferred  47 D-type flip-flop(s).
	inferred   4 Multiplexer(s).
Unit <simple_uart_wb> synthesized.

Synthesizing Unit <uart_baud_gen>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd".
        g_baud_acc_width = 16
    Found 8-bit register for signal <Baud_sreg>.
    Found 17-bit register for signal <Baud8GeneratorAcc>.
    Found 17-bit adder for signal <GND_495_o_Baud8GeneratorInc[16]_add_1_OUT> created at line 39.
    Summary:
	inferred   1 Adder/Subtractor(s).
	inferred  25 D-type flip-flop(s).
	inferred   1 Multiplexer(s).
Unit <uart_baud_gen> synthesized.

Synthesizing Unit <uart_async_tx>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd".
    Found 4-bit register for signal <state>.
    Found 1-bit register for signal <TxD>.
    Found 8-bit register for signal <TxD_dataReg>.
    Found finite state machine <FSM_11> for signal <state>.
    -----------------------------------------------------------------------
    | States             | 13                                             |
    | Transitions        | 26                                             |
    | Inputs             | 2                                              |
    | Outputs            | 6                                              |
    | Clock              | clk_sys_i (rising_edge)                        |
    | Reset              | rst_n_i_INV_1074_o (positive)                  |
    | Reset type         | synchronous                                    |
    | Reset State        | 0000                                           |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 1-bit 8-to-1 multiplexer for signal <muxbit> created at line 130.
    Summary:
	inferred   9 D-type flip-flop(s).
	inferred   1 Multiplexer(s).
	inferred   1 Finite State Machine(s).
Unit <uart_async_tx> synthesized.

Synthesizing Unit <uart_async_rx>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd".
    Found 1-bit register for signal <RxD_bit_inv>.
    Found 2-bit register for signal <RxD_cnt_inv>.
    Found 4-bit register for signal <bit_spacing>.
    Found 4-bit register for signal <state>.
    Found 8-bit register for signal <RxD_data>.
    Found 1-bit register for signal <RxD_data_error>.
    Found 1-bit register for signal <RxD_data_ready>.
    Found 2-bit register for signal <RxD_sync_inv>.
    Found finite state machine <FSM_12> for signal <state>.
    -----------------------------------------------------------------------
    | States             | 10                                             |
    | Transitions        | 30                                             |
    | Inputs             | 3                                              |
    | Outputs            | 3                                              |
    | Clock              | clk_sys_i (rising_edge)                        |
    | Reset              | rst_n_i_INV_1084_o (positive)                  |
    | Reset type         | synchronous                                    |
    | Reset State        | 0000                                           |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 2-bit adder for signal <RxD_cnt_inv[1]_GND_497_o_add_4_OUT> created at line 1241.
    Found 4-bit adder for signal <GND_497_o_GND_497_o_add_16_OUT> created at line 1241.
    Found 2-bit subtractor for signal <GND_497_o_GND_497_o_sub_7_OUT<1:0>> created at line 1308.
    Summary:
	inferred   2 Adder/Subtractor(s).
	inferred  19 D-type flip-flop(s).
	inferred   1 Multiplexer(s).
	inferred   1 Finite State Machine(s).
Unit <uart_async_rx> synthesized.

Synthesizing Unit <xwb_gpio_port>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd".
        g_interface_mode = classic
        g_address_granularity = byte
        g_num_pins = 8
        g_with_builtin_tristates = false
WARNING:Xst:647 - Input <slave_i_adr<31:8>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:653 - Signal <desc_o> is used but never assigned. This sourceless signal will be automatically connected to value GND.
    Summary:
	no macro.
Unit <xwb_gpio_port> synthesized.

Synthesizing Unit <wb_gpio_port>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd".
        g_interface_mode = classic
        g_address_granularity = byte
        g_num_pins = 8
        g_with_builtin_tristates = false
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 97: Output port <slave_o_dat> of the instance <U_Adapter> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 97: Output port <ma_adr_o> of the instance <U_Adapter> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 97: Output port <ma_dat_o> of the instance <U_Adapter> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 97: Output port <ma_sel_o> of the instance <U_Adapter> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 97: Output port <sl_err_o> of the instance <U_Adapter> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 97: Output port <sl_rty_o> of the instance <U_Adapter> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 97: Output port <sl_int_o> of the instance <U_Adapter> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 97: Output port <slave_o_ack> of the instance <U_Adapter> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 97: Output port <slave_o_err> of the instance <U_Adapter> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 97: Output port <slave_o_rty> of the instance <U_Adapter> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 97: Output port <slave_o_stall> of the instance <U_Adapter> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 97: Output port <slave_o_int> of the instance <U_Adapter> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 97: Output port <ma_cyc_o> of the instance <U_Adapter> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 97: Output port <ma_stb_o> of the instance <U_Adapter> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 97: Output port <ma_we_o> of the instance <U_Adapter> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 123: Output port <npulse_o> of the instance <GEN_SYNC_FFS[0].INPUT_SYNC> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 123: Output port <ppulse_o> of the instance <GEN_SYNC_FFS[0].INPUT_SYNC> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 123: Output port <npulse_o> of the instance <GEN_SYNC_FFS[1].INPUT_SYNC> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 123: Output port <ppulse_o> of the instance <GEN_SYNC_FFS[1].INPUT_SYNC> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 123: Output port <npulse_o> of the instance <GEN_SYNC_FFS[2].INPUT_SYNC> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 123: Output port <ppulse_o> of the instance <GEN_SYNC_FFS[2].INPUT_SYNC> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 123: Output port <npulse_o> of the instance <GEN_SYNC_FFS[3].INPUT_SYNC> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 123: Output port <ppulse_o> of the instance <GEN_SYNC_FFS[3].INPUT_SYNC> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 123: Output port <npulse_o> of the instance <GEN_SYNC_FFS[4].INPUT_SYNC> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 123: Output port <ppulse_o> of the instance <GEN_SYNC_FFS[4].INPUT_SYNC> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 123: Output port <npulse_o> of the instance <GEN_SYNC_FFS[5].INPUT_SYNC> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 123: Output port <ppulse_o> of the instance <GEN_SYNC_FFS[5].INPUT_SYNC> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 123: Output port <npulse_o> of the instance <GEN_SYNC_FFS[6].INPUT_SYNC> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 123: Output port <ppulse_o> of the instance <GEN_SYNC_FFS[6].INPUT_SYNC> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 123: Output port <npulse_o> of the instance <GEN_SYNC_FFS[7].INPUT_SYNC> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 123: Output port <ppulse_o> of the instance <GEN_SYNC_FFS[7].INPUT_SYNC> is unconnected or connected to loadless signal.
WARNING:Xst:2563 - Inout <gpio_b> is never assigned. Tied to value Z.
WARNING:Xst:653 - Signal <gpio_in_synced<31:8>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
    Found 32-bit register for signal <out_reg>.
    Found 32-bit register for signal <wb_out_dat>.
    Found 1-bit register for signal <ack_int>.
    Found 32-bit register for signal <dir_reg>.
    Found 8x1-bit Read Only RAM for signal <write_mask<0>>
    Found 8-bit tristate buffer for signal <gpio_b> created at line 56
    Summary:
	inferred   1 RAM(s).
	inferred  97 D-type flip-flop(s).
	inferred   8 Multiplexer(s).
	inferred   1 Tristate(s).
Unit <wb_gpio_port> synthesized.

Synthesizing Unit <wb_slave_adapter_6>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd".
        g_master_use_struct = true
        g_master_mode = classic
        g_master_granularity = word
        g_slave_use_struct = false
        g_slave_mode = classic
        g_slave_granularity = byte
WARNING:Xst:647 - Input <slave_i_adr<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <slave_i_sel<3:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <slave_i_dat<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ma_dat_i<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clk_sys_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <rst_n_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <slave_i_cyc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <slave_i_stb> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <slave_i_we> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ma_err_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ma_rty_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ma_ack_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ma_stall_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ma_int_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:653 - Signal <ma_adr_o> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <ma_dat_o> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <ma_sel_o> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <ma_cyc_o> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <ma_stb_o> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <ma_we_o> is used but never assigned. This sourceless signal will be automatically connected to value GND.
    Summary:
	no macro.
Unit <wb_slave_adapter_6> synthesized.

=========================================================================
HDL Synthesis Report

Macro Statistics
# RAMs                                                 : 16
 1024x32-bit dual-port RAM                             : 1
 16384x32-bit dual-port RAM                            : 1
 16x32-bit dual-port RAM                               : 1
 256x20-bit dual-port RAM                              : 1
 256x32-bit dual-port RAM                              : 4
 256x32-bit single-port Read Only RAM                  : 1
 32768x32-bit dual-port RAM                            : 1
 32x32-bit dual-port RAM                               : 2
 4x2-bit single-port Read Only RAM                     : 1
 4x6-bit single-port Read Only RAM                     : 1
 8x1-bit single-port Read Only RAM                     : 2
# Multipliers                                          : 3
 16x16-bit multiplier                                  : 3
# Adders/Subtractors                                   : 114
 10-bit adder                                          : 1
 11-bit adder                                          : 2
 11-bit subtractor                                     : 1
 12-bit adder                                          : 2
 13-bit adder                                          : 1
 14-bit subtractor                                     : 1
 15-bit subtractor                                     : 3
 16-bit adder                                          : 11
 16-bit subtractor                                     : 3
 17-bit adder                                          : 2
 17-bit subtractor                                     : 1
 2-bit adder                                           : 7
 2-bit addsub                                          : 1
 2-bit subtractor                                      : 1
 28-bit adder                                          : 1
 29-bit adder                                          : 2
 3-bit adder                                           : 4
 3-bit subtractor                                      : 1
 30-bit adder                                          : 3
 32-bit adder                                          : 7
 32-bit subtractor                                     : 3
 33-bit adder                                          : 2
 33-bit subtractor                                     : 2
 4-bit adder                                           : 10
 4-bit addsub                                          : 2
 5-bit adder                                           : 10
 6-bit adder                                           : 3
 7-bit adder                                           : 2
 8-bit adder                                           : 10
 8-bit addsub                                          : 3
 8-bit subtractor                                      : 6
 9-bit subtractor                                      : 6
# Registers                                            : 986
 1-bit register                                        : 638
 10-bit register                                       : 4
 11-bit register                                       : 7
 12-bit register                                       : 8
 15-bit register                                       : 3
 16-bit register                                       : 37
 160-bit register                                      : 3
 17-bit register                                       : 1
 2-bit register                                        : 22
 23-bit register                                       : 2
 24-bit register                                       : 1
 28-bit register                                       : 1
 29-bit register                                       : 9
 3-bit register                                        : 13
 30-bit register                                       : 3
 32-bit register                                       : 76
 4-bit register                                        : 45
 48-bit register                                       : 4
 5-bit register                                        : 15
 6-bit register                                        : 4
 64-bit register                                       : 2
 7-bit register                                        : 7
 8-bit register                                        : 72
 9-bit register                                        : 8
 96-bit register                                       : 1
# Comparators                                          : 93
 1-bit comparator equal                                : 2
 10-bit comparator equal                               : 1
 11-bit comparator equal                               : 5
 11-bit comparator greater                             : 2
 12-bit comparator equal                               : 1
 12-bit comparator greater                             : 1
 14-bit comparator equal                               : 1
 16-bit comparator equal                               : 5
 16-bit comparator greater                             : 9
 16-bit comparator lessequal                           : 1
 20-bit comparator equal                               : 1
 32-bit comparator equal                               : 5
 32-bit comparator greater                             : 3
 32-bit comparator lessequal                           : 2
 4-bit comparator equal                                : 2
 4-bit comparator greater                              : 12
 4-bit comparator lessequal                            : 1
 5-bit comparator equal                                : 8
 5-bit comparator not equal                            : 3
 6-bit comparator equal                                : 2
 7-bit comparator greater                              : 3
 7-bit comparator lessequal                            : 3
 7-bit comparator not equal                            : 1
 8-bit comparator equal                                : 12
 8-bit comparator greater                              : 6
 8-bit comparator lessequal                            : 1
# Multiplexers                                         : 1150
 1-bit 2-to-1 multiplexer                              : 731
 1-bit 3-to-1 multiplexer                              : 1
 1-bit 4-to-1 multiplexer                              : 41
 1-bit 8-to-1 multiplexer                              : 3
 11-bit 2-to-1 multiplexer                             : 2
 12-bit 2-to-1 multiplexer                             : 8
 15-bit 2-to-1 multiplexer                             : 3
 16-bit 2-to-1 multiplexer                             : 22
 16-bit 3-to-1 multiplexer                             : 1
 2-bit 2-to-1 multiplexer                              : 23
 23-bit 2-to-1 multiplexer                             : 2
 24-bit 2-to-1 multiplexer                             : 5
 28-bit 2-to-1 multiplexer                             : 4
 29-bit 2-to-1 multiplexer                             : 7
 3-bit 2-to-1 multiplexer                              : 13
 30-bit 2-to-1 multiplexer                             : 4
 32-bit 2-to-1 multiplexer                             : 105
 32-bit 25-to-1 multiplexer                            : 1
 32-bit 3-to-1 multiplexer                             : 3
 32-bit 7-to-1 multiplexer                             : 2
 32-bit 8-to-1 multiplexer                             : 2
 4-bit 2-to-1 multiplexer                              : 34
 48-bit 2-to-1 multiplexer                             : 9
 5-bit 2-to-1 multiplexer                              : 16
 6-bit 2-to-1 multiplexer                              : 3
 64-bit 2-to-1 multiplexer                             : 1
 7-bit 2-to-1 multiplexer                              : 6
 8-bit 2-to-1 multiplexer                              : 86
 8-bit 4-to-1 multiplexer                              : 3
 9-bit 2-to-1 multiplexer                              : 8
 96-bit 2-to-1 multiplexer                             : 1
# Logic shifters                                       : 1
 64-bit shifter logical right                          : 1
# Tristates                                            : 3
 1-bit tristate buffer                                 : 1
 8-bit tristate buffer                                 : 2
# FSMs                                                 : 13
# Xors                                                 : 275
 1-bit xor2                                            : 175
 1-bit xor3                                            : 10
 1-bit xor4                                            : 2
 32-bit xor2                                           : 88

=========================================================================
INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing.

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Reading core <../../platform/virtex6/chipscope/chipscope_ila.ngc>.
Reading core <../../platform/virtex6/chipscope/icon_4_port/chipscope_icon_4_port.ngc>.
Loading core <chipscope_ila> for timing and area information for instance <cmp_chipscope_ila_1_ethmac_tx>.
Loading core <chipscope_ila> for timing and area information for instance <cmp_chipscope_ila_1_ethmac_rx>.
Loading core <chipscope_ila> for timing and area information for instance <cmp_chipscope_ila_0_ethmac>.
Loading core <chipscope_icon_4_port> for timing and area information for instance <cmp_chipscope_icon_0>.
Loading core <chipscope_ila> for timing and area information for instance <cmp_chipscope_ila_1_ethmac_miim>.
INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1
INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1
INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1
INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1
INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1
INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1
INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1
INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1
INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1
INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1
INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1
INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1
INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1
INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1
WARNING:Xst:1290 - Hierarchical block <grss.gpe.rdpe> is unconnected in block <gl0.rd>.
   It will be removed from the design.
WARNING:Xst:1290 - Hierarchical block <gwhf.whf> is unconnected in block <gl0.wr>.
   It will be removed from the design.
WARNING:Xst:1290 - Hierarchical block <grss.gpe.rdpe> is unconnected in block <gl0.rd>.
   It will be removed from the design.
WARNING:Xst:1290 - Hierarchical block <grss.gdc.dc> is unconnected in block <gl0.rd>.
   It will be removed from the design.
WARNING:Xst:1290 - Hierarchical block <gwhf.whf> is unconnected in block <gl0.wr>.
   It will be removed from the design.
INFO:Xst:2261 - The FF/Latch <counter_comp_0> in Unit <RXCTRL> is equivalent to the following 6 FFs/Latches, which will be removed : <counter_comp_5> <counter_comp_6> <counter_comp_7> <counter_comp_8> <counter_comp_9> <counter_comp_10> 
INFO:Xst:2261 - The FF/Latch <s_EB_TX_HDR_EB_MAGIC_4> in Unit <EB> is equivalent to the following 14 FFs/Latches, which will be removed : <s_EB_TX_HDR_EB_MAGIC_7> <s_EB_TX_HDR_EB_MAGIC_8> <s_EB_TX_HDR_EB_MAGIC_12> <s_EB_TX_HDR_EB_MAGIC_13> <s_EB_TX_HDR_EB_MAGIC_15> <s_EB_TX_HDR_VER_1> <s_EB_TX_HDR_VER_2> <s_EB_TX_HDR_VER_3> <s_EB_TX_HDR_ADDR_SIZE_0> <s_EB_TX_HDR_ADDR_SIZE_1> <s_EB_TX_HDR_ADDR_SIZE_3> <s_EB_TX_HDR_PORT_SIZE_0> <s_EB_TX_HDR_PORT_SIZE_1> <s_EB_TX_HDR_PORT_SIZE_3> 
INFO:Xst:2261 - The FF/Latch <s_EB_TX_HDR_EB_MAGIC_0> in Unit <EB> is equivalent to the following 12 FFs/Latches, which will be removed : <s_EB_TX_HDR_EB_MAGIC_1> <s_EB_TX_HDR_EB_MAGIC_2> <s_EB_TX_HDR_EB_MAGIC_3> <s_EB_TX_HDR_EB_MAGIC_5> <s_EB_TX_HDR_EB_MAGIC_6> <s_EB_TX_HDR_EB_MAGIC_9> <s_EB_TX_HDR_EB_MAGIC_10> <s_EB_TX_HDR_EB_MAGIC_11> <s_EB_TX_HDR_EB_MAGIC_14> <s_EB_TX_HDR_VER_0> <s_EB_TX_HDR_ADDR_SIZE_2> <s_EB_TX_HDR_PORT_SIZE_2> 
INFO:Xst:2261 - The FF/Latch <sh_chk_en> in Unit <TXCTRL> is equivalent to the following FF/Latch, which will be removed : <calc_chk_en> 
INFO:Xst:2261 - The FF/Latch <s_ETH_end_2> in Unit <TXCTRL> is equivalent to the following FF/Latch, which will be removed : <s_ETH_end_3> 
INFO:Xst:2261 - The FF/Latch <s_src_padding_o_dat_1> in Unit <TXCTRL> is equivalent to the following 7 FFs/Latches, which will be removed : <s_src_padding_o_dat_2> <s_src_padding_o_dat_3> <s_src_padding_o_dat_5> <s_src_padding_o_dat_8> <s_src_padding_o_dat_10> <s_src_padding_o_dat_13> <s_src_padding_o_dat_14> 
INFO:Xst:2261 - The FF/Latch <s_ETH_end_0> in Unit <TXCTRL> is equivalent to the following 2 FFs/Latches, which will be removed : <s_ETH_end_1> <s_ETH_end_4> 
INFO:Xst:2261 - The FF/Latch <ETH_TX_TYP_11> in Unit <TXCTRL> is equivalent to the following 7 FFs/Latches, which will be removed : <IPV4_TX_VER_2> <IPV4_TX_IHL_0> <IPV4_TX_IHL_2> <IPV4_TX_FLG_1> <IPV4_TX_TTL_6> <IPV4_TX_PRO_0> <IPV4_TX_PRO_4> 
INFO:Xst:2261 - The FF/Latch <ETH_TX_TYP_0> in Unit <TXCTRL> is equivalent to the following 34 FFs/Latches, which will be removed : <ETH_TX_TYP_1> <ETH_TX_TYP_2> <ETH_TX_TYP_3> <ETH_TX_TYP_4> <ETH_TX_TYP_5> <ETH_TX_TYP_6> <ETH_TX_TYP_7> <ETH_TX_TYP_8> <ETH_TX_TYP_9> <ETH_TX_TYP_10> <ETH_TX_TYP_12> <ETH_TX_TYP_13> <ETH_TX_TYP_14> <ETH_TX_TYP_15> <IPV4_TX_VER_0> <IPV4_TX_VER_1> <IPV4_TX_VER_3> <IPV4_TX_IHL_1> <IPV4_TX_IHL_3> <IPV4_TX_FLG_0> <IPV4_TX_FLG_2> <IPV4_TX_TTL_0> <IPV4_TX_TTL_1> <IPV4_TX_TTL_2> <IPV4_TX_TTL_3> <IPV4_TX_TTL_4> <IPV4_TX_TTL_5> <IPV4_TX_TTL_7> <IPV4_TX_PRO_1> <IPV4_TX_PRO_2> <IPV4_TX_PRO_3> <IPV4_TX_PRO_5> <IPV4_TX_PRO_6> <IPV4_TX_PRO_7> 
INFO:Xst:2261 - The FF/Latch <s_src_padding_o_dat_0> in Unit <TXCTRL> is equivalent to the following 7 FFs/Latches, which will be removed : <s_src_padding_o_dat_4> <s_src_padding_o_dat_6> <s_src_padding_o_dat_7> <s_src_padding_o_dat_9> <s_src_padding_o_dat_11> <s_src_padding_o_dat_12> <s_src_padding_o_dat_15> 
INFO:Xst:2261 - The FF/Latch <i_dat_o_0> in Unit <instruction_unit> is equivalent to the following 3 FFs/Latches, which will be removed : <i_dat_o_8> <i_dat_o_16> <i_dat_o_24> 
INFO:Xst:2261 - The FF/Latch <i_dat_o_1> in Unit <instruction_unit> is equivalent to the following 3 FFs/Latches, which will be removed : <i_dat_o_9> <i_dat_o_17> <i_dat_o_25> 
INFO:Xst:2261 - The FF/Latch <i_dat_o_2> in Unit <instruction_unit> is equivalent to the following 3 FFs/Latches, which will be removed : <i_dat_o_10> <i_dat_o_18> <i_dat_o_26> 
INFO:Xst:2261 - The FF/Latch <i_dat_o_3> in Unit <instruction_unit> is equivalent to the following 3 FFs/Latches, which will be removed : <i_dat_o_11> <i_dat_o_19> <i_dat_o_27> 
INFO:Xst:2261 - The FF/Latch <i_dat_o_4> in Unit <instruction_unit> is equivalent to the following 3 FFs/Latches, which will be removed : <i_dat_o_12> <i_dat_o_20> <i_dat_o_28> 
INFO:Xst:2261 - The FF/Latch <i_dat_o_5> in Unit <instruction_unit> is equivalent to the following 3 FFs/Latches, which will be removed : <i_dat_o_13> <i_dat_o_21> <i_dat_o_29> 
INFO:Xst:2261 - The FF/Latch <i_dat_o_6> in Unit <instruction_unit> is equivalent to the following 3 FFs/Latches, which will be removed : <i_dat_o_14> <i_dat_o_22> <i_dat_o_30> 
INFO:Xst:2261 - The FF/Latch <i_dat_o_7> in Unit <instruction_unit> is equivalent to the following 3 FFs/Latches, which will be removed : <i_dat_o_15> <i_dat_o_23> <i_dat_o_31> 
WARNING:Xst:1710 - FF/Latch <rx_ram_o_we> (without init value) has a constant value of 0 in block <cmp_xwb_ethmac_adapter>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <rx_ram_o_dat_0> (without init value) has a constant value of 0 in block <cmp_xwb_ethmac_adapter>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <rx_ram_o_dat_1> (without init value) has a constant value of 0 in block <cmp_xwb_ethmac_adapter>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <rx_ram_o_dat_2> (without init value) has a constant value of 0 in block <cmp_xwb_ethmac_adapter>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <rx_ram_o_dat_3> (without init value) has a constant value of 0 in block <cmp_xwb_ethmac_adapter>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <rx_ram_o_dat_4> (without init value) has a constant value of 0 in block <cmp_xwb_ethmac_adapter>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <rx_ram_o_dat_5> (without init value) has a constant value of 0 in block <cmp_xwb_ethmac_adapter>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <rx_ram_o_dat_6> (without init value) has a constant value of 0 in block <cmp_xwb_ethmac_adapter>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <rx_ram_o_dat_7> (without init value) has a constant value of 0 in block <cmp_xwb_ethmac_adapter>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <rx_ram_o_dat_8> (without init value) has a constant value of 0 in block <cmp_xwb_ethmac_adapter>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <rx_ram_o_dat_9> (without init value) has a constant value of 0 in block <cmp_xwb_ethmac_adapter>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <rx_ram_o_dat_10> (without init value) has a constant value of 0 in block <cmp_xwb_ethmac_adapter>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <rx_ram_o_dat_11> (without init value) has a constant value of 0 in block <cmp_xwb_ethmac_adapter>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <rx_ram_o_dat_12> (without init value) has a constant value of 0 in block <cmp_xwb_ethmac_adapter>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <rx_ram_o_dat_13> (without init value) has a constant value of 0 in block <cmp_xwb_ethmac_adapter>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <rx_ram_o_dat_14> (without init value) has a constant value of 0 in block <cmp_xwb_ethmac_adapter>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <rx_ram_o_dat_31> (without init value) has a constant value of 0 in block <cmp_xwb_ethmac_adapter>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <rx_ram_o_dat_30> (without init value) has a constant value of 0 in block <cmp_xwb_ethmac_adapter>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <rx_ram_o_dat_29> (without init value) has a constant value of 0 in block <cmp_xwb_ethmac_adapter>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <rx_ram_o_dat_28> (without init value) has a constant value of 0 in block <cmp_xwb_ethmac_adapter>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <rx_ram_o_dat_27> (without init value) has a constant value of 0 in block <cmp_xwb_ethmac_adapter>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <rx_ram_o_dat_26> (without init value) has a constant value of 0 in block <cmp_xwb_ethmac_adapter>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <rx_ram_o_dat_25> (without init value) has a constant value of 0 in block <cmp_xwb_ethmac_adapter>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <rx_ram_o_dat_24> (without init value) has a constant value of 0 in block <cmp_xwb_ethmac_adapter>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <rx_ram_o_dat_23> (without init value) has a constant value of 0 in block <cmp_xwb_ethmac_adapter>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <rx_ram_o_dat_22> (without init value) has a constant value of 0 in block <cmp_xwb_ethmac_adapter>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <rx_ram_o_dat_21> (without init value) has a constant value of 0 in block <cmp_xwb_ethmac_adapter>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <rx_ram_o_dat_20> (without init value) has a constant value of 0 in block <cmp_xwb_ethmac_adapter>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <rx_ram_o_dat_19> (without init value) has a constant value of 0 in block <cmp_xwb_ethmac_adapter>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <rx_ram_o_dat_18> (without init value) has a constant value of 0 in block <cmp_xwb_ethmac_adapter>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <rx_ram_o_dat_17> (without init value) has a constant value of 0 in block <cmp_xwb_ethmac_adapter>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <rx_ram_o_dat_16> (without init value) has a constant value of 0 in block <cmp_xwb_ethmac_adapter>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <rx_ram_o_dat_15> (without init value) has a constant value of 0 in block <cmp_xwb_ethmac_adapter>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ack_sreg_8> (without init value) has a constant value of 0 in block <U_WB_SLAVE>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <sipo_clr> (without init value) has a constant value of 0 in block <RXCTRL>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <snk_hdr_fsm_stall_0001> (without init value) has a constant value of 0 in block <RXCTRL>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <counter_comp_0> has a constant value of 0 in block <RXCTRL>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <eb_slave_o_err> (without init value) has a constant value of 0 in block <cfg_space>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <eb_slave_o_stall> (without init value) has a constant value of 0 in block <cfg_space>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <local_slave_o_err> (without init value) has a constant value of 0 in block <cfg_space>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <s_EB_TX_CUR_CYCLE_BCA_CFG> (without init value) has a constant value of 0 in block <EB>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <s_EB_TX_CUR_CYCLE_RCA_CFG> (without init value) has a constant value of 0 in block <EB>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <s_EB_TX_CUR_CYCLE_RESERVED1> (without init value) has a constant value of 0 in block <EB>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <s_EB_TX_CUR_CYCLE_RESERVED2> (without init value) has a constant value of 0 in block <EB>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <s_EB_TX_CUR_CYCLE_UNUSED_0> (without init value) has a constant value of 0 in block <EB>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <s_EB_TX_CUR_CYCLE_UNUSED_1> (without init value) has a constant value of 0 in block <EB>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <wb_slave_o_stall> (without init value) has a constant value of 0 in block <cmp_xwb_ethmac_adapter>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <wb_slave_o_rty> (without init value) has a constant value of 0 in block <cmp_xwb_ethmac_adapter>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <wb_slave_o_err> (without init value) has a constant value of 0 in block <cmp_xwb_ethmac_adapter>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <s_ETH_end_2> has a constant value of 1 in block <TXCTRL>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <s_ETH_end_0> has a constant value of 0 in block <TXCTRL>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <s_src_padding_o_dat_1> (without init value) has a constant value of 0 in block <TXCTRL>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <s_src_padding_o_dat_0> (without init value) has a constant value of 1 in block <TXCTRL>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ETH_TX_TYP_11> (without init value) has a constant value of 1 in block <TXCTRL>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ETH_TX_TYP_0> (without init value) has a constant value of 0 in block <TXCTRL>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <s_EB_TX_HDR_EB_MAGIC_4> (without init value) has a constant value of 0 in block <EB>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <s_EB_TX_HDR_EB_MAGIC_0> (without init value) has a constant value of 1 in block <EB>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <s_EB_TX_CUR_CYCLE_UNUSED_3> (without init value) has a constant value of 0 in block <EB>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <s_EB_TX_CUR_CYCLE_UNUSED_2> (without init value) has a constant value of 0 in block <EB>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_7> (without init value) has a constant value of 0 in block <U_WB_SLAVE>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_6> (without init value) has a constant value of 0 in block <U_WB_SLAVE>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_5> (without init value) has a constant value of 0 in block <U_WB_SLAVE>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_4> (without init value) has a constant value of 0 in block <U_WB_SLAVE>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_3> (without init value) has a constant value of 0 in block <U_WB_SLAVE>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_2> (without init value) has a constant value of 0 in block <U_WB_SLAVE>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_1> (without init value) has a constant value of 0 in block <U_WB_SLAVE>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:2677 - Node <uart_bcr_17> of sequential type is unconnected in block <U_Wrapped_UART>.
WARNING:Xst:2677 - Node <uart_bcr_18> of sequential type is unconnected in block <U_Wrapped_UART>.
WARNING:Xst:2677 - Node <uart_bcr_19> of sequential type is unconnected in block <U_Wrapped_UART>.
WARNING:Xst:2677 - Node <uart_bcr_20> of sequential type is unconnected in block <U_Wrapped_UART>.
WARNING:Xst:2677 - Node <uart_bcr_21> of sequential type is unconnected in block <U_Wrapped_UART>.
WARNING:Xst:2677 - Node <uart_bcr_22> of sequential type is unconnected in block <U_Wrapped_UART>.
WARNING:Xst:2677 - Node <uart_bcr_23> of sequential type is unconnected in block <U_Wrapped_UART>.
WARNING:Xst:2677 - Node <uart_bcr_24> of sequential type is unconnected in block <U_Wrapped_UART>.
WARNING:Xst:2677 - Node <uart_bcr_25> of sequential type is unconnected in block <U_Wrapped_UART>.
WARNING:Xst:2677 - Node <uart_bcr_26> of sequential type is unconnected in block <U_Wrapped_UART>.
WARNING:Xst:2677 - Node <uart_bcr_27> of sequential type is unconnected in block <U_Wrapped_UART>.
WARNING:Xst:2677 - Node <uart_bcr_28> of sequential type is unconnected in block <U_Wrapped_UART>.
WARNING:Xst:2677 - Node <uart_bcr_29> of sequential type is unconnected in block <U_Wrapped_UART>.
WARNING:Xst:2677 - Node <uart_bcr_30> of sequential type is unconnected in block <U_Wrapped_UART>.
WARNING:Xst:2677 - Node <uart_bcr_31> of sequential type is unconnected in block <U_Wrapped_UART>.
WARNING:Xst:2677 - Node <sh_reg_144> of sequential type is unconnected in block <Shift_in>.
WARNING:Xst:2677 - Node <sh_reg_145> of sequential type is unconnected in block <Shift_in>.
WARNING:Xst:2677 - Node <sh_reg_146> of sequential type is unconnected in block <Shift_in>.
WARNING:Xst:2677 - Node <sh_reg_147> of sequential type is unconnected in block <Shift_in>.
WARNING:Xst:2677 - Node <sh_reg_148> of sequential type is unconnected in block <Shift_in>.
WARNING:Xst:2677 - Node <sh_reg_149> of sequential type is unconnected in block <Shift_in>.
WARNING:Xst:2677 - Node <sh_reg_150> of sequential type is unconnected in block <Shift_in>.
WARNING:Xst:2677 - Node <sh_reg_151> of sequential type is unconnected in block <Shift_in>.
WARNING:Xst:2677 - Node <sh_reg_156> of sequential type is unconnected in block <Shift_in>.
WARNING:Xst:2677 - Node <sh_reg_157> of sequential type is unconnected in block <Shift_in>.
WARNING:Xst:2677 - Node <sh_reg_158> of sequential type is unconnected in block <Shift_in>.
WARNING:Xst:2677 - Node <sh_reg_159> of sequential type is unconnected in block <Shift_in>.
WARNING:Xst:2677 - Node <ngwrdrst.grst.wr_rst_reg_0> of sequential type is unconnected in block <rstblk>.
WARNING:Xst:2677 - Node <ngwrdrst.grst.rd_rst_reg_1> of sequential type is unconnected in block <rstblk>.
WARNING:Xst:2677 - Node <ngwrdrst.grst.wr_rst_reg_0> of sequential type is unconnected in block <rstblk>.
WARNING:Xst:2677 - Node <ngwrdrst.grst.rd_rst_reg_1> of sequential type is unconnected in block <rstblk>.
WARNING:Xst:2677 - Node <s_EB_RX_HDR_ADDR_SIZE_0> of sequential type is unconnected in block <EB>.
WARNING:Xst:2677 - Node <s_EB_RX_HDR_ADDR_SIZE_1> of sequential type is unconnected in block <EB>.
WARNING:Xst:2677 - Node <s_EB_RX_HDR_ADDR_SIZE_3> of sequential type is unconnected in block <EB>.
WARNING:Xst:2677 - Node <s_EB_RX_HDR_PORT_SIZE_0> of sequential type is unconnected in block <EB>.
WARNING:Xst:2677 - Node <s_EB_RX_HDR_PORT_SIZE_1> of sequential type is unconnected in block <EB>.
WARNING:Xst:2677 - Node <s_EB_RX_HDR_PORT_SIZE_3> of sequential type is unconnected in block <EB>.
WARNING:Xst:2404 -  FFs/Latches <ack_sreg<8:1>> (without init value) have a constant value of 0 in block <simple_uart_wb>.
WARNING:Xst:2404 -  FFs/Latches <s_EB_TX_HDR_EB_MAGIC<15:15>> (without init value) have a constant value of 0 in block <eb_main_fsm>.
WARNING:Xst:2404 -  FFs/Latches <s_EB_TX_HDR_ADDR_SIZE<3:3>> (without init value) have a constant value of 0 in block <eb_main_fsm>.
WARNING:Xst:2404 -  FFs/Latches <s_EB_TX_HDR_VER<3:1>> (without init value) have a constant value of 0 in block <eb_main_fsm>.
WARNING:Xst:2404 -  FFs/Latches <s_EB_TX_HDR_PORT_SIZE<3:3>> (without init value) have a constant value of 0 in block <eb_main_fsm>.
WARNING:Xst:2404 -  FFs/Latches <ETH_TX_TYP<15:12>> (without init value) have a constant value of 0 in block <EB_TX_CTRL>.
WARNING:Xst:2404 -  FFs/Latches <IPV4_TX_VER<3:3>> (without init value) have a constant value of 0 in block <EB_TX_CTRL>.
WARNING:Xst:2404 -  FFs/Latches <IPV4_TX_IHL<3:3>> (without init value) have a constant value of 0 in block <EB_TX_CTRL>.
WARNING:Xst:2404 -  FFs/Latches <IPV4_TX_FLG<2:2>> (without init value) have a constant value of 0 in block <EB_TX_CTRL>.
WARNING:Xst:2404 -  FFs/Latches <IPV4_TX_TTL<7:7>> (without init value) have a constant value of 0 in block <EB_TX_CTRL>.
WARNING:Xst:2404 -  FFs/Latches <IPV4_TX_PRO<7:5>> (without init value) have a constant value of 0 in block <EB_TX_CTRL>.

Synthesizing (advanced) Unit <EB_RX_CTRL>.
The following registers are absorbed into counter <s_timeout_cnt>: 1 register on signal <s_timeout_cnt>.
The following registers are absorbed into accumulator <byte_count>: 1 register on signal <byte_count>.
Unit <EB_RX_CTRL> synthesized (advanced).

Synthesizing (advanced) Unit <EB_TX_CTRL>.
The following registers are absorbed into counter <s_timeout_cnt>: 1 register on signal <s_timeout_cnt>.
The following registers are absorbed into accumulator <byte_count>: 1 register on signal <byte_count>.
Unit <EB_TX_CTRL> synthesized (advanced).

Synthesizing (advanced) Unit <eb_main_fsm>.
The following registers are absorbed into counter <s_timeout_cnt>: 1 register on signal <s_timeout_cnt>.
The following registers are absorbed into counter <s_EB_probe_wait_cnt>: 1 register on signal <s_EB_probe_wait_cnt>.
The following registers are absorbed into counter <s_EB_TX_CUR_CYCLE_WR_CNT>: 1 register on signal <s_EB_TX_CUR_CYCLE_WR_CNT>.
The following registers are absorbed into counter <s_EB_RX_CUR_CYCLE_WR_CNT>: 1 register on signal <s_EB_RX_CUR_CYCLE_WR_CNT>.
The following registers are absorbed into counter <s_EB_RX_CUR_CYCLE_RD_CNT>: 1 register on signal <s_EB_RX_CUR_CYCLE_RD_CNT>.
Unit <eb_main_fsm> synthesized (advanced).

Synthesizing (advanced) Unit <eth_fifo>.
The following registers are absorbed into counter <cnt>: 1 register on signal <cnt>.
The following registers are absorbed into counter <raddr>: 1 register on signal <raddr>.
The following registers are absorbed into counter <waddr>: 1 register on signal <waddr>.
Unit <eth_fifo> synthesized (advanced).

Synthesizing (advanced) Unit <eth_receivecontrol>.
The following registers are absorbed into counter <PauseTimer>: 1 register on signal <PauseTimer>.
The following registers are absorbed into counter <DlyCrcCnt>: 1 register on signal <DlyCrcCnt>.
The following registers are absorbed into counter <ByteCnt>: 1 register on signal <ByteCnt>.
The following registers are absorbed into counter <SlotTimer>: 1 register on signal <SlotTimer>.
Unit <eth_receivecontrol> synthesized (advanced).

Synthesizing (advanced) Unit <eth_rxcounters>.
The following registers are absorbed into counter <IFGCounter>: 1 register on signal <IFGCounter>.
The following registers are absorbed into counter <ByteCnt>: 1 register on signal <ByteCnt>.
Unit <eth_rxcounters> synthesized (advanced).

Synthesizing (advanced) Unit <eth_spram_256x32>.
INFO:Xst:3226 - The RAM <Mram_mem> will be implemented as a BLOCK RAM, absorbing the following register(s): <raddr>
    -----------------------------------------------------------------------
    | ram_type           | Block                               |          |
    -----------------------------------------------------------------------
    | Port A                                                              |
    |     aspect ratio   | 256-word x 32-bit                   |          |
    |     mode           | write-first                         |          |
    |     clkA           | connected to signal <clk>           | rise     |
    |     weA            | connected to signal <we>            | high     |
    |     addrA          | connected to signal <addr>          |          |
    |     diA            | connected to signal <di>            |          |
    |     doA            | connected to internal node          |          |
    -----------------------------------------------------------------------
    | optimization       | speed                               |          |
    -----------------------------------------------------------------------
Unit <eth_spram_256x32> synthesized (advanced).

Synthesizing (advanced) Unit <eth_transmitcontrol>.
The following registers are absorbed into accumulator <ByteCnt>: 1 register on signal <ByteCnt>.
The following registers are absorbed into counter <DlyCrcCnt>: 1 register on signal <DlyCrcCnt>.
Unit <eth_transmitcontrol> synthesized (advanced).

Synthesizing (advanced) Unit <eth_txcounters>.
The following registers are absorbed into counter <ByteCnt>: 1 register on signal <ByteCnt>.
The following registers are absorbed into counter <NibCnt>: 1 register on signal <NibCnt>.
The following registers are absorbed into counter <DlyCrcCnt>: 1 register on signal <DlyCrcCnt>.
Unit <eth_txcounters> synthesized (advanced).

Synthesizing (advanced) Unit <eth_txethmac>.
The following registers are absorbed into counter <RetryCnt>: 1 register on signal <RetryCnt>.
Unit <eth_txethmac> synthesized (advanced).

Synthesizing (advanced) Unit <eth_wishbone>.
The following registers are absorbed into counter <RxValidBytes>: 1 register on signal <RxValidBytes>.
The following registers are absorbed into counter <TxPointerMSB>: 1 register on signal <TxPointerMSB>.
The following registers are absorbed into counter <RxPointerMSB>: 1 register on signal <RxPointerMSB>.
INFO:Xst:3226 - The RAM <rx_fifo1/Mram_fifo> will be implemented as a BLOCK RAM, absorbing the following register(s): <rx_fifo1/raddr_reg>
    -----------------------------------------------------------------------
    | ram_type           | Block                               |          |
    -----------------------------------------------------------------------
    | Port A                                                              |
    |     aspect ratio   | 256-word x 32-bit                   |          |
    |     mode           | read-first                          |          |
    |     clkA           | connected to signal <WB_CLK_I>      | rise     |
    |     weA            | connected to internal node          | high     |
    |     addrA          | connected to signal <rx_fifo1/waddr> |          |
    |     diA            | connected to signal <RxDataLatched2> |          |
    -----------------------------------------------------------------------
    | optimization       | speed                               |          |
    -----------------------------------------------------------------------
    | Port B                                                              |
    |     aspect ratio   | 256-word x 32-bit                   |          |
    |     mode           | read-first                          |          |
    |     clkB           | connected to signal <WB_CLK_I>      | rise     |
    |     addrB          | connected to signal <rx_fifo1/raddr_reg[7]_raddr[7]_mux_26_OUT> |          |
    |     doB            | connected to signal <rx_fifo1_data_out> |          |
    -----------------------------------------------------------------------
    | optimization       | speed                               |          |
    -----------------------------------------------------------------------
INFO:Xst:3226 - The RAM <rx_fifo0/Mram_fifo> will be implemented as a BLOCK RAM, absorbing the following register(s): <rx_fifo0/raddr_reg>
    -----------------------------------------------------------------------
    | ram_type           | Block                               |          |
    -----------------------------------------------------------------------
    | Port A                                                              |
    |     aspect ratio   | 256-word x 32-bit                   |          |
    |     mode           | read-first                          |          |
    |     clkA           | connected to signal <WB_CLK_I>      | rise     |
    |     weA            | connected to internal node          | high     |
    |     addrA          | connected to signal <rx_fifo0/waddr> |          |
    |     diA            | connected to signal <RxDataLatched2> |          |
    -----------------------------------------------------------------------
    | optimization       | speed                               |          |
    -----------------------------------------------------------------------
    | Port B                                                              |
    |     aspect ratio   | 256-word x 32-bit                   |          |
    |     mode           | read-first                          |          |
    |     clkB           | connected to signal <WB_CLK_I>      | rise     |
    |     addrB          | connected to signal <rx_fifo0/raddr_reg[7]_raddr[7]_mux_26_OUT> |          |
    |     doB            | connected to signal <rx_fifo0_data_out> |          |
    -----------------------------------------------------------------------
    | optimization       | speed                               |          |
    -----------------------------------------------------------------------
INFO:Xst:3226 - The RAM <tx_fifo/Mram_fifo> will be implemented as a BLOCK RAM, absorbing the following register(s): <tx_fifo/raddr_reg>
    -----------------------------------------------------------------------
    | ram_type           | Block                               |          |
    -----------------------------------------------------------------------
    | Port A                                                              |
    |     aspect ratio   | 256-word x 32-bit                   |          |
    |     mode           | read-first                          |          |
    |     clkA           | connected to signal <WB_CLK_I>      | rise     |
    |     weA            | connected to internal node          | high     |
    |     addrA          | connected to signal <tx_fifo/waddr> |          |
    |     diA            | connected to signal <m_wb_dat_i>    |          |
    -----------------------------------------------------------------------
    | optimization       | speed                               |          |
    -----------------------------------------------------------------------
    | Port B                                                              |
    |     aspect ratio   | 256-word x 32-bit                   |          |
    |     mode           | read-first                          |          |
    |     clkB           | connected to signal <WB_CLK_I>      | rise     |
    |     addrB          | connected to signal <tx_fifo/raddr_reg[7]_raddr[7]_mux_26_OUT> |          |
    |     doB            | connected to signal <TxData_wb>     |          |
    -----------------------------------------------------------------------
    | optimization       | speed                               |          |
    -----------------------------------------------------------------------
INFO:Xst:3218 - HDL ADVISOR - The RAM <Mram_TxPointerLSB[1]_GND_180_o_wide_mux_213_OUT> will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
    -----------------------------------------------------------------------
    | ram_type           | Distributed                         |          |
    -----------------------------------------------------------------------
    | Port A                                                              |
    |     aspect ratio   | 4-word x 2-bit                      |          |
    |     weA            | connected to signal <GND>           | high     |
    |     addrA          | connected to signal <TxPointerLSB>  |          |
    |     diA            | connected to signal <GND>           |          |
    |     doA            | connected to internal node          |          |
    -----------------------------------------------------------------------
INFO:Xst:3218 - HDL ADVISOR - The RAM <Mram__n1569> will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
    -----------------------------------------------------------------------
    | ram_type           | Distributed                         |          |
    -----------------------------------------------------------------------
    | Port A                                                              |
    |     aspect ratio   | 4-word x 6-bit                      |          |
    |     weA            | connected to signal <GND>           | high     |
    |     addrA          | connected to signal <RxPointerLSB_rst> |          |
    |     diA            | connected to signal <GND>           |          |
    |     doA            | connected to internal node          |          |
    -----------------------------------------------------------------------
Unit <eth_wishbone> synthesized (advanced).

Synthesizing (advanced) Unit <gc_extend_pulse>.
The following registers are absorbed into counter <cntr>: 1 register on signal <cntr>.
Unit <gc_extend_pulse> synthesized (advanced).

Synthesizing (advanced) Unit <gc_reset>.
The following registers are absorbed into counter <locked_count>: 1 register on signal <locked_count>.
Unit <gc_reset> synthesized (advanced).

Synthesizing (advanced) Unit <generic_dpram_sameclock_1>.
INFO:Xst:3226 - The RAM <Mram_ram> will be implemented as a BLOCK RAM, absorbing the following register(s): <qa_o> <qb_o>
    -----------------------------------------------------------------------
    | ram_type           | Block                               |          |
    -----------------------------------------------------------------------
    | Port A                                                              |
    |     aspect ratio   | 32768-word x 32-bit                 |          |
    |     mode           | read-first                          |          |
    |     clkA           | connected to signal <clk_i>         | rise     |
    |     weA<3>         | connected to signal <s_we_a<3>>     | high     |
    |     weA<2>         | connected to signal <s_we_a<2>>     | high     |
    |     weA<1>         | connected to signal <s_we_a<1>>     | high     |
    |     weA<0>         | connected to signal <s_we_a<0>>     | high     |
    |     addrA          | connected to signal <aa_i>          |          |
    |     diA            | connected to signal <da_i>          |          |
    |     doA            | connected to signal <qa_o>          |          |
    -----------------------------------------------------------------------
    | optimization       | speed                               |          |
    -----------------------------------------------------------------------
    | Port B                                                              |
    |     aspect ratio   | 32768-word x 32-bit                 |          |
    |     mode           | read-first                          |          |
    |     clkB           | connected to signal <clk_i>         | rise     |
    |     weB<3>         | connected to signal <s_we_b<3>>     | high     |
    |     weB<2>         | connected to signal <s_we_b<2>>     | high     |
    |     weB<1>         | connected to signal <s_we_b<1>>     | high     |
    |     weB<0>         | connected to signal <s_we_b<0>>     | high     |
    |     addrB          | connected to signal <ab_i>          |          |
    |     diB            | connected to signal <db_i>          |          |
    |     doB            | connected to signal <qb_o>          |          |
    -----------------------------------------------------------------------
    | optimization       | speed                               |          |
    -----------------------------------------------------------------------
Unit <generic_dpram_sameclock_1> synthesized (advanced).

Synthesizing (advanced) Unit <generic_dpram_sameclock_2>.
INFO:Xst:3226 - The RAM <Mram_ram> will be implemented as a BLOCK RAM, absorbing the following register(s): <qa_o> <qb_o>
    -----------------------------------------------------------------------
    | ram_type           | Block                               |          |
    -----------------------------------------------------------------------
    | Port A                                                              |
    |     aspect ratio   | 16384-word x 32-bit                 |          |
    |     mode           | read-first                          |          |
    |     clkA           | connected to signal <clk_i>         | rise     |
    |     weA<3>         | connected to signal <s_we_a<3>>     | high     |
    |     weA<2>         | connected to signal <s_we_a<2>>     | high     |
    |     weA<1>         | connected to signal <s_we_a<1>>     | high     |
    |     weA<0>         | connected to signal <s_we_a<0>>     | high     |
    |     addrA          | connected to signal <aa_i>          |          |
    |     diA            | connected to signal <da_i>          |          |
    |     doA            | connected to signal <qa_o>          |          |
    -----------------------------------------------------------------------
    | optimization       | speed                               |          |
    -----------------------------------------------------------------------
    | Port B                                                              |
    |     aspect ratio   | 16384-word x 32-bit                 |          |
    |     mode           | read-first                          |          |
    |     clkB           | connected to signal <clk_i>         | rise     |
    |     weB<3>         | connected to signal <s_we_b<3>>     | high     |
    |     weB<2>         | connected to signal <s_we_b<2>>     | high     |
    |     weB<1>         | connected to signal <s_we_b<1>>     | high     |
    |     weB<0>         | connected to signal <s_we_b<0>>     | high     |
    |     addrB          | connected to signal <ab_i>          |          |
    |     diB            | connected to signal <db_i>          |          |
    |     doB            | connected to signal <qb_o>          |          |
    -----------------------------------------------------------------------
    | optimization       | speed                               |          |
    -----------------------------------------------------------------------
Unit <generic_dpram_sameclock_2> synthesized (advanced).

Synthesizing (advanced) Unit <lm32_cpu_medium_icache_debug>.
INFO:Xst:3226 - The RAM <reg_0/Mram_ram> will be implemented as a BLOCK RAM, absorbing the following register(s): <reg_0/raddr_r>
    -----------------------------------------------------------------------
    | ram_type           | Block                               |          |
    -----------------------------------------------------------------------
    | Port A                                                              |
    |     aspect ratio   | 32-word x 32-bit                    |          |
    |     mode           | read-first                          |          |
    |     clkA           | connected to signal <clk_i>         | rise     |
    |     weA            | connected to signal <reg_write_enable_q_w> | high     |
    |     addrA          | connected to signal <write_idx_w>   |          |
    |     diA            | connected to signal <w_result>      |          |
    -----------------------------------------------------------------------
    | optimization       | speed                               |          |
    -----------------------------------------------------------------------
    | Port B                                                              |
    |     aspect ratio   | 32-word x 32-bit                    |          |
    |     mode           | read-first                          |          |
    |     clkB           | connected to signal <clk_i>         | rise     |
    |     addrB          | connected to signal <instruction_f<25:21>> |          |
    |     doB            | connected to signal <regfile_data_0> |          |
    -----------------------------------------------------------------------
    | optimization       | speed                               |          |
    -----------------------------------------------------------------------
INFO:Xst:3226 - The RAM <reg_1/Mram_ram> will be implemented as a BLOCK RAM, absorbing the following register(s): <reg_1/raddr_r>
    -----------------------------------------------------------------------
    | ram_type           | Block                               |          |
    -----------------------------------------------------------------------
    | Port A                                                              |
    |     aspect ratio   | 32-word x 32-bit                    |          |
    |     mode           | read-first                          |          |
    |     clkA           | connected to signal <clk_i>         | rise     |
    |     weA            | connected to signal <reg_write_enable_q_w> | high     |
    |     addrA          | connected to signal <write_idx_w>   |          |
    |     diA            | connected to signal <w_result>      |          |
    -----------------------------------------------------------------------
    | optimization       | speed                               |          |
    -----------------------------------------------------------------------
    | Port B                                                              |
    |     aspect ratio   | 32-word x 32-bit                    |          |
    |     mode           | read-first                          |          |
    |     clkB           | connected to signal <clk_i>         | rise     |
    |     addrB          | connected to signal <instruction_f<20:16>> |          |
    |     doB            | connected to signal <regfile_data_1> |          |
    -----------------------------------------------------------------------
    | optimization       | speed                               |          |
    -----------------------------------------------------------------------
Unit <lm32_cpu_medium_icache_debug> synthesized (advanced).

Synthesizing (advanced) Unit <lm32_icache_medium_icache_debug>.
The following registers are absorbed into counter <flush_set>: 1 register on signal <flush_set>.
INFO:Xst:3226 - The RAM <memories[0].way_0_data_ram/Mram_mem> will be implemented as a BLOCK RAM, absorbing the following register(s): <memories[0].way_0_data_ram/ra>
    -----------------------------------------------------------------------
    | ram_type           | Block                               |          |
    -----------------------------------------------------------------------
    | Port A                                                              |
    |     aspect ratio   | 1024-word x 32-bit                  |          |
    |     mode           | read-first                          |          |
    |     clkA           | connected to signal <clk_i>         | rise     |
    |     weA            | connected to signal <way_mem_we>    | high     |
    |     addrA          | connected to signal <(refill_address<11:4>,refill_offset)> |          |
    |     diA            | connected to signal <refill_data>   |          |
    -----------------------------------------------------------------------
    | optimization       | speed                               |          |
    -----------------------------------------------------------------------
    | Port B                                                              |
    |     aspect ratio   | 1024-word x 32-bit                  |          |
    |     mode           | write-first                         |          |
    |     clkB           | connected to signal <clk_i>         | rise     |
    |     addrB          | connected to signal <address_a>     |          |
    |     doB            | connected to signal <way_data<0>>   |          |
    -----------------------------------------------------------------------
    | optimization       | speed                               |          |
    -----------------------------------------------------------------------
Unit <lm32_icache_medium_icache_debug> synthesized (advanced).

Synthesizing (advanced) Unit <lm32_multiplier>.
	Multiplier <Mmult_n0056> in block <lm32_multiplier> and adder/subtractor <Madd_c1[15]_e1[15]_add_17_OUT> in block <lm32_multiplier> are combined into a MAC<Maddsub_n0056>.
	The following registers are also absorbed by the MAC: <e1> in block <lm32_multiplier>, <result1,result0> in block <lm32_multiplier>.
	Multiplier <Mmult_n0055> in block <lm32_multiplier> and adder/subtractor <Madd_n0077> in block <lm32_multiplier> are combined into a MAC<Maddsub_n0055>.
	The following registers are also absorbed by the MAC: <d1> in block <lm32_multiplier>.
	Found pipelined multiplier on signal <a0[15]_b0[15]_MuLt_9_OUT>:
		- 1 pipeline level(s) found in a register connected to the multiplier macro output.
		Pushing register(s) into the multiplier macro.
INFO:Xst:2385 - HDL ADVISOR - You can improve the performance of the multiplier Mmult_a0[15]_b0[15]_MuLt_9_OUT by adding 1 register level(s).
Unit <lm32_multiplier> synthesized (advanced).

Synthesizing (advanced) Unit <lm32_ram_2>.
INFO:Xst:3226 - The RAM <Mram_mem> will be implemented as a BLOCK RAM, absorbing the following register(s): <ra>
    -----------------------------------------------------------------------
    | ram_type           | Block                               |          |
    -----------------------------------------------------------------------
    | Port A                                                              |
    |     aspect ratio   | 256-word x 20-bit                   |          |
    |     mode           | write-first                         |          |
    |     clkA           | connected to signal <write_clk>     | rise     |
    |     weA            | connected to signal <write_enable>  | high     |
    |     addrA          | connected to signal <write_address> |          |
    |     diA            | connected to signal <write_data>    |          |
    -----------------------------------------------------------------------
    | optimization       | speed                               |          |
    -----------------------------------------------------------------------
    | Port B                                                              |
    |     aspect ratio   | 256-word x 20-bit                   |          |
    |     mode           | write-first                         |          |
    |     clkB           | connected to signal <read_clk>      | rise     |
    |     addrB          | connected to signal <read_address>  |          |
    |     doB            | connected to internal node          |          |
    -----------------------------------------------------------------------
    | optimization       | speed                               |          |
    -----------------------------------------------------------------------
Unit <lm32_ram_2> synthesized (advanced).

Synthesizing (advanced) Unit <piso_flag_1>.
The following registers are absorbed into counter <sh_cnt>: 1 register on signal <sh_cnt>.
Unit <piso_flag_1> synthesized (advanced).

Synthesizing (advanced) Unit <piso_flag_2>.
The following registers are absorbed into counter <sh_cnt>: 1 register on signal <sh_cnt>.
Unit <piso_flag_2> synthesized (advanced).

Synthesizing (advanced) Unit <piso_flag_3>.
The following registers are absorbed into counter <sh_cnt>: 1 register on signal <sh_cnt>.
Unit <piso_flag_3> synthesized (advanced).

Synthesizing (advanced) Unit <sdb_rom>.
INFO:Xst:3226 - The RAM <Mram_rom> will be implemented as a BLOCK RAM, absorbing the following register(s): <adr_reg>
    -----------------------------------------------------------------------
    | ram_type           | Block                               |          |
    -----------------------------------------------------------------------
    | Port A                                                              |
    |     aspect ratio   | 256-word x 32-bit                   |          |
    |     mode           | write-first                         |          |
    |     clkA           | connected to signal <clk_sys_i>     | rise     |
    |     weA            | connected to signal <GND>           | high     |
    |     addrA          | connected to signal <slave_i_adr>   |          |
    |     diA            | connected to signal <GND>           |          |
    |     doA            | connected to internal node          |          |
    -----------------------------------------------------------------------
    | optimization       | speed                               |          |
    -----------------------------------------------------------------------
Unit <sdb_rom> synthesized (advanced).

Synthesizing (advanced) Unit <sipo_flag_2>.
The following registers are absorbed into counter <cnt>: 1 register on signal <cnt>.
Unit <sipo_flag_2> synthesized (advanced).

Synthesizing (advanced) Unit <uart_async_rx>.
The following registers are absorbed into counter <RxD_cnt_inv>: 1 register on signal <RxD_cnt_inv>.
Unit <uart_async_rx> synthesized (advanced).

Synthesizing (advanced) Unit <updn_cntr>.
The following registers are absorbed into counter <count>: 1 register on signal <count>.
Unit <updn_cntr> synthesized (advanced).

Synthesizing (advanced) Unit <wb_gpio_port>.
INFO:Xst:3218 - HDL ADVISOR - The RAM <Mram_write_mask<0>> will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
    -----------------------------------------------------------------------
    | ram_type           | Distributed                         |          |
    -----------------------------------------------------------------------
    | Port A                                                              |
    |     aspect ratio   | 8-word x 1-bit                      |          |
    |     weA            | connected to signal <GND>           | high     |
    |     addrA          | connected to signal <wb_in_adr<5:3>> |          |
    |     diA            | connected to signal <GND>           |          |
    |     doA            | connected to signal <write_mask>    |          |
    -----------------------------------------------------------------------
Unit <wb_gpio_port> synthesized (advanced).

Synthesizing (advanced) Unit <xwb_dma>.
The following registers are absorbed into counter <read_result_offset>: 1 register on signal <read_result_offset>.
The following registers are absorbed into counter <write_issue_offset>: 1 register on signal <write_issue_offset>.
The following registers are absorbed into counter <write_result_offset>: 1 register on signal <write_result_offset>.
The following registers are absorbed into counter <read_issue_offset>: 1 register on signal <read_issue_offset>.
INFO:Xst:3218 - HDL ADVISOR - The RAM <Mram_ring> will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
    -----------------------------------------------------------------------
    | ram_type           | Distributed                         |          |
    -----------------------------------------------------------------------
    | Port A                                                              |
    |     aspect ratio   | 16-word x 32-bit                    |          |
    |     clkA           | connected to signal <clk_i>         | rise     |
    |     weA            | connected to internal node          | high     |
    |     addrA          | connected to signal <read_result_offset<3:0>> |          |
    |     diA            | connected to signal <r_master_i_dat> |          |
    -----------------------------------------------------------------------
    | Port B                                                              |
    |     aspect ratio   | 16-word x 32-bit                    |          |
    |     addrB          | connected to signal <write_issue_offset<3:0>> |          |
    |     doB            | connected to internal node          |          |
    -----------------------------------------------------------------------
Unit <xwb_dma> synthesized (advanced).
WARNING:Xst:2677 - Node <uart_bcr_17> of sequential type is unconnected in block <wb_simple_uart>.
WARNING:Xst:2677 - Node <uart_bcr_18> of sequential type is unconnected in block <wb_simple_uart>.
WARNING:Xst:2677 - Node <uart_bcr_19> of sequential type is unconnected in block <wb_simple_uart>.
WARNING:Xst:2677 - Node <uart_bcr_20> of sequential type is unconnected in block <wb_simple_uart>.
WARNING:Xst:2677 - Node <uart_bcr_21> of sequential type is unconnected in block <wb_simple_uart>.
WARNING:Xst:2677 - Node <uart_bcr_22> of sequential type is unconnected in block <wb_simple_uart>.
WARNING:Xst:2677 - Node <uart_bcr_23> of sequential type is unconnected in block <wb_simple_uart>.
WARNING:Xst:2677 - Node <uart_bcr_24> of sequential type is unconnected in block <wb_simple_uart>.
WARNING:Xst:2677 - Node <uart_bcr_25> of sequential type is unconnected in block <wb_simple_uart>.
WARNING:Xst:2677 - Node <uart_bcr_26> of sequential type is unconnected in block <wb_simple_uart>.
WARNING:Xst:2677 - Node <uart_bcr_27> of sequential type is unconnected in block <wb_simple_uart>.
WARNING:Xst:2677 - Node <uart_bcr_28> of sequential type is unconnected in block <wb_simple_uart>.
WARNING:Xst:2677 - Node <uart_bcr_29> of sequential type is unconnected in block <wb_simple_uart>.
WARNING:Xst:2677 - Node <uart_bcr_30> of sequential type is unconnected in block <wb_simple_uart>.
WARNING:Xst:2677 - Node <uart_bcr_31> of sequential type is unconnected in block <wb_simple_uart>.
WARNING:Xst:2677 - Node <s_EB_RX_HDR_ADDR_SIZE_0> of sequential type is unconnected in block <eb_main_fsm>.
WARNING:Xst:2677 - Node <s_EB_RX_HDR_ADDR_SIZE_1> of sequential type is unconnected in block <eb_main_fsm>.
WARNING:Xst:2677 - Node <s_EB_RX_HDR_ADDR_SIZE_3> of sequential type is unconnected in block <eb_main_fsm>.
WARNING:Xst:2677 - Node <s_EB_RX_HDR_PORT_SIZE_0> of sequential type is unconnected in block <eb_main_fsm>.
WARNING:Xst:2677 - Node <s_EB_RX_HDR_PORT_SIZE_1> of sequential type is unconnected in block <eb_main_fsm>.
WARNING:Xst:2677 - Node <s_EB_RX_HDR_PORT_SIZE_3> of sequential type is unconnected in block <eb_main_fsm>.

=========================================================================
Advanced HDL Synthesis Report

Macro Statistics
# RAMs                                                 : 16
 1024x32-bit dual-port block RAM                       : 1
 16384x32-bit dual-port block RAM                      : 1
 16x32-bit dual-port distributed RAM                   : 1
 256x20-bit dual-port block RAM                        : 1
 256x32-bit dual-port block RAM                        : 3
 256x32-bit single-port block RAM                      : 1
 256x32-bit single-port block Read Only RAM            : 1
 32768x32-bit dual-port block RAM                      : 1
 32x32-bit dual-port block RAM                         : 2
 4x2-bit single-port distributed Read Only RAM         : 1
 4x6-bit single-port distributed Read Only RAM         : 1
 8x1-bit single-port distributed Read Only RAM         : 2
# MACs                                                 : 2
 16x16-to-16-bit MAC                                   : 2
# Multipliers                                          : 1
 16x16-bit registered multiplier                       : 1
# Adders/Subtractors                                   : 65
 1-bit subtractor                                      : 1
 11-bit adder                                          : 1
 11-bit subtractor                                     : 1
 12-bit adder                                          : 2
 14-bit adder                                          : 1
 16-bit adder                                          : 6
 16-bit subtractor                                     : 2
 17-bit adder                                          : 1
 17-bit subtractor                                     : 1
 2-bit adder                                           : 6
 28-bit adder                                          : 1
 29-bit adder                                          : 2
 3-bit adder                                           : 2
 3-bit subtractor                                      : 1
 30-bit adder                                          : 1
 32-bit adder                                          : 7
 32-bit subtractor                                     : 2
 33-bit adder carry in                                 : 1
 33-bit subtractor borrow in                           : 1
 4-bit adder                                           : 6
 5-bit adder                                           : 8
 6-bit adder                                           : 1
 7-bit adder                                           : 4
 8-bit adder                                           : 2
 8-bit subtractor                                      : 2
 9-bit subtractor                                      : 2
# Counters                                             : 45
 10-bit up counter                                     : 1
 15-bit down counter                                   : 3
 16-bit down counter                                   : 1
 16-bit up counter                                     : 3
 2-bit up counter                                      : 1
 2-bit updown counter                                  : 1
 3-bit up counter                                      : 2
 30-bit up counter                                     : 2
 32-bit down counter                                   : 1
 4-bit up counter                                      : 4
 4-bit updown counter                                  : 2
 5-bit up counter                                      : 6
 6-bit up counter                                      : 1
 8-bit down counter                                    : 4
 8-bit up counter                                      : 6
 8-bit updown counter                                  : 3
 9-bit down counter                                    : 4
# Accumulators                                         : 3
 11-bit up accumulator                                 : 2
 6-bit up loadable accumulator                         : 1
# Registers                                            : 5612
 Flip-Flops                                            : 5612
# Comparators                                          : 93
 1-bit comparator equal                                : 2
 10-bit comparator equal                               : 1
 11-bit comparator equal                               : 5
 11-bit comparator greater                             : 2
 12-bit comparator equal                               : 1
 12-bit comparator greater                             : 1
 14-bit comparator equal                               : 1
 16-bit comparator equal                               : 5
 16-bit comparator greater                             : 9
 16-bit comparator lessequal                           : 1
 20-bit comparator equal                               : 1
 32-bit comparator equal                               : 5
 32-bit comparator greater                             : 3
 32-bit comparator lessequal                           : 2
 4-bit comparator equal                                : 2
 4-bit comparator greater                              : 12
 4-bit comparator lessequal                            : 1
 5-bit comparator equal                                : 8
 5-bit comparator not equal                            : 3
 6-bit comparator equal                                : 2
 7-bit comparator greater                              : 3
 7-bit comparator lessequal                            : 3
 7-bit comparator not equal                            : 1
 8-bit comparator equal                                : 12
 8-bit comparator greater                              : 6
 8-bit comparator lessequal                            : 1
# Multiplexers                                         : 1345
 1-bit 2-to-1 multiplexer                              : 993
 1-bit 3-to-1 multiplexer                              : 1
 1-bit 4-to-1 multiplexer                              : 41
 1-bit 8-to-1 multiplexer                              : 3
 11-bit 2-to-1 multiplexer                             : 1
 12-bit 2-to-1 multiplexer                             : 8
 16-bit 2-to-1 multiplexer                             : 17
 16-bit 3-to-1 multiplexer                             : 1
 2-bit 2-to-1 multiplexer                              : 20
 23-bit 2-to-1 multiplexer                             : 2
 24-bit 2-to-1 multiplexer                             : 5
 28-bit 2-to-1 multiplexer                             : 4
 29-bit 2-to-1 multiplexer                             : 7
 3-bit 2-to-1 multiplexer                              : 10
 30-bit 2-to-1 multiplexer                             : 2
 32-bit 2-to-1 multiplexer                             : 95
 32-bit 25-to-1 multiplexer                            : 1
 32-bit 3-to-1 multiplexer                             : 3
 32-bit 7-to-1 multiplexer                             : 2
 32-bit 8-to-1 multiplexer                             : 2
 4-bit 2-to-1 multiplexer                              : 28
 48-bit 2-to-1 multiplexer                             : 9
 5-bit 2-to-1 multiplexer                              : 14
 6-bit 2-to-1 multiplexer                              : 1
 64-bit 2-to-1 multiplexer                             : 1
 7-bit 2-to-1 multiplexer                              : 6
 8-bit 2-to-1 multiplexer                              : 60
 8-bit 4-to-1 multiplexer                              : 3
 9-bit 2-to-1 multiplexer                              : 4
 96-bit 2-to-1 multiplexer                             : 1
# Logic shifters                                       : 1
 64-bit shifter logical right                          : 1
# FSMs                                                 : 13
# Xors                                                 : 275
 1-bit xor2                                            : 175
 1-bit xor3                                            : 10
 1-bit xor4                                            : 2
 32-bit xor2                                           : 88

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1710 - FF/Latch <sipo_clr> (without init value) has a constant value of 0 in block <EB_RX_CTRL>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <snk_hdr_fsm_stall_0001> (without init value) has a constant value of 0 in block <EB_RX_CTRL>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <counter_comp_0> has a constant value of 0 in block <EB_RX_CTRL>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <counter_comp_5> has a constant value of 0 in block <EB_RX_CTRL>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <counter_comp_6> has a constant value of 0 in block <EB_RX_CTRL>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <counter_comp_7> has a constant value of 0 in block <EB_RX_CTRL>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <counter_comp_8> has a constant value of 0 in block <EB_RX_CTRL>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <counter_comp_9> has a constant value of 0 in block <EB_RX_CTRL>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <counter_comp_10> has a constant value of 0 in block <EB_RX_CTRL>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <eb_slave_o_stall> (without init value) has a constant value of 0 in block <eb_config>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <eb_slave_o_err> (without init value) has a constant value of 0 in block <eb_config>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <eb_slave_o_rty> (without init value) has a constant value of 0 in block <eb_config>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <eb_slave_o_int> (without init value) has a constant value of 0 in block <eb_config>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <local_slave_o_err> (without init value) has a constant value of 0 in block <eb_config>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <local_slave_o_rty> (without init value) has a constant value of 0 in block <eb_config>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <EB_TX_o_adr_23> (without init value) has a constant value of 0 in block <eb_main_fsm>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <EB_TX_o_adr_24> (without init value) has a constant value of 0 in block <eb_main_fsm>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <EB_TX_o_adr_25> (without init value) has a constant value of 0 in block <eb_main_fsm>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <EB_TX_o_adr_26> (without init value) has a constant value of 0 in block <eb_main_fsm>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <EB_TX_o_adr_27> (without init value) has a constant value of 0 in block <eb_main_fsm>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <EB_TX_o_adr_28> (without init value) has a constant value of 0 in block <eb_main_fsm>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <EB_TX_o_adr_29> (without init value) has a constant value of 0 in block <eb_main_fsm>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <EB_TX_o_adr_30> (without init value) has a constant value of 0 in block <eb_main_fsm>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <EB_TX_o_adr_31> (without init value) has a constant value of 0 in block <eb_main_fsm>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <s_EB_TX_HDR_EB_MAGIC_0> (without init value) has a constant value of 1 in block <eb_main_fsm>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <s_EB_TX_HDR_EB_MAGIC_1> (without init value) has a constant value of 1 in block <eb_main_fsm>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <s_EB_TX_HDR_EB_MAGIC_2> (without init value) has a constant value of 1 in block <eb_main_fsm>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <s_EB_TX_HDR_EB_MAGIC_3> (without init value) has a constant value of 1 in block <eb_main_fsm>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <s_EB_TX_HDR_EB_MAGIC_4> (without init value) has a constant value of 0 in block <eb_main_fsm>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <s_EB_TX_HDR_EB_MAGIC_5> (without init value) has a constant value of 1 in block <eb_main_fsm>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <s_EB_TX_HDR_EB_MAGIC_6> (without init value) has a constant value of 1 in block <eb_main_fsm>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <s_EB_TX_HDR_EB_MAGIC_7> (without init value) has a constant value of 0 in block <eb_main_fsm>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <s_EB_TX_HDR_EB_MAGIC_8> (without init value) has a constant value of 0 in block <eb_main_fsm>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <s_EB_TX_HDR_EB_MAGIC_9> (without init value) has a constant value of 1 in block <eb_main_fsm>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <s_EB_TX_HDR_EB_MAGIC_10> (without init value) has a constant value of 1 in block <eb_main_fsm>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <s_EB_TX_HDR_EB_MAGIC_11> (without init value) has a constant value of 1 in block <eb_main_fsm>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <s_EB_TX_HDR_EB_MAGIC_12> (without init value) has a constant value of 0 in block <eb_main_fsm>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <s_EB_TX_HDR_EB_MAGIC_13> (without init value) has a constant value of 0 in block <eb_main_fsm>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <s_EB_TX_HDR_EB_MAGIC_14> (without init value) has a constant value of 1 in block <eb_main_fsm>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <s_EB_TX_HDR_ADDR_SIZE_0> (without init value) has a constant value of 0 in block <eb_main_fsm>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <s_EB_TX_HDR_ADDR_SIZE_1> (without init value) has a constant value of 0 in block <eb_main_fsm>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <s_EB_TX_HDR_ADDR_SIZE_2> (without init value) has a constant value of 1 in block <eb_main_fsm>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <s_EB_TX_HDR_VER> (without init value) has a constant value of 1 in block <eb_main_fsm>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <s_EB_TX_HDR_PORT_SIZE_0> (without init value) has a constant value of 0 in block <eb_main_fsm>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <s_EB_TX_HDR_PORT_SIZE_1> (without init value) has a constant value of 0 in block <eb_main_fsm>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <s_EB_TX_HDR_PORT_SIZE_2> (without init value) has a constant value of 1 in block <eb_main_fsm>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <s_EB_TX_CUR_CYCLE_BCA_CFG> (without init value) has a constant value of 0 in block <eb_main_fsm>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <s_EB_TX_CUR_CYCLE_RCA_CFG> (without init value) has a constant value of 0 in block <eb_main_fsm>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <s_EB_TX_CUR_CYCLE_RESERVED1> (without init value) has a constant value of 0 in block <eb_main_fsm>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <s_EB_TX_CUR_CYCLE_RESERVED2> (without init value) has a constant value of 0 in block <eb_main_fsm>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <s_EB_TX_CUR_CYCLE_UNUSED_0> (without init value) has a constant value of 0 in block <eb_main_fsm>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <s_EB_TX_CUR_CYCLE_UNUSED_1> (without init value) has a constant value of 0 in block <eb_main_fsm>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <s_EB_TX_CUR_CYCLE_UNUSED_2> (without init value) has a constant value of 0 in block <eb_main_fsm>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <s_EB_TX_CUR_CYCLE_UNUSED_3> (without init value) has a constant value of 0 in block <eb_main_fsm>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <EB_TX_o_adr_0> (without init value) has a constant value of 0 in block <eb_main_fsm>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <EB_TX_o_adr_1> (without init value) has a constant value of 0 in block <eb_main_fsm>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <EB_TX_o_adr_2> (without init value) has a constant value of 0 in block <eb_main_fsm>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <EB_TX_o_adr_3> (without init value) has a constant value of 0 in block <eb_main_fsm>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <EB_TX_o_adr_4> (without init value) has a constant value of 0 in block <eb_main_fsm>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <EB_TX_o_adr_5> (without init value) has a constant value of 0 in block <eb_main_fsm>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <EB_TX_o_adr_6> (without init value) has a constant value of 0 in block <eb_main_fsm>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <EB_TX_o_adr_7> (without init value) has a constant value of 0 in block <eb_main_fsm>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <EB_TX_o_adr_8> (without init value) has a constant value of 0 in block <eb_main_fsm>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <EB_TX_o_adr_9> (without init value) has a constant value of 0 in block <eb_main_fsm>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <EB_TX_o_adr_10> (without init value) has a constant value of 0 in block <eb_main_fsm>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <EB_TX_o_adr_11> (without init value) has a constant value of 0 in block <eb_main_fsm>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <EB_TX_o_adr_12> (without init value) has a constant value of 0 in block <eb_main_fsm>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <EB_TX_o_adr_13> (without init value) has a constant value of 0 in block <eb_main_fsm>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <EB_TX_o_adr_14> (without init value) has a constant value of 0 in block <eb_main_fsm>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <EB_TX_o_adr_15> (without init value) has a constant value of 0 in block <eb_main_fsm>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <EB_TX_o_adr_16> (without init value) has a constant value of 0 in block <eb_main_fsm>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <EB_TX_o_adr_17> (without init value) has a constant value of 0 in block <eb_main_fsm>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <EB_TX_o_adr_18> (without init value) has a constant value of 0 in block <eb_main_fsm>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <EB_TX_o_adr_19> (without init value) has a constant value of 0 in block <eb_main_fsm>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <EB_TX_o_adr_20> (without init value) has a constant value of 0 in block <eb_main_fsm>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <EB_TX_o_adr_21> (without init value) has a constant value of 0 in block <eb_main_fsm>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <EB_TX_o_adr_22> (without init value) has a constant value of 0 in block <eb_main_fsm>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ETH_TX_TYP_6> (without init value) has a constant value of 0 in block <EB_TX_CTRL>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ETH_TX_TYP_7> (without init value) has a constant value of 0 in block <EB_TX_CTRL>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ETH_TX_TYP_8> (without init value) has a constant value of 0 in block <EB_TX_CTRL>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ETH_TX_TYP_9> (without init value) has a constant value of 0 in block <EB_TX_CTRL>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ETH_TX_TYP_10> (without init value) has a constant value of 0 in block <EB_TX_CTRL>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ETH_TX_TYP_11> (without init value) has a constant value of 1 in block <EB_TX_CTRL>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <IPV4_TX_VER_0> (without init value) has a constant value of 0 in block <EB_TX_CTRL>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <IPV4_TX_VER_1> (without init value) has a constant value of 0 in block <EB_TX_CTRL>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <IPV4_TX_VER_2> (without init value) has a constant value of 1 in block <EB_TX_CTRL>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <IPV4_TX_IHL_0> (without init value) has a constant value of 1 in block <EB_TX_CTRL>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <IPV4_TX_IHL_1> (without init value) has a constant value of 0 in block <EB_TX_CTRL>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <IPV4_TX_IHL_2> (without init value) has a constant value of 1 in block <EB_TX_CTRL>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <IPV4_TX_FLG_0> (without init value) has a constant value of 0 in block <EB_TX_CTRL>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <IPV4_TX_FLG_1> (without init value) has a constant value of 1 in block <EB_TX_CTRL>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <IPV4_TX_TTL_0> (without init value) has a constant value of 0 in block <EB_TX_CTRL>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <IPV4_TX_TTL_1> (without init value) has a constant value of 0 in block <EB_TX_CTRL>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <IPV4_TX_TTL_2> (without init value) has a constant value of 0 in block <EB_TX_CTRL>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <IPV4_TX_TTL_3> (without init value) has a constant value of 0 in block <EB_TX_CTRL>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <IPV4_TX_TTL_4> (without init value) has a constant value of 0 in block <EB_TX_CTRL>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <IPV4_TX_TTL_5> (without init value) has a constant value of 0 in block <EB_TX_CTRL>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <IPV4_TX_TTL_6> (without init value) has a constant value of 1 in block <EB_TX_CTRL>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <IPV4_TX_PRO_0> (without init value) has a constant value of 1 in block <EB_TX_CTRL>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <IPV4_TX_PRO_1> (without init value) has a constant value of 0 in block <EB_TX_CTRL>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <IPV4_TX_PRO_2> (without init value) has a constant value of 0 in block <EB_TX_CTRL>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <IPV4_TX_PRO_3> (without init value) has a constant value of 0 in block <EB_TX_CTRL>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <IPV4_TX_PRO_4> (without init value) has a constant value of 1 in block <EB_TX_CTRL>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <s_src_padding_o_dat_0> (without init value) has a constant value of 1 in block <EB_TX_CTRL>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <s_src_padding_o_dat_1> (without init value) has a constant value of 0 in block <EB_TX_CTRL>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <s_src_padding_o_dat_2> (without init value) has a constant value of 0 in block <EB_TX_CTRL>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <s_src_padding_o_dat_3> (without init value) has a constant value of 0 in block <EB_TX_CTRL>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <s_src_padding_o_dat_4> (without init value) has a constant value of 1 in block <EB_TX_CTRL>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <s_src_padding_o_dat_5> (without init value) has a constant value of 0 in block <EB_TX_CTRL>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <s_src_padding_o_dat_6> (without init value) has a constant value of 1 in block <EB_TX_CTRL>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <s_src_padding_o_dat_7> (without init value) has a constant value of 1 in block <EB_TX_CTRL>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <s_src_padding_o_dat_8> (without init value) has a constant value of 0 in block <EB_TX_CTRL>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <s_src_padding_o_dat_9> (without init value) has a constant value of 1 in block <EB_TX_CTRL>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <s_src_padding_o_dat_10> (without init value) has a constant value of 0 in block <EB_TX_CTRL>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <s_src_padding_o_dat_11> (without init value) has a constant value of 1 in block <EB_TX_CTRL>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <s_src_padding_o_dat_12> (without init value) has a constant value of 1 in block <EB_TX_CTRL>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <s_src_padding_o_dat_13> (without init value) has a constant value of 0 in block <EB_TX_CTRL>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <s_src_padding_o_dat_14> (without init value) has a constant value of 0 in block <EB_TX_CTRL>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <s_src_padding_o_dat_15> (without init value) has a constant value of 1 in block <EB_TX_CTRL>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <s_ETH_end_0> has a constant value of 0 in block <EB_TX_CTRL>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <s_ETH_end_1> has a constant value of 0 in block <EB_TX_CTRL>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <s_ETH_end_2> has a constant value of 1 in block <EB_TX_CTRL>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <s_ETH_end_3> has a constant value of 1 in block <EB_TX_CTRL>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <s_ETH_end_4> has a constant value of 0 in block <EB_TX_CTRL>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ETH_TX_TYP_0> (without init value) has a constant value of 0 in block <EB_TX_CTRL>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ETH_TX_TYP_1> (without init value) has a constant value of 0 in block <EB_TX_CTRL>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ETH_TX_TYP_2> (without init value) has a constant value of 0 in block <EB_TX_CTRL>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ETH_TX_TYP_3> (without init value) has a constant value of 0 in block <EB_TX_CTRL>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ETH_TX_TYP_4> (without init value) has a constant value of 0 in block <EB_TX_CTRL>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ETH_TX_TYP_5> (without init value) has a constant value of 0 in block <EB_TX_CTRL>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <rx_eb32_o_adr_13> (without init value) has a constant value of 0 in block <xwb_ethmac_adapter>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rx_eb32_o_adr_12> (without init value) has a constant value of 0 in block <xwb_ethmac_adapter>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rx_eb32_o_adr_11> (without init value) has a constant value of 0 in block <xwb_ethmac_adapter>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rx_eb32_o_adr_10> (without init value) has a constant value of 0 in block <xwb_ethmac_adapter>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rx_eb32_o_adr_9> (without init value) has a constant value of 0 in block <xwb_ethmac_adapter>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rx_eb32_o_adr_8> (without init value) has a constant value of 0 in block <xwb_ethmac_adapter>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rx_eb32_o_adr_7> (without init value) has a constant value of 0 in block <xwb_ethmac_adapter>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rx_eb32_o_adr_6> (without init value) has a constant value of 0 in block <xwb_ethmac_adapter>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rx_eb32_o_adr_5> (without init value) has a constant value of 0 in block <xwb_ethmac_adapter>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rx_eb32_o_adr_4> (without init value) has a constant value of 0 in block <xwb_ethmac_adapter>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rx_eb32_o_adr_3> (without init value) has a constant value of 0 in block <xwb_ethmac_adapter>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rx_eb32_o_adr_2> (without init value) has a constant value of 0 in block <xwb_ethmac_adapter>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rx_eb32_o_adr_1> (without init value) has a constant value of 0 in block <xwb_ethmac_adapter>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rx_eb32_o_adr_0> (without init value) has a constant value of 0 in block <xwb_ethmac_adapter>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rx_ram_o_dat_31> (without init value) has a constant value of 0 in block <xwb_ethmac_adapter>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rx_ram_o_dat_30> (without init value) has a constant value of 0 in block <xwb_ethmac_adapter>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rx_ram_o_dat_29> (without init value) has a constant value of 0 in block <xwb_ethmac_adapter>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rx_eb32_o_adr_31> (without init value) has a constant value of 0 in block <xwb_ethmac_adapter>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rx_eb32_o_adr_30> (without init value) has a constant value of 0 in block <xwb_ethmac_adapter>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rx_eb32_o_adr_29> (without init value) has a constant value of 0 in block <xwb_ethmac_adapter>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rx_eb32_o_adr_28> (without init value) has a constant value of 0 in block <xwb_ethmac_adapter>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rx_eb32_o_adr_27> (without init value) has a constant value of 0 in block <xwb_ethmac_adapter>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rx_eb32_o_adr_26> (without init value) has a constant value of 0 in block <xwb_ethmac_adapter>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rx_eb32_o_adr_25> (without init value) has a constant value of 0 in block <xwb_ethmac_adapter>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rx_eb32_o_adr_24> (without init value) has a constant value of 0 in block <xwb_ethmac_adapter>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rx_eb32_o_adr_23> (without init value) has a constant value of 0 in block <xwb_ethmac_adapter>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rx_eb32_o_adr_22> (without init value) has a constant value of 0 in block <xwb_ethmac_adapter>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rx_eb32_o_adr_21> (without init value) has a constant value of 0 in block <xwb_ethmac_adapter>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rx_eb32_o_adr_20> (without init value) has a constant value of 0 in block <xwb_ethmac_adapter>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rx_eb32_o_adr_19> (without init value) has a constant value of 0 in block <xwb_ethmac_adapter>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rx_eb32_o_adr_18> (without init value) has a constant value of 0 in block <xwb_ethmac_adapter>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rx_eb32_o_adr_17> (without init value) has a constant value of 0 in block <xwb_ethmac_adapter>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rx_eb32_o_adr_16> (without init value) has a constant value of 0 in block <xwb_ethmac_adapter>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rx_eb32_o_adr_15> (without init value) has a constant value of 0 in block <xwb_ethmac_adapter>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rx_eb32_o_adr_14> (without init value) has a constant value of 0 in block <xwb_ethmac_adapter>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rx_ram_o_dat_10> (without init value) has a constant value of 0 in block <xwb_ethmac_adapter>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rx_ram_o_dat_9> (without init value) has a constant value of 0 in block <xwb_ethmac_adapter>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rx_ram_o_dat_8> (without init value) has a constant value of 0 in block <xwb_ethmac_adapter>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rx_ram_o_dat_7> (without init value) has a constant value of 0 in block <xwb_ethmac_adapter>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rx_ram_o_dat_6> (without init value) has a constant value of 0 in block <xwb_ethmac_adapter>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rx_ram_o_dat_5> (without init value) has a constant value of 0 in block <xwb_ethmac_adapter>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rx_ram_o_dat_4> (without init value) has a constant value of 0 in block <xwb_ethmac_adapter>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rx_ram_o_dat_3> (without init value) has a constant value of 0 in block <xwb_ethmac_adapter>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rx_ram_o_dat_2> (without init value) has a constant value of 0 in block <xwb_ethmac_adapter>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rx_ram_o_dat_1> (without init value) has a constant value of 0 in block <xwb_ethmac_adapter>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rx_ram_o_dat_0> (without init value) has a constant value of 0 in block <xwb_ethmac_adapter>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rx_ram_o_we> (without init value) has a constant value of 0 in block <xwb_ethmac_adapter>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <tx_eb32_o_err> (without init value) has a constant value of 0 in block <xwb_ethmac_adapter>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <tx_eb32_o_rty> (without init value) has a constant value of 0 in block <xwb_ethmac_adapter>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <wb_slave_o_int> (without init value) has a constant value of 0 in block <xwb_ethmac_adapter>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <wb_slave_o_stall> (without init value) has a constant value of 0 in block <xwb_ethmac_adapter>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <wb_slave_o_err> (without init value) has a constant value of 0 in block <xwb_ethmac_adapter>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <wb_slave_o_rty> (without init value) has a constant value of 0 in block <xwb_ethmac_adapter>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rx_ram_o_dat_28> (without init value) has a constant value of 0 in block <xwb_ethmac_adapter>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rx_ram_o_dat_27> (without init value) has a constant value of 0 in block <xwb_ethmac_adapter>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rx_ram_o_dat_26> (without init value) has a constant value of 0 in block <xwb_ethmac_adapter>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rx_ram_o_dat_25> (without init value) has a constant value of 0 in block <xwb_ethmac_adapter>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rx_ram_o_dat_24> (without init value) has a constant value of 0 in block <xwb_ethmac_adapter>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rx_ram_o_dat_23> (without init value) has a constant value of 0 in block <xwb_ethmac_adapter>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rx_ram_o_dat_22> (without init value) has a constant value of 0 in block <xwb_ethmac_adapter>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rx_ram_o_dat_21> (without init value) has a constant value of 0 in block <xwb_ethmac_adapter>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rx_ram_o_dat_20> (without init value) has a constant value of 0 in block <xwb_ethmac_adapter>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rx_ram_o_dat_19> (without init value) has a constant value of 0 in block <xwb_ethmac_adapter>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rx_ram_o_dat_18> (without init value) has a constant value of 0 in block <xwb_ethmac_adapter>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rx_ram_o_dat_17> (without init value) has a constant value of 0 in block <xwb_ethmac_adapter>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rx_ram_o_dat_16> (without init value) has a constant value of 0 in block <xwb_ethmac_adapter>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rx_ram_o_dat_15> (without init value) has a constant value of 0 in block <xwb_ethmac_adapter>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rx_ram_o_dat_14> (without init value) has a constant value of 0 in block <xwb_ethmac_adapter>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rx_ram_o_dat_13> (without init value) has a constant value of 0 in block <xwb_ethmac_adapter>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rx_ram_o_dat_12> (without init value) has a constant value of 0 in block <xwb_ethmac_adapter>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rx_ram_o_dat_11> (without init value) has a constant value of 0 in block <xwb_ethmac_adapter>. This FF/Latch will be trimmed during the optimization process.
INFO:Xst:2261 - The FF/Latch <sh_chk_en> in Unit <EB_TX_CTRL> is equivalent to the following FF/Latch, which will be removed : <calc_chk_en> 
INFO:Xst:2261 - The FF/Latch <i_dat_o_0> in Unit <lm32_instruction_unit_medium_icache_debug> is equivalent to the following 3 FFs/Latches, which will be removed : <i_dat_o_8> <i_dat_o_16> <i_dat_o_24> 
INFO:Xst:2261 - The FF/Latch <i_dat_o_1> in Unit <lm32_instruction_unit_medium_icache_debug> is equivalent to the following 3 FFs/Latches, which will be removed : <i_dat_o_9> <i_dat_o_17> <i_dat_o_25> 
INFO:Xst:2261 - The FF/Latch <i_cyc_o> in Unit <lm32_instruction_unit_medium_icache_debug> is equivalent to the following FF/Latch, which will be removed : <i_stb_o> 
INFO:Xst:2261 - The FF/Latch <i_dat_o_2> in Unit <lm32_instruction_unit_medium_icache_debug> is equivalent to the following 3 FFs/Latches, which will be removed : <i_dat_o_10> <i_dat_o_18> <i_dat_o_26> 
INFO:Xst:2261 - The FF/Latch <i_dat_o_3> in Unit <lm32_instruction_unit_medium_icache_debug> is equivalent to the following 3 FFs/Latches, which will be removed : <i_dat_o_11> <i_dat_o_19> <i_dat_o_27> 
INFO:Xst:2261 - The FF/Latch <i_dat_o_4> in Unit <lm32_instruction_unit_medium_icache_debug> is equivalent to the following 3 FFs/Latches, which will be removed : <i_dat_o_12> <i_dat_o_20> <i_dat_o_28> 
INFO:Xst:2261 - The FF/Latch <i_dat_o_5> in Unit <lm32_instruction_unit_medium_icache_debug> is equivalent to the following 3 FFs/Latches, which will be removed : <i_dat_o_13> <i_dat_o_21> <i_dat_o_29> 
INFO:Xst:2261 - The FF/Latch <i_dat_o_6> in Unit <lm32_instruction_unit_medium_icache_debug> is equivalent to the following 3 FFs/Latches, which will be removed : <i_dat_o_14> <i_dat_o_22> <i_dat_o_30> 
INFO:Xst:2261 - The FF/Latch <i_dat_o_7> in Unit <lm32_instruction_unit_medium_icache_debug> is equivalent to the following 3 FFs/Latches, which will be removed : <i_dat_o_15> <i_dat_o_23> <i_dat_o_31> 
INFO:Xst:2261 - The FF/Latch <d_stb_o> in Unit <lm32_load_store_unit_medium_icache_debug> is equivalent to the following FF/Latch, which will be removed : <d_cyc_o> 
WARNING:Xst:2973 - All outputs of instance <RX_FIFO/wrapped_gen/grf.rf/gl0.rd/grss.gpe.rdpe> of block <rd_pe_ss> are unconnected in block <eb_main_fsm>. Underlying logic will be removed.
WARNING:Xst:2973 - All outputs of instance <TX_FIFO/wrapped_gen/grf.rf/gl0.rd/grss.gpe.rdpe> of block <rd_pe_ss> are unconnected in block <eb_main_fsm>. Underlying logic will be removed.
WARNING:Xst:2677 - Node <TX_FIFO/wrapped_gen/grf.rf/gl0.wr/gwhf.whf/OVERFLOW> of sequential type is unconnected in block <eb_main_fsm>.
WARNING:Xst:2677 - Node <RX_FIFO/wrapped_gen/grf.rf/gl0.wr/gwhf.whf/OVERFLOW> of sequential type is unconnected in block <eb_main_fsm>.
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <cmp_uart/U_Wrapped_UART/gen_phys_uart.U_TX/FSM_11> on signal <state[1:4]> with user encoding.
-------------------
 State | Encoding
-------------------
 0000  | 0000
 0001  | 0001
 0100  | 0100
 0011  | 0011
 1000  | 1000
 1001  | 1001
 1010  | 1010
 1011  | 1011
 1100  | 1100
 1101  | 1101
 1110  | 1110
 1111  | 1111
 0010  | 0010
-------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <cmp_uart/U_Wrapped_UART/gen_phys_uart.U_RX/FSM_12> on signal <state[1:4]> with sequential encoding.
-------------------
 State | Encoding
-------------------
 0000  | 0000
 1000  | 0001
 1001  | 0010
 1010  | 0011
 1011  | 0100
 1100  | 0101
 1101  | 0110
 1110  | 0111
 1111  | 1000
 0001  | 1001
-------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <cmp_eb_slave_core/RXCTRL/FSM_7> on signal <parse[1:4]> with user encoding.
---------------------------
 State         | Encoding
---------------------------
 idle          | 0000
 eth           | 0001
 eth_capture   | 0010
 eth_chk       | 0011
 ipv4          | 0100
 ipv4_capture  | 0101
 ipv4_chksum   | unreached
 ipv4_opt      | 0111
 udp           | 1000
 udp_fetch_buf | 1001
 udp_capture   | 1010
 chk           | 1011
 done          | 1100
 errors        | 1101
 waits         | 1110
---------------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <cmp_eb_slave_core/RXCTRL/FSM_8> on signal <state[1:3]> with user encoding.
---------------------
 State   | Encoding
---------------------
 idle    | 000
 header  | 001
 payload | 010
 padding | 011
 done    | 100
 errors  | 101
---------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <cmp_eb_slave_core/EB/FSM_10> on signal <s_state_RX[1:5]> with user encoding.
-----------------------------------
 State                 | Encoding
-----------------------------------
 idle                  | 00000
 eb_hdr_rec            | 00001
 eb_hdr_proc           | 00010
 eb_hdr_probe_id       | 00011
 eb_hdr_probe_rdy      | 00100
 cyc_hdr_rec           | 00101
 cyc_hdr_read_proc     | 00110
 cyc_hdr_read_get_adr  | 00111
 wb_read_rdy           | 01000
 wb_read               | 01001
 cyc_hdr_write_proc    | 01010
 cyc_hdr_write_get_adr | 01011
 wb_write_rdy          | 01100
 wb_write              | 01101
 wb_write_done         | 01110
 cyc_done              | 01111
 eb_done               | 10000
 error                 | 10001
 error_wait            | 10010
-----------------------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <cmp_eb_slave_core/EB/FSM_9> on signal <s_state_TX[1:12]> with one-hot encoding.
-------------------------------------
 State               | Encoding
-------------------------------------
 idle                | 000000000001
 eb_hdr_init         | 000000000100
 eb_hdr_probe_id     | 001000000000
 eb_hdr_probe_wait   | 000010000000
 packet_hdr_send     | 000001000000
 eb_hdr_send         | 000100000000
 rdy                 | 000000000010
 cyc_hdr_init        | 000000001000
 cyc_hdr_send        | 010000000000
 base_write_adr_send | 000000010000
 data_send           | 100000000000
 zero_pad_write      | 000000100000
 zero_pad_wait       | unreached
 error               | unreached
-------------------------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <cmp_eb_slave_core/TXCTRL/FSM_5> on signal <state[1:4]> with user encoding.
---------------------------
 State         | Encoding
---------------------------
 idle          | 0000
 calc_chksum   | 0001
 wait_send_req | 0010
 prep_eth      | 0011
 eth           | 0100
 ipv4          | 0101
 udp           | 0110
 hdr_send      | 0111
 payload_send  | 1000
 padding       | 1001
 wait_ifgap    | 1010
 error         | 1011
---------------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <cmp_eb_slave_core/TXCTRL/chksum_generator/FSM_6> on signal <state[1:3]> with user encoding.
----------------------
 State    | Encoding
----------------------
 idle     | 000
 addup    | 001
 carries  | 010
 finalise | 011
 output   | 100
----------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <cmp_xwb_ethmac_adapter/FSM_3> on signal <state_tx[1:2]> with gray encoding.
----------------------
 State    | Encoding
----------------------
 idle     | 00
 init     | 01
 transfer | 11
 waiting  | unreached
 done     | 10
----------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <cmp_xwb_ethmac_adapter/FSM_4> on signal <state_rx[1:3]> with user encoding.
----------------------
 State    | Encoding
----------------------
 idle     | 000
 init     | 001
 transfer | 010
 waiting  | unreached
 done     | 100
----------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/FSM_1> on signal <state[1:4]> with sequential encoding.
-------------------
 State | Encoding
-------------------
 0000  | 0000
 0001  | 0001
 0110  | 0010
 0101  | 0011
 0010  | 0100
 0011  | 0101
 0100  | 0110
 0111  | 0111
 1000  | 1000
-------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/FSM_0> on signal <state[1:2]> with gray encoding.
-------------------
 State | Encoding
-------------------
 0001  | 00
 0010  | 01
 0100  | 11
 1000  | 10
-------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/FSM_2> on signal <state[1:3]> with user encoding.
-------------------
 State | Encoding
-------------------
 000   | 000
 001   | 001
 010   | 010
 011   | 011
 100   | 100
-------------------
WARNING:Xst:1426 - The value init of the FF/Latch counter_comp_1 hinder the constant cleaning in the block EB_RX_CTRL.
   You should achieve better results by setting this init to 1.
WARNING:Xst:2677 - Node <DlyCrcCnt_3> of sequential type is unconnected in block <eth_transmitcontrol>.
WARNING:Xst:2677 - Node <out_reg_8> of sequential type is unconnected in block <wb_gpio_port>.
WARNING:Xst:2677 - Node <out_reg_9> of sequential type is unconnected in block <wb_gpio_port>.
WARNING:Xst:2677 - Node <out_reg_10> of sequential type is unconnected in block <wb_gpio_port>.
WARNING:Xst:2677 - Node <out_reg_11> of sequential type is unconnected in block <wb_gpio_port>.
WARNING:Xst:2677 - Node <out_reg_12> of sequential type is unconnected in block <wb_gpio_port>.
WARNING:Xst:2677 - Node <out_reg_13> of sequential type is unconnected in block <wb_gpio_port>.
WARNING:Xst:2677 - Node <out_reg_14> of sequential type is unconnected in block <wb_gpio_port>.
WARNING:Xst:2677 - Node <out_reg_15> of sequential type is unconnected in block <wb_gpio_port>.
WARNING:Xst:2677 - Node <out_reg_16> of sequential type is unconnected in block <wb_gpio_port>.
WARNING:Xst:2677 - Node <out_reg_17> of sequential type is unconnected in block <wb_gpio_port>.
WARNING:Xst:2677 - Node <out_reg_18> of sequential type is unconnected in block <wb_gpio_port>.
WARNING:Xst:2677 - Node <out_reg_19> of sequential type is unconnected in block <wb_gpio_port>.
WARNING:Xst:2677 - Node <out_reg_20> of sequential type is unconnected in block <wb_gpio_port>.
WARNING:Xst:2677 - Node <out_reg_21> of sequential type is unconnected in block <wb_gpio_port>.
WARNING:Xst:2677 - Node <out_reg_22> of sequential type is unconnected in block <wb_gpio_port>.
WARNING:Xst:2677 - Node <out_reg_23> of sequential type is unconnected in block <wb_gpio_port>.
WARNING:Xst:2677 - Node <out_reg_24> of sequential type is unconnected in block <wb_gpio_port>.
WARNING:Xst:2677 - Node <out_reg_25> of sequential type is unconnected in block <wb_gpio_port>.
WARNING:Xst:2677 - Node <out_reg_26> of sequential type is unconnected in block <wb_gpio_port>.
WARNING:Xst:2677 - Node <out_reg_27> of sequential type is unconnected in block <wb_gpio_port>.
WARNING:Xst:2677 - Node <out_reg_28> of sequential type is unconnected in block <wb_gpio_port>.
WARNING:Xst:2677 - Node <out_reg_29> of sequential type is unconnected in block <wb_gpio_port>.
WARNING:Xst:2677 - Node <out_reg_30> of sequential type is unconnected in block <wb_gpio_port>.
WARNING:Xst:2677 - Node <out_reg_31> of sequential type is unconnected in block <wb_gpio_port>.
WARNING:Xst:1710 - FF/Latch <rddata_reg_31> (without init value) has a constant value of 0 in block <simple_uart_wb>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_30> (without init value) has a constant value of 0 in block <simple_uart_wb>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_29> (without init value) has a constant value of 0 in block <simple_uart_wb>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_28> (without init value) has a constant value of 0 in block <simple_uart_wb>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_27> (without init value) has a constant value of 0 in block <simple_uart_wb>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_26> (without init value) has a constant value of 0 in block <simple_uart_wb>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_25> (without init value) has a constant value of 0 in block <simple_uart_wb>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_24> (without init value) has a constant value of 0 in block <simple_uart_wb>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_23> (without init value) has a constant value of 0 in block <simple_uart_wb>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_22> (without init value) has a constant value of 0 in block <simple_uart_wb>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_21> (without init value) has a constant value of 0 in block <simple_uart_wb>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_20> (without init value) has a constant value of 0 in block <simple_uart_wb>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_19> (without init value) has a constant value of 0 in block <simple_uart_wb>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_18> (without init value) has a constant value of 0 in block <simple_uart_wb>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_17> (without init value) has a constant value of 0 in block <simple_uart_wb>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_16> (without init value) has a constant value of 0 in block <simple_uart_wb>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_15> (without init value) has a constant value of 0 in block <simple_uart_wb>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_14> (without init value) has a constant value of 0 in block <simple_uart_wb>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_13> (without init value) has a constant value of 0 in block <simple_uart_wb>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_12> (without init value) has a constant value of 0 in block <simple_uart_wb>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_11> (without init value) has a constant value of 0 in block <simple_uart_wb>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_10> (without init value) has a constant value of 0 in block <simple_uart_wb>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_9> (without init value) has a constant value of 0 in block <simple_uart_wb>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_8> (without init value) has a constant value of 0 in block <simple_uart_wb>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <byte_count_0> has a constant value of 0 in block <EB_RX_CTRL>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <s_EB_RX_byte_cnt_0> (without init value) has a constant value of 0 in block <eb_main_fsm>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <s_EB_RX_byte_cnt_1> (without init value) has a constant value of 0 in block <eb_main_fsm>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <byte_count_0> has a constant value of 0 in block <EB_TX_CTRL>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <i_cti_o_1> (without init value) has a constant value of 1 in block <lm32_instruction_unit_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <slave2_out_ack> (without init value) has a constant value of 0 in block <xwb_dpram_2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <inst_LPM_FF1_3> (without init value) has a constant value of 0 in block <generic_dpram_sameclock_2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <inst_LPM_FF1_2> (without init value) has a constant value of 0 in block <generic_dpram_sameclock_2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <inst_LPM_FF1_1> (without init value) has a constant value of 0 in block <generic_dpram_sameclock_2>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <inst_LPM_FF1_0> (without init value) has a constant value of 0 in block <generic_dpram_sameclock_2>. This FF/Latch will be trimmed during the optimization process.
INFO:Xst:2261 - The FF/Latch <counter_comp_2> in Unit <EB_RX_CTRL> is equivalent to the following FF/Latch, which will be removed : <counter_comp_3> 
INFO:Xst:2261 - The FF/Latch <i_cti_o_0> in Unit <lm32_instruction_unit_medium_icache_debug> is equivalent to the following FF/Latch, which will be removed : <i_cti_o_2> 
WARNING:Xst:2042 - Unit wb_gpio_port: 8 internal tristates are replaced by logic (pull-up yes): gpio_b<0>, gpio_b<1>, gpio_b<2>, gpio_b<3>, gpio_b<4>, gpio_b<5>, gpio_b<6>, gpio_b<7>.

Optimizing unit <eth_register_15> ...

Optimizing unit <eth_register_2> ...

Optimizing unit <eth_register_7> ...

Optimizing unit <eth_register_12> ...

Optimizing unit <dbe_bpm_ebone> ...

Optimizing unit <ethmac> ...

Optimizing unit <eth_registers> ...

Optimizing unit <eth_register_1> ...

Optimizing unit <eth_register_8> ...

Optimizing unit <eth_register_14> ...

Optimizing unit <eth_wishbone> ...
WARNING:Xst:1710 - FF/Latch <m_wb_bte_o_1> (without init value) has a constant value of 0 in block <eth_wishbone>. This FF/Latch will be trimmed during the optimization process.

Optimizing unit <eth_miim> ...

Optimizing unit <eth_clockgen> ...
WARNING:Xst:1710 - FF/Latch <Counter_7> (without init value) has a constant value of 0 in block <eth_clockgen>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <Counter_7> (without init value) has a constant value of 0 in block <eth_clockgen>. This FF/Latch will be trimmed during the optimization process.

Optimizing unit <eth_shiftreg> ...

Optimizing unit <eth_outputcontrol> ...

Optimizing unit <eth_maccontrol> ...

Optimizing unit <eth_receivecontrol> ...

Optimizing unit <eth_transmitcontrol> ...

Optimizing unit <eth_txethmac> ...

Optimizing unit <eth_txcounters> ...

Optimizing unit <eth_txstatem> ...

Optimizing unit <eth_crc> ...

Optimizing unit <eth_random> ...

Optimizing unit <eth_rxethmac> ...

Optimizing unit <eth_rxcounters> ...

Optimizing unit <eth_rxaddrcheck> ...

Optimizing unit <eth_rxstatem> ...

Optimizing unit <eth_macstatus> ...

Optimizing unit <wb_gpio_port> ...

Optimizing unit <gc_sync_ffs> ...

Optimizing unit <wb_simple_uart> ...

Optimizing unit <simple_uart_wb> ...

Optimizing unit <uart_baud_gen> ...

Optimizing unit <uart_async_tx> ...

Optimizing unit <uart_async_rx> ...

Optimizing unit <xwb_crossbar> ...

Optimizing unit <EB_RX_CTRL> ...

Optimizing unit <WB_bus_adapter_streaming_sg_1> ...

Optimizing unit <sipo_flag_1> ...
WARNING:Xst:1710 - FF/Latch <cnt_1> (without init value) has a constant value of 0 in block <sipo_flag_1>. This FF/Latch will be trimmed during the optimization process.

Optimizing unit <sipo_flag_2> ...

Optimizing unit <eb_config> ...

Optimizing unit <eb_main_fsm> ...

Optimizing unit <reset_blk_ramfifo> ...

Optimizing unit <rd_status_flags_ss> ...

Optimizing unit <rd_pe_ss> ...

Optimizing unit <rd_bin_cntr> ...

Optimizing unit <wr_status_flags_ss> ...

Optimizing unit <wr_pf_ss> ...

Optimizing unit <wr_bin_cntr> ...

Optimizing unit <EB_TX_CTRL> ...

Optimizing unit <WB_bus_adapter_streaming_sg_2> ...

Optimizing unit <piso_flag_1> ...

Optimizing unit <piso_flag_2> ...

Optimizing unit <EB_checksum> ...

Optimizing unit <piso_flag_3> ...

Optimizing unit <xwb_ethmac_adapter> ...

Optimizing unit <xwb_dma> ...

Optimizing unit <xwb_lm32> ...

Optimizing unit <lm32_cpu_medium_icache_debug> ...

Optimizing unit <lm32_interrupt_medium_icache_debug> ...
WARNING:Xst:1710 - FF/Latch <ip_31> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_30> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_29> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_28> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_27> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_26> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_25> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_24> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_23> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_22> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_21> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_20> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_19> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_18> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_17> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_16> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_15> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_14> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_13> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_12> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_11> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_10> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_9> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_8> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_7> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_6> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_5> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ip_31> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_30> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_29> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_28> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_27> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_26> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_25> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_24> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_23> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_22> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_21> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_20> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_19> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_18> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_17> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_16> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_15> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_14> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_13> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_12> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_11> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_10> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_9> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_8> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_7> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_6> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_5> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.

Optimizing unit <lm32_jtag_medium_icache_debug> ...

Optimizing unit <lm32_instruction_unit_medium_icache_debug> ...

Optimizing unit <lm32_icache_medium_icache_debug> ...

Optimizing unit <lm32_ram_2> ...

Optimizing unit <lm32_load_store_unit_medium_icache_debug> ...

Optimizing unit <lm32_shifter> ...

Optimizing unit <lm32_multiplier> ...

Optimizing unit <lm32_debug_medium_icache_debug> ...

Optimizing unit <lm32_decoder_medium_icache_debug> ...

Optimizing unit <jtag_cores> ...

Optimizing unit <xwb_dpram_2> ...

Optimizing unit <generic_dpram_sameclock_2> ...

Optimizing unit <xwb_dpram_1> ...

Optimizing unit <generic_dpram_sameclock_1> ...
WARNING:Xst:1710 - FF/Latch <cmp_interconnect/crossbar/matrix_old_6_11> (without init value) has a constant value of 0 in block <dbe_bpm_ebone>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_interconnect/crossbar/matrix_old_6_10> (without init value) has a constant value of 0 in block <dbe_bpm_ebone>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_interconnect/crossbar/matrix_old_6_9> (without init value) has a constant value of 0 in block <dbe_bpm_ebone>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_interconnect/crossbar/matrix_old_6_8> (without init value) has a constant value of 0 in block <dbe_bpm_ebone>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_interconnect/crossbar/matrix_old_6_7> (without init value) has a constant value of 0 in block <dbe_bpm_ebone>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_interconnect/crossbar/matrix_old_6_6> (without init value) has a constant value of 0 in block <dbe_bpm_ebone>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_interconnect/crossbar/matrix_old_6_5> (without init value) has a constant value of 0 in block <dbe_bpm_ebone>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_interconnect/crossbar/matrix_old_6_4> (without init value) has a constant value of 0 in block <dbe_bpm_ebone>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_interconnect/crossbar/matrix_old_6_3> (without init value) has a constant value of 0 in block <dbe_bpm_ebone>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_interconnect/crossbar/matrix_old_6_2> (without init value) has a constant value of 0 in block <dbe_bpm_ebone>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_interconnect/crossbar/matrix_old_6_1> (without init value) has a constant value of 0 in block <dbe_bpm_ebone>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:2677 - Node <cmp_xwb_ethmac/cmp_wrapper_wb_ethmac/cmp_wrapper_ethmac/wishbone/m_wb_cti_o_2> of sequential type is unconnected in block <dbe_bpm_ebone>.
WARNING:Xst:2677 - Node <cmp_xwb_ethmac/cmp_wrapper_wb_ethmac/cmp_wrapper_ethmac/wishbone/m_wb_cti_o_1> of sequential type is unconnected in block <dbe_bpm_ebone>.
WARNING:Xst:2677 - Node <cmp_xwb_ethmac/cmp_wrapper_wb_ethmac/cmp_wrapper_ethmac/wishbone/m_wb_cti_o_0> of sequential type is unconnected in block <dbe_bpm_ebone>.
WARNING:Xst:2677 - Node <cmp_xwb_ethmac/cmp_wrapper_wb_ethmac/cmp_wrapper_ethmac/wishbone/m_wb_bte_o_0> of sequential type is unconnected in block <dbe_bpm_ebone>.
WARNING:Xst:2677 - Node <cmp_buttons/Wrapped_GPIO/out_reg_7> of sequential type is unconnected in block <dbe_bpm_ebone>.
WARNING:Xst:2677 - Node <cmp_buttons/Wrapped_GPIO/out_reg_6> of sequential type is unconnected in block <dbe_bpm_ebone>.
WARNING:Xst:2677 - Node <cmp_buttons/Wrapped_GPIO/out_reg_5> of sequential type is unconnected in block <dbe_bpm_ebone>.
WARNING:Xst:2677 - Node <cmp_buttons/Wrapped_GPIO/out_reg_4> of sequential type is unconnected in block <dbe_bpm_ebone>.
WARNING:Xst:2677 - Node <cmp_buttons/Wrapped_GPIO/out_reg_3> of sequential type is unconnected in block <dbe_bpm_ebone>.
WARNING:Xst:2677 - Node <cmp_buttons/Wrapped_GPIO/out_reg_2> of sequential type is unconnected in block <dbe_bpm_ebone>.
WARNING:Xst:2677 - Node <cmp_buttons/Wrapped_GPIO/out_reg_1> of sequential type is unconnected in block <dbe_bpm_ebone>.
WARNING:Xst:2677 - Node <cmp_buttons/Wrapped_GPIO/out_reg_0> of sequential type is unconnected in block <dbe_bpm_ebone>.
WARNING:Xst:2677 - Node <cmp_leds/Wrapped_GPIO/GEN_SYNC_FFS[7].INPUT_SYNC/ppulse_o> of sequential type is unconnected in block <dbe_bpm_ebone>.
WARNING:Xst:2677 - Node <cmp_leds/Wrapped_GPIO/GEN_SYNC_FFS[7].INPUT_SYNC/npulse_o> of sequential type is unconnected in block <dbe_bpm_ebone>.
WARNING:Xst:2677 - Node <cmp_leds/Wrapped_GPIO/GEN_SYNC_FFS[6].INPUT_SYNC/ppulse_o> of sequential type is unconnected in block <dbe_bpm_ebone>.
WARNING:Xst:2677 - Node <cmp_leds/Wrapped_GPIO/GEN_SYNC_FFS[6].INPUT_SYNC/npulse_o> of sequential type is unconnected in block <dbe_bpm_ebone>.
WARNING:Xst:2677 - Node <cmp_leds/Wrapped_GPIO/GEN_SYNC_FFS[5].INPUT_SYNC/ppulse_o> of sequential type is unconnected in block <dbe_bpm_ebone>.
WARNING:Xst:2677 - Node <cmp_leds/Wrapped_GPIO/GEN_SYNC_FFS[5].INPUT_SYNC/npulse_o> of sequential type is unconnected in block <dbe_bpm_ebone>.
WARNING:Xst:2677 - Node <cmp_leds/Wrapped_GPIO/GEN_SYNC_FFS[4].INPUT_SYNC/ppulse_o> of sequential type is unconnected in block <dbe_bpm_ebone>.
WARNING:Xst:2677 - Node <cmp_leds/Wrapped_GPIO/GEN_SYNC_FFS[4].INPUT_SYNC/npulse_o> of sequential type is unconnected in block <dbe_bpm_ebone>.
WARNING:Xst:2677 - Node <cmp_leds/Wrapped_GPIO/GEN_SYNC_FFS[3].INPUT_SYNC/ppulse_o> of sequential type is unconnected in block <dbe_bpm_ebone>.
WARNING:Xst:2677 - Node <cmp_leds/Wrapped_GPIO/GEN_SYNC_FFS[3].INPUT_SYNC/npulse_o> of sequential type is unconnected in block <dbe_bpm_ebone>.
WARNING:Xst:2677 - Node <cmp_leds/Wrapped_GPIO/GEN_SYNC_FFS[2].INPUT_SYNC/ppulse_o> of sequential type is unconnected in block <dbe_bpm_ebone>.
WARNING:Xst:2677 - Node <cmp_leds/Wrapped_GPIO/GEN_SYNC_FFS[2].INPUT_SYNC/npulse_o> of sequential type is unconnected in block <dbe_bpm_ebone>.
WARNING:Xst:2677 - Node <cmp_leds/Wrapped_GPIO/GEN_SYNC_FFS[1].INPUT_SYNC/ppulse_o> of sequential type is unconnected in block <dbe_bpm_ebone>.
WARNING:Xst:2677 - Node <cmp_leds/Wrapped_GPIO/GEN_SYNC_FFS[1].INPUT_SYNC/npulse_o> of sequential type is unconnected in block <dbe_bpm_ebone>.
WARNING:Xst:2677 - Node <cmp_leds/Wrapped_GPIO/GEN_SYNC_FFS[0].INPUT_SYNC/ppulse_o> of sequential type is unconnected in block <dbe_bpm_ebone>.
WARNING:Xst:2677 - Node <cmp_leds/Wrapped_GPIO/GEN_SYNC_FFS[0].INPUT_SYNC/npulse_o> of sequential type is unconnected in block <dbe_bpm_ebone>.
WARNING:Xst:2677 - Node <cmp_buttons/Wrapped_GPIO/GEN_SYNC_FFS[7].INPUT_SYNC/ppulse_o> of sequential type is unconnected in block <dbe_bpm_ebone>.
WARNING:Xst:2677 - Node <cmp_buttons/Wrapped_GPIO/GEN_SYNC_FFS[7].INPUT_SYNC/npulse_o> of sequential type is unconnected in block <dbe_bpm_ebone>.
WARNING:Xst:2677 - Node <cmp_buttons/Wrapped_GPIO/GEN_SYNC_FFS[6].INPUT_SYNC/ppulse_o> of sequential type is unconnected in block <dbe_bpm_ebone>.
WARNING:Xst:2677 - Node <cmp_buttons/Wrapped_GPIO/GEN_SYNC_FFS[6].INPUT_SYNC/npulse_o> of sequential type is unconnected in block <dbe_bpm_ebone>.
WARNING:Xst:2677 - Node <cmp_buttons/Wrapped_GPIO/GEN_SYNC_FFS[5].INPUT_SYNC/ppulse_o> of sequential type is unconnected in block <dbe_bpm_ebone>.
WARNING:Xst:2677 - Node <cmp_buttons/Wrapped_GPIO/GEN_SYNC_FFS[5].INPUT_SYNC/npulse_o> of sequential type is unconnected in block <dbe_bpm_ebone>.
WARNING:Xst:2677 - Node <cmp_buttons/Wrapped_GPIO/GEN_SYNC_FFS[4].INPUT_SYNC/ppulse_o> of sequential type is unconnected in block <dbe_bpm_ebone>.
WARNING:Xst:2677 - Node <cmp_buttons/Wrapped_GPIO/GEN_SYNC_FFS[4].INPUT_SYNC/npulse_o> of sequential type is unconnected in block <dbe_bpm_ebone>.
WARNING:Xst:2677 - Node <cmp_buttons/Wrapped_GPIO/GEN_SYNC_FFS[3].INPUT_SYNC/ppulse_o> of sequential type is unconnected in block <dbe_bpm_ebone>.
WARNING:Xst:2677 - Node <cmp_buttons/Wrapped_GPIO/GEN_SYNC_FFS[3].INPUT_SYNC/npulse_o> of sequential type is unconnected in block <dbe_bpm_ebone>.
WARNING:Xst:2677 - Node <cmp_buttons/Wrapped_GPIO/GEN_SYNC_FFS[2].INPUT_SYNC/ppulse_o> of sequential type is unconnected in block <dbe_bpm_ebone>.
WARNING:Xst:2677 - Node <cmp_buttons/Wrapped_GPIO/GEN_SYNC_FFS[2].INPUT_SYNC/npulse_o> of sequential type is unconnected in block <dbe_bpm_ebone>.
WARNING:Xst:2677 - Node <cmp_buttons/Wrapped_GPIO/GEN_SYNC_FFS[1].INPUT_SYNC/ppulse_o> of sequential type is unconnected in block <dbe_bpm_ebone>.
WARNING:Xst:2677 - Node <cmp_buttons/Wrapped_GPIO/GEN_SYNC_FFS[1].INPUT_SYNC/npulse_o> of sequential type is unconnected in block <dbe_bpm_ebone>.
WARNING:Xst:2677 - Node <cmp_buttons/Wrapped_GPIO/GEN_SYNC_FFS[0].INPUT_SYNC/ppulse_o> of sequential type is unconnected in block <dbe_bpm_ebone>.
WARNING:Xst:2677 - Node <cmp_buttons/Wrapped_GPIO/GEN_SYNC_FFS[0].INPUT_SYNC/npulse_o> of sequential type is unconnected in block <dbe_bpm_ebone>.
WARNING:Xst:2677 - Node <cmp_button_sys_ffs/npulse_o> of sequential type is unconnected in block <dbe_bpm_ebone>.
WARNING:Xst:2677 - Node <cmp_uart/U_Wrapped_UART/U_WB_SLAVE/host_rack_o> of sequential type is unconnected in block <dbe_bpm_ebone>.
WARNING:Xst:2677 - Node <cmp_uart/U_Wrapped_UART/gen_phys_uart.U_RX/RxD_data_error> of sequential type is unconnected in block <dbe_bpm_ebone>.
WARNING:Xst:2677 - Node <cmp_eb_slave_core/RXCTRL/snk_hdr_fsm_ACK> of sequential type is unconnected in block <dbe_bpm_ebone>.
WARNING:Xst:2677 - Node <cmp_eb_slave_core/RXCTRL/uut/A_ACK_o> of sequential type is unconnected in block <dbe_bpm_ebone>.
WARNING:Xst:2677 - Node <cmp_eb_slave_core/RXCTRL/uut/PIPELINED.A_LESSER_B.gather/empty> of sequential type is unconnected in block <dbe_bpm_ebone>.
WARNING:Xst:2677 - Node <cmp_eb_slave_core/RXCTRL/Shift_in/cnt_3> of sequential type is unconnected in block <dbe_bpm_ebone>.
WARNING:Xst:2677 - Node <cmp_eb_slave_core/RXCTRL/Shift_in/cnt_2> of sequential type is unconnected in block <dbe_bpm_ebone>.
WARNING:Xst:2677 - Node <cmp_eb_slave_core/RXCTRL/Shift_in/cnt_1> of sequential type is unconnected in block <dbe_bpm_ebone>.
WARNING:Xst:2677 - Node <cmp_eb_slave_core/RXCTRL/Shift_in/cnt_0> of sequential type is unconnected in block <dbe_bpm_ebone>.
WARNING:Xst:2677 - Node <cmp_eb_slave_core/RXCTRL/Shift_in/sh_reg_159> of sequential type is unconnected in block <dbe_bpm_ebone>.
WARNING:Xst:2677 - Node <cmp_eb_slave_core/RXCTRL/Shift_in/sh_reg_158> of sequential type is unconnected in block <dbe_bpm_ebone>.
WARNING:Xst:2677 - Node <cmp_eb_slave_core/RXCTRL/Shift_in/sh_reg_157> of sequential type is unconnected in block <dbe_bpm_ebone>.
WARNING:Xst:2677 - Node <cmp_eb_slave_core/RXCTRL/Shift_in/sh_reg_156> of sequential type is unconnected in block <dbe_bpm_ebone>.
WARNING:Xst:2677 - Node <cmp_eb_slave_core/RXCTRL/Shift_in/sh_reg_151> of sequential type is unconnected in block <dbe_bpm_ebone>.
WARNING:Xst:2677 - Node <cmp_eb_slave_core/RXCTRL/Shift_in/sh_reg_150> of sequential type is unconnected in block <dbe_bpm_ebone>.
WARNING:Xst:2677 - Node <cmp_eb_slave_core/RXCTRL/Shift_in/sh_reg_149> of sequential type is unconnected in block <dbe_bpm_ebone>.
WARNING:Xst:2677 - Node <cmp_eb_slave_core/RXCTRL/Shift_in/sh_reg_148> of sequential type is unconnected in block <dbe_bpm_ebone>.
WARNING:Xst:2677 - Node <cmp_eb_slave_core/RXCTRL/Shift_in/sh_reg_147> of sequential type is unconnected in block <dbe_bpm_ebone>.
WARNING:Xst:2677 - Node <cmp_eb_slave_core/RXCTRL/Shift_in/sh_reg_146> of sequential type is unconnected in block <dbe_bpm_ebone>.
WARNING:Xst:2677 - Node <cmp_eb_slave_core/RXCTRL/Shift_in/sh_reg_145> of sequential type is unconnected in block <dbe_bpm_ebone>.
WARNING:Xst:2677 - Node <cmp_eb_slave_core/RXCTRL/Shift_in/sh_reg_144> of sequential type is unconnected in block <dbe_bpm_ebone>.
WARNING:Xst:2677 - Node <cmp_eb_slave_core/RXCTRL/Shift_in/full> of sequential type is unconnected in block <dbe_bpm_ebone>.
WARNING:Xst:2677 - Node <cmp_eb_slave_core/RXCTRL/Shift_in/empty> of sequential type is unconnected in block <dbe_bpm_ebone>.
WARNING:Xst:2677 - Node <cmp_eb_slave_core/EB/s_EB_RX_ACK> of sequential type is unconnected in block <dbe_bpm_ebone>.
WARNING:Xst:2677 - Node <cmp_eb_slave_core/EB/RX_FIFO/wrapped_gen/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1> of sequential type is unconnected in block <dbe_bpm_ebone>.
WARNING:Xst:2677 - Node <cmp_eb_slave_core/EB/RX_FIFO/wrapped_gen/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_0> of sequential type is unconnected in block <dbe_bpm_ebone>.
WARNING:Xst:2677 - Node <cmp_eb_slave_core/EB/TX_FIFO/wrapped_gen/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_1> of sequential type is unconnected in block <dbe_bpm_ebone>.
WARNING:Xst:2677 - Node <cmp_eb_slave_core/EB/TX_FIFO/wrapped_gen/grf.rf/rstblk/ngwrdrst.grst.wr_rst_reg_0> of sequential type is unconnected in block <dbe_bpm_ebone>.
WARNING:Xst:2677 - Node <cmp_eb_slave_core/EB/RX_FIFO/wrapped_gen/grf.rf/gl0.wr/gwss.wsts/ram_full_i> of sequential type is unconnected in block <dbe_bpm_ebone>.
WARNING:Xst:2677 - Node <cmp_eb_slave_core/TXCTRL/uut/A_ACK_o> of sequential type is unconnected in block <dbe_bpm_ebone>.
WARNING:Xst:2677 - Node <cmp_eb_slave_core/TXCTRL/Shift_out/sh_cnt_8> of sequential type is unconnected in block <dbe_bpm_ebone>.
WARNING:Xst:2677 - Node <cmp_eb_slave_core/TXCTRL/Shift_out/sh_cnt_7> of sequential type is unconnected in block <dbe_bpm_ebone>.
WARNING:Xst:2677 - Node <cmp_eb_slave_core/TXCTRL/Shift_out/sh_cnt_6> of sequential type is unconnected in block <dbe_bpm_ebone>.
WARNING:Xst:2677 - Node <cmp_eb_slave_core/TXCTRL/Shift_out/sh_cnt_5> of sequential type is unconnected in block <dbe_bpm_ebone>.
WARNING:Xst:2677 - Node <cmp_eb_slave_core/TXCTRL/Shift_out/sh_cnt_4> of sequential type is unconnected in block <dbe_bpm_ebone>.
WARNING:Xst:2677 - Node <cmp_eb_slave_core/TXCTRL/Shift_out/sh_cnt_3> of sequential type is unconnected in block <dbe_bpm_ebone>.
WARNING:Xst:2677 - Node <cmp_eb_slave_core/TXCTRL/Shift_out/sh_cnt_2> of sequential type is unconnected in block <dbe_bpm_ebone>.
WARNING:Xst:2677 - Node <cmp_eb_slave_core/TXCTRL/Shift_out/sh_cnt_1> of sequential type is unconnected in block <dbe_bpm_ebone>.
WARNING:Xst:2677 - Node <cmp_eb_slave_core/TXCTRL/Shift_out/sh_cnt_0> of sequential type is unconnected in block <dbe_bpm_ebone>.
WARNING:Xst:2677 - Node <cmp_eb_slave_core/TXCTRL/Shift_out/full> of sequential type is unconnected in block <dbe_bpm_ebone>.
WARNING:Xst:2677 - Node <cmp_xwb_ethmac_adapter/cmp_rx_adapter_32_to_16/A_ACK_o> of sequential type is unconnected in block <dbe_bpm_ebone>.
WARNING:Xst:2677 - Node <cmp_xwb_ethmac_adapter/cmp_tx_adapter_16_to_32/PIPELINED.A_LESSER_B.gather/empty> of sequential type is unconnected in block <dbe_bpm_ebone>.
WARNING:Xst:2677 - Node <cmp_xwb_ethmac_adapter/cmp_tx_adapter_16_to_32/A_ACK_o> of sequential type is unconnected in block <dbe_bpm_ebone>.
WARNING:Xst:2677 - Node <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_w_30> of sequential type is unconnected in block <dbe_bpm_ebone>.
WARNING:Xst:2677 - Node <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_w_29> of sequential type is unconnected in block <dbe_bpm_ebone>.
WARNING:Xst:2677 - Node <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_w_28> of sequential type is unconnected in block <dbe_bpm_ebone>.
WARNING:Xst:2677 - Node <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_w_27> of sequential type is unconnected in block <dbe_bpm_ebone>.
WARNING:Xst:2677 - Node <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_w_26> of sequential type is unconnected in block <dbe_bpm_ebone>.
WARNING:Xst:2677 - Node <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_w_25> of sequential type is unconnected in block <dbe_bpm_ebone>.
WARNING:Xst:2677 - Node <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_w_24> of sequential type is unconnected in block <dbe_bpm_ebone>.
WARNING:Xst:2677 - Node <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_w_23> of sequential type is unconnected in block <dbe_bpm_ebone>.
WARNING:Xst:2677 - Node <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_w_22> of sequential type is unconnected in block <dbe_bpm_ebone>.
WARNING:Xst:2677 - Node <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_w_21> of sequential type is unconnected in block <dbe_bpm_ebone>.
WARNING:Xst:2677 - Node <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_w_20> of sequential type is unconnected in block <dbe_bpm_ebone>.
WARNING:Xst:2677 - Node <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_w_19> of sequential type is unconnected in block <dbe_bpm_ebone>.
WARNING:Xst:2677 - Node <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_w_18> of sequential type is unconnected in block <dbe_bpm_ebone>.
WARNING:Xst:2677 - Node <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_w_17> of sequential type is unconnected in block <dbe_bpm_ebone>.
WARNING:Xst:2677 - Node <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_w_16> of sequential type is unconnected in block <dbe_bpm_ebone>.
WARNING:Xst:2677 - Node <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_w_15> of sequential type is unconnected in block <dbe_bpm_ebone>.
WARNING:Xst:2677 - Node <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_w_14> of sequential type is unconnected in block <dbe_bpm_ebone>.
WARNING:Xst:2677 - Node <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_w_13> of sequential type is unconnected in block <dbe_bpm_ebone>.
WARNING:Xst:2677 - Node <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_w_12> of sequential type is unconnected in block <dbe_bpm_ebone>.
WARNING:Xst:2677 - Node <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_w_11> of sequential type is unconnected in block <dbe_bpm_ebone>.
WARNING:Xst:2677 - Node <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_w_10> of sequential type is unconnected in block <dbe_bpm_ebone>.
WARNING:Xst:2677 - Node <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_w_9> of sequential type is unconnected in block <dbe_bpm_ebone>.
WARNING:Xst:2677 - Node <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_w_8> of sequential type is unconnected in block <dbe_bpm_ebone>.
WARNING:Xst:2677 - Node <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_w_7> of sequential type is unconnected in block <dbe_bpm_ebone>.
WARNING:Xst:2677 - Node <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_w_6> of sequential type is unconnected in block <dbe_bpm_ebone>.
WARNING:Xst:2677 - Node <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_w_5> of sequential type is unconnected in block <dbe_bpm_ebone>.
WARNING:Xst:2677 - Node <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_w_4> of sequential type is unconnected in block <dbe_bpm_ebone>.
WARNING:Xst:2677 - Node <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_w_3> of sequential type is unconnected in block <dbe_bpm_ebone>.
WARNING:Xst:2677 - Node <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_w_2> of sequential type is unconnected in block <dbe_bpm_ebone>.
WARNING:Xst:638 - in unit dbe_bpm_ebone Conflict on KEEP property on signal cmp_ethmac_buf_ram/U_DPRAM/gen_single_clk.U_RAM_SC/s_we_b<0> and cmp_ethmac_buf_ram/U_DPRAM/gen_single_clk.U_RAM_SC/s_we_b<1> cmp_ethmac_buf_ram/U_DPRAM/gen_single_clk.U_RAM_SC/s_we_b<1> signal will be lost.
WARNING:Xst:638 - in unit dbe_bpm_ebone Conflict on KEEP property on signal cmp_ethmac_buf_ram/U_DPRAM/gen_single_clk.U_RAM_SC/s_we_b<0> and cmp_ethmac_buf_ram/U_DPRAM/gen_single_clk.U_RAM_SC/s_we_b<2> cmp_ethmac_buf_ram/U_DPRAM/gen_single_clk.U_RAM_SC/s_we_b<2> signal will be lost.
WARNING:Xst:638 - in unit dbe_bpm_ebone Conflict on KEEP property on signal cmp_ethmac_buf_ram/U_DPRAM/gen_single_clk.U_RAM_SC/s_we_b<0> and cmp_ethmac_buf_ram/U_DPRAM/gen_single_clk.U_RAM_SC/s_we_b<3> cmp_ethmac_buf_ram/U_DPRAM/gen_single_clk.U_RAM_SC/s_we_b<3> signal will be lost.
WARNING:Xst:2677 - Node <cmp_xwb_ethmac/cmp_wrapper_wb_ethmac/cmp_wrapper_ethmac/maccontrol1/receivecontrol1/DlyCrcCnt_2> of sequential type is unconnected in block <dbe_bpm_ebone>.
WARNING:Xst:2677 - Node <cmp_xwb_ethmac/cmp_wrapper_wb_ethmac/cmp_wrapper_ethmac/maccontrol1/receivecontrol1/DlyCrcCnt_1> of sequential type is unconnected in block <dbe_bpm_ebone>.
WARNING:Xst:2677 - Node <cmp_xwb_ethmac/cmp_wrapper_wb_ethmac/cmp_wrapper_ethmac/maccontrol1/receivecontrol1/DlyCrcCnt_0> of sequential type is unconnected in block <dbe_bpm_ebone>.
WARNING:Xst:2677 - Node <cmp_xwb_ethmac/cmp_wrapper_wb_ethmac/cmp_wrapper_ethmac/maccontrol1/transmitcontrol1/DlyCrcCnt_2> of sequential type is unconnected in block <dbe_bpm_ebone>.
WARNING:Xst:2677 - Node <cmp_xwb_ethmac/cmp_wrapper_wb_ethmac/cmp_wrapper_ethmac/maccontrol1/transmitcontrol1/DlyCrcCnt_1> of sequential type is unconnected in block <dbe_bpm_ebone>.
WARNING:Xst:2677 - Node <cmp_xwb_ethmac/cmp_wrapper_wb_ethmac/cmp_wrapper_ethmac/maccontrol1/transmitcontrol1/DlyCrcCnt_0> of sequential type is unconnected in block <dbe_bpm_ebone>.
WARNING:Xst:1710 - FF/Latch <cmp_xwb_ethmac/cmp_wrapper_wb_ethmac/cmp_wrapper_ethmac/miim1/clkgen/Counter_7> (without init value) has a constant value of 0 in block <dbe_bpm_ebone>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_button_sys_rst/cntr_30> (without init value) has a constant value of 0 in block <dbe_bpm_ebone>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_button_sys_rst/cntr_29> (without init value) has a constant value of 0 in block <dbe_bpm_ebone>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_button_sys_rst/cntr_31> (without init value) has a constant value of 0 in block <dbe_bpm_ebone>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_button_sys_rst/cntr_28> (without init value) has a constant value of 0 in block <dbe_bpm_ebone>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_button_sys_rst/cntr_27> (without init value) has a constant value of 0 in block <dbe_bpm_ebone>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_button_sys_rst/cntr_26> (without init value) has a constant value of 0 in block <dbe_bpm_ebone>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_button_sys_rst/cntr_25> (without init value) has a constant value of 0 in block <dbe_bpm_ebone>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_button_sys_rst/cntr_24> (without init value) has a constant value of 0 in block <dbe_bpm_ebone>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_button_sys_rst/cntr_23> (without init value) has a constant value of 0 in block <dbe_bpm_ebone>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_button_sys_rst/cntr_22> (without init value) has a constant value of 0 in block <dbe_bpm_ebone>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_button_sys_rst/cntr_21> (without init value) has a constant value of 0 in block <dbe_bpm_ebone>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_button_sys_rst/cntr_8> (without init value) has a constant value of 0 in block <dbe_bpm_ebone>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_button_sys_rst/cntr_9> (without init value) has a constant value of 0 in block <dbe_bpm_ebone>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_button_sys_rst/cntr_10> (without init value) has a constant value of 0 in block <dbe_bpm_ebone>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_button_sys_rst/cntr_11> (without init value) has a constant value of 0 in block <dbe_bpm_ebone>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_button_sys_rst/cntr_12> (without init value) has a constant value of 0 in block <dbe_bpm_ebone>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_button_sys_rst/cntr_13> (without init value) has a constant value of 0 in block <dbe_bpm_ebone>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_button_sys_rst/cntr_16> (without init value) has a constant value of 0 in block <dbe_bpm_ebone>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_button_sys_rst/cntr_14> (without init value) has a constant value of 0 in block <dbe_bpm_ebone>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_button_sys_rst/cntr_15> (without init value) has a constant value of 0 in block <dbe_bpm_ebone>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_button_sys_rst/cntr_17> (without init value) has a constant value of 0 in block <dbe_bpm_ebone>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_button_sys_rst/cntr_18> (without init value) has a constant value of 0 in block <dbe_bpm_ebone>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_button_sys_rst/cntr_19> (without init value) has a constant value of 0 in block <dbe_bpm_ebone>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_button_sys_rst/cntr_20> (without init value) has a constant value of 0 in block <dbe_bpm_ebone>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <cmp_xwb_ethmac/cmp_wrapper_wb_ethmac/cmp_wrapper_ethmac/txethmac1/txcounters1/DlyCrcCnt_2> (without init value) has a constant value of 0 in block <dbe_bpm_ebone>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <cmp_xwb_ethmac/cmp_wrapper_wb_ethmac/cmp_wrapper_ethmac/txethmac1/txcounters1/DlyCrcCnt_1> (without init value) has a constant value of 0 in block <dbe_bpm_ebone>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <cmp_xwb_ethmac/cmp_wrapper_wb_ethmac/cmp_wrapper_ethmac/txethmac1/txcounters1/DlyCrcCnt_0> (without init value) has a constant value of 0 in block <dbe_bpm_ebone>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <cmp_xwb_ethmac/cmp_wrapper_wb_ethmac/cmp_wrapper_ethmac/rxethmac1/rxcounters1/DlyCrcCnt_3> (without init value) has a constant value of 0 in block <dbe_bpm_ebone>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <cmp_xwb_ethmac/cmp_wrapper_wb_ethmac/cmp_wrapper_ethmac/rxethmac1/rxcounters1/DlyCrcCnt_2> (without init value) has a constant value of 0 in block <dbe_bpm_ebone>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <cmp_xwb_ethmac/cmp_wrapper_wb_ethmac/cmp_wrapper_ethmac/rxethmac1/rxcounters1/DlyCrcCnt_1> (without init value) has a constant value of 0 in block <dbe_bpm_ebone>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <cmp_xwb_ethmac/cmp_wrapper_wb_ethmac/cmp_wrapper_ethmac/rxethmac1/rxcounters1/DlyCrcCnt_0> (without init value) has a constant value of 0 in block <dbe_bpm_ebone>. This FF/Latch will be trimmed during the optimization process.
INFO:Xst:2261 - The FF/Latch <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/logic_op_x_3> in Unit <dbe_bpm_ebone> is equivalent to the following FF/Latch, which will be removed : <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/direction_x> 
INFO:Xst:2261 - The FF/Latch <cmp_eb_slave_core/TXCTRL/shift_hdr_chk_sum/sh_cnt_8> in Unit <dbe_bpm_ebone> is equivalent to the following 5 FFs/Latches, which will be removed : <cmp_eb_slave_core/TXCTRL/shift_hdr_chk_sum/sh_cnt_7> <cmp_eb_slave_core/TXCTRL/shift_hdr_chk_sum/sh_cnt_6> <cmp_eb_slave_core/TXCTRL/shift_hdr_chk_sum/sh_cnt_5> <cmp_eb_slave_core/TXCTRL/shift_hdr_chk_sum/sh_cnt_4> <cmp_eb_slave_core/TXCTRL/shift_hdr_chk_sum/sh_cnt_3> 
INFO:Xst:2261 - The FF/Latch <cmp_eb_slave_core/EB/RX_FIFO/wrapped_gen/grf.rf/rstblk/rd_rst_asreg_d1> in Unit <dbe_bpm_ebone> is equivalent to the following 3 FFs/Latches, which will be removed : <cmp_eb_slave_core/EB/RX_FIFO/wrapped_gen/grf.rf/rstblk/wr_rst_asreg_d1> <cmp_eb_slave_core/EB/TX_FIFO/wrapped_gen/grf.rf/rstblk/rd_rst_asreg_d1> <cmp_eb_slave_core/EB/TX_FIFO/wrapped_gen/grf.rf/rstblk/wr_rst_asreg_d1> 
INFO:Xst:2261 - The FF/Latch <cmp_eb_slave_core/EB/RX_FIFO/wrapped_gen/grf.rf/rstblk/rd_rst_asreg_d2> in Unit <dbe_bpm_ebone> is equivalent to the following 3 FFs/Latches, which will be removed : <cmp_eb_slave_core/EB/RX_FIFO/wrapped_gen/grf.rf/rstblk/wr_rst_asreg_d2> <cmp_eb_slave_core/EB/TX_FIFO/wrapped_gen/grf.rf/rstblk/rd_rst_asreg_d2> <cmp_eb_slave_core/EB/TX_FIFO/wrapped_gen/grf.rf/rstblk/wr_rst_asreg_d2> 
INFO:Xst:2261 - The FF/Latch <cmp_uart/U_Wrapped_UART/U_WB_SLAVE/ack_sreg> in Unit <dbe_bpm_ebone> is equivalent to the following FF/Latch, which will be removed : <cmp_uart/U_Wrapped_UART/U_WB_SLAVE/ack_in_progress> 
INFO:Xst:2261 - The FF/Latch <cmp_eb_slave_core/EB/RX_FIFO/wrapped_gen/grf.rf/rstblk/RST_FULL_GEN> in Unit <dbe_bpm_ebone> is equivalent to the following FF/Latch, which will be removed : <cmp_eb_slave_core/EB/TX_FIFO/wrapped_gen/grf.rf/rstblk/RST_FULL_GEN> 
INFO:Xst:2261 - The FF/Latch <cmp_eb_slave_core/EB/RX_FIFO/wrapped_gen/grf.rf/rstblk/rd_rst_asreg> in Unit <dbe_bpm_ebone> is equivalent to the following 3 FFs/Latches, which will be removed : <cmp_eb_slave_core/EB/RX_FIFO/wrapped_gen/grf.rf/rstblk/wr_rst_asreg> <cmp_eb_slave_core/EB/TX_FIFO/wrapped_gen/grf.rf/rstblk/rd_rst_asreg> <cmp_eb_slave_core/EB/TX_FIFO/wrapped_gen/grf.rf/rstblk/wr_rst_asreg> 
INFO:Xst:2261 - The FF/Latch <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/memories[0].way_0_data_ram/ra_2> in Unit <dbe_bpm_ebone> is equivalent to the following FF/Latch, which will be removed : <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/memories[0].way_0_tag_ram/ra_0> 
INFO:Xst:2261 - The FF/Latch <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/memories[0].way_0_data_ram/ra_3> in Unit <dbe_bpm_ebone> is equivalent to the following FF/Latch, which will be removed : <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/memories[0].way_0_tag_ram/ra_1> 
INFO:Xst:2261 - The FF/Latch <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/memories[0].way_0_data_ram/ra_4> in Unit <dbe_bpm_ebone> is equivalent to the following FF/Latch, which will be removed : <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/memories[0].way_0_tag_ram/ra_2> 
INFO:Xst:2261 - The FF/Latch <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/memories[0].way_0_data_ram/ra_5> in Unit <dbe_bpm_ebone> is equivalent to the following FF/Latch, which will be removed : <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/memories[0].way_0_tag_ram/ra_3> 
INFO:Xst:2261 - The FF/Latch <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/memories[0].way_0_data_ram/ra_6> in Unit <dbe_bpm_ebone> is equivalent to the following FF/Latch, which will be removed : <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/memories[0].way_0_tag_ram/ra_4> 
INFO:Xst:2261 - The FF/Latch <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/memories[0].way_0_data_ram/ra_7> in Unit <dbe_bpm_ebone> is equivalent to the following FF/Latch, which will be removed : <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/memories[0].way_0_tag_ram/ra_5> 
INFO:Xst:2261 - The FF/Latch <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/memories[0].way_0_data_ram/ra_8> in Unit <dbe_bpm_ebone> is equivalent to the following FF/Latch, which will be removed : <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/memories[0].way_0_tag_ram/ra_6> 
INFO:Xst:2261 - The FF/Latch <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/memories[0].way_0_data_ram/ra_9> in Unit <dbe_bpm_ebone> is equivalent to the following FF/Latch, which will be removed : <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/memories[0].way_0_tag_ram/ra_7> 
INFO:Xst:2261 - The FF/Latch <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_x> in Unit <dbe_bpm_ebone> is equivalent to the following FF/Latch, which will be removed : <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/w_result_sel_load_x> 
INFO:Xst:2261 - The FF/Latch <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/condition_x_0> in Unit <dbe_bpm_ebone> is equivalent to the following 2 FFs/Latches, which will be removed : <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/logic_op_x_0> <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/size_x_0> 
INFO:Xst:2261 - The FF/Latch <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/condition_x_1> in Unit <dbe_bpm_ebone> is equivalent to the following 2 FFs/Latches, which will be removed : <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/logic_op_x_1> <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/size_x_1> 
INFO:Xst:2261 - The FF/Latch <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/condition_x_2> in Unit <dbe_bpm_ebone> is equivalent to the following 2 FFs/Latches, which will be removed : <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/logic_op_x_2> <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/sign_extend_x> 
INFO:Xst:2261 - The FF/Latch <cmp_xwb_ethmac_adapter/cmp_rx_adapter_32_to_16/PIPELINED.A_GREATER_B.scatter/sh_cnt_1> in Unit <dbe_bpm_ebone> is equivalent to the following 7 FFs/Latches, which will be removed : <cmp_xwb_ethmac_adapter/cmp_rx_adapter_32_to_16/PIPELINED.A_GREATER_B.scatter/sh_cnt_2> <cmp_xwb_ethmac_adapter/cmp_rx_adapter_32_to_16/PIPELINED.A_GREATER_B.scatter/sh_cnt_3> <cmp_xwb_ethmac_adapter/cmp_rx_adapter_32_to_16/PIPELINED.A_GREATER_B.scatter/sh_cnt_4> <cmp_xwb_ethmac_adapter/cmp_rx_adapter_32_to_16/PIPELINED.A_GREATER_B.scatter/sh_cnt_5> <cmp_xwb_ethmac_adapter/cmp_rx_adapter_32_to_16/PIPELINED.A_GREATER_B.scatter/sh_cnt_6> <cmp_xwb_ethmac_adapter/cmp_rx_adapter_32_to_16/PIPELINED.A_GREATER_B.scatter/sh_cnt_7> <cmp_xwb_ethmac_adapter/cmp_rx_adapter_32_to_16/PIPELINED.A_GREATER_B.scatter/sh_cnt_8> 
INFO:Xst:2261 - The FF/Latch <cmp_eb_slave_core/EB/RX_FIFO/wrapped_gen/grf.rf/rstblk/grstd1.grst_full.rst_d1> in Unit <dbe_bpm_ebone> is equivalent to the following FF/Latch, which will be removed : <cmp_eb_slave_core/EB/TX_FIFO/wrapped_gen/grf.rf/rstblk/grstd1.grst_full.rst_d1> 
INFO:Xst:2261 - The FF/Latch <cmp_eb_slave_core/EB/RX_FIFO/wrapped_gen/grf.rf/rstblk/grstd1.grst_full.rst_d2> in Unit <dbe_bpm_ebone> is equivalent to the following FF/Latch, which will be removed : <cmp_eb_slave_core/EB/TX_FIFO/wrapped_gen/grf.rf/rstblk/grstd1.grst_full.rst_d2> 
INFO:Xst:2261 - The FF/Latch <cmp_eb_slave_core/EB/RX_FIFO/wrapped_gen/grf.rf/rstblk/grstd1.grst_full.rst_d3> in Unit <dbe_bpm_ebone> is equivalent to the following FF/Latch, which will be removed : <cmp_eb_slave_core/EB/TX_FIFO/wrapped_gen/grf.rf/rstblk/grstd1.grst_full.rst_d3> 
INFO:Xst:2261 - The FF/Latch <cmp_eb_slave_core/TXCTRL/uut/PIPELINED.A_GREATER_B.scatter/sh_cnt_8> in Unit <dbe_bpm_ebone> is equivalent to the following 7 FFs/Latches, which will be removed : <cmp_eb_slave_core/TXCTRL/uut/PIPELINED.A_GREATER_B.scatter/sh_cnt_7> <cmp_eb_slave_core/TXCTRL/uut/PIPELINED.A_GREATER_B.scatter/sh_cnt_6> <cmp_eb_slave_core/TXCTRL/uut/PIPELINED.A_GREATER_B.scatter/sh_cnt_5> <cmp_eb_slave_core/TXCTRL/uut/PIPELINED.A_GREATER_B.scatter/sh_cnt_4> <cmp_eb_slave_core/TXCTRL/uut/PIPELINED.A_GREATER_B.scatter/sh_cnt_3> <cmp_eb_slave_core/TXCTRL/uut/PIPELINED.A_GREATER_B.scatter/sh_cnt_2> <cmp_eb_slave_core/TXCTRL/uut/PIPELINED.A_GREATER_B.scatter/sh_cnt_1> 
INFO:Xst:3203 - The FF/Latch <cmp_eb_slave_core/EB/RX_FIFO/wrapped_gen/grf.rf/gl0.rd/rpntr/gc0.count_d1_0> in Unit <dbe_bpm_ebone> is the opposite to the following FF/Latch, which will be removed : <cmp_eb_slave_core/EB/RX_FIFO/wrapped_gen/grf.rf/gl0.rd/rpntr/gc0.count_0> 
INFO:Xst:3203 - The FF/Latch <cmp_eb_slave_core/EB/RX_FIFO/wrapped_gen/grf.rf/gl0.wr/wpntr/gcc0.gc0.count_d1_0> in Unit <dbe_bpm_ebone> is the opposite to the following FF/Latch, which will be removed : <cmp_eb_slave_core/EB/RX_FIFO/wrapped_gen/grf.rf/gl0.wr/wpntr/gcc0.gc0.count_0> 
INFO:Xst:3203 - The FF/Latch <cmp_eb_slave_core/EB/TX_FIFO/wrapped_gen/grf.rf/gl0.rd/rpntr/gc0.count_d1_0> in Unit <dbe_bpm_ebone> is the opposite to the following FF/Latch, which will be removed : <cmp_eb_slave_core/EB/TX_FIFO/wrapped_gen/grf.rf/gl0.rd/rpntr/gc0.count_0> 
INFO:Xst:3203 - The FF/Latch <cmp_eb_slave_core/EB/TX_FIFO/wrapped_gen/grf.rf/gl0.wr/wpntr/gcc0.gc0.count_d1_0> in Unit <dbe_bpm_ebone> is the opposite to the following FF/Latch, which will be removed : <cmp_eb_slave_core/EB/TX_FIFO/wrapped_gen/grf.rf/gl0.wr/wpntr/gcc0.gc0.count_0> 

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block dbe_bpm_ebone, actual ratio is 9.

Final Macro Processing ...

Processing Unit <dbe_bpm_ebone> :
	Found 3-bit shift register for signal <cmp_reset/shifters_0_0>.
	Found 2-bit shift register for signal <cmp_xwb_ethmac/cmp_wrapper_wb_ethmac/cmp_wrapper_ethmac/WillTransmit_q2>.
	Found 2-bit shift register for signal <cmp_xwb_ethmac/cmp_wrapper_wb_ethmac/cmp_wrapper_ethmac/wishbone/rx_shift_ended_wb_shr_2>.
	Found 5-bit shift register for signal <cmp_eb_slave_core/RXCTRL/Shift_in/sh_reg_143>.
	Found 5-bit shift register for signal <cmp_eb_slave_core/RXCTRL/Shift_in/sh_reg_142>.
	Found 5-bit shift register for signal <cmp_eb_slave_core/RXCTRL/Shift_in/sh_reg_141>.
	Found 5-bit shift register for signal <cmp_eb_slave_core/RXCTRL/Shift_in/sh_reg_140>.
	Found 5-bit shift register for signal <cmp_eb_slave_core/RXCTRL/Shift_in/sh_reg_139>.
	Found 5-bit shift register for signal <cmp_eb_slave_core/RXCTRL/Shift_in/sh_reg_138>.
	Found 5-bit shift register for signal <cmp_eb_slave_core/RXCTRL/Shift_in/sh_reg_137>.
	Found 5-bit shift register for signal <cmp_eb_slave_core/RXCTRL/Shift_in/sh_reg_136>.
	Found 2-bit shift register for signal <cmp_button_sys_ffs/sync1>.
Unit <dbe_bpm_ebone> processed.

=========================================================================
Final Register Report

Macro Statistics
# Registers                                            : 5437
 Flip-Flops                                            : 5437
# Shift Registers                                      : 12
 2-bit shift register                                  : 3
 3-bit shift register                                  : 1
 5-bit shift register                                  : 8

=========================================================================

=========================================================================
*                           Partition Report                            *
=========================================================================

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

=========================================================================
*                            Design Summary                             *
=========================================================================

Clock Information:
------------------
------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------+-------+
Clock Signal                                                                                          | Clock buffer(FF name)                                                                         | Load  |
------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------+-------+
sys_clk_p_i                                                                                           | IBUFGDS+BUFG                                                                                  | 11    |
sys_clk_p_i                                                                                           | MMCM_ADV:CLKOUT0                                                                              | 6554  |
mrx_clk_pad_i                                                                                         | BUFGP                                                                                         | 1068  |
mtx_clk_pad_i                                                                                         | BUFGP                                                                                         | 1006  |
cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/jtck                                          | NONE(cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/jtag_cores/jtag_tap/update_delay)| 23    |
cmp_chipscope_icon_0/U0/U_ICON/I_YES_BSCAN.U_BS/iDRCK_LOCAL                                           | BUFG                                                                                          | 731   |
cmp_chipscope_icon_0/CONTROL3<13>(cmp_chipscope_icon_0/U0/U_ICON/U_CTRL_OUT/F_NCP[3].F_CMD[9].U_LCE:O)| NONE(*)(cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_STAT/U_DIRTY_LDC)                   | 1     |
cmp_chipscope_icon_0/CONTROL0<13>(cmp_chipscope_icon_0/U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[9].U_LCE:O)| NONE(*)(cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_STAT/U_DIRTY_LDC)                        | 1     |
cmp_chipscope_icon_0/CONTROL1<13>(cmp_chipscope_icon_0/U0/U_ICON/U_CTRL_OUT/F_NCP[1].F_CMD[9].U_LCE:O)| NONE(*)(cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_STAT/U_DIRTY_LDC)                     | 1     |
cmp_chipscope_icon_0/CONTROL2<13>(cmp_chipscope_icon_0/U0/U_ICON/U_CTRL_OUT/F_NCP[2].F_CMD[9].U_LCE:O)| NONE(*)(cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_STAT/U_DIRTY_LDC)                     | 1     |
cmp_chipscope_icon_0/U0/iUPDATE_OUT                                                                   | NONE(cmp_chipscope_icon_0/U0/U_ICON/U_iDATA_CMD)                                              | 1     |
------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------+-------+
(*) These 4 clock signal(s) are generated by combinatorial logic,
and XST is not able to identify which are the primary clock signals.
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.

Asynchronous Control Signals Information:
----------------------------------------
FindSrcOfAsyncThruGates : 100 (1)
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------+
Control Signal                                                                                                                                                                                                                                                                                                                                                                                            | Buffer(FF name)                                                                                                                                                                                                                                                                                                                                                  | Load  |
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------+
cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/XST_VCC:P)            | NONE(cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36)       | 124   |
cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/XST_VCC:P)          | NONE(cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36)     | 124   |
cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/XST_VCC:P)          | NONE(cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36)     | 124   |
cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/XST_VCC:P)          | NONE(cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36)     | 124   |
cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/XST_VCC:P)          | NONE(cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36)     | 124   |
cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/XST_VCC:P)            | NONE(cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36)       | 124   |
cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/XST_VCC:P)            | NONE(cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36)       | 124   |
cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/XST_VCC:P)            | NONE(cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36)       | 124   |
cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/XST_VCC:P)            | NONE(cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36)       | 124   |
cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/XST_VCC:P)            | NONE(cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36)       | 124   |
cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/XST_VCC:P)            | NONE(cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36)       | 124   |
cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/XST_VCC:P)            | NONE(cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36)       | 124   |
cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/XST_VCC:P)            | NONE(cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36)       | 124   |
cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/XST_VCC:P)            | NONE(cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36)       | 124   |
cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/XST_VCC:P)  | NONE(cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36)  | 124   |
cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36)| 124   |
cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36)| 124   |
cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36)| 124   |
cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36)| 124   |
cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/XST_VCC:P)  | NONE(cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36)  | 124   |
cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/XST_VCC:P)  | NONE(cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36)  | 124   |
cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/XST_VCC:P)  | NONE(cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36)  | 124   |
cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/XST_VCC:P)  | NONE(cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36)  | 124   |
cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/XST_VCC:P)  | NONE(cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36)  | 124   |
cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/XST_VCC:P)  | NONE(cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36)  | 124   |
cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/XST_VCC:P)  | NONE(cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36)  | 124   |
cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/XST_VCC:P)  | NONE(cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36)  | 124   |
cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/XST_VCC:P)  | NONE(cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36)  | 124   |
cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/XST_VCC:P)      | NONE(cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36)    | 124   |
cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/XST_VCC:P)    | NONE(cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36)  | 124   |
cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/XST_VCC:P)    | NONE(cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36)  | 124   |
cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/XST_VCC:P)    | NONE(cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36)  | 124   |
cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/XST_VCC:P)    | NONE(cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36)  | 124   |
cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/XST_VCC:P)      | NONE(cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36)    | 124   |
cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/XST_VCC:P)      | NONE(cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36)    | 124   |
cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/XST_VCC:P)      | NONE(cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36)    | 124   |
cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/XST_VCC:P)      | NONE(cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36)    | 124   |
cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/XST_VCC:P)      | NONE(cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36)    | 124   |
cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/XST_VCC:P)      | NONE(cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36)    | 124   |
cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/XST_VCC:P)      | NONE(cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36)    | 124   |
cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/XST_VCC:P)      | NONE(cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36)    | 124   |
cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/XST_VCC:P)      | NONE(cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36)    | 124   |
cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/XST_VCC:P)      | NONE(cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36)    | 124   |
cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/XST_VCC:P)    | NONE(cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36)  | 124   |
cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/XST_VCC:P)    | NONE(cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36)  | 124   |
cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/XST_VCC:P)    | NONE(cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36)  | 124   |
cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/XST_VCC:P)    | NONE(cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36)  | 124   |
cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/XST_VCC:P)      | NONE(cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36)    | 124   |
cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/XST_VCC:P)      | NONE(cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36)    | 124   |
cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/XST_VCC:P)      | NONE(cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36)    | 124   |
cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/XST_VCC:P)      | NONE(cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36)    | 124   |
cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/XST_VCC:P)      | NONE(cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36)    | 124   |
cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/XST_VCC:P)      | NONE(cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36)    | 124   |
cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/XST_VCC:P)      | NONE(cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36)    | 124   |
cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/XST_VCC:P)      | NONE(cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36)    | 124   |
cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/XST_VCC:P)      | NONE(cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36)    | 124   |
cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/XST_GND:G)             | NONE(cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36)       | 72    |
cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/XST_GND:G)           | NONE(cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36)     | 72    |
cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/XST_GND:G)           | NONE(cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36)     | 72    |
cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/XST_GND:G)           | NONE(cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36)     | 72    |
cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/XST_GND:G)           | NONE(cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36)     | 72    |
cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/XST_GND:G)             | NONE(cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36)       | 72    |
cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/XST_GND:G)             | NONE(cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36)       | 72    |
cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/XST_GND:G)             | NONE(cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36)       | 72    |
cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/XST_GND:G)             | NONE(cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36)       | 72    |
cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/XST_GND:G)             | NONE(cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36)       | 72    |
cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/XST_GND:G)             | NONE(cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36)       | 72    |
cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/XST_GND:G)             | NONE(cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36)       | 72    |
cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/XST_GND:G)             | NONE(cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36)       | 72    |
cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/XST_GND:G)             | NONE(cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36)       | 72    |
cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/XST_GND:G)   | NONE(cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36)  | 72    |
cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36)| 72    |
cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36)| 72    |
cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36)| 72    |
cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36)| 72    |
cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/XST_GND:G)   | NONE(cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36)  | 72    |
cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/XST_GND:G)   | NONE(cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36)  | 72    |
cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/XST_GND:G)   | NONE(cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36)  | 72    |
cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/XST_GND:G)   | NONE(cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36)  | 72    |
cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/XST_GND:G)   | NONE(cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36)  | 72    |
cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/XST_GND:G)   | NONE(cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36)  | 72    |
cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/XST_GND:G)   | NONE(cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36)  | 72    |
cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/XST_GND:G)   | NONE(cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36)  | 72    |
cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/XST_GND:G)   | NONE(cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36)  | 72    |
cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/XST_GND:G)       | NONE(cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36)    | 72    |
cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/XST_GND:G)     | NONE(cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36)  | 72    |
cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/XST_GND:G)     | NONE(cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36)  | 72    |
cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/XST_GND:G)     | NONE(cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36)  | 72    |
cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/XST_GND:G)     | NONE(cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36)  | 72    |
cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/XST_GND:G)       | NONE(cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36)    | 72    |
cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/XST_GND:G)       | NONE(cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36)    | 72    |
cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/XST_GND:G)       | NONE(cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36)    | 72    |
cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/XST_GND:G)       | NONE(cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36)    | 72    |
cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/XST_GND:G)       | NONE(cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36)    | 72    |
cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/XST_GND:G)       | NONE(cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36)    | 72    |
cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/XST_GND:G)       | NONE(cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36)    | 72    |
cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/XST_GND:G)       | NONE(cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36)    | 72    |
cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/XST_GND:G)       | NONE(cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36)    | 72    |
cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/XST_GND:G)       | NONE(cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36)    | 72    |
cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/XST_GND:G)     | NONE(cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36)  | 72    |
cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/XST_GND:G)     | NONE(cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36)  | 72    |
cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/XST_GND:G)     | NONE(cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36)  | 72    |
cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/XST_GND:G)     | NONE(cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36)  | 72    |
cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/XST_GND:G)       | NONE(cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36)    | 72    |
cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/XST_GND:G)       | NONE(cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36)    | 72    |
cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/XST_GND:G)       | NONE(cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36)    | 72    |
cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/XST_GND:G)       | NONE(cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36)    | 72    |
cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/XST_GND:G)       | NONE(cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36)    | 72    |
cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/XST_GND:G)       | NONE(cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36)    | 72    |
cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/XST_GND:G)       | NONE(cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36)    | 72    |
cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/XST_GND:G)       | NONE(cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36)    | 72    |
cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/XST_GND:G)       | NONE(cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36)    | 72    |
cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_STAT/U_ECR_glue_set(cmp_chipscope_ila_0_ethmac/XST_VCC:P)                                                                                                                                                                                                                                                                                                    | NONE(cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36)       | 56    |
cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_STAT/U_ECR_glue_set(cmp_chipscope_ila_1_ethmac_miim/XST_VCC:P)                                                                                                                                                                                                                                                                                          | NONE(cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36)  | 56    |
cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_STAT/U_ECR_glue_set(cmp_chipscope_ila_1_ethmac_rx/XST_VCC:P)                                                                                                                                                                                                                                                                                              | NONE(cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36)    | 56    |
cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_STAT/U_ECR_glue_set(cmp_chipscope_ila_1_ethmac_tx/XST_VCC:P)                                                                                                                                                                                                                                                                                              | NONE(cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36)    | 56    |
cmp_ethmac_buf_ram/U_DPRAM/gen_single_clk.U_RAM_SC/s_we_b<0>(XST_GND:G)                                                                                                                                                                                                                                                                                                                                   | NONE(cmp_eb_slave_core/EB/TX_FIFO/wrapped_gen/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v6_noinit.ram/SDP.SIMPLE_PRIM36.ram)                                                                                                                                                                                             | 10    |
cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/iCAP_WR_EN(cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_INTCAP_F.U_CAPWE1:Q)                                                                                                                                                                                                                                                                 | NONE(cmp_chipscope_ila_0_ethmac/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B18KGT0.u_ramb18/U_RAMB18E1)                                                                                                                                                                              | 8     |
cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/iCAP_WR_EN(cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_INTCAP_F.U_CAPWE1:Q)                                                                                                                                                                                                                                                       | NONE(cmp_chipscope_ila_1_ethmac_miim/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B18KGT0.u_ramb18/U_RAMB18E1)                                                                                                                                                                         | 8     |
cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/iCAP_WR_EN(cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_INTCAP_F.U_CAPWE1:Q)                                                                                                                                                                                                                                                           | NONE(cmp_chipscope_ila_1_ethmac_rx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B18KGT0.u_ramb18/U_RAMB18E1)                                                                                                                                                                           | 8     |
cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/iCAP_WR_EN(cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_INTCAP_F.U_CAPWE1:Q)                                                                                                                                                                                                                                                           | NONE(cmp_chipscope_ila_1_ethmac_tx/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B18KGT0.u_ramb18/U_RAMB18E1)                                                                                                                                                                           | 8     |
cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/reg_write_enable_q_w(cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/reg_write_enable_q_w1:O)                                                                                                                                                                                                                                     | NONE(cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/reg_1/Mram_ram)                                                                                                                                                                                                                                                                                 | 8     |
cmp_xwb_ethmac/cmp_wrapper_wb_ethmac/cmp_wrapper_ethmac/wishbone/ram_we<0>(cmp_xwb_ethmac/cmp_wrapper_wb_ethmac/cmp_wrapper_ethmac/wishbone/ram_we<0>1:O)                                                                                                                                                                                                                                                 | NONE(cmp_xwb_ethmac/cmp_wrapper_wb_ethmac/cmp_wrapper_ethmac/wishbone/bd_ram/Mram_mem1)                                                                                                                                                                                                                                                                          | 6     |
cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/way_mem_we[0]_flushing_OR_12454_o(cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/way_mem_we[0]_flushing_OR_12454_o1:O)                                                                                                                                                           | NONE(cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/memories[0].way_0_tag_ram/Mram_mem)                                                                                                                                                                                                                                     | 4     |
cmp_xwb_ethmac/cmp_wrapper_wb_ethmac/cmp_wrapper_ethmac/wishbone/rx_fifo0_write(cmp_xwb_ethmac/cmp_wrapper_wb_ethmac/cmp_wrapper_ethmac/wishbone/rx_fifo0_write1:O)                                                                                                                                                                                                                                       | NONE(cmp_xwb_ethmac/cmp_wrapper_wb_ethmac/cmp_wrapper_ethmac/wishbone/rx_fifo0/Mram_fifo)                                                                                                                                                                                                                                                                        | 4     |
cmp_xwb_ethmac/cmp_wrapper_wb_ethmac/cmp_wrapper_ethmac/wishbone/rx_fifo1_write(cmp_xwb_ethmac/cmp_wrapper_wb_ethmac/cmp_wrapper_ethmac/wishbone/rx_fifo1_write1:O)                                                                                                                                                                                                                                       | NONE(cmp_xwb_ethmac/cmp_wrapper_wb_ethmac/cmp_wrapper_ethmac/wishbone/rx_fifo1/Mram_fifo)                                                                                                                                                                                                                                                                        | 4     |
cmp_xwb_ethmac/cmp_wrapper_wb_ethmac/cmp_wrapper_ethmac/wishbone/tx_fifo/write_full_AND_11801_o(cmp_xwb_ethmac/cmp_wrapper_wb_ethmac/cmp_wrapper_ethmac/wishbone/tx_fifo/write_full_AND_11801_o1:O)                                                                                                                                                                                                       | NONE(cmp_xwb_ethmac/cmp_wrapper_wb_ethmac/cmp_wrapper_ethmac/wishbone/tx_fifo/Mram_fifo)                                                                                                                                                                                                                                                                         | 4     |
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------+

Timing Summary:
---------------
Speed Grade: -1

   Minimum period: 6.577ns (Maximum Frequency: 152.045MHz)
   Minimum input arrival time before clock: 4.777ns
   Maximum output required time after clock: 1.820ns
   Maximum combinational path delay: No path found

=========================================================================

Process "Synthesize - XST" completed successfully

Started : "Translate".
Running ngdbuild...
Command Line: ngdbuild -intstyle ise -dd _ngo -sd ../../platform/virtex6/chipscope/icon_1_port -sd ../../platform/virtex6/chipscope/icon_2_port -sd ../../platform/virtex6/chipscope/icon_4_port -sd ../../platform/virtex6/chipscope -sd ../../modules/dbe_wishbone/wb_fmc150/netlist -sd ../../modules/dbe_wishbone/wb_fmc516/coregen -nt timestamp -uc /home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_ebone/dbe_bpm_ebone.ucf -p xc6vlx240t-ff1156-1 dbe_bpm_ebone.ngc dbe_bpm_ebone.ngd

Command Line: /opt/Xilinx/13.4/ISE_DS/ISE/bin/lin64/unwrapped/ngdbuild -intstyle
ise -dd _ngo -sd ../../platform/virtex6/chipscope/icon_1_port -sd
../../platform/virtex6/chipscope/icon_2_port -sd
../../platform/virtex6/chipscope/icon_4_port -sd
../../platform/virtex6/chipscope -sd
../../modules/dbe_wishbone/wb_fmc150/netlist -sd
../../modules/dbe_wishbone/wb_fmc516/coregen -nt timestamp -uc
/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_ebone/dbe_bpm_ebone.ucf -p
xc6vlx240t-ff1156-1 dbe_bpm_ebone.ngc dbe_bpm_ebone.ngd

Reading NGO file
"/home/lerwys/Repos/bpm-sw/hdl/syn/dbe_bpm_ebone/dbe_bpm_ebone.ngc" ...
Loading design module "../../platform/virtex6/chipscope/chipscope_ila.ngc"...
Loading design module
"../../platform/virtex6/chipscope/icon_4_port/chipscope_icon_4_port.ngc"...
	/dbe_bpm_ebone/dbe_bpm_ebone
	/dbe_bpm_ebone/cmp_chipscope_ila_1_ethmac_miim
	/dbe_bpm_ebone/cmp_chipscope_ila_0_ethmac
	/dbe_bpm_ebone/cmp_chipscope_ila_1_ethmac_rx
	/dbe_bpm_ebone/cmp_chipscope_ila_1_ethmac_tx

-----------------------------------------------
WARNING:Security:42 - Your software subscription period has lapsed. Your current
version of Xilinx tools will continue to function, but you no longer qualify for
Xilinx software updates or new releases.

-----------------------------------------------

-----------------------------------------------
Gathering constraint information from source properties...
Done.

Annotating constraints to design from ucf file
"/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_ebone/dbe_bpm_ebone.ucf" ...
Resolving constraint associations...
Checking Constraint Associations...
Done...

Checking expanded design ...

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Writing NGD file "dbe_bpm_ebone.ngd" ...
Total REAL time to NGDBUILD completion:  21 sec
Total CPU time to NGDBUILD completion:   20 sec

Writing NGDBUILD log file "dbe_bpm_ebone.bld"...

NGDBUILD done.

Process "Translate" completed successfully

Started : "Map".
Running map...
Command Line: map -intstyle ise -p xc6vlx240t-ff1156-1 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt 2 -ir off -pr off -lc off -power off -o dbe_bpm_ebone_map.ncd dbe_bpm_ebone.ngd dbe_bpm_ebone.pcf
Using target part "6vlx240tff1156-1".
INFO:Map:284 - Map is running with the multi-threading option on. Map currently
   supports the use of up to 2 processors. Based on the the user options and
   machine load, Map will use 2 processors during this run.
vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv
INFO:Security:56 - Part 'xc6vlx240t' is not a WebPack part.
WARNING:Security:9b - No 'ISE' feature version 2012.01 was available for part
'xc6vlx240t'.
WARNING:Security:42 - Your software subscription period has lapsed. Your current
version of Xilinx tools will continue to function, but you no longer qualify for
Xilinx software updates or new releases.
WARNING:Security:42 - Your software subscription period has lapsed. Your current
version of Xilinx tools will continue to function, but you no longer qualify for
Xilinx software updates or new releases.
----------------------------------------------------------------------
Mapping design into LUTs...
Running directed packing...
Running delay-based LUT packing...
Updating timing models...
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
   (.mrp).
Running timing-driven placement...
Total REAL time at the beginning of Placer: 46 secs 
Total CPU  time at the beginning of Placer: 45 secs 

Phase 1.1  Initial Placement Analysis
Phase 1.1  Initial Placement Analysis (Checksum:8c1ca42e) REAL time: 57 secs 

Phase 2.7  Design Feasibility Check
Phase 2.7  Design Feasibility Check (Checksum:8c1ca42e) REAL time: 58 secs 

Phase 3.31  Local Placement Optimization
Phase 3.31  Local Placement Optimization (Checksum:fe0c584d) REAL time: 58 secs 

Phase 4.37  Local Placement Optimization
Phase 4.37  Local Placement Optimization (Checksum:fe0c584d) REAL time: 58 secs 

Phase 5.2  Initial Placement for Architecture Specific Features

Phase 5.2  Initial Placement for Architecture Specific Features
(Checksum:d06d9c09) REAL time: 1 mins 4 secs 

Phase 6.36  Local Placement Optimization
Phase 6.36  Local Placement Optimization (Checksum:d06d9c09) REAL time: 1 mins 4 secs 

Phase 7.30  Global Clock Region Assignment
Phase 7.30  Global Clock Region Assignment (Checksum:d06d9c09) REAL time: 1 mins 4 secs 

Phase 8.3  Local Placement Optimization
Phase 8.3  Local Placement Optimization (Checksum:d06d9c09) REAL time: 1 mins 4 secs 

Phase 9.5  Local Placement Optimization
Phase 9.5  Local Placement Optimization (Checksum:d06d9c09) REAL time: 1 mins 4 secs 

Phase 10.8  Global Placement
........................................
......................................................................................................................................................................................
............................................................................
......................
Phase 10.8  Global Placement (Checksum:76d2473e) REAL time: 1 mins 30 secs 

Phase 11.5  Local Placement Optimization
Phase 11.5  Local Placement Optimization (Checksum:76d2473e) REAL time: 1 mins 30 secs 

Phase 12.18  Placement Optimization
Phase 12.18  Placement Optimization (Checksum:5085956) REAL time: 1 mins 56 secs 

Phase 13.5  Local Placement Optimization
Phase 13.5  Local Placement Optimization (Checksum:5085956) REAL time: 1 mins 56 secs 

Phase 14.34  Placement Validation
Phase 14.34  Placement Validation (Checksum:ddc915e9) REAL time: 1 mins 57 secs 

Total REAL time to Placer completion: 1 mins 57 secs 
Total CPU  time to Placer completion: 2 mins 6 secs 
Running post-placement packing...
Writing output files...

Design Summary:
Number of errors:      0
Number of warnings:    9
Slice Logic Utilization:
  Number of Slice Registers:                 8,298 out of 301,440    2%
    Number used as Flip Flops:               8,292
    Number used as Latches:                      5
    Number used as Latch-thrus:                  0
    Number used as AND/OR logics:                1
  Number of Slice LUTs:                     10,984 out of 150,720    7%
    Number used as logic:                    9,634 out of 150,720    6%
      Number using O6 output only:           7,562
      Number using O5 output only:             430
      Number using O5 and O6:                1,642
      Number used as ROM:                        0
    Number used as Memory:                     712 out of  58,400    1%
      Number used as Dual Port RAM:             24
        Number using O6 output only:             4
        Number using O5 output only:             0
        Number using O5 and O6:                 20
      Number used as Single Port RAM:            0
      Number used as Shift Register:           688
        Number using O6 output only:           460
        Number using O5 output only:             0
        Number using O5 and O6:                228
    Number used exclusively as route-thrus:    638
      Number with same-slice register load:    602
      Number with same-slice carry load:        36
      Number with other load:                    0

Slice Logic Distribution:
  Number of occupied Slices:                 3,901 out of  37,680   10%
  Number of LUT Flip Flop pairs used:       12,676
    Number with an unused Flip Flop:         5,808 out of  12,676   45%
    Number with an unused LUT:               1,692 out of  12,676   13%
    Number of fully used LUT-FF pairs:       5,176 out of  12,676   40%
    Number of unique control sets:             428
    Number of slice register sites lost
      to control set restrictions:           1,343 out of 301,440    1%

  A LUT Flip Flop pair for this architecture represents one LUT paired with
  one Flip Flop within a slice.  A control set is a unique combination of
  clock, reset, set, and enable signals for a registered element.
  The Slice Logic Distribution report is not meaningful if the design is
  over-mapped for a non-slice resource or if Placement fails.
  OVERMAPPING of BRAM resources should be ignored if the design is
  over-mapped for a non-BRAM resource or if placement fails.

IO Utilization:
  Number of bonded IOBs:                        40 out of     600    6%
    Number of LOCed IOBs:                       40 out of      40  100%

Specific Feature Utilization:
  Number of RAMB36E1/FIFO36E1s:                107 out of     416   25%
    Number using RAMB36E1 only:                107
    Number using FIFO36E1 only:                  0
  Number of RAMB18E1/FIFO18E1s:                 12 out of     832    1%
    Number using RAMB18E1 only:                 12
    Number using FIFO18E1 only:                  0
  Number of BUFG/BUFGCTRLs:                      7 out of      32   21%
    Number used as BUFGs:                        7
    Number used as BUFGCTRLs:                    0
  Number of ILOGICE1/ISERDESE1s:                 0 out of     720    0%
  Number of OLOGICE1/OSERDESE1s:                 1 out of     720    1%
    Number used as OLOGICE1s:                    1
    Number used as OSERDESE1s:                   0
  Number of BSCANs:                              2 out of       4   50%
  Number of BUFHCEs:                             0 out of     144    0%
  Number of BUFIODQSs:                           0 out of      72    0%
  Number of BUFRs:                               0 out of      36    0%
  Number of CAPTUREs:                            0 out of       1    0%
  Number of DSP48E1s:                            3 out of     768    1%
  Number of EFUSE_USRs:                          0 out of       1    0%
  Number of FRAME_ECCs:                          0 out of       1    0%
  Number of GTXE1s:                              0 out of      20    0%
  Number of IBUFDS_GTXE1s:                       0 out of      12    0%
  Number of ICAPs:                               0 out of       2    0%
  Number of IDELAYCTRLs:                         0 out of      18    0%
  Number of IODELAYE1s:                          0 out of     720    0%
  Number of MMCM_ADVs:                           1 out of      12    8%
  Number of PCIE_2_0s:                           0 out of       2    0%
  Number of STARTUPs:                            1 out of       1  100%
  Number of SYSMONs:                             0 out of       1    0%
  Number of TEMAC_SINGLEs:                       0 out of       4    0%

  Number of RPM macros:           48
Average Fanout of Non-Clock Nets:                3.87

Peak Memory Usage:  1348 MB
Total REAL time to MAP completion:  2 mins 8 secs 
Total CPU time to MAP completion (all processors):   2 mins 16 secs 

Mapping completed.
See MAP report file "dbe_bpm_ebone_map.mrp" for details.

Process "Map" completed successfully

Started : "Place & Route".
Running par...
Command Line: par -w -intstyle ise -ol high -mt off dbe_bpm_ebone_map.ncd dbe_bpm_ebone.ncd dbe_bpm_ebone.pcf



Constraints file: dbe_bpm_ebone.pcf.
Loading device for application Rf_Device from file '6vlx240t.nph' in environment /opt/Xilinx/13.4/ISE_DS/ISE/.
   "dbe_bpm_ebone" is an NCD, version 3.2, device xc6vlx240t, package ff1156, speed -1
vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv
INFO:Security:56 - Part 'xc6vlx240t' is not a WebPack part.
WARNING:Security:9b - No 'ISE' feature version 2012.01 was available for part 'xc6vlx240t'.
WARNING:Security:42 - Your software subscription period has lapsed. Your current version of Xilinx tools will continue
to function, but you no longer qualify for Xilinx software updates or new releases.
WARNING:Security:42 - Your software subscription period has lapsed. Your current version of Xilinx tools will continue
to function, but you no longer qualify for Xilinx software updates or new releases.

----------------------------------------------------------------------

Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
Initializing voltage to 0.950 Volts. (default - Range: 0.950 to 1.050 Volts)


Device speed data version:  "PRODUCTION 1.17 2012-01-07".



Device Utilization Summary:

Slice Logic Utilization:
  Number of Slice Registers:                 8,298 out of 301,440    2%
    Number used as Flip Flops:               8,292
    Number used as Latches:                      5
    Number used as Latch-thrus:                  0
    Number used as AND/OR logics:                1
  Number of Slice LUTs:                     10,984 out of 150,720    7%
    Number used as logic:                    9,634 out of 150,720    6%
      Number using O6 output only:           7,562
      Number using O5 output only:             430
      Number using O5 and O6:                1,642
      Number used as ROM:                        0
    Number used as Memory:                     712 out of  58,400    1%
      Number used as Dual Port RAM:             24
        Number using O6 output only:             4
        Number using O5 output only:             0
        Number using O5 and O6:                 20
      Number used as Single Port RAM:            0
      Number used as Shift Register:           688
        Number using O6 output only:           460
        Number using O5 output only:             0
        Number using O5 and O6:                228
    Number used exclusively as route-thrus:    638
      Number with same-slice register load:    602
      Number with same-slice carry load:        36
      Number with other load:                    0

Slice Logic Distribution:
  Number of occupied Slices:                 3,901 out of  37,680   10%
  Number of LUT Flip Flop pairs used:       12,676
    Number with an unused Flip Flop:         5,808 out of  12,676   45%
    Number with an unused LUT:               1,692 out of  12,676   13%
    Number of fully used LUT-FF pairs:       5,176 out of  12,676   40%
    Number of slice register sites lost
      to control set restrictions:               0 out of 301,440    0%

  A LUT Flip Flop pair for this architecture represents one LUT paired with
  one Flip Flop within a slice.  A control set is a unique combination of
  clock, reset, set, and enable signals for a registered element.
  The Slice Logic Distribution report is not meaningful if the design is
  over-mapped for a non-slice resource or if Placement fails.
  OVERMAPPING of BRAM resources should be ignored if the design is
  over-mapped for a non-BRAM resource or if placement fails.

IO Utilization:
  Number of bonded IOBs:                        40 out of     600    6%
    Number of LOCed IOBs:                       40 out of      40  100%

Specific Feature Utilization:
  Number of RAMB36E1/FIFO36E1s:                107 out of     416   25%
    Number using RAMB36E1 only:                107
    Number using FIFO36E1 only:                  0
  Number of RAMB18E1/FIFO18E1s:                 12 out of     832    1%
    Number using RAMB18E1 only:                 12
    Number using FIFO18E1 only:                  0
  Number of BUFG/BUFGCTRLs:                      7 out of      32   21%
    Number used as BUFGs:                        7
    Number used as BUFGCTRLs:                    0
  Number of ILOGICE1/ISERDESE1s:                 0 out of     720    0%
  Number of OLOGICE1/OSERDESE1s:                 1 out of     720    1%
    Number used as OLOGICE1s:                    1
    Number used as OSERDESE1s:                   0
  Number of BSCANs:                              2 out of       4   50%
  Number of BUFHCEs:                             0 out of     144    0%
  Number of BUFIODQSs:                           0 out of      72    0%
  Number of BUFRs:                               0 out of      36    0%
  Number of CAPTUREs:                            0 out of       1    0%
  Number of DSP48E1s:                            3 out of     768    1%
  Number of EFUSE_USRs:                          0 out of       1    0%
  Number of FRAME_ECCs:                          0 out of       1    0%
  Number of GTXE1s:                              0 out of      20    0%
  Number of IBUFDS_GTXE1s:                       0 out of      12    0%
  Number of ICAPs:                               0 out of       2    0%
  Number of IDELAYCTRLs:                         0 out of      18    0%
  Number of IODELAYE1s:                          0 out of     720    0%
  Number of MMCM_ADVs:                           1 out of      12    8%
  Number of PCIE_2_0s:                           0 out of       2    0%
  Number of STARTUPs:                            1 out of       1  100%
  Number of SYSMONs:                             0 out of       1    0%
  Number of TEMAC_SINGLEs:                       0 out of       4    0%


Overall effort level (-ol):   High 
Router effort level (-rl):    High 

Starting initial Timing Analysis.  REAL time: 14 secs 
Finished initial Timing Analysis.  REAL time: 14 secs 

WARNING:Par:288 - The signal cmp_dma/Mram_ring5_RAMD_D1_O has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_dma/Mram_ring4_RAMD_D1_O has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_dma/Mram_ring1_RAMD_D1_O has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_dma/Mram_ring3_RAMD_D1_O has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_dma/Mram_ring2_RAMD_D1_O has no load.  PAR will not attempt to route this signal.
Starting Router


Phase  1  : 92673 unrouted;      REAL time: 18 secs 

Phase  2  : 71706 unrouted;      REAL time: 24 secs 

Phase  3  : 30721 unrouted;      REAL time: 1 mins 1 secs 

Phase  4  : 30721 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 1 mins 8 secs 

Updating file: dbe_bpm_ebone.ncd with current fully routed design.

Phase  5  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 1 mins 26 secs 

Phase  6  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 1 mins 26 secs 

Phase  7  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 1 mins 26 secs 

Phase  8  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 1 mins 26 secs 

Phase  9  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 1 mins 26 secs 

Phase 10  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 1 mins 26 secs 
Total REAL time to Router completion: 1 mins 26 secs 
Total CPU time to Router completion: 1 mins 26 secs 

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

Generating "PAR" statistics.

**************************
Generating Clock Report
**************************

+---------------------+--------------+------+------+------------+-------------+
|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|         CONTROL0<0> |BUFGCTRL_X0Y29| No   |  321 |  0.428     |  2.020      |
+---------------------+--------------+------+------+------------+-------------+
|             clk_sys | BUFGCTRL_X0Y3| No   | 2075 |  0.321     |  1.905      |
+---------------------+--------------+------+------+------------+-------------+
| mrx_clk_pad_i_BUFGP | BUFGCTRL_X0Y1| No   |  267 |  0.361     |  2.007      |
+---------------------+--------------+------+------+------------+-------------+
| mtx_clk_pad_i_BUFGP | BUFGCTRL_X0Y0| No   |  265 |  0.335     |  2.019      |
+---------------------+--------------+------+------+------------+-------------+
|         sys_clk_gen |BUFGCTRL_X0Y31| No   |    5 |  0.003     |  1.826      |
+---------------------+--------------+------+------+------------+-------------+
|cmp_chipscope_icon_0 |              |      |      |            |             |
|     /U0/iUPDATE_OUT |         Local|      |    1 |  0.000     |  1.959      |
+---------------------+--------------+------+------+------------+-------------+
|cmp_lm32/gen_profile |              |      |      |            |             |
|_medium_icache_debug |              |      |      |            |             |
|.U_Wrapped_LM32/jtck |              |      |      |            |             |
|                     |         Local|      |    7 |  0.955     |  2.149      |
+---------------------+--------------+------+------+------------+-------------+
|        CONTROL0<13> |         Local|      |    4 |  0.000     |  0.578      |
+---------------------+--------------+------+------+------------+-------------+
|MMCM_PHASE_CALIBRATI |              |      |      |            |             |
|ON_ML_LUT2_60_ML_NEW |              |      |      |            |             |
|                _CLK |         Local|      |    3 |  0.255     |  0.609      |
+---------------------+--------------+------+------+------------+-------------+
|cmp_sys_pll_inst/cmp |              |      |      |            |             |
|     _mmcm_ML_NEW_I1 |         Local|      |    3 |  0.000     |  1.495      |
+---------------------+--------------+------+------+------------+-------------+
|cmp_sys_pll_inst/cmp |              |      |      |            |             |
|    _mmcm_ML_NEW_OUT |         Local|      |    2 |  0.000     |  0.562      |
+---------------------+--------------+------+------+------------+-------------+
|        CONTROL1<13> |         Local|      |    4 |  0.000     |  0.624      |
+---------------------+--------------+------+------+------------+-------------+
|        CONTROL2<13> |         Local|      |    4 |  0.000     |  0.496      |
+---------------------+--------------+------+------+------------+-------------+
|        CONTROL3<13> |         Local|      |    4 |  0.000     |  0.365      |
+---------------------+--------------+------+------+------------+-------------+

* Net Skew is the difference between the minimum and maximum routing
only delays for the net. Note this is different from Clock Skew which
is reported in TRCE timing report. Clock Skew is the difference between
the minimum and maximum path delays which includes logic delays.

* The fanout is the number of component pins not the individual BEL loads,
for example SLICE loads not FF loads.

Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0)



Generating Pad Report.

All signals are completely routed.

WARNING:Par:283 - There are 5 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.

Total REAL time to PAR completion: 1 mins 33 secs 
Total CPU time to PAR completion: 1 mins 32 secs 

Peak Memory Usage:  1227 MB

Placer: Placement generated during map.
Routing: Completed - No errors found.
Timing: Completed - No errors found.

Number of error messages: 0
Number of warning meINFO:TclTasksC:1850 - process run : Generate Programming File is done.
ssages: 7
Number of info messages: 0

Writing design to file dbe_bpm_ebone.ncd



PAR done!

Process "Place & Route" completed successfully

Started : "Generate Post-Place & Route Static Timing".
Running trce...
Command Line: trce -intstyle ise -v 3 -s 1 -n 3 -fastpaths -xml dbe_bpm_ebone.twx dbe_bpm_ebone.ncd -o dbe_bpm_ebone.twr dbe_bpm_ebone.pcf
Loading device for application Rf_Device from file '6vlx240t.nph' in environment
/opt/Xilinx/13.4/ISE_DS/ISE/.
   "dbe_bpm_ebone" is an NCD, version 3.2, device xc6vlx240t, package ff1156,
speed -1

Analysis completed Mon Feb 25 09:32:38 2013
--------------------------------------------------------------------------------

Generating Report ...

Number of warnings: 0
Total time: 26 secs 

Process "Generate Post-Place & Route Static Timing" completed successfully

Started : "Generate Programming File".
Running bitgen...
Command Line: bitgen -intstyle ise -f dbe_bpm_ebone.ut dbe_bpm_ebone.ncd
INFO:Bitgen:40 - Replacing "Auto" with "NoWait" for option "Match_cycle".  Most
   commonly, bitgen has determined and will use a specific value instead of the
   generic command-line value of "Auto".  Alternately, this message appears if
   the same option is specified multiple times on the command-line.  In this
   case, the option listed last will be used.
WARNING:PhysDesignRules:372 - Gated clock. Clock net CONTROL0<13> is sourced by
   a combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net CONTROL1<13> is sourced by
   a combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net CONTROL2<13> is sourced by
   a combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net CONTROL3<13> is sourced by
   a combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.
WARNING:PhysDesignRules:367 - The signal <cmp_dma/Mram_ring5_RAMD_D1_O> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <cmp_dma/Mram_ring4_RAMD_D1_O> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <cmp_dma/Mram_ring1_RAMD_D1_O> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <cmp_dma/Mram_ring3_RAMD_D1_O> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <cmp_dma/Mram_ring2_RAMD_D1_O> is
   incomplete. The signal does not drive any load pins in the design.

Process "Generate Programming File" completed successfully
