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		<property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
		<property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
		<property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
		<property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
		<property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
		<property xil_pn:name="Reduce Control Sets" xil_pn:value="Auto" xil_pn:valueState="default"/>
		<property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
		<property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
		<property xil_pn:name="Register Duplication Map" xil_pn:value="Off" xil_pn:valueState="default"/>
		<property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
		<property xil_pn:name="Register Ordering virtex6" xil_pn:value="4" xil_pn:valueState="default"/>
		<property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
		<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
		<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
		<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="" xil_pn:valueState="default"/>
		<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
		<property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
		<property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
		<property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
		<property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
		<property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
		<property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
		<property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
		<property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
		<property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
		<property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
		<property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
		<property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
		<property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
		<property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
		<property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
		<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
		<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
		<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
		<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
		<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
		<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
		<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
		<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
		<property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
		<property xil_pn:name="Shift Register Minimum Size virtex6" xil_pn:value="2" xil_pn:valueState="default"/>
		<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
		<property xil_pn:name="Simulation Model Target" xil_pn:value="Verilog" xil_pn:valueState="default"/>
		<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
		<property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
		<property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
		<property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
		<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
		<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
		<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
		<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/>
		<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
		<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
		<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
		<property xil_pn:name="Speed Grade" xil_pn:value="-1" xil_pn:valueState="non-default"/>
		<property xil_pn:name="Starting Address for Fallback Configuration virtex6" xil_pn:value="None" xil_pn:valueState="default"/>
		<property xil_pn:name="Starting Placer Cost Table (1-100)" xil_pn:value="1" xil_pn:valueState="default"/>
		<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
		<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
		<property xil_pn:name="Timing Mode Map" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
		<property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
		<property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
		<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
		<property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
		<property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
		<property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
		<property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
		<property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/>
		<property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
		<property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
		<property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
		<property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
		<property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
		<property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
		<property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
		<property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
		<property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
		<property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
		<property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
		<property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
		<property xil_pn:name="Use DSP Block" xil_pn:value="Auto" xil_pn:valueState="default"/>
		<property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
		<property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
		<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
		<property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
		<property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
		<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
		<property xil_pn:name="User Access Register Value" xil_pn:value="None" xil_pn:valueState="default"/>
		<property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
		<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
		<property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
		<property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
		<property xil_pn:name="Wait for DCI Match (Output Events) virtex5" xil_pn:value="Auto" xil_pn:valueState="default"/>
		<property xil_pn:name="Wait for PLL Lock (Output Events) virtex6" xil_pn:value="No Wait" xil_pn:valueState="default"/>
		<property xil_pn:name="Watchdog Timer Mode virtex5" xil_pn:value="Off" xil_pn:valueState="default"/>
		<property xil_pn:name="Watchdog Timer Value virtex5" xil_pn:value="0x000000" xil_pn:valueState="default"/>
		<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
		<property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
		<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
		<property xil_pn:name="PROP_DesignName" xil_pn:value="dbe_bpm_ebone" xil_pn:valueState="non-default"/>
		<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="virtex6" xil_pn:valueState="default"/>
		<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
		<property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
		<property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
		<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
		<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
		<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
		<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2013-02-16T14:54:42" xil_pn:valueState="non-default"/>
		<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="594C720F7F5218A9D1537E862D1713A4" xil_pn:valueState="non-default"/>
		<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
		<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
</properties>
	<libraries>
		<library xil_pn:name="blk_mem_gen_v4_1"/>
		<library xil_pn:name="fifo_generator_v6_1"/>
</libraries>
	<files>
		<file xil_pn:name="../../../top/ml_605/dbe_bpm_ebone/dbe_bpm_ebone.ucf" xil_pn:type="FILE_UCF">
			<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file>
		<file xil_pn:name="../../../top/ml_605/dbe_bpm_ebone/dbe_bpm_ebone.vhd" xil_pn:type="FILE_VHDL">
			<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
</file>
		<file xil_pn:name="../../../top/ml_605/dbe_bpm_ebone/sys_pll.vhd" xil_pn:type="FILE_VHDL">
			<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
</file>
		<file xil_pn:name="../../../top/ml_605/dbe_bpm_ebone/clk_gen.vhd" xil_pn:type="FILE_VHDL">
			<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
</file>
		<file xil_pn:name="../../../modules/dbe_wishbone/dbe_wishbone_pkg.vhd" xil_pn:type="FILE_VHDL">
			<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
</file>
		<file xil_pn:name="../../../modules/dbe_common/dbe_common_pkg.vhd" xil_pn:type="FILE_VHDL">
			<association xil_pn:name="Implementation" xil_pn:seqID="6"/>
</file>
		<file xil_pn:name="../../../modules/fabric/wr_fabric_pkg.vhd" xil_pn:type="FILE_VHDL">
			<association xil_pn:name="Implementation" xil_pn:seqID="7"/>
</file>
		<file xil_pn:name="../../../modules/fabric/xwb_fabric_sink.vhd" xil_pn:type="FILE_VHDL">
			<association xil_pn:name="Implementation" xil_pn:seqID="8"/>
</file>
		<file xil_pn:name="../../../modules/fabric/xwb_fabric_source.vhd" xil_pn:type="FILE_VHDL">
			<association xil_pn:name="Implementation" xil_pn:seqID="9"/>
</file>
		<file xil_pn:name="../../../modules/fmc_adc_common/fmc_adc_clk.vhd" xil_pn:type="FILE_VHDL">
			<association xil_pn:name="Implementation" xil_pn:seqID="10"/>
</file>
		<file xil_pn:name="../../../modules/fmc_adc_common/fmc_adc_data.vhd" xil_pn:type="FILE_VHDL">
			<association xil_pn:name="Implementation" xil_pn:seqID="11"/>
</file>
		<file xil_pn:name="../../../modules/fmc_adc_common/fmc_adc_dly_iface.vhd" xil_pn:type="FILE_VHDL">
			<association xil_pn:name="Implementation" xil_pn:seqID="12"/>
</file>
		<file xil_pn:name="../../../modules/fmc_adc_common/fmc_adc_buf.vhd" xil_pn:type="FILE_VHDL">
			<association xil_pn:name="Implementation" xil_pn:seqID="13"/>
</file>
		<file xil_pn:name="../../../modules/fmc_adc_common/fmc_adc_iface.vhd" xil_pn:type="FILE_VHDL">
			<association xil_pn:name="Implementation" xil_pn:seqID="14"/>
</file>
		<file xil_pn:name="../../../modules/fmc_adc_common/fmc_adc_sync_chains.vhd" xil_pn:type="FILE_VHDL">
			<association xil_pn:name="Implementation" xil_pn:seqID="15"/>
</file>
		<file xil_pn:name="../../../modules/fmc_adc_common/fmc_adc_pkg.vhd" xil_pn:type="FILE_VHDL">
			<association xil_pn:name="Implementation" xil_pn:seqID="16"/>
</file>
		<file xil_pn:name="../../../modules/fmc_adc_common/fmc_adc_private_pkg.vhd" xil_pn:type="FILE_VHDL">
			<association xil_pn:name="Implementation" xil_pn:seqID="17"/>
</file>
		<file xil_pn:name="../../../platform/virtex6/chipscope/icon_1_port/chipscope_icon_1_port.ngc" xil_pn:type="FILE_NGC">
			<association xil_pn:name="Implementation" xil_pn:seqID="18"/>
</file>
		<file xil_pn:name="../../../platform/virtex6/chipscope/icon_1_port/chipscope_icon_1_port.vhd" xil_pn:type="FILE_VHDL">
			<association xil_pn:name="Implementation" xil_pn:seqID="19"/>
</file>
		<file xil_pn:name="../../../platform/virtex6/chipscope/icon_2_port/chipscope_icon_2_port.ngc" xil_pn:type="FILE_NGC">
			<association xil_pn:name="Implementation" xil_pn:seqID="20"/>
</file>
		<file xil_pn:name="../../../platform/virtex6/chipscope/icon_4_port/chipscope_icon_4_port.ngc" xil_pn:type="FILE_NGC">
			<association xil_pn:name="Implementation" xil_pn:seqID="21"/>
</file>
		<file xil_pn:name="../../../platform/virtex6/chipscope/icon_4_port/chipscope_icon_4_port.vhd" xil_pn:type="FILE_VHDL">
			<association xil_pn:name="Implementation" xil_pn:seqID="22"/>
</file>
		<file xil_pn:name="../../../platform/virtex6/chipscope/icon_7_port/chipscope_icon_7_port.ngc" xil_pn:type="FILE_NGC">
			<association xil_pn:name="Implementation" xil_pn:seqID="23"/>
</file>
		<file xil_pn:name="../../../platform/virtex6/chipscope/icon_7_port/chipscope_icon_7_port.vhd" xil_pn:type="FILE_VHDL">
			<association xil_pn:name="Implementation" xil_pn:seqID="24"/>
</file>
		<file xil_pn:name="../../../platform/virtex6/chipscope/icon_8_port/chipscope_icon_8_port.ngc" xil_pn:type="FILE_NGC">
			<association xil_pn:name="Implementation" xil_pn:seqID="25"/>
</file>
		<file xil_pn:name="../../../platform/virtex6/chipscope/icon_8_port/chipscope_icon_8_port.vhd" xil_pn:type="FILE_VHDL">
			<association xil_pn:name="Implementation" xil_pn:seqID="26"/>
</file>
		<file xil_pn:name="../../../platform/virtex6/chipscope/icon_13_port/chipscope_icon_13_port.ngc" xil_pn:type="FILE_NGC">
			<association xil_pn:name="Implementation" xil_pn:seqID="27"/>
</file>
		<file xil_pn:name="../../../platform/virtex6/chipscope/icon_13_port/chipscope_icon_13_port.vhd" xil_pn:type="FILE_VHDL">
			<association xil_pn:name="Implementation" xil_pn:seqID="28"/>
</file>
		<file xil_pn:name="../../../platform/virtex6/chipscope/ila/chipscope_ila.ngc" xil_pn:type="FILE_NGC">
			<association xil_pn:name="Implementation" xil_pn:seqID="29"/>
</file>
		<file xil_pn:name="../../../platform/virtex6/chipscope/ila/chipscope_ila.vhd" xil_pn:type="FILE_VHDL">
			<association xil_pn:name="Implementation" xil_pn:seqID="30"/>
</file>
		<file xil_pn:name="../../../platform/virtex6/chipscope/ila/chipscope_ila_1024.ngc" xil_pn:type="FILE_NGC">
			<association xil_pn:name="Implementation" xil_pn:seqID="31"/>
</file>
		<file xil_pn:name="../../../platform/virtex6/chipscope/ila/chipscope_ila_1024.vhd" xil_pn:type="FILE_VHDL">
			<association xil_pn:name="Implementation" xil_pn:seqID="32"/>
</file>
		<file xil_pn:name="../../../platform/virtex6/chipscope/ila/chipscope_ila_4096.ngc" xil_pn:type="FILE_NGC">
			<association xil_pn:name="Implementation" xil_pn:seqID="33"/>
</file>
		<file xil_pn:name="../../../platform/virtex6/chipscope/ila/chipscope_ila_4096.vhd" xil_pn:type="FILE_VHDL">
			<association xil_pn:name="Implementation" xil_pn:seqID="34"/>
</file>
		<file xil_pn:name="../../../platform/virtex6/chipscope/ila/chipscope_ila_8192.ngc" xil_pn:type="FILE_NGC">
			<association xil_pn:name="Implementation" xil_pn:seqID="35"/>
</file>
		<file xil_pn:name="../../../platform/virtex6/chipscope/ila/chipscope_ila_8192.vhd" xil_pn:type="FILE_VHDL">
			<association xil_pn:name="Implementation" xil_pn:seqID="36"/>
</file>
		<file xil_pn:name="../../../platform/virtex6/chipscope/ila/chipscope_ila_32768.ngc" xil_pn:type="FILE_NGC">
			<association xil_pn:name="Implementation" xil_pn:seqID="37"/>
</file>
		<file xil_pn:name="../../../platform/virtex6/chipscope/ila/chipscope_ila_32768.vhd" xil_pn:type="FILE_VHDL">
			<association xil_pn:name="Implementation" xil_pn:seqID="38"/>
</file>
		<file xil_pn:name="../../../platform/virtex6/chipscope/ila/chipscope_ila_65536.ngc" xil_pn:type="FILE_NGC">
			<association xil_pn:name="Implementation" xil_pn:seqID="39"/>
</file>
		<file xil_pn:name="../../../platform/virtex6/chipscope/ila/chipscope_ila_65536.vhd" xil_pn:type="FILE_VHDL">
			<association xil_pn:name="Implementation" xil_pn:seqID="40"/>
</file>
		<file xil_pn:name="../../../platform/virtex6/chipscope/ila/chipscope_ila_131072.ngc" xil_pn:type="FILE_NGC">
			<association xil_pn:name="Implementation" xil_pn:seqID="41"/>
</file>
		<file xil_pn:name="../../../platform/virtex6/chipscope/ila/chipscope_ila_131072.vhd" xil_pn:type="FILE_VHDL">
			<association xil_pn:name="Implementation" xil_pn:seqID="42"/>
</file>
		<file xil_pn:name="../../../platform/virtex6/chipscope/vio/chipscope_vio_256.ngc" xil_pn:type="FILE_NGC">
			<association xil_pn:name="Implementation" xil_pn:seqID="43"/>
</file>
		<file xil_pn:name="../../../platform/virtex6/chipscope/vio/chipscope_vio_256.vhd" xil_pn:type="FILE_VHDL">
			<association xil_pn:name="Implementation" xil_pn:seqID="44"/>
</file>
		<file xil_pn:name="../../../platform/virtex6/ip_cores/dds_adc_input.ngc" xil_pn:type="FILE_NGC">
			<association xil_pn:name="Implementation" xil_pn:seqID="45"/>
</file>
		<file xil_pn:name="../../../platform/virtex6/ip_cores/dds_adc_input.v" xil_pn:type="FILE_VERILOG">
			<association xil_pn:name="Implementation" xil_pn:seqID="46"/>
</file>
		<file xil_pn:name="../../../modules/dbe_wishbone/wb_stream/wb_stream_pkg.vhd" xil_pn:type="FILE_VHDL">
			<association xil_pn:name="Implementation" xil_pn:seqID="47"/>
</file>
		<file xil_pn:name="../../../modules/dbe_wishbone/wb_stream/xwb_stream_sink.vhd" xil_pn:type="FILE_VHDL">
			<association xil_pn:name="Implementation" xil_pn:seqID="48"/>
</file>
		<file xil_pn:name="../../../modules/dbe_wishbone/wb_stream/xwb_stream_source.vhd" xil_pn:type="FILE_VHDL">
			<association xil_pn:name="Implementation" xil_pn:seqID="49"/>
</file>
		<file xil_pn:name="../../../modules/dbe_wishbone/wb_fmc150/wb_fmc150.vhd" xil_pn:type="FILE_VHDL">
			<association xil_pn:name="Implementation" xil_pn:seqID="50"/>
</file>
		<file xil_pn:name="../../../modules/dbe_wishbone/wb_fmc150/xwb_fmc150.vhd" xil_pn:type="FILE_VHDL">
			<association xil_pn:name="Implementation" xil_pn:seqID="51"/>
</file>
		<file xil_pn:name="../../../modules/dbe_wishbone/wb_fmc150/xfmc150_regs_pkg.vhd" xil_pn:type="FILE_VHDL">
			<association xil_pn:name="Implementation" xil_pn:seqID="52"/>
</file>
		<file xil_pn:name="../../../modules/dbe_wishbone/wb_fmc150/wb_fmc150_port.vhd" xil_pn:type="FILE_VHDL">
			<association xil_pn:name="Implementation" xil_pn:seqID="53"/>
</file>
		<file xil_pn:name="../../../modules/dbe_wishbone/wb_fmc516/wb_fmc516.vhd" xil_pn:type="FILE_VHDL">
			<association xil_pn:name="Implementation" xil_pn:seqID="54"/>
</file>
		<file xil_pn:name="../../../modules/dbe_wishbone/wb_fmc516/xwb_fmc516.vhd" xil_pn:type="FILE_VHDL">
			<association xil_pn:name="Implementation" xil_pn:seqID="55"/>
</file>
		<file xil_pn:name="../../../modules/dbe_wishbone/wb_fmc516/wbgen/wb_fmc516_regs_pkg.vhd" xil_pn:type="FILE_VHDL">
			<association xil_pn:name="Implementation" xil_pn:seqID="56"/>
</file>
		<file xil_pn:name="../../../modules/dbe_wishbone/wb_fmc516/wbgen/wb_fmc516_regs.vhd" xil_pn:type="FILE_VHDL">
			<association xil_pn:name="Implementation" xil_pn:seqID="57"/>
</file>
		<file xil_pn:name="../../../modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd" xil_pn:type="FILE_VHDL">
			<association xil_pn:name="Implementation" xil_pn:seqID="58"/>
</file>
		<file xil_pn:name="../../../modules/dbe_wishbone/wb_fmc130m_4ch/xwb_fmc130m_4ch.vhd" xil_pn:type="FILE_VHDL">
			<association xil_pn:name="Implementation" xil_pn:seqID="59"/>
</file>
		<file xil_pn:name="../../../modules/dbe_wishbone/wb_fmc130m_4ch/wbgen/fmc_130m_4ch_regs_pkg.vhd" xil_pn:type="FILE_VHDL">
			<association xil_pn:name="Implementation" xil_pn:seqID="60"/>
</file>
		<file xil_pn:name="../../../modules/dbe_wishbone/wb_fmc130m_4ch/wbgen/fmc_130m_4ch_regs.vhd" xil_pn:type="FILE_VHDL">
			<association xil_pn:name="Implementation" xil_pn:seqID="61"/>
</file>
		<file xil_pn:name="../../../modules/dbe_wishbone/wb_ethmac_adapter/xwb_ethmac_adapter.vhd" xil_pn:type="FILE_VHDL">
			<association xil_pn:name="Implementation" xil_pn:seqID="62"/>
</file>
		<file xil_pn:name="../../../modules/dbe_wishbone/wb_ethmac/timescale.v" xil_pn:type="FILE_VERILOG">
			<association xil_pn:name="Implementation" xil_pn:seqID="63"/>
</file>
		<file xil_pn:name="../../../modules/dbe_wishbone/wb_ethmac/eth_txcounters.v" xil_pn:type="FILE_VERILOG">
			<association xil_pn:name="Implementation" xil_pn:seqID="64"/>
</file>
		<file xil_pn:name="../../../modules/dbe_wishbone/wb_ethmac/eth_clockgen.v" xil_pn:type="FILE_VERILOG">
			<association xil_pn:name="Implementation" xil_pn:seqID="65"/>
</file>
		<file xil_pn:name="../../../modules/dbe_wishbone/wb_ethmac/eth_receivecontrol.v" xil_pn:type="FILE_VERILOG">
			<association xil_pn:name="Implementation" xil_pn:seqID="66"/>
</file>
		<file xil_pn:name="../../../modules/dbe_wishbone/wb_ethmac/eth_txethmac.v" xil_pn:type="FILE_VERILOG">
			<association xil_pn:name="Implementation" xil_pn:seqID="67"/>
</file>
		<file xil_pn:name="../../../modules/dbe_wishbone/wb_ethmac/eth_cop.v" xil_pn:type="FILE_VERILOG">
			<association xil_pn:name="Implementation" xil_pn:seqID="68"/>
</file>
		<file xil_pn:name="../../../modules/dbe_wishbone/wb_ethmac/eth_registers.v" xil_pn:type="FILE_VERILOG">
			<association xil_pn:name="Implementation" xil_pn:seqID="69"/>
</file>
		<file xil_pn:name="../../../modules/dbe_wishbone/wb_ethmac/eth_txstatem.v" xil_pn:type="FILE_VERILOG">
			<association xil_pn:name="Implementation" xil_pn:seqID="70"/>
</file>
		<file xil_pn:name="../../../modules/dbe_wishbone/wb_ethmac/eth_crc.v" xil_pn:type="FILE_VERILOG">
			<association xil_pn:name="Implementation" xil_pn:seqID="71"/>
</file>
		<file xil_pn:name="../../../modules/dbe_wishbone/wb_ethmac/eth_register.v" xil_pn:type="FILE_VERILOG">
			<association xil_pn:name="Implementation" xil_pn:seqID="72"/>
</file>
		<file xil_pn:name="../../../modules/dbe_wishbone/wb_ethmac/eth_wishbone.v" xil_pn:type="FILE_VERILOG">
			<association xil_pn:name="Implementation" xil_pn:seqID="73"/>
</file>
		<file xil_pn:name="../../../modules/dbe_wishbone/wb_ethmac/eth_defines.v" xil_pn:type="FILE_VERILOG">
			<association xil_pn:name="Implementation" xil_pn:seqID="74"/>
</file>
		<file xil_pn:name="../../../modules/dbe_wishbone/wb_ethmac/eth_rxaddrcheck.v" xil_pn:type="FILE_VERILOG">
			<association xil_pn:name="Implementation" xil_pn:seqID="75"/>
</file>
		<file xil_pn:name="../../../modules/dbe_wishbone/wb_ethmac/eth_fifo.v" xil_pn:type="FILE_VERILOG">
			<association xil_pn:name="Implementation" xil_pn:seqID="76"/>
</file>
		<file xil_pn:name="../../../modules/dbe_wishbone/wb_ethmac/eth_rxcounters.v" xil_pn:type="FILE_VERILOG">
			<association xil_pn:name="Implementation" xil_pn:seqID="77"/>
</file>
		<file xil_pn:name="../../../modules/dbe_wishbone/wb_ethmac/eth_random.v" xil_pn:type="FILE_VERILOG">
			<association xil_pn:name="Implementation" xil_pn:seqID="78"/>
</file>
		<file xil_pn:name="../../../ip_cores/general-cores/modules/wishbone/wb_spi_bidir/timescale.v" xil_pn:type="FILE_VERILOG">
			<association xil_pn:name="Implementation" xil_pn:seqID="79"/>
</file>
		<file xil_pn:name="../../../modules/dbe_wishbone/wb_ethmac/eth_rxethmac.v" xil_pn:type="FILE_VERILOG">
			<association xil_pn:name="Implementation" xil_pn:seqID="80"/>
</file>
		<file xil_pn:name="../../../modules/dbe_wishbone/wb_ethmac/ethmac_defines.v" xil_pn:type="FILE_VERILOG">
			<association xil_pn:name="Implementation" xil_pn:seqID="81"/>
</file>
		<file xil_pn:name="../../../modules/dbe_wishbone/wb_ethmac/eth_rxstatem.v" xil_pn:type="FILE_VERILOG">
			<association xil_pn:name="Implementation" xil_pn:seqID="82"/>
</file>
		<file xil_pn:name="../../../modules/dbe_wishbone/wb_ethmac/eth_macstatus.v" xil_pn:type="FILE_VERILOG">
			<association xil_pn:name="Implementation" xil_pn:seqID="83"/>
</file>
		<file xil_pn:name="../../../modules/dbe_wishbone/wb_ethmac/eth_shiftreg.v" xil_pn:type="FILE_VERILOG">
			<association xil_pn:name="Implementation" xil_pn:seqID="84"/>
</file>
		<file xil_pn:name="../../../modules/dbe_wishbone/wb_ethmac/xilinx_dist_ram_16x32.v" xil_pn:type="FILE_VERILOG">
			<association xil_pn:name="Implementation" xil_pn:seqID="85"/>
</file>
		<file xil_pn:name="../../../modules/dbe_wishbone/wb_ethmac/ethmac.v" xil_pn:type="FILE_VERILOG">
			<association xil_pn:name="Implementation" xil_pn:seqID="86"/>
</file>
		<file xil_pn:name="../../../modules/dbe_wishbone/wb_ethmac/eth_spram_256x32.v" xil_pn:type="FILE_VERILOG">
			<association xil_pn:name="Implementation" xil_pn:seqID="87"/>
</file>
		<file xil_pn:name="../../../modules/dbe_wishbone/wb_ethmac/eth_miim.v" xil_pn:type="FILE_VERILOG">
			<association xil_pn:name="Implementation" xil_pn:seqID="88"/>
</file>
		<file xil_pn:name="../../../modules/dbe_wishbone/wb_ethmac/eth_top.v" xil_pn:type="FILE_VERILOG">
			<association xil_pn:name="Implementation" xil_pn:seqID="89"/>
</file>
		<file xil_pn:name="../../../modules/dbe_wishbone/wb_ethmac/eth_outputcontrol.v" xil_pn:type="FILE_VERILOG">
			<association xil_pn:name="Implementation" xil_pn:seqID="90"/>
</file>
		<file xil_pn:name="../../../modules/dbe_wishbone/wb_ethmac/eth_transmitcontrol.v" xil_pn:type="FILE_VERILOG">
			<association xil_pn:name="Implementation" xil_pn:seqID="91"/>
</file>
		<file xil_pn:name="../../../modules/dbe_wishbone/wb_ethmac/wb_ethmac.vhd" xil_pn:type="FILE_VHDL">
			<association xil_pn:name="Implementation" xil_pn:seqID="92"/>
</file>
		<file xil_pn:name="../../../modules/dbe_wishbone/wb_ethmac/xwb_ethmac.vhd" xil_pn:type="FILE_VHDL">
			<association xil_pn:name="Implementation" xil_pn:seqID="93"/>
</file>
		<file xil_pn:name="../../../modules/dbe_wishbone/wb_ethmac/ethmac_pkg.vhd" xil_pn:type="FILE_VHDL">
			<association xil_pn:name="Implementation" xil_pn:seqID="94"/>
</file>
		<file xil_pn:name="../../../modules/dbe_wishbone/wb_dbe_periph/wb_dbe_periph.vhd" xil_pn:type="FILE_VHDL">
			<association xil_pn:name="Implementation" xil_pn:seqID="95"/>
</file>
		<file xil_pn:name="../../../modules/dbe_wishbone/wb_dbe_periph/xwb_dbe_periph.vhd" xil_pn:type="FILE_VHDL">
			<association xil_pn:name="Implementation" xil_pn:seqID="96"/>
</file>
		<file xil_pn:name="../../../modules/dbe_wishbone/wb_rs232_syscon/auto_baud.v" xil_pn:type="FILE_VERILOG">
			<association xil_pn:name="Implementation" xil_pn:seqID="97"/>
</file>
		<file xil_pn:name="../../../modules/dbe_wishbone/wb_rs232_syscon/rs232_syscon.v" xil_pn:type="FILE_VERILOG">
			<association xil_pn:name="Implementation" xil_pn:seqID="98"/>
</file>
		<file xil_pn:name="../../../modules/dbe_wishbone/wb_rs232_syscon/rs232_syscon_top.v" xil_pn:type="FILE_VERILOG">
			<association xil_pn:name="Implementation" xil_pn:seqID="99"/>
</file>
		<file xil_pn:name="../../../modules/dbe_wishbone/wb_rs232_syscon/wb_rs232_syscon.vhd" xil_pn:type="FILE_VHDL">
			<association xil_pn:name="Implementation" xil_pn:seqID="100"/>
</file>
		<file xil_pn:name="../../../modules/dbe_wishbone/wb_rs232_syscon/xwb_rs232_syscon.vhd" xil_pn:type="FILE_VHDL">
			<association xil_pn:name="Implementation" xil_pn:seqID="101"/>
</file>
		<file xil_pn:name="../../../modules/dbe_wishbone/wb_rs232_syscon/serial.v" xil_pn:type="FILE_VERILOG">
			<association xil_pn:name="Implementation" xil_pn:seqID="102"/>
</file>
		<file xil_pn:name="../../../modules/dbe_wishbone/wb_stream/generic/wb_stream_generic_pkg.vhd" xil_pn:type="FILE_VHDL">
			<association xil_pn:name="Implementation" xil_pn:seqID="103"/>
</file>
		<file xil_pn:name="../../../modules/dbe_wishbone/wb_stream/generic/wb_stream_sink_gen.vhd" xil_pn:type="FILE_VHDL">
			<association xil_pn:name="Implementation" xil_pn:seqID="104"/>
</file>
		<file xil_pn:name="../../../modules/dbe_wishbone/wb_stream/generic/wb_stream_source_gen.vhd" xil_pn:type="FILE_VHDL">
			<association xil_pn:name="Implementation" xil_pn:seqID="105"/>
</file>
		<file xil_pn:name="../../../modules/dbe_wishbone/wb_stream/generic/xwb_stream_sink_gen.vhd" xil_pn:type="FILE_VHDL">
			<association xil_pn:name="Implementation" xil_pn:seqID="106"/>
</file>
		<file xil_pn:name="../../../modules/dbe_wishbone/wb_stream/generic/xwb_stream_source_gen.vhd" xil_pn:type="FILE_VHDL">
			<association xil_pn:name="Implementation" xil_pn:seqID="107"/>
</file>
		<file xil_pn:name="../../../modules/dbe_wishbone/wb_fmc150/adc/adc_channel_lvds_ddr.vhd" xil_pn:type="FILE_VHDL">
			<association xil_pn:name="Implementation" xil_pn:seqID="108"/>
</file>
		<file xil_pn:name="../../../modules/dbe_wishbone/wb_fmc150/adc/adc_pkg.vhd" xil_pn:type="FILE_VHDL">
			<association xil_pn:name="Implementation" xil_pn:seqID="109"/>
</file>
		<file xil_pn:name="../../../modules/dbe_wishbone/wb_fmc150/adc/strobe_lvds.vhd" xil_pn:type="FILE_VHDL">
			<association xil_pn:name="Implementation" xil_pn:seqID="110"/>
</file>
		<file xil_pn:name="../../../modules/dbe_wishbone/wb_fmc150/fmc150/ads62p49_ctrl.vhd" xil_pn:type="FILE_VHDL">
			<association xil_pn:name="Implementation" xil_pn:seqID="111"/>
</file>
		<file xil_pn:name="../../../modules/dbe_wishbone/wb_fmc150/fmc150/amc7823_ctrl.vhd" xil_pn:type="FILE_VHDL">
			<association xil_pn:name="Implementation" xil_pn:seqID="112"/>
</file>
		<file xil_pn:name="../../../modules/dbe_wishbone/wb_fmc150/fmc150/cdce72010_ctrl.vhd" xil_pn:type="FILE_VHDL">
			<association xil_pn:name="Implementation" xil_pn:seqID="113"/>
</file>
		<file xil_pn:name="../../../modules/dbe_wishbone/wb_fmc150/fmc150/dac3283_ctrl.vhd" xil_pn:type="FILE_VHDL">
			<association xil_pn:name="Implementation" xil_pn:seqID="114"/>
</file>
		<file xil_pn:name="../../../modules/dbe_wishbone/wb_fmc150/fmc150/fmc150_adc_if.vhd" xil_pn:type="FILE_VHDL">
			<association xil_pn:name="Implementation" xil_pn:seqID="115"/>
</file>
		<file xil_pn:name="../../../modules/dbe_wishbone/wb_fmc150/fmc150/fmc150_dac_if.vhd" xil_pn:type="FILE_VHDL">
			<association xil_pn:name="Implementation" xil_pn:seqID="116"/>
</file>
		<file xil_pn:name="../../../modules/dbe_wishbone/wb_fmc150/fmc150/fmc150_pkg.vhd" xil_pn:type="FILE_VHDL">
			<association xil_pn:name="Implementation" xil_pn:seqID="117"/>
</file>
		<file xil_pn:name="../../../modules/dbe_wishbone/wb_fmc150/fmc150/fmc150_spi_ctrl.vhd" xil_pn:type="FILE_VHDL">
			<association xil_pn:name="Implementation" xil_pn:seqID="118"/>
</file>
		<file xil_pn:name="../../../modules/dbe_wishbone/wb_fmc150/fmc150/fmc150_stellar_cmd.vhd" xil_pn:type="FILE_VHDL">
			<association xil_pn:name="Implementation" xil_pn:seqID="119"/>
</file>
		<file xil_pn:name="../../../modules/dbe_wishbone/wb_fmc150/fmc150/fmc150_testbench.vhd" xil_pn:type="FILE_VHDL">
			<association xil_pn:name="Implementation" xil_pn:seqID="120"/>
</file>
		<file xil_pn:name="../../../modules/dbe_wishbone/wb_fmc150/fmc150/pulse2pulse.vhd" xil_pn:type="FILE_VHDL">
			<association xil_pn:name="Implementation" xil_pn:seqID="121"/>
</file>
		<file xil_pn:name="../../../modules/dbe_wishbone/wb_fmc150/netlist/ads62p49_init_mem.ngc" xil_pn:type="FILE_NGC">
			<association xil_pn:name="Implementation" xil_pn:seqID="122"/>
</file>
		<file xil_pn:name="../../../modules/dbe_wishbone/wb_fmc150/netlist/amc7823_init_mem.ngc" xil_pn:type="FILE_NGC">
			<association xil_pn:name="Implementation" xil_pn:seqID="123"/>
</file>
		<file xil_pn:name="../../../modules/dbe_wishbone/wb_fmc150/netlist/cdce72010_init_mem_ext.ngc" xil_pn:type="FILE_NGC">
			<association xil_pn:name="Implementation" xil_pn:seqID="124"/>
</file>
		<file xil_pn:name="../../../modules/dbe_wishbone/wb_fmc150/netlist/cdce72010_init_mem_int.ngc" xil_pn:type="FILE_NGC">
			<association xil_pn:name="Implementation" xil_pn:seqID="125"/>
</file>
		<file xil_pn:name="../../../modules/dbe_wishbone/wb_fmc150/netlist/dac3283_init_mem.ngc" xil_pn:type="FILE_NGC">
			<association xil_pn:name="Implementation" xil_pn:seqID="126"/>
</file>
		<file xil_pn:name="../../../modules/dbe_common/reset_synch/reset_synch.vhd" xil_pn:type="FILE_VHDL">
			<association xil_pn:name="Implementation" xil_pn:seqID="127"/>
</file>
		<file xil_pn:name="../../../modules/rffe_top/bpm_swap_ctrl/rf_ch_swap.vhd" xil_pn:type="FILE_VHDL">
			<association xil_pn:name="Implementation" xil_pn:seqID="128"/>
</file>
		<file xil_pn:name="../../../modules/rffe_top/bpm_gain_ctrl/utilities_package.vhd" xil_pn:type="FILE_VHDL">
			<association xil_pn:name="Implementation" xil_pn:seqID="129"/>
</file>
		<file xil_pn:name="../../../modules/rffe_top/bpm_gain_ctrl/mc_serial_ctrl.vhd" xil_pn:type="FILE_VHDL">
			<association xil_pn:name="Implementation" xil_pn:seqID="130"/>
</file>
		<file xil_pn:name="../../../ip_cores/general-cores/modules/common/gencores_pkg.vhd" xil_pn:type="FILE_VHDL">
			<association xil_pn:name="Implementation" xil_pn:seqID="131"/>
</file>
		<file xil_pn:name="../../../ip_cores/general-cores/modules/common/gc_crc_gen.vhd" xil_pn:type="FILE_VHDL">
			<association xil_pn:name="Implementation" xil_pn:seqID="132"/>
</file>
		<file xil_pn:name="../../../ip_cores/general-cores/modules/common/gc_moving_average.vhd" xil_pn:type="FILE_VHDL">
			<association xil_pn:name="Implementation" xil_pn:seqID="133"/>
</file>
		<file xil_pn:name="../../../ip_cores/general-cores/modules/common/gc_extend_pulse.vhd" xil_pn:type="FILE_VHDL">
			<association xil_pn:name="Implementation" xil_pn:seqID="134"/>
</file>
		<file xil_pn:name="../../../ip_cores/general-cores/modules/common/gc_ext_pulse_sync.vhd" xil_pn:type="FILE_VHDL">
			<association xil_pn:name="Implementation" xil_pn:seqID="135"/>
</file>
		<file xil_pn:name="../../../ip_cores/general-cores/modules/common/gc_delay_gen.vhd" xil_pn:type="FILE_VHDL">
			<association xil_pn:name="Implementation" xil_pn:seqID="136"/>
</file>
		<file xil_pn:name="../../../ip_cores/general-cores/modules/common/gc_dual_pi_controller.vhd" xil_pn:type="FILE_VHDL">
			<association xil_pn:name="Implementation" xil_pn:seqID="137"/>
</file>
		<file xil_pn:name="../../../ip_cores/general-cores/modules/common/gc_reset.vhd" xil_pn:type="FILE_VHDL">
			<association xil_pn:name="Implementation" xil_pn:seqID="138"/>
</file>
		<file xil_pn:name="../../../ip_cores/general-cores/modules/common/gc_serial_dac.vhd" xil_pn:type="FILE_VHDL">
			<association xil_pn:name="Implementation" xil_pn:seqID="139"/>
</file>
		<file xil_pn:name="../../../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd" xil_pn:type="FILE_VHDL">
			<association xil_pn:name="Implementation" xil_pn:seqID="140"/>
</file>
		<file xil_pn:name="../../../ip_cores/general-cores/modules/common/gc_arbitrated_mux.vhd" xil_pn:type="FILE_VHDL">
			<association xil_pn:name="Implementation" xil_pn:seqID="141"/>
</file>
		<file xil_pn:name="../../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd" xil_pn:type="FILE_VHDL">
			<association xil_pn:name="Implementation" xil_pn:seqID="142"/>
</file>
		<file xil_pn:name="../../../ip_cores/general-cores/modules/common/gc_frequency_meter.vhd" xil_pn:type="FILE_VHDL">
			<association xil_pn:name="Implementation" xil_pn:seqID="143"/>
</file>
		<file xil_pn:name="../../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd" xil_pn:type="FILE_VHDL">
			<association xil_pn:name="Implementation" xil_pn:seqID="144"/>
</file>
		<file xil_pn:name="../../../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd" xil_pn:type="FILE_VHDL">
			<association xil_pn:name="Implementation" xil_pn:seqID="145"/>
</file>
		<file xil_pn:name="../../../ip_cores/general-cores/modules/genrams/generic_shiftreg_fifo.vhd" xil_pn:type="FILE_VHDL">
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		<file xil_pn:name="../../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v6_init.vhd" xil_pn:type="FILE_VHDL">
			<library xil_pn:name="blk_mem_gen_v4_1"/>
			<association xil_pn:name="Implementation" xil_pn:seqID="319"/>
</file>
		<file xil_pn:name="../../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v5.vhd" xil_pn:type="FILE_VHDL">
			<library xil_pn:name="blk_mem_gen_v4_1"/>
			<association xil_pn:name="Implementation" xil_pn:seqID="320"/>
</file>
		<file xil_pn:name="../../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v5_init.vhd" xil_pn:type="FILE_VHDL">
			<library xil_pn:name="blk_mem_gen_v4_1"/>
			<association xil_pn:name="Implementation" xil_pn:seqID="321"/>
</file>
		<file xil_pn:name="../../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v4.vhd" xil_pn:type="FILE_VHDL">
			<library xil_pn:name="blk_mem_gen_v4_1"/>
			<association xil_pn:name="Implementation" xil_pn:seqID="322"/>
</file>
		<file xil_pn:name="../../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v4_init.vhd" xil_pn:type="FILE_VHDL">
			<library xil_pn:name="blk_mem_gen_v4_1"/>
			<association xil_pn:name="Implementation" xil_pn:seqID="323"/>
</file>
		<file xil_pn:name="../../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3.vhd" xil_pn:type="FILE_VHDL">
			<library xil_pn:name="blk_mem_gen_v4_1"/>
			<association xil_pn:name="Implementation" xil_pn:seqID="324"/>
</file>
		<file xil_pn:name="../../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3_init.vhd" xil_pn:type="FILE_VHDL">
			<library xil_pn:name="blk_mem_gen_v4_1"/>
			<association xil_pn:name="Implementation" xil_pn:seqID="325"/>
</file>
		<file xil_pn:name="../../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_width.vhd" xil_pn:type="FILE_VHDL">
			<library xil_pn:name="blk_mem_gen_v4_1"/>
			<association xil_pn:name="Implementation" xil_pn:seqID="326"/>
</file>
		<file xil_pn:name="../../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_generic_cstr.vhd" xil_pn:type="FILE_VHDL">
			<library xil_pn:name="blk_mem_gen_v4_1"/>
			<association xil_pn:name="Implementation" xil_pn:seqID="327"/>
</file>
		<file xil_pn:name="../../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_ecc_encoder.vhd" xil_pn:type="FILE_VHDL">
			<library xil_pn:name="blk_mem_gen_v4_1"/>
			<association xil_pn:name="Implementation" xil_pn:seqID="328"/>
</file>
		<file xil_pn:name="../../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_ecc_decoder.vhd" xil_pn:type="FILE_VHDL">
			<library xil_pn:name="blk_mem_gen_v4_1"/>
			<association xil_pn:name="Implementation" xil_pn:seqID="329"/>
</file>
		<file xil_pn:name="../../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_input_block.vhd" xil_pn:type="FILE_VHDL">
			<library xil_pn:name="blk_mem_gen_v4_1"/>
			<association xil_pn:name="Implementation" xil_pn:seqID="330"/>
</file>
		<file xil_pn:name="../../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_output_block.vhd" xil_pn:type="FILE_VHDL">
			<library xil_pn:name="blk_mem_gen_v4_1"/>
			<association xil_pn:name="Implementation" xil_pn:seqID="331"/>
</file>
		<file xil_pn:name="../../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_top.vhd" xil_pn:type="FILE_VHDL">
			<library xil_pn:name="blk_mem_gen_v4_1"/>
			<association xil_pn:name="Implementation" xil_pn:seqID="332"/>
</file>
		<file xil_pn:name="../../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_v4_1_xst.vhd" xil_pn:type="FILE_VHDL">
			<library xil_pn:name="blk_mem_gen_v4_1"/>
			<association xil_pn:name="Implementation" xil_pn:seqID="333"/>
</file>
		<file xil_pn:name="../../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_v6_1_pkg.vhd" xil_pn:type="FILE_VHDL">
			<library xil_pn:name="fifo_generator_v6_1"/>
			<association xil_pn:name="Implementation" xil_pn:seqID="334"/>
</file>
		<file xil_pn:name="../../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_v6_1_defaults.vhd" xil_pn:type="FILE_VHDL">
			<library xil_pn:name="fifo_generator_v6_1"/>
			<association xil_pn:name="Implementation" xil_pn:seqID="335"/>
</file>
		<file xil_pn:name="../../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_v6_1_xst_comp.vhd" xil_pn:type="FILE_VHDL">
			<library xil_pn:name="fifo_generator_v6_1"/>
			<association xil_pn:name="Implementation" xil_pn:seqID="336"/>
</file>
		<file xil_pn:name="../../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/input_blk.vhd" xil_pn:type="FILE_VHDL">
			<library xil_pn:name="fifo_generator_v6_1"/>
			<association xil_pn:name="Implementation" xil_pn:seqID="337"/>
</file>
		<file xil_pn:name="../../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/output_blk.vhd" xil_pn:type="FILE_VHDL">
			<library xil_pn:name="fifo_generator_v6_1"/>
			<association xil_pn:name="Implementation" xil_pn:seqID="338"/>
</file>
		<file xil_pn:name="../../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/shft_wrapper.vhd" xil_pn:type="FILE_VHDL">
			<library xil_pn:name="fifo_generator_v6_1"/>
			<association xil_pn:name="Implementation" xil_pn:seqID="339"/>
</file>
		<file xil_pn:name="../../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/shft_ram.vhd" xil_pn:type="FILE_VHDL">
			<library xil_pn:name="fifo_generator_v6_1"/>
			<association xil_pn:name="Implementation" xil_pn:seqID="340"/>
</file>
		<file xil_pn:name="../../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/dmem.vhd" xil_pn:type="FILE_VHDL">
			<library xil_pn:name="fifo_generator_v6_1"/>
			<association xil_pn:name="Implementation" xil_pn:seqID="341"/>
</file>
		<file xil_pn:name="../../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/memory.vhd" xil_pn:type="FILE_VHDL">
			<library xil_pn:name="fifo_generator_v6_1"/>
			<association xil_pn:name="Implementation" xil_pn:seqID="342"/>
</file>
		<file xil_pn:name="../../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/compare.vhd" xil_pn:type="FILE_VHDL">
			<library xil_pn:name="fifo_generator_v6_1"/>
			<association xil_pn:name="Implementation" xil_pn:seqID="343"/>
</file>
		<file xil_pn:name="../../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_bin_cntr.vhd" xil_pn:type="FILE_VHDL">
			<library xil_pn:name="fifo_generator_v6_1"/>
			<association xil_pn:name="Implementation" xil_pn:seqID="344"/>
</file>
		<file xil_pn:name="../../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_bin_cntr.vhd" xil_pn:type="FILE_VHDL">
			<library xil_pn:name="fifo_generator_v6_1"/>
			<association xil_pn:name="Implementation" xil_pn:seqID="345"/>
</file>
		<file xil_pn:name="../../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/updn_cntr.vhd" xil_pn:type="FILE_VHDL">
			<library xil_pn:name="fifo_generator_v6_1"/>
			<association xil_pn:name="Implementation" xil_pn:seqID="346"/>
</file>
		<file xil_pn:name="../../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_status_flags_as.vhd" xil_pn:type="FILE_VHDL">
			<library xil_pn:name="fifo_generator_v6_1"/>
			<association xil_pn:name="Implementation" xil_pn:seqID="347"/>
</file>
		<file xil_pn:name="../../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_status_flags_ss.vhd" xil_pn:type="FILE_VHDL">
			<library xil_pn:name="fifo_generator_v6_1"/>
			<association xil_pn:name="Implementation" xil_pn:seqID="348"/>
</file>
		<file xil_pn:name="../../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_pe_as.vhd" xil_pn:type="FILE_VHDL">
			<library xil_pn:name="fifo_generator_v6_1"/>
			<association xil_pn:name="Implementation" xil_pn:seqID="349"/>
</file>
		<file xil_pn:name="../../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_pe_ss.vhd" xil_pn:type="FILE_VHDL">
			<library xil_pn:name="fifo_generator_v6_1"/>
			<association xil_pn:name="Implementation" xil_pn:seqID="350"/>
</file>
		<file xil_pn:name="../../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_handshaking_flags.vhd" xil_pn:type="FILE_VHDL">
			<library xil_pn:name="fifo_generator_v6_1"/>
			<association xil_pn:name="Implementation" xil_pn:seqID="351"/>
</file>
		<file xil_pn:name="../../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_dc_as.vhd" xil_pn:type="FILE_VHDL">
			<library xil_pn:name="fifo_generator_v6_1"/>
			<association xil_pn:name="Implementation" xil_pn:seqID="352"/>
</file>
		<file xil_pn:name="../../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_dc_fwft_ext_as.vhd" xil_pn:type="FILE_VHDL">
			<library xil_pn:name="fifo_generator_v6_1"/>
			<association xil_pn:name="Implementation" xil_pn:seqID="353"/>
</file>
		<file xil_pn:name="../../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/dc_ss.vhd" xil_pn:type="FILE_VHDL">
			<library xil_pn:name="fifo_generator_v6_1"/>
			<association xil_pn:name="Implementation" xil_pn:seqID="354"/>
</file>
		<file xil_pn:name="../../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/dc_ss_fwft.vhd" xil_pn:type="FILE_VHDL">
			<library xil_pn:name="fifo_generator_v6_1"/>
			<association xil_pn:name="Implementation" xil_pn:seqID="355"/>
</file>
		<file xil_pn:name="../../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_fwft.vhd" xil_pn:type="FILE_VHDL">
			<library xil_pn:name="fifo_generator_v6_1"/>
			<association xil_pn:name="Implementation" xil_pn:seqID="356"/>
</file>
		<file xil_pn:name="../../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_logic.vhd" xil_pn:type="FILE_VHDL">
			<library xil_pn:name="fifo_generator_v6_1"/>
			<association xil_pn:name="Implementation" xil_pn:seqID="357"/>
</file>
		<file xil_pn:name="../../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/reset_blk_ramfifo.vhd" xil_pn:type="FILE_VHDL">
			<library xil_pn:name="fifo_generator_v6_1"/>
			<association xil_pn:name="Implementation" xil_pn:seqID="358"/>
</file>
		<file xil_pn:name="../../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/clk_x_pntrs.vhd" xil_pn:type="FILE_VHDL">
			<library xil_pn:name="fifo_generator_v6_1"/>
			<association xil_pn:name="Implementation" xil_pn:seqID="359"/>
</file>
		<file xil_pn:name="../../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_status_flags_as.vhd" xil_pn:type="FILE_VHDL">
			<library xil_pn:name="fifo_generator_v6_1"/>
			<association xil_pn:name="Implementation" xil_pn:seqID="360"/>
</file>
		<file xil_pn:name="../../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_status_flags_ss.vhd" xil_pn:type="FILE_VHDL">
			<library xil_pn:name="fifo_generator_v6_1"/>
			<association xil_pn:name="Implementation" xil_pn:seqID="361"/>
</file>
		<file xil_pn:name="../../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_pf_as.vhd" xil_pn:type="FILE_VHDL">
			<library xil_pn:name="fifo_generator_v6_1"/>
			<association xil_pn:name="Implementation" xil_pn:seqID="362"/>
</file>
		<file xil_pn:name="../../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_pf_ss.vhd" xil_pn:type="FILE_VHDL">
			<library xil_pn:name="fifo_generator_v6_1"/>
			<association xil_pn:name="Implementation" xil_pn:seqID="363"/>
</file>
		<file xil_pn:name="../../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_handshaking_flags.vhd" xil_pn:type="FILE_VHDL">
			<library xil_pn:name="fifo_generator_v6_1"/>
			<association xil_pn:name="Implementation" xil_pn:seqID="364"/>
</file>
		<file xil_pn:name="../../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_dc_as.vhd" xil_pn:type="FILE_VHDL">
			<library xil_pn:name="fifo_generator_v6_1"/>
			<association xil_pn:name="Implementation" xil_pn:seqID="365"/>
</file>
		<file xil_pn:name="../../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_dc_fwft_ext_as.vhd" xil_pn:type="FILE_VHDL">
			<library xil_pn:name="fifo_generator_v6_1"/>
			<association xil_pn:name="Implementation" xil_pn:seqID="366"/>
</file>
		<file xil_pn:name="../../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_logic.vhd" xil_pn:type="FILE_VHDL">
			<library xil_pn:name="fifo_generator_v6_1"/>
			<association xil_pn:name="Implementation" xil_pn:seqID="367"/>
</file>
		<file xil_pn:name="../../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_status_flags_sshft.vhd" xil_pn:type="FILE_VHDL">
			<library xil_pn:name="fifo_generator_v6_1"/>
			<association xil_pn:name="Implementation" xil_pn:seqID="368"/>
</file>
		<file xil_pn:name="../../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_status_flags_sshft.vhd" xil_pn:type="FILE_VHDL">
			<library xil_pn:name="fifo_generator_v6_1"/>
			<association xil_pn:name="Implementation" xil_pn:seqID="369"/>
</file>
		<file xil_pn:name="../../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_pf_sshft.vhd" xil_pn:type="FILE_VHDL">
			<library xil_pn:name="fifo_generator_v6_1"/>
			<association xil_pn:name="Implementation" xil_pn:seqID="370"/>
</file>
		<file xil_pn:name="../../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_pe_sshft.vhd" xil_pn:type="FILE_VHDL">
			<library xil_pn:name="fifo_generator_v6_1"/>
			<association xil_pn:name="Implementation" xil_pn:seqID="371"/>
</file>
		<file xil_pn:name="../../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/logic_sshft.vhd" xil_pn:type="FILE_VHDL">
			<library xil_pn:name="fifo_generator_v6_1"/>
			<association xil_pn:name="Implementation" xil_pn:seqID="372"/>
</file>
		<file xil_pn:name="../../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_ramfifo.vhd" xil_pn:type="FILE_VHDL">
			<library xil_pn:name="fifo_generator_v6_1"/>
			<association xil_pn:name="Implementation" xil_pn:seqID="373"/>
</file>
		<file xil_pn:name="../../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_v6_1_comps_builtin.vhd" xil_pn:type="FILE_VHDL">
			<library xil_pn:name="fifo_generator_v6_1"/>
			<association xil_pn:name="Implementation" xil_pn:seqID="374"/>
</file>
		<file xil_pn:name="../../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/delay.vhd" xil_pn:type="FILE_VHDL">
			<library xil_pn:name="fifo_generator_v6_1"/>
			<association xil_pn:name="Implementation" xil_pn:seqID="375"/>
</file>
		<file xil_pn:name="../../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/clk_x_pntrs_builtin.vhd" xil_pn:type="FILE_VHDL">
			<library xil_pn:name="fifo_generator_v6_1"/>
			<association xil_pn:name="Implementation" xil_pn:seqID="376"/>
</file>
		<file xil_pn:name="../../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/bin_cntr.vhd" xil_pn:type="FILE_VHDL">
			<library xil_pn:name="fifo_generator_v6_1"/>
			<association xil_pn:name="Implementation" xil_pn:seqID="377"/>
</file>
		<file xil_pn:name="../../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/logic_builtin.vhd" xil_pn:type="FILE_VHDL">
			<library xil_pn:name="fifo_generator_v6_1"/>
			<association xil_pn:name="Implementation" xil_pn:seqID="378"/>
</file>
		<file xil_pn:name="../../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/reset_builtin.vhd" xil_pn:type="FILE_VHDL">
			<library xil_pn:name="fifo_generator_v6_1"/>
			<association xil_pn:name="Implementation" xil_pn:seqID="379"/>
</file>
		<file xil_pn:name="../../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/builtin_prim.vhd" xil_pn:type="FILE_VHDL">
			<library xil_pn:name="fifo_generator_v6_1"/>
			<association xil_pn:name="Implementation" xil_pn:seqID="380"/>
</file>
		<file xil_pn:name="../../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/builtin_extdepth.vhd" xil_pn:type="FILE_VHDL">
			<library xil_pn:name="fifo_generator_v6_1"/>
			<association xil_pn:name="Implementation" xil_pn:seqID="381"/>
</file>
		<file xil_pn:name="../../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/builtin_top.vhd" xil_pn:type="FILE_VHDL">
			<library xil_pn:name="fifo_generator_v6_1"/>
			<association xil_pn:name="Implementation" xil_pn:seqID="382"/>
</file>
		<file xil_pn:name="../../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/builtin_prim_v6.vhd" xil_pn:type="FILE_VHDL">
			<library xil_pn:name="fifo_generator_v6_1"/>
			<association xil_pn:name="Implementation" xil_pn:seqID="383"/>
</file>
		<file xil_pn:name="../../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/builtin_extdepth_v6.vhd" xil_pn:type="FILE_VHDL">
			<library xil_pn:name="fifo_generator_v6_1"/>
			<association xil_pn:name="Implementation" xil_pn:seqID="384"/>
</file>
		<file xil_pn:name="../../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/builtin_top_v6.vhd" xil_pn:type="FILE_VHDL">
			<library xil_pn:name="fifo_generator_v6_1"/>
			<association xil_pn:name="Implementation" xil_pn:seqID="385"/>
</file>
		<file xil_pn:name="../../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_v6_1_builtin.vhd" xil_pn:type="FILE_VHDL">
			<library xil_pn:name="fifo_generator_v6_1"/>
			<association xil_pn:name="Implementation" xil_pn:seqID="386"/>
</file>
		<file xil_pn:name="../../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rgtw.vhd" xil_pn:type="FILE_VHDL">
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		<file xil_pn:name="../../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wgtr.vhd" xil_pn:type="FILE_VHDL">
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		<file xil_pn:name="../../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/input_block_fifo16_patch.vhd" xil_pn:type="FILE_VHDL">
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		<file xil_pn:name="../../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/output_block_fifo16_patch.vhd" xil_pn:type="FILE_VHDL">
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		<file xil_pn:name="../../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo16_patch_top.vhd" xil_pn:type="FILE_VHDL">
			<library xil_pn:name="fifo_generator_v6_1"/>
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		<file xil_pn:name="../../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_v6_1_fifo16_patch.vhd" xil_pn:type="FILE_VHDL">
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