#######################################################################
##                      Virtex6 Board ML605                          ##
#######################################################################

NET "sys_clk_n_i"                             LOC = H9   | IOSTANDARD = LVDS_25; # 5 on U11, 5 on U89 (DNP)
NET "sys_clk_p_i"                             LOC = J9   | IOSTANDARD = LVDS_25; # 4 on U11, 4 on U89 (DNP)

NET "rs232_rxd_i"                             LOC = J24  | IOSTANDARD = LVCMOS25; # 25 on U34
NET "rs232_txd_o"                             LOC = J25  | IOSTANDARD = LVCMOS25; # 24 on U34

NET "sys_rst_button_i"                        LOC = H10 | IOSTANDARD = "SSTL15" | TIG;

# MMCM Status
NET "fmc_mmcm_lock_led_o"                     LOC = "AP24"  |  IOSTANDARD = "LVCMOS25"; # GPIO_LED_C, DS16

# LMK clock distribution Status
NET "fmc_pll_status_led_o"                    LOC = "AD21"  |  IOSTANDARD = "LVCMOS25"; # GPIO_LED_W, DS17

#NET "led_south_o"                            LOC = "AH28"  |  IOSTANDARD = "LVCMOS25"; # GPIO_LED_S, DS18
#NET "led_east_o"                             LOC = "AE21"  |  IOSTANDARD = "LVCMOS25"; # GPIO_LED_E, DS19
#NET "led_north_o"                            LOC = "AH27"  |  IOSTANDARD = "LVCMOS25"; # GPIO_LED_N, DS20

#NET "board_led1_o"                           LOC = AC22 | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = SLOW; // User led 0
#NET "board_led2_o"                           LOC = AC24 | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = SLOW; // User led 1
#NET "board_led3_o"                           LOC = AE22 | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = SLOW; // User led 2

NET "clk_swap_o"                              LOC = V34  | IOSTANDARD = LVCMOS25; # USER_SMA_GPIO_P
NET "clk_swap2x_o"                            LOC = L23  | IOSTANDARD = LVCMOS25; # USER_SMA_CLK_P
NET "flag1_o"                                 LOC = W34  | IOSTANDARD = LVCMOS25; # USER_SMA_GPIO_N
NET "flag2_o"                                 LOC = M22  | IOSTANDARD = LVCMOS25; # USER_SMA_CLK_N

#######################################################################
##                      Button/LEDs Contraints                       ##
#######################################################################

#NET "buttons_i[0]"                            LOC = D22 | IOSTANDARD = LVCMOS25;
#NET "buttons_i[1]"                            LOC = C22 | IOSTANDARD = LVCMOS25;
#NET "buttons_i[2]"                            LOC = L21 | IOSTANDARD = LVCMOS25;
#NET "buttons_i[3]"                            LOC = L20 | IOSTANDARD = LVCMOS25;
#NET "buttons_i[4]"                            LOC = C18 | IOSTANDARD = LVCMOS25;
#NET "buttons_i[5]"                            LOC = B18 | IOSTANDARD = LVCMOS25;
#NET "buttons_i[6]"                            LOC = K22 | IOSTANDARD = LVCMOS25;
#NET "buttons_i[7]"                            LOC = K21 | IOSTANDARD = LVCMOS25;
NET "leds_o[0]"                               LOC = AC22 | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = SLOW;
NET "leds_o[1]"                               LOC = AC24 | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = SLOW;
NET "leds_o[2]"                               LOC = AE22 | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = SLOW;
NET "leds_o[3]"                               LOC = AE23 | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = SLOW;
NET "leds_o[4]"                               LOC = AB23 | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = SLOW;
NET "leds_o[5]"                               LOC = AG23 | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = SLOW;
NET "leds_o[6]"                               LOC = AE24 | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = SLOW;
NET "leds_o[7]"                               LOC = AD24 | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = SLOW;

#######################################################################
##                        UART Constraints                           ##
#######################################################################

#######################################################################
##                    Clock and Reset Contraints                     ##
#######################################################################

NET "sys_clk_n_i"                             LOC = H9 | IOSTANDARD = LVDS_25;
NET "sys_clk_p_i"                             LOC = J9 | IOSTANDARD = LVDS_25;
NET "sys_rst_button_i"                        LOC = H10 | IOSTANDARD = SSTL15 | TIG;

NET "clk_sys"                                 TNM_NET = "sys_clk_group";
NET "clk_200mhz"                              TNM_NET = "sys_clk200_group";

TIMESPEC "TS_sys_clk_group"                   = PERIOD "sys_clk_group" 10 ns; # 100 MHz
TIMESPEC "TS_sys_clk200_group"                = PERIOD "sys_clk200_group" 5 ns; # 200 MHz

#######################################################################
##             Ethernet Contraints. MII 10/100 Mode                  ##
#######################################################################

NET "mrstn_o"                                 LOC = AH13;
NET "mcoll_pad_i"                             LOC = AK13;   ## 114 on U80
NET "mcrs_pad_i"                              LOC = AL13;   ## 115 on U80
# NET "PHY_INT"                               LOC = AH14;   ## 32  on U80
NET "mdc_pad_o"                               LOC = AP14;   ## 35  on U80
NET "md_pad_b"                                LOC = AN14;   ## 33  on U80
# NET "PHY_RESET"                             LOC = AH13;   ## 36  on U80
NET "mrx_clk_pad_i"                           LOC = AP11;   ## 7   on U80
NET "mrxdv_pad_i"                             LOC = AM13;   ## 4   on U80
NET "mrxd_pad_i[0]"                           LOC = AN13;   ## 3   on U80
NET "mrxd_pad_i[1]"                           LOC = AF14;   ## 128 on U80
NET "mrxd_pad_i[2]"                           LOC = AE14;   ## 126 on U80
NET "mrxd_pad_i[3]"                           LOC = AN12;   ## 125 on U80
# NET "PHY_RXD4"                              LOC = AM12;   ## 124 on U80
# NET "PHY_RXD5"                              LOC = AD11;   ## 123 on U80
# NET "PHY_RXD6"                              LOC = AC12;   ## 121 on U80
# NET "PHY_RXD7"                              LOC = AC13;   ## 120 on U80
NET "mrxerr_pad_i"                            LOC = AG12;   ## 9   on U80
NET "mtx_clk_pad_i"                           LOC = AD12;   ## 10  on U80
NET "mtxen_pad_o"                             LOC = AJ10;   ## 16  on U80
# NET "PHY_TXC_GTXCLK"                        LOC = AH12;   ## 14  on U80
NET "mtxd_pad_o[0]"                           LOC = AM11;   ## 18  on U80
NET "mtxd_pad_o[1]"                           LOC = AL11;   ## 19  on U80
NET "mtxd_pad_o[2]"                           LOC = AG10;   ## 20  on U80
NET "mtxd_pad_o[3]"                           LOC = AG11;   ## 24  on U80
# NET "PHY_TXD4"                              LOC = AL10;   ## 25  on U80
# NET "PHY_TXD5"                              LOC = AM10;   ## 26  on U80
# NET "PHY_TXD6"                              LOC = AE11;   ## 28  on U80
# NET "PHY_TXD7"                              LOC = AF11;   ## 29  on U80
NET "mtxerr_pad_o"                            LOC = AH10;   ## 13  on U80

#######################################################################
##                      FMC Connector HPC                            ##
#######################################################################


NET  "fmc_prsnt_i"                            LOC = AP25 | IOSTANDARD = "LVCMOS25";
NET  "fmc_pg_m2c_i"                           LOC = AK29 | IOSTANDARD = "LVCMOS25"; // LA31_N

// Trigger
NET "fmc_trig_dir_o"                          LOC = AK27 | IOSTANDARD = "LVCMOS25"; // LA28_P
NET "fmc_trig_term_o"                         LOC = AL25 | IOSTANDARD = "LVCMOS25"; // LA26_N
NET "fmc_trig_val_p_b"                        LOC = AG25 | IOSTANDARD = "BLVDS_25"; // LA32_P
NET "fmc_trig_val_n_b"                        LOC = AG26 | IOSTANDARD = "BLVDS_25"; // LA32_N

// Si571 clock gen
NET "si571_scl_pad_b"                         LOC = AE32 | IOSTANDARD = "LVCMOS25"; // HA12_N
NET "si571_sda_pad_b"                         LOC = AE31 | IOSTANDARD = "LVCMOS25"; // HA13_P
NET "fmc_si571_oe_o"                          LOC = AD32 | IOSTANDARD = "LVCMOS25"; // HA12_P

// AD9510 clock distribution PLL
NET "spi_ad9510_cs_o"                         LOC = AN18 | IOSTANDARD = "LVCMOS25";  // LA13_N
NET "spi_ad9510_sclk_o"                       LOC = AP19 | IOSTANDARD = "LVCMOS25"; // LA13_P
NET "spi_ad9510_mosi_o"                       LOC = AL18 | IOSTANDARD = "LVCMOS25"; // LA09_N
NET "spi_ad9510_miso_i"                       LOC = AN19 | IOSTANDARD = "LVCMOS25"; // LA14_P
NET "fmc_pll_function_o"                      LOC = AN20 | IOSTANDARD = "LVCMOS25"; // LA14_N
NET "fmc_pll_status_i"                        LOC = AM18 | IOSTANDARD = "LVCMOS25"; // LA09_P

#NET "fmc_fpga_clk_p_i"                       LOC = K24  | IOSTANDARD = "LVDS_25"; // CLK0_M2C_P
#NET "fmc_fpga_clk_n_i"                       LOC = K23  | IOSTANDARD = "LVDS_25"; // CLK0_M2C_N

// Clock reference selection (TS3USB221)
NET "fmc_clk_sel_o"                           LOC = AL29 | IOSTANDARD = "LVCMOS25"; // LA31_P

// EEPROM (multiplexer PCA9548)
NET "eeprom_scl_pad_b"                        LOC = AK9  | IOSTANDARD ="LVCMOS25"; # SCL C30
NET "eeprom_sda_pad_b"                        LOC = AE9  | IOSTANDARD ="LVCMOS25"; # SDA C31

// LM75 temperature monitor (can be used without multiplexer on KC705 board)
NET "lm75_scl_pad_b"                          LOC = AP30 | IOSTANDARD = "LVCMOS25"; // LA27_P
NET "lm75_sda_pad_b"                          LOC = AP31 | IOSTANDARD = "LVCMOS25"; // LA27_N
NET "fmc_lm75_temp_alarm_i"                   LOC = AJ27 | IOSTANDARD = "LVCMOS25"; // LA28_N

// LTC ADC control pins
NET "fmc_adc_pga_o"                           LOC = AG20 | IOSTANDARD = "LVCMOS25"; // LA06_P
NET "fmc_adc_shdn_o"                          LOC = AL20 | IOSTANDARD = "LVCMOS25"; // LA10_N
NET "fmc_adc_dith_o"                          LOC = AM20 | IOSTANDARD = "LVCMOS25"; // LA10_P
NET "fmc_adc_rand_o"                          LOC = AG21 | IOSTANDARD = "LVCMOS25"; // LA06_N

// LEDs
NET "fmc_led1_o"                              LOC = AN23 | IOSTANDARD = "LVCMOS25"; // LA16_N
NET "fmc_led2_o"                              LOC = AP22 | IOSTANDARD = "LVCMOS25"; // LA16_P
NET "fmc_led3_o"                              LOC = AM25 | IOSTANDARD = "LVCMOS25";  // LA26_P

#######################################################################
##                       FMC Connector HPC                            #
##                         LTC ADC lines                              #
#######################################################################

// ADC0
NET "fmc_adc0_clk_i"                          LOC = AN27  | IOSTANDARD = "LVCMOS25"; // LA17_CC_P

NET "fmc_adc0_data_i[0]"                      LOC = AN30  | IOSTANDARD = "LVCMOS25"; // LA24_P
NET "fmc_adc0_data_i[1]"                      LOC = AM30  | IOSTANDARD = "LVCMOS25"; // LA24_N
NET "fmc_adc0_data_i[2]"                      LOC = AN28  | IOSTANDARD = "LVCMOS25"; // LA25_P
NET "fmc_adc0_data_i[3]"                      LOC = AM28  | IOSTANDARD = "LVCMOS25"; // LA25_N
NET "fmc_adc0_data_i[4]"                      LOC = AN29  | IOSTANDARD = "LVCMOS25"; // LA21_P
NET "fmc_adc0_data_i[5]"                      LOC = AP29  | IOSTANDARD = "LVCMOS25"; // LA21_N
NET "fmc_adc0_data_i[6]"                      LOC = AP27  | IOSTANDARD = "LVCMOS25"; // LA22_P
NET "fmc_adc0_data_i[7]"                      LOC = AP26  | IOSTANDARD = "LVCMOS25"; // LA22_N
NET "fmc_adc0_data_i[8]"                      LOC = AM26  | IOSTANDARD = "LVCMOS25"; // LA23_N
NET "fmc_adc0_data_i[9]"                      LOC = AN24  | IOSTANDARD = "LVCMOS25"; // LA19_N
NET "fmc_adc0_data_i[10]"                     LOC = AJ25  | IOSTANDARD = "LVCMOS25"; // LA18_CC_N
NET "fmc_adc0_data_i[11]"                     LOC = AL26  | IOSTANDARD = "LVCMOS25"; // LA23_P
NET "fmc_adc0_data_i[12]"                     LOC = AL24  | IOSTANDARD = "LVCMOS25"; // LA20_N
NET "fmc_adc0_data_i[13]"                     LOC = AN25  | IOSTANDARD = "LVCMOS25"; // LA19_P
NET "fmc_adc0_data_i[14]"                     LOC = AH25  | IOSTANDARD = "LVCMOS25"; // LA18_CC_P
NET "fmc_adc0_data_i[15]"                     LOC = AK23  | IOSTANDARD = "LVCMOS25"; // LA20_P
NET "fmc_adc0_of_i"                           LOC = AL28  | IOSTANDARD = "LVCMOS25"; // LA29_P

// ADC1
NET "fmc_adc1_clk_i"                          LOC = V30   | IOSTANDARD = "LVCMOS25"; // HA17_CC_P

NET "fmc_adc1_data_i[15]"                     LOC = AD34  | IOSTANDARD = "LVCMOS25"; // HA10_P
NET "fmc_adc1_data_i[14]"                     LOC = AG33  | IOSTANDARD = "LVCMOS25"; // HA11_P
NET "fmc_adc1_data_i[13]"                     LOC = AC34  | IOSTANDARD = "LVCMOS25"; // HA10_N
NET "fmc_adc1_data_i[12]"                     LOC = AG32  | IOSTANDARD = "LVCMOS25"; // HA11_N
NET "fmc_adc1_data_i[11]"                     LOC = AB32  | IOSTANDARD = "LVCMOS25"; // HA15_P
NET "fmc_adc1_data_i[10]"                     LOC = AA30  | IOSTANDARD = "LVCMOS25"; // HA14_P
NET "fmc_adc1_data_i[9]"                      LOC = AC32  | IOSTANDARD = "LVCMOS25"; // HA15_N
NET "fmc_adc1_data_i[8]"                      LOC = AA31  | IOSTANDARD = "LVCMOS25"; // HA14_N
NET "fmc_adc1_data_i[7]"                      LOC = T34   | IOSTANDARD = "LVCMOS25"; // HA18_N
NET "fmc_adc1_data_i[6]"                      LOC = T33   | IOSTANDARD = "LVCMOS25"; // HA18_P
NET "fmc_adc1_data_i[5]"                      LOC = U32   | IOSTANDARD = "LVCMOS25"; // HA19_N
NET "fmc_adc1_data_i[4]"                      LOC = U31   | IOSTANDARD = "LVCMOS25"; // HA21_P
NET "fmc_adc1_data_i[3]"                      LOC = U28   | IOSTANDARD = "LVCMOS25"; // HA22_P
NET "fmc_adc1_data_i[2]"                      LOC = U30   | IOSTANDARD = "LVCMOS25"; // HA21_N
NET "fmc_adc1_data_i[1]"                      LOC = U26   | IOSTANDARD = "LVCMOS25"; // HA23_P
NET "fmc_adc1_data_i[0]"                      LOC = V29   | IOSTANDARD = "LVCMOS25"; // HA22_N
NET "fmc_adc1_of_i"                           LOC = U27   | IOSTANDARD = "LVCMOS25"; // HA23_N

// ADC2
NET "fmc_adc2_clk_i"                          LOC = AF20  | IOSTANDARD = "LVCMOS25"; // LA00_CC_P

NET "fmc_adc2_data_i[15]"                     LOC = AK19  | IOSTANDARD = "LVCMOS25"; // LA01_CC_P
NET "fmc_adc2_data_i[14]"                     LOC = AC20  | IOSTANDARD = "LVCMOS25"; // LA02_P
NET "fmc_adc2_data_i[13]"                     LOC = AL19  | IOSTANDARD = "LVCMOS25"; // LA01_CC_N
NET "fmc_adc2_data_i[12]"                     LOC = AD20  | IOSTANDARD = "LVCMOS25"; // LA02_N
NET "fmc_adc2_data_i[11]"                     LOC = AD19  | IOSTANDARD = "LVCMOS25"; // LA03_N
NET "fmc_adc2_data_i[10]"                     LOC = AC19  | IOSTANDARD = "LVCMOS25"; // LA03_P
NET "fmc_adc2_data_i[9]"                      LOC = AE19  | IOSTANDARD = "LVCMOS25"; // LA04_N
NET "fmc_adc2_data_i[8]"                      LOC = AF19  | IOSTANDARD = "LVCMOS25"; // LA04_P
NET "fmc_adc2_data_i[7]"                      LOC = AH22  | IOSTANDARD = "LVCMOS25"; // LA05_N
NET "fmc_adc2_data_i[6]"                      LOC = AG22  | IOSTANDARD = "LVCMOS25"; // LA05_P
NET "fmc_adc2_data_i[5]"                      LOC = AJ22  | IOSTANDARD = "LVCMOS25"; // LA08_N
NET "fmc_adc2_data_i[4]"                      LOC = AK22  | IOSTANDARD = "LVCMOS25"; // LA08_P
NET "fmc_adc2_data_i[3]"                      LOC = AJ21  | IOSTANDARD = "LVCMOS25"; // LA07_N
NET "fmc_adc2_data_i[2]"                      LOC = AK21  | IOSTANDARD = "LVCMOS25"; // LA07_P
NET "fmc_adc2_data_i[1]"                      LOC = AL21  | IOSTANDARD = "LVCMOS25"; // LA12_N
NET "fmc_adc2_data_i[0]"                      LOC = AM21  | IOSTANDARD = "LVCMOS25"; // LA12_P
NET "fmc_adc2_of_i"                           LOC = AM22  | IOSTANDARD = "LVCMOS25"; // LA11_P

// ADC3
NET "fmc_adc3_clk_i"                          LOC = AD29  | IOSTANDARD = "LVCMOS25"; // HA01_CC_P

NET "fmc_adc3_data_i[15]"                     LOC = AF33  | IOSTANDARD = "LVCMOS25"; // HA00_CC_N
NET "fmc_adc3_data_i[14]"                     LOC = AE33  | IOSTANDARD = "LVCMOS25"; // HA00_CC_P
NET "fmc_adc3_data_i[13]"                     LOC = AC27  | IOSTANDARD = "LVCMOS25"; // HA05_N
NET "fmc_adc3_data_i[12]"                     LOC = AB27  | IOSTANDARD = "LVCMOS25"; // HA05_P
NET "fmc_adc3_data_i[11]"                     LOC = AC28  | IOSTANDARD = "LVCMOS25"; // HA04_N
NET "fmc_adc3_data_i[10]"                     LOC = AB28  | IOSTANDARD = "LVCMOS25"; // HA04_P
NET "fmc_adc3_data_i[9]"                      LOC = AB31  | IOSTANDARD = "LVCMOS25"; // HA09_N
NET "fmc_adc3_data_i[8]"                      LOC = AB30  | IOSTANDARD = "LVCMOS25"; // HA09_P
NET "fmc_adc3_data_i[7]"                      LOC = Y26   | IOSTANDARD = "LVCMOS25"; // HA03_N
NET "fmc_adc3_data_i[6]"                      LOC = AA25  | IOSTANDARD = "LVCMOS25"; // HA03_P
NET "fmc_adc3_data_i[5]"                      LOC = AG31  | IOSTANDARD = "LVCMOS25"; // HA08_P
NET "fmc_adc3_data_i[4]"                      LOC = AB25  | IOSTANDARD = "LVCMOS25"; // HA02_P
NET "fmc_adc3_data_i[3]"                      LOC = AA26  | IOSTANDARD = "LVCMOS25"; // HA07_P
NET "fmc_adc3_data_i[2]"                      LOC = AC25  | IOSTANDARD = "LVCMOS25"; // HA02_N
NET "fmc_adc3_data_i[1]"                      LOC = AA28  | IOSTANDARD = "LVCMOS25"; // HA06_P
NET "fmc_adc3_data_i[0]"                      LOC = AB26  | IOSTANDARD = "LVCMOS25"; // HA07_N
NET "fmc_adc3_of_i"                           LOC = AA29  | IOSTANDARD = "LVCMOS25"; // HA06_N

#######################################################################
##               Pinout and Related I/O Constraints                  ##
#######################################################################

# On ML605 kit, all clock pins are assigned to MRCC pins. However, two of them
# (fmc_adc1_clk and fmc_adc3_clk) are located in the outer left/right column
# I/Os. These locations cannot connect to BUFG primitives, only inner (center)
# left/right column I/Os on the same half top/bottom can!
#
# For 7-series FPGAs there is no such impediment, apparently.

#######################################################################
##                         DIFF TERM                                 ##
#######################################################################

NET "sys_clk_p_i" DIFF_TERM = TRUE;
NET "sys_clk_n_i" DIFF_TERM = TRUE;

NET "fmc_trig_val_p_b" DIFF_TERM = TRUE;
NET "fmc_trig_val_n_b" DIFF_TERM = TRUE;

#NET "fmc_fpga_clk_p_i" DIFF_TERM = TRUE;
#NET "fmc_fpga_clk_n_i" DIFF_TERM = TRUE;

#######################################################################
##                    Timing constraints                             ##
#######################################################################

# Overrides default_delay hdl parameter for the VARIABLE mode.
# For Virtex-6: Average Tap Delay at 200 MHz = 78 ps, at 300 MHz = 52 ps
INST "*cmp_fmc_adc_iface/gen_adc_data_chains[0].*.*/gen_adc_data[?].*.cmp_adc_data_iodelay" IDELAY_VALUE = 29;
INST "*cmp_fmc_adc_iface/gen_adc_data_chains[1].*.*/gen_adc_data[?].*.cmp_adc_data_iodelay" IDELAY_VALUE = 31;
INST "*cmp_fmc_adc_iface/gen_adc_data_chains[2].*.*/gen_adc_data[?].*.cmp_adc_data_iodelay" IDELAY_VALUE = 17;
INST "*cmp_fmc_adc_iface/gen_adc_data_chains[3].*.*/gen_adc_data[?].*.cmp_adc_data_iodelay" IDELAY_VALUE = 26;

# Overrides default_delay hdl parameter
 INST "*cmp_fmc_adc_iface/gen_clock_chains[0].*.*/*.cmp_ibufds_clk_iodelay" IDELAY_VALUE = 0;
 INST "*cmp_fmc_adc_iface/gen_clock_chains[1].*.*/*.cmp_ibufds_clk_iodelay" IDELAY_VALUE = 0;
# INST "*cmp_fmc_adc_iface/gen_clock_chains[2].*.*/*.cmp_ibufds_clk_iodelay" IDELAY_VALUE = 0;
# INST "*cmp_fmc_adc_iface/gen_clock_chains[3].*.*/*.cmp_ibufds_clk_iodelay" IDELAY_VALUE = 0;

#######################################################################
##                          Clocks                                   ##
#######################################################################

# 200 MHz onboard input clock
NET "sys_clk_p_i" TNM_NET = "sys_clk_group";
TIMESPEC "TS_sys_clk_group" = PERIOD "sys_clk_group" 5 ns HIGH 50%;

# 100 MHz wihsbone clock
NET "clk_sys" TNM_NET = "clk_sys_group";
TIMESPEC "TS_clk_sys_group" = PERIOD "clk_sys_group" 10 ns HIGH 50%;

# 200 MHz DDR3 and IDELAY CONTROL clock
NET "clk_200mhz" TNM_NET = TNM_200mhz_sys_clk;
TIMESPEC "TS_200mhz_sys_clk" = PERIOD "TNM_200mhz_sys_clk" 5 ns HIGH 50%;

# 200 MHz DDR3 UI Clock
NET "*/u_infrastructure/clk_pll" TNM_NET = "TNM_ddr_sys_clk";
TIMESPEC "TS_ddr_sys_clk" = PERIOD "TNM_ddr_sys_clk" 5 ns HIGH 50%;
NET "clk_sys" TNM_NET = "TNM_clk_sys_group_ffs";
TIMESPEC TS_clk_sys_to_ddr3_ui_clk = FROM "TNM_clk_sys_group_ffs" TO "TNM_ddr_sys_clk" 10 ns DATAPATHONLY;

// real jitter is about 22ps peak-to-peak
NET "fmc_adc0_clk_i" TNM_NET = fmc_adc0_clk_i;
// TIMESPEC TS_fmc_adc0_clk_i = PERIOD "fmc_adc0_clk_i" 130 MHz HIGH 50% INPUT_JITTER 50 ps;
//TIMESPEC TS_fmc_adc0_clk_i = PERIOD "fmc_adc0_clk_i" 112.5831 MHz HIGH 50% INPUT_JITTER 50 ps;
TIMESPEC TS_fmc_adc0_clk_i = PERIOD "fmc_adc0_clk_i" 8.88 ns HIGH 50% INPUT_JITTER 50 ps;

NET "fmc_adc1_clk_i" TNM_NET = fmc_adc1_clk_i;
// TIMESPEC TS_fmc_adc1_clk_i = PERIOD "fmc_adc1_clk_i" 130 MHz HIGH 50% INPUT_JITTER 50 ps;
// TIMESPEC TS_fmc_adc1_clk_i = PERIOD "fmc_adc1_clk_i" 112.5831 MHz HIGH 50% INPUT_JITTER 50 ps;
TIMESPEC TS_fmc_adc1_clk_i = PERIOD "fmc_adc1_clk_i" 8.88 ns HIGH 50% INPUT_JITTER 50 ps;

NET "fmc_adc2_clk_i" TNM_NET = fmc_adc2_clk_i;
// TIMESPEC TS_fmc_adc2_clk_i = PERIOD "fmc_adc2_clk_i" 130 MHz HIGH 50% INPUT_JITTER 50 ps;
// TIMESPEC TS_fmc_adc2_clk_i = PERIOD "fmc_adc2_clk_i" 112.5831 MHz HIGH 50% INPUT_JITTER 50 ps;
TIMESPEC TS_fmc_adc2_clk_i = PERIOD "fmc_adc2_clk_i" 8.88 ns HIGH 50% INPUT_JITTER 50 ps;

NET "fmc_adc3_clk_i" TNM_NET = fmc_adc3_clk_i;
// TIMESPEC TS_fmc_adc3_clk_i = PERIOD "fmc_adc3_clk_i" 130 MHz HIGH 50% INPUT_JITTER 50 ps;
// TIMESPEC TS_fmc_adc3_clk_i = PERIOD "fmc_adc3_clk_i" 112.5831 MHz HIGH 50% INPUT_JITTER 50 ps;
TIMESPEC TS_fmc_adc3_clk_i = PERIOD "fmc_adc3_clk_i" 8.88 ns HIGH 50% INPUT_JITTER 50 ps;

//NET "fmc_fpga_clk_p" TNM_NET = fmc_fpga_clk_p;
//TIMESPEC TS_fmc_fpga_clk_p = PERIOD "fmc_fpga_clk_p" 130 MHz HIGH 50% INPUT_JITTER 40 ps;

#######################################################################
##                                Data                               ##
#######################################################################

#INST "fmc_adc_130m_4ch_i/ltcInterface_adc0_i/IDELAYCTRL_adc0_inst" LOC = IDELAYCTRL_X0Y1;
#INST "fmc_adc_130m_4ch_i/ltcInterface_adc1_i/IDELAYCTRL_adc0_inst" LOC = IDELAYCTRL_X0Y2;
#INST "fmc_adc_130m_4ch_i/ltcInterface_adc2_i/IDELAYCTRL_adc0_inst" LOC = IDELAYCTRL_X0Y0;
#INST "fmc_adc_130m_4ch_i/ltcInterface_adc3_i/IDELAYCTRL_adc0_inst" LOC = IDELAYCTRL_X0Y1; // same as ADC1

// including 50ps jitter, for 130MHz clock
// since design uses copy of input ADC clock
// there is additional delay for clock/ data (tC)

INST "fmc_adc0_data_i<*>" TNM = fmc_adc0_data_i;
INST "fmc_adc1_data_i<*>" TNM = fmc_adc1_data_i;
INST "fmc_adc2_data_i<*>" TNM = fmc_adc2_data_i;
INST "fmc_adc3_data_i<*>" TNM = fmc_adc3_data_i;

TIMEGRP "fmc_adc0_data_i" OFFSET = IN -0.7 ns VALID 7.6 ns BEFORE "fmc_adc0_clk_i";
TIMEGRP "fmc_adc1_data_i" OFFSET = IN -0.7 ns VALID 7.6 ns BEFORE "fmc_adc1_clk_i";
TIMEGRP "fmc_adc2_data_i" OFFSET = IN -0.7 ns VALID 7.6 ns BEFORE "fmc_adc2_clk_i";
TIMEGRP "fmc_adc3_data_i" OFFSET = IN -0.7 ns VALID 7.6 ns BEFORE "fmc_adc3_clk_i";

#######################################################################
##                          PCIe constraints                        ##
#######################################################################
#
CONFIG PART = xc6vlx240t-ff1156-1;

#PCIe reset
NET "pcie_rst_n_i" IOSTANDARD = "LVCMOS25" | PULLUP | NODELAY;
NET "pcie_rst_n_i" TIG;
# Bank 16 VCCO - VADJ_FPGA - IO_25_16
NET "pcie_rst_n_i" LOC = AE13;
#PCIe reset
#PCIe clock
NET "pcie_clk_n_i" LOC = P5;
# Bank 115 - MGTREFCLK1N_115
NET "pcie_clk_p_i" LOC = P6;

#######################################################################
##                         DDR controller                            ##
#######################################################################
NET   "ddr3_dq_b[0]"    LOC = "J11"  | IOSTANDARD = SSTL15_T_DCI ;
NET   "ddr3_dq_b[1]"    LOC = "E13"  | IOSTANDARD = SSTL15_T_DCI ;
NET   "ddr3_dq_b[2]"    LOC = "F13"  | IOSTANDARD = SSTL15_T_DCI ;
NET   "ddr3_dq_b[3]"    LOC = "K11"  | IOSTANDARD = SSTL15_T_DCI ;
NET   "ddr3_dq_b[4]"    LOC = "L11"  | IOSTANDARD = SSTL15_T_DCI ;
NET   "ddr3_dq_b[5]"    LOC = "K13"  | IOSTANDARD = SSTL15_T_DCI ;
NET   "ddr3_dq_b[6]"    LOC = "K12"  | IOSTANDARD = SSTL15_T_DCI ;
NET   "ddr3_dq_b[7]"    LOC = "D11"  | IOSTANDARD = SSTL15_T_DCI ;
NET   "ddr3_dq_b[8]"    LOC = "M13"  | IOSTANDARD = SSTL15_T_DCI ;
NET   "ddr3_dq_b[9]"    LOC = "J14"  | IOSTANDARD = SSTL15_T_DCI ;
NET   "ddr3_dq_b[10]"   LOC = "B13"  | IOSTANDARD = SSTL15_T_DCI ;
NET   "ddr3_dq_b[11]"   LOC = "B12"  | IOSTANDARD = SSTL15_T_DCI ;
NET   "ddr3_dq_b[12]"   LOC = "G10"  | IOSTANDARD = SSTL15_T_DCI ;
NET   "ddr3_dq_b[13]"   LOC = "M11"  | IOSTANDARD = SSTL15_T_DCI ;
NET   "ddr3_dq_b[14]"   LOC = "C12"  | IOSTANDARD = SSTL15_T_DCI ;
NET   "ddr3_dq_b[15]"   LOC = "A11"  | IOSTANDARD = SSTL15_T_DCI ;
NET   "ddr3_dq_b[16]"   LOC = "G11"  | IOSTANDARD = SSTL15_T_DCI ;
NET   "ddr3_dq_b[17]"   LOC = "F11"  | IOSTANDARD = SSTL15_T_DCI ;
NET   "ddr3_dq_b[18]"   LOC = "D14"  | IOSTANDARD = SSTL15_T_DCI ;
NET   "ddr3_dq_b[19]"   LOC = "C14"  | IOSTANDARD = SSTL15_T_DCI ;
NET   "ddr3_dq_b[20]"   LOC = "G12"  | IOSTANDARD = SSTL15_T_DCI ;
NET   "ddr3_dq_b[21]"   LOC = "G13"  | IOSTANDARD = SSTL15_T_DCI ;
NET   "ddr3_dq_b[22]"   LOC = "F14"  | IOSTANDARD = SSTL15_T_DCI ;
NET   "ddr3_dq_b[23]"   LOC = "H14"  | IOSTANDARD = SSTL15_T_DCI ;
NET   "ddr3_dq_b[24]"   LOC = "C19"  | IOSTANDARD = SSTL15_T_DCI ;
NET   "ddr3_dq_b[25]"   LOC = "G20"  | IOSTANDARD = SSTL15_T_DCI ;
NET   "ddr3_dq_b[26]"   LOC = "E19"  | IOSTANDARD = SSTL15_T_DCI ;
NET   "ddr3_dq_b[27]"   LOC = "F20"  | IOSTANDARD = SSTL15_T_DCI ;
NET   "ddr3_dq_b[28]"   LOC = "A20"  | IOSTANDARD = SSTL15_T_DCI ;
NET   "ddr3_dq_b[29]"   LOC = "A21"  | IOSTANDARD = SSTL15_T_DCI ;
NET   "ddr3_dq_b[30]"   LOC = "E22"  | IOSTANDARD = SSTL15_T_DCI ;
NET   "ddr3_dq_b[31]"   LOC = "E23"  | IOSTANDARD = SSTL15_T_DCI ;
NET   "ddr3_dq_b[32]"   LOC = "G21"  | IOSTANDARD = SSTL15_T_DCI ;
NET   "ddr3_dq_b[33]"   LOC = "B21"  | IOSTANDARD = SSTL15_T_DCI ;
NET   "ddr3_dq_b[34]"   LOC = "A23"  | IOSTANDARD = SSTL15_T_DCI ;
NET   "ddr3_dq_b[35]"   LOC = "A24"  | IOSTANDARD = SSTL15_T_DCI ;
NET   "ddr3_dq_b[36]"   LOC = "C20"  | IOSTANDARD = SSTL15_T_DCI ;
NET   "ddr3_dq_b[37]"   LOC = "D20"  | IOSTANDARD = SSTL15_T_DCI ;
NET   "ddr3_dq_b[38]"   LOC = "J20"  | IOSTANDARD = SSTL15_T_DCI ;
NET   "ddr3_dq_b[39]"   LOC = "G22"  | IOSTANDARD = SSTL15_T_DCI ;
NET   "ddr3_dq_b[40]"   LOC = "D26"  | IOSTANDARD = SSTL15_T_DCI ;
NET   "ddr3_dq_b[41]"   LOC = "F26"  | IOSTANDARD = SSTL15_T_DCI ;
NET   "ddr3_dq_b[42]"   LOC = "B26"  | IOSTANDARD = SSTL15_T_DCI ;
NET   "ddr3_dq_b[43]"   LOC = "E26"  | IOSTANDARD = SSTL15_T_DCI ;
NET   "ddr3_dq_b[44]"   LOC = "C24"  | IOSTANDARD = SSTL15_T_DCI ;
NET   "ddr3_dq_b[45]"   LOC = "D25"  | IOSTANDARD = SSTL15_T_DCI ;
NET   "ddr3_dq_b[46]"   LOC = "D27"  | IOSTANDARD = SSTL15_T_DCI ;
NET   "ddr3_dq_b[47]"   LOC = "C25"  | IOSTANDARD = SSTL15_T_DCI ;
NET   "ddr3_dq_b[48]"   LOC = "C27"  | IOSTANDARD = SSTL15_T_DCI ;
NET   "ddr3_dq_b[49]"   LOC = "B28"  | IOSTANDARD = SSTL15_T_DCI ;
NET   "ddr3_dq_b[50]"   LOC = "D29"  | IOSTANDARD = SSTL15_T_DCI ;
NET   "ddr3_dq_b[51]"   LOC = "B27"  | IOSTANDARD = SSTL15_T_DCI ;
NET   "ddr3_dq_b[52]"   LOC = "G27"  | IOSTANDARD = SSTL15_T_DCI ;
NET   "ddr3_dq_b[53]"   LOC = "A28"  | IOSTANDARD = SSTL15_T_DCI ;
NET   "ddr3_dq_b[54]"   LOC = "E24"  | IOSTANDARD = SSTL15_T_DCI ;
NET   "ddr3_dq_b[55]"   LOC = "G25"  | IOSTANDARD = SSTL15_T_DCI ;
NET   "ddr3_dq_b[56]"   LOC = "F28"  | IOSTANDARD = SSTL15_T_DCI ;
NET   "ddr3_dq_b[57]"   LOC = "B31"  | IOSTANDARD = SSTL15_T_DCI ;
NET   "ddr3_dq_b[58]"   LOC = "H29"  | IOSTANDARD = SSTL15_T_DCI ;
NET   "ddr3_dq_b[59]"   LOC = "H28"  | IOSTANDARD = SSTL15_T_DCI ;
NET   "ddr3_dq_b[60]"   LOC = "B30"  | IOSTANDARD = SSTL15_T_DCI ;
NET   "ddr3_dq_b[61]"   LOC = "A30"  | IOSTANDARD = SSTL15_T_DCI ;
NET   "ddr3_dq_b[62]"   LOC = "E29"  | IOSTANDARD = SSTL15_T_DCI ;
NET   "ddr3_dq_b[63]"   LOC = "F29"  | IOSTANDARD = SSTL15_T_DCI ;
NET   "ddr3_addr_o[13]" LOC = "J15"  | IOSTANDARD = SSTL15 ;
NET   "ddr3_addr_o[12]" LOC = "H15"  | IOSTANDARD = SSTL15 ;
NET   "ddr3_addr_o[11]" LOC = "M15"  | IOSTANDARD = SSTL15 ;
NET   "ddr3_addr_o[10]" LOC = "M16"  | IOSTANDARD = SSTL15 ;
NET   "ddr3_addr_o[9]"  LOC = "F15"  | IOSTANDARD = SSTL15 ;
NET   "ddr3_addr_o[8]"  LOC = "G15"  | IOSTANDARD = SSTL15 ;
NET   "ddr3_addr_o[7]"  LOC = "B15"  | IOSTANDARD = SSTL15 ;
NET   "ddr3_addr_o[6]"  LOC = "A15"  | IOSTANDARD = SSTL15 ;
NET   "ddr3_addr_o[5]"  LOC = "J17"  | IOSTANDARD = SSTL15 ;
NET   "ddr3_addr_o[4]"  LOC = "D16"  | IOSTANDARD = SSTL15 ;
NET   "ddr3_addr_o[3]"  LOC = "E16"  | IOSTANDARD = SSTL15 ;
NET   "ddr3_addr_o[2]"  LOC = "B16"  | IOSTANDARD = SSTL15 ;
NET   "ddr3_addr_o[1]"  LOC = "A16"  | IOSTANDARD = SSTL15 ;
NET   "ddr3_addr_o[0]"  LOC = "L14"  | IOSTANDARD = SSTL15 ;
NET   "ddr3_ba_o[2]"    LOC = "L15"  | IOSTANDARD = SSTL15 ;
NET   "ddr3_ba_o[1]"    LOC = "J19"  | IOSTANDARD = SSTL15 ;
NET   "ddr3_ba_o[0]"    LOC = "K19"  | IOSTANDARD = SSTL15 ;
NET   "ddr3_ras_n_o"    LOC = "L19"  | IOSTANDARD = SSTL15 ;
NET   "ddr3_cas_n_o"    LOC = "C17"  | IOSTANDARD = SSTL15 ;
NET   "ddr3_we_n_o"     LOC = "B17"  | IOSTANDARD = SSTL15 ;
NET   "ddr3_reset_n_o"  LOC = "E18"  | IOSTANDARD = LVCMOS15 ;
NET   "ddr3_cke_o[0]"   LOC = "M18"  | IOSTANDARD = SSTL15 ;
NET   "ddr3_odt_o[0]"   LOC = "F18"  | IOSTANDARD = SSTL15 ;
NET   "ddr3_cs_n_o[0]"  LOC = "K18"  | IOSTANDARD = SSTL15 ;
NET   "ddr3_dm_o[0]"    LOC = "E11"  | IOSTANDARD = SSTL15 ;
NET   "ddr3_dm_o[1]"    LOC = "B11"  | IOSTANDARD = SSTL15 ;
NET   "ddr3_dm_o[2]"    LOC = "E14"  | IOSTANDARD = SSTL15 ;
NET   "ddr3_dm_o[3]"    LOC = "D19"  | IOSTANDARD = SSTL15 ;
NET   "ddr3_dm_o[4]"    LOC = "B22"  | IOSTANDARD = SSTL15 ;
NET   "ddr3_dm_o[5]"    LOC = "A26"  | IOSTANDARD = SSTL15 ;
NET   "ddr3_dm_o[6]"    LOC = "A29"  | IOSTANDARD = SSTL15 ;
NET   "ddr3_dm_o[7]"    LOC = "A31"  | IOSTANDARD = SSTL15 ;
NET   "ddr3_dqs_p_b[0]" LOC = "D12"  | IOSTANDARD = DIFF_SSTL15_T_DCI ;
NET   "ddr3_dqs_n_b[0]" LOC = "E12"  | IOSTANDARD = DIFF_SSTL15_T_DCI ;
NET   "ddr3_dqs_p_b[1]" LOC = "H12"  | IOSTANDARD = DIFF_SSTL15_T_DCI ;
NET   "ddr3_dqs_n_b[1]" LOC = "J12"  | IOSTANDARD = DIFF_SSTL15_T_DCI ;
NET   "ddr3_dqs_p_b[2]" LOC = "A13"  | IOSTANDARD = DIFF_SSTL15_T_DCI ;
NET   "ddr3_dqs_n_b[2]" LOC = "A14"  | IOSTANDARD = DIFF_SSTL15_T_DCI ;
NET   "ddr3_dqs_p_b[3]" LOC = "H19"  | IOSTANDARD = DIFF_SSTL15_T_DCI ;
NET   "ddr3_dqs_n_b[3]" LOC = "H20"  | IOSTANDARD = DIFF_SSTL15_T_DCI ;
NET   "ddr3_dqs_p_b[4]" LOC = "B23"  | IOSTANDARD = DIFF_SSTL15_T_DCI ;
NET   "ddr3_dqs_n_b[4]" LOC = "C23"  | IOSTANDARD = DIFF_SSTL15_T_DCI ;
NET   "ddr3_dqs_p_b[5]" LOC = "B25"  | IOSTANDARD = DIFF_SSTL15_T_DCI ;
NET   "ddr3_dqs_n_b[5]" LOC = "A25"  | IOSTANDARD = DIFF_SSTL15_T_DCI ;
NET   "ddr3_dqs_p_b[6]" LOC = "H27"  | IOSTANDARD = DIFF_SSTL15_T_DCI ;
NET   "ddr3_dqs_n_b[6]" LOC = "G28"  | IOSTANDARD = DIFF_SSTL15_T_DCI ;
NET   "ddr3_dqs_p_b[7]" LOC = "C30"  | IOSTANDARD = DIFF_SSTL15_T_DCI ;
NET   "ddr3_dqs_n_b[7]" LOC = "D30"  | IOSTANDARD = DIFF_SSTL15_T_DCI ;
NET   "ddr3_ck_p_o[0]"  LOC = "G18"  | IOSTANDARD = DIFF_SSTL15 ;
NET   "ddr3_ck_n_o[0]"  LOC = "H18"  | IOSTANDARD = DIFF_SSTL15 ;
#NET   "ddr_sys_clk_p_i" LOC = "J9"  | IOSTANDARD = LVDS_25;
#NET   "ddr_sys_clk_n_i" LOC = "H9"  | IOSTANDARD = LVDS_25;

#######################################################################
# Pinout and Related I/O Constraints
#######################################################################

#
# SYS clock 100 MHz (input) signal. The sys_clk_p and sys_clk_n
# signals are the PCI Express reference clock. Virtex-6 GT
# Transceiver architecture requires the use of a dedicated clock
# resources (FPGA input pins) associated with each GT Transceiver.
# To use these pins an IBUFDS primitive (refclk_ibuf) is
# instantiated in user's design.
# Please refer to the Virtex-6 GT Transceiver User Guide
# (UG) for guidelines regarding clock resource selection.
#

INST "*/pcieclk_ibuf" LOC = IBUFDS_GTXE1_X0Y6;

#
# Transceiver instance placement.  This constraint selects the
# transceivers to be used, which also dictates the pinout for the
# transmit and receive differential pairs.  Please refer to the
# Virtex-6 GT Transceiver User Guide (UG) for more information.
#
# PCIe Lane 0
INST "*/pcie_2_0_i/pcie_gt_i/gtx_v6_i/no_of_lanes.GTXD[0].GTX" LOC = GTXE1_X0Y15;
# PCIe Lane 1
INST "*/pcie_2_0_i/pcie_gt_i/gtx_v6_i/no_of_lanes.GTXD[1].GTX" LOC = GTXE1_X0Y14;
# PCIe Lane 2
INST "*/pcie_2_0_i/pcie_gt_i/gtx_v6_i/no_of_lanes.GTXD[2].GTX" LOC = GTXE1_X0Y13;
# PCIe Lane 3
INST "*/pcie_2_0_i/pcie_gt_i/gtx_v6_i/no_of_lanes.GTXD[3].GTX" LOC = GTXE1_X0Y12;

#
# PCI Express Block placement. This constraint selects the PCI Express
# Block to be used.
#
INST "*/pcie_2_0_i/pcie_block_i" LOC = PCIE_X0Y1;


#
# DDR controller component placement
# Check it after changing memory controller paramenters

#--------------------------------
#DCI_CASCADING
#Syntax : CONFIG DCI_CASCADE = "<master> <slave1> <slave2> ..";
#--------------------------------

CONFIG DCI_CASCADE = "26 25";#
CONFIG DCI_CASCADE = "36 35";#

#--------------------------------
## The logic of this pin is used internally to drive a BUFR in the column. This chosen pin must  
## be a clock pin capable of spanning to all of the banks containing data bytes in the particular
## column. That is, all byte groups must be within +/- 1 bank of this pin. This pin cannot be    
## used for other functions and should not be connected externally. If a different pin is chosen,
## he corresponding LOC constraint must also be changed.                                         
#--------------------------------
CONFIG PROHIBIT = C29,M12;

#--------------------------------
## The logic of this pin is used internally to drive a BUFIO for the byte group. Any clock      
## capable pin in the same bank as the data byte group (DQS, DQ, DM if used) can be used for    
## this pin. This pin cannot be used for other functions and should not be connected externally.
## If a different pin is chosen, the corresponding LOC constraint must also be changed.         
#--------------------------------
CONFIG PROHIBIT = B20,C13,C28,D24,F21,F25,K14,L13;

#--------------------------------
#Place RSYNC OSERDES and IODELAYy
#--------------------------------

##Site: C29 -- Bank 25
INST "*/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_loop_col1.u_oserdes_rsync"
  LOC = "OLOGIC_X1Y139";
INST "*/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_loop_col1.u_odelay_rsync"
  LOC = "IODELAY_X1Y139";

INST "*/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_loop_col1.u_bufr_rsync"
  LOC = "BUFR_X1Y6";

##Site: M12 -- Bank 35
INST "*/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_loop_col0.u_oserdes_rsync"
  LOC = "OLOGIC_X2Y139";
INST "*/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_loop_col0.u_odelay_rsync"
  LOC = "IODELAY_X2Y139";

INST "*/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_loop_col0.u_bufr_rsync"
  LOC = "BUFR_X2Y6";
  
#--------------------------------
# Place CPT OSERDES and IODELAY:
#--------------------------------

##Site: C13 -- Bank 35
INST "*/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[0].u_oserdes_cpt"
  LOC = "OLOGIC_X2Y137";
INST "*/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[0].u_odelay_cpt"
  LOC = "IODELAY_X2Y137";

##Site: L13 -- Bank 35
INST "*/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[1].u_oserdes_cpt"
  LOC = "OLOGIC_X2Y141";
INST "*/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[1].u_odelay_cpt"
  LOC = "IODELAY_X2Y141";

##Site: K14 -- Bank 35
INST "*/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[2].u_oserdes_cpt"
  LOC = "OLOGIC_X2Y143";
INST "*/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[2].u_odelay_cpt"
  LOC = "IODELAY_X2Y143";

##Site: F21 -- Bank 26
INST "*/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[3].u_oserdes_cpt"
  LOC = "OLOGIC_X1Y179";
INST "*/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[3].u_odelay_cpt"
  LOC = "IODELAY_X1Y179";

##Site: B20 -- Bank 26
INST "*/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[4].u_oserdes_cpt"
  LOC = "OLOGIC_X1Y181";
INST "*/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[4].u_odelay_cpt"
  LOC = "IODELAY_X1Y181";

##Site: F25 -- Bank 25
INST "*/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[5].u_oserdes_cpt"
  LOC = "OLOGIC_X1Y137";
INST "*/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[5].u_odelay_cpt"
  LOC = "IODELAY_X1Y137";

##Site: C28 -- Bank 25
INST "*/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[6].u_oserdes_cpt"
  LOC = "OLOGIC_X1Y141";
INST "*/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[6].u_odelay_cpt"
  LOC = "IODELAY_X1Y141";

##Site: D24 -- Bank 25
INST "*/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[7].u_oserdes_cpt"
  LOC = "OLOGIC_X1Y143";
INST "*/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[7].u_odelay_cpt"
  LOC = "IODELAY_X1Y143";

INST "*/u_infrastructure/u_mmcm_adv" LOC = "MMCM_ADV_X0Y8"; #Banks 16, 26, 36

#######################################################################
# Timing Constraints
#######################################################################

NET "*/sys_clk_c" TNM_NET = "SYSCLK" ;
NET "*/pcie_clocking_i/clk_125" TNM_NET = "CLK_125" ;
NET "*/TxOutClk_bufg" TNM_NET = "TXOUTCLKBUFG";

TIMESPEC "TS_SYSCLK"  = PERIOD "SYSCLK" 100 MHz HIGH 50 % PRIORITY 100 ;
TIMESPEC "TS_CLK_125"  = PERIOD "CLK_125" TS_SYSCLK*1.25 HIGH 50 % PRIORITY 1 ;
TIMESPEC "TS_TXOUTCLKBUFG"  = PERIOD "TXOUTCLKBUFG" 100 MHz HIGH 50 % PRIORITY 100 ;


PIN "*/trn_reset_n_int_i.CLR" TIG ;
PIN "*/trn_reset_n_i.CLR" TIG ;
PIN "*/pcie_clocking_i/mmcm_adv_i.RST" TIG ;

INST "*/pcie_clocking_i/mmcm_adv_i" LOC = MMCM_ADV_X0Y7;

#--------------------------------
#              DDR
#--------------------------------
          
# Constrain BUFR clocks used to synchronize data from IOB to fabric logic
# Note that ISE cannot infer this from other PERIOD constraints because
# of the use of OSERDES blocks in the BUFR clock generation path
NET "*/u_memc_ui_top/u_mem_intfc/phy_top0/clk_rsync[?]" TNM_NET = TNM_clk_rsync;
TIMESPEC "TS_clk_rsync" = PERIOD "TNM_clk_rsync" 5 ns;

# Paths between DQ/DQS ISERDES.Q outputs and CLB flops clocked by falling
# edge of BUFR will by design only be used if DYNCLKDIVSEL is asserted for
# that particular flop. Mark this path as being a full-cycle, rather than
# a half cycle path for timing purposes. NOTE: This constraint forces full-
# cycle timing to be applied globally for all rising->falling edge paths
# in all resynchronizaton clock domains. If the user had modified the logic
# in the resync clock domain such that other rising->falling edge paths
# exist, then constraint below should be modified to utilize pattern
# matching to specific affect only the DQ/DQS ISERDES.Q outputs
TIMEGRP "TG_clk_rsync_rise" = RISING  "TNM_clk_rsync";
TIMEGRP "TG_clk_rsync_fall" = FALLING "TNM_clk_rsync";
TIMESPEC "TS_clk_rsync_rise_to_fall" =
  FROM "TG_clk_rsync_rise" TO "TG_clk_rsync_fall" "TS_ddr_sys_clk" * 4;

# Signal to select between controller and physical layer signals. Four divided by two clock
# cycles (4 memory clock cycles) are provided by design for the signal to settle down.
# Used only by the phy modules.
INST "*/u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_init/u_ff_phy_init_data_sel" TNM = "TNM_PHY_INIT_SEL";
TIMESPEC "TS_MC_PHY_INIT_SEL" = FROM "TNM_PHY_INIT_SEL" TO FFS = "TS_ddr_sys_clk"*8;

#######################################################################
##                      Placement Constraints                        ##
#######################################################################

#INST "*/cmp_wb_position_calc_core" AREA_GROUP = "GRP_position_core";
#AREA_GROUP "GRP_position_core" RANGE = CLOCKREGION_X1Y1:CLOCKREGION_X1Y4;

## Constrain the PCIe core elements placement, so that it won't fail
## timing analysis.
## Comment out because we use nonstandard GTP location
#INST "*/pcie_core_i" AREA_GROUP = "GRP_PCIE_CORE";
#AREA_GROUP "GRP_PCIE_CORE" RANGE = CLOCKREGION_X0Y4;
#
## Place the DMA design not far from PCIe core, otherwise it also breaks timing
#INST "*/theTlpControl" AREA_GROUP = "GRP_tlpControl";
#AREA_GROUP "GRP_tlpControl" RANGE = CLOCKREGION_X0Y2:CLOCKREGION_X0Y4;
