##################################################################################################
##
##  Xilinx, Inc. 2010            www.xilinx.com
##  sáb fev 21 11:40:05 2015
##  Generated by MIG Version 2.3
##
##################################################################################################
##  File name :       ddr_core.xdc
##  Details :     Constraints file
##                    FPGA Family:       ARTIX7
##                    FPGA Part:         XC7A200T-FFG1156
##                    Speedgrade:        -1
##                    Design Entry:      VHDL
##                    Frequency:         0 MHz
##                    Time Period:       2500 ps
##################################################################################################

##################################################################################################
## Controller 0
## Memory Device: DDR3_SDRAM->Components->MT41J512M8XX-125
## Data Width: 32
## Time Period: 2500
## Data Mask: 1
##################################################################################################

#create_clock -period -2.14748e+06 [get_ports sys_clk_i]
#set_propagated_clock sys_clk_i

############## NET - IOSTANDARD ##################


# PadFunction: IO_L22P_T3_33
set_property SLEW FAST [get_ports {ddr3_dq_b[0]}]
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq_b[0]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq_b[0]}]
set_property PACKAGE_PIN AD11 [get_ports {ddr3_dq_b[0]}]

# PadFunction: IO_L24N_T3_33
set_property SLEW FAST [get_ports {ddr3_dq_b[1]}]
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq_b[1]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq_b[1]}]
set_property PACKAGE_PIN AE10 [get_ports {ddr3_dq_b[1]}]

# PadFunction: IO_L20P_T3_33
set_property SLEW FAST [get_ports {ddr3_dq_b[2]}]
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq_b[2]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq_b[2]}]
set_property PACKAGE_PIN AF12 [get_ports {ddr3_dq_b[2]}]

# PadFunction: IO_L23P_T3_33
set_property SLEW FAST [get_ports {ddr3_dq_b[3]}]
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq_b[3]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq_b[3]}]
set_property PACKAGE_PIN AG11 [get_ports {ddr3_dq_b[3]}]

# PadFunction: IO_L22N_T3_33
set_property SLEW FAST [get_ports {ddr3_dq_b[4]}]
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq_b[4]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq_b[4]}]
set_property PACKAGE_PIN AE11 [get_ports {ddr3_dq_b[4]}]

# PadFunction: IO_L23N_T3_33
set_property SLEW FAST [get_ports {ddr3_dq_b[5]}]
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq_b[5]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq_b[5]}]
set_property PACKAGE_PIN AH11 [get_ports {ddr3_dq_b[5]}]

# PadFunction: IO_L20N_T3_33
set_property SLEW FAST [get_ports {ddr3_dq_b[6]}]
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq_b[6]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq_b[6]}]
set_property PACKAGE_PIN AG12 [get_ports {ddr3_dq_b[6]}]

# PadFunction: IO_L19P_T3_33
set_property SLEW FAST [get_ports {ddr3_dq_b[7]}]
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq_b[7]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq_b[7]}]
set_property PACKAGE_PIN AH9 [get_ports {ddr3_dq_b[7]}]

# PadFunction: IO_L13P_T2_MRCC_33
set_property SLEW FAST [get_ports {ddr3_dq_b[8]}]
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq_b[8]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq_b[8]}]
set_property PACKAGE_PIN AD6 [get_ports {ddr3_dq_b[8]}]

# PadFunction: IO_L14N_T2_SRCC_33
set_property SLEW FAST [get_ports {ddr3_dq_b[9]}]
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq_b[9]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq_b[9]}]
set_property PACKAGE_PIN AG7 [get_ports {ddr3_dq_b[9]}]

# PadFunction: IO_L18P_T2_33
set_property SLEW FAST [get_ports {ddr3_dq_b[10]}]
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq_b[10]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq_b[10]}]
set_property PACKAGE_PIN AF9 [get_ports {ddr3_dq_b[10]}]

# PadFunction: IO_L17P_T2_33
set_property SLEW FAST [get_ports {ddr3_dq_b[11]}]
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq_b[11]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq_b[11]}]
set_property PACKAGE_PIN AH7 [get_ports {ddr3_dq_b[11]}]

# PadFunction: IO_L16P_T2_33
set_property SLEW FAST [get_ports {ddr3_dq_b[12]}]
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq_b[12]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq_b[12]}]
set_property PACKAGE_PIN AE8 [get_ports {ddr3_dq_b[12]}]

# PadFunction: IO_L18N_T2_33
set_property SLEW FAST [get_ports {ddr3_dq_b[13]}]
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq_b[13]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq_b[13]}]
set_property PACKAGE_PIN AF8 [get_ports {ddr3_dq_b[13]}]

# PadFunction: IO_L16N_T2_33
set_property SLEW FAST [get_ports {ddr3_dq_b[14]}]
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq_b[14]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq_b[14]}]
set_property PACKAGE_PIN AE7 [get_ports {ddr3_dq_b[14]}]

# PadFunction: IO_L14P_T2_SRCC_33
set_property SLEW FAST [get_ports {ddr3_dq_b[15]}]
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq_b[15]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq_b[15]}]
set_property PACKAGE_PIN AF7 [get_ports {ddr3_dq_b[15]}]

# PadFunction: IO_L7P_T1_33
set_property SLEW FAST [get_ports {ddr3_dq_b[16]}]
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq_b[16]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq_b[16]}]
set_property PACKAGE_PIN AF4 [get_ports {ddr3_dq_b[16]}]

# PadFunction: IO_L12N_T1_MRCC_33
set_property SLEW FAST [get_ports {ddr3_dq_b[17]}]
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq_b[17]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq_b[17]}]
set_property PACKAGE_PIN AF5 [get_ports {ddr3_dq_b[17]}]

# PadFunction: IO_L10P_T1_33
set_property SLEW FAST [get_ports {ddr3_dq_b[18]}]
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq_b[18]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq_b[18]}]
set_property PACKAGE_PIN AD3 [get_ports {ddr3_dq_b[18]}]

# PadFunction: IO_L11N_T1_SRCC_33
set_property SLEW FAST [get_ports {ddr3_dq_b[19]}]
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq_b[19]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq_b[19]}]
set_property PACKAGE_PIN AG5 [get_ports {ddr3_dq_b[19]}]

# PadFunction: IO_L8P_T1_33
set_property SLEW FAST [get_ports {ddr3_dq_b[20]}]
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq_b[20]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq_b[20]}]
set_property PACKAGE_PIN AD5 [get_ports {ddr3_dq_b[20]}]

# PadFunction: IO_L11P_T1_SRCC_33
set_property SLEW FAST [get_ports {ddr3_dq_b[21]}]
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq_b[21]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq_b[21]}]
set_property PACKAGE_PIN AG6 [get_ports {ddr3_dq_b[21]}]

# PadFunction: IO_L8N_T1_33
set_property SLEW FAST [get_ports {ddr3_dq_b[22]}]
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq_b[22]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq_b[22]}]
set_property PACKAGE_PIN AD4 [get_ports {ddr3_dq_b[22]}]

# PadFunction: IO_L10N_T1_33
set_property SLEW FAST [get_ports {ddr3_dq_b[23]}]
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq_b[23]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq_b[23]}]
set_property PACKAGE_PIN AE3 [get_ports {ddr3_dq_b[23]}]

# PadFunction: IO_L1P_T0_33
set_property SLEW FAST [get_ports {ddr3_dq_b[24]}]
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq_b[24]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq_b[24]}]
set_property PACKAGE_PIN AG1 [get_ports {ddr3_dq_b[24]}]

# PadFunction: IO_L5N_T0_33
set_property SLEW FAST [get_ports {ddr3_dq_b[25]}]
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq_b[25]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq_b[25]}]
set_property PACKAGE_PIN AG2 [get_ports {ddr3_dq_b[25]}]

# PadFunction: IO_L2N_T0_33
set_property SLEW FAST [get_ports {ddr3_dq_b[26]}]
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq_b[26]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq_b[26]}]
set_property PACKAGE_PIN AE1 [get_ports {ddr3_dq_b[26]}]

# PadFunction: IO_L5P_T0_33
set_property SLEW FAST [get_ports {ddr3_dq_b[27]}]
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq_b[27]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq_b[27]}]
set_property PACKAGE_PIN AF3 [get_ports {ddr3_dq_b[27]}]

# PadFunction: IO_L4P_T0_33
set_property SLEW FAST [get_ports {ddr3_dq_b[28]}]
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq_b[28]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq_b[28]}]
set_property PACKAGE_PIN AE2 [get_ports {ddr3_dq_b[28]}]

# PadFunction: IO_L6P_T0_33
set_property SLEW FAST [get_ports {ddr3_dq_b[29]}]
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq_b[29]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq_b[29]}]
set_property PACKAGE_PIN AH3 [get_ports {ddr3_dq_b[29]}]

# PadFunction: IO_L2P_T0_33
set_property SLEW FAST [get_ports {ddr3_dq_b[30]}]
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq_b[30]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq_b[30]}]
set_property PACKAGE_PIN AD1 [get_ports {ddr3_dq_b[30]}]

# PadFunction: IO_L4N_T0_33
set_property SLEW FAST [get_ports {ddr3_dq_b[31]}]
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq_b[31]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq_b[31]}]
set_property PACKAGE_PIN AF2 [get_ports {ddr3_dq_b[31]}]

# PadFunction: IO_L5N_T0_32
set_property SLEW FAST [get_ports {ddr3_addr_o[15]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr_o[15]}]
set_property PACKAGE_PIN AP3 [get_ports {ddr3_addr_o[15]}]

# PadFunction: IO_L15N_T2_DQS_32
set_property SLEW FAST [get_ports {ddr3_addr_o[14]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr_o[14]}]
set_property PACKAGE_PIN AK8 [get_ports {ddr3_addr_o[14]}]

# PadFunction: IO_L14P_T2_SRCC_32
set_property SLEW FAST [get_ports {ddr3_addr_o[13]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr_o[13]}]
set_property PACKAGE_PIN AM7 [get_ports {ddr3_addr_o[13]}]

# PadFunction: IO_L9N_T1_DQS_32
set_property SLEW FAST [get_ports {ddr3_addr_o[12]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr_o[12]}]
set_property PACKAGE_PIN AP5 [get_ports {ddr3_addr_o[12]}]

# PadFunction: IO_L15P_T2_DQS_32
set_property SLEW FAST [get_ports {ddr3_addr_o[11]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr_o[11]}]
set_property PACKAGE_PIN AJ8 [get_ports {ddr3_addr_o[11]}]

# PadFunction: IO_L3N_T0_DQS_32
set_property SLEW FAST [get_ports {ddr3_addr_o[10]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr_o[10]}]
set_property PACKAGE_PIN AN2 [get_ports {ddr3_addr_o[10]}]

# PadFunction: IO_L10P_T1_32
set_property SLEW FAST [get_ports {ddr3_addr_o[9]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr_o[9]}]
set_property PACKAGE_PIN AL4 [get_ports {ddr3_addr_o[9]}]

# PadFunction: IO_L12N_T1_MRCC_32
set_property SLEW FAST [get_ports {ddr3_addr_o[8]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr_o[8]}]
set_property PACKAGE_PIN AK6 [get_ports {ddr3_addr_o[8]}]

# PadFunction: IO_L9P_T1_DQS_32
set_property SLEW FAST [get_ports {ddr3_addr_o[7]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr_o[7]}]
set_property PACKAGE_PIN AP6 [get_ports {ddr3_addr_o[7]}]

# PadFunction: IO_L8N_T1_32
set_property SLEW FAST [get_ports {ddr3_addr_o[6]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr_o[6]}]
set_property PACKAGE_PIN AK5 [get_ports {ddr3_addr_o[6]}]

# PadFunction: IO_L6P_T0_32
set_property SLEW FAST [get_ports {ddr3_addr_o[5]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr_o[5]}]
set_property PACKAGE_PIN AK3 [get_ports {ddr3_addr_o[5]}]

# PadFunction: IO_L7P_T1_32
set_property SLEW FAST [get_ports {ddr3_addr_o[4]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr_o[4]}]
set_property PACKAGE_PIN AN4 [get_ports {ddr3_addr_o[4]}]

# PadFunction: IO_L14N_T2_SRCC_32
set_property SLEW FAST [get_ports {ddr3_addr_o[3]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr_o[3]}]
set_property PACKAGE_PIN AM6 [get_ports {ddr3_addr_o[3]}]

# PadFunction: IO_L10N_T1_32
set_property SLEW FAST [get_ports {ddr3_addr_o[2]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr_o[2]}]
set_property PACKAGE_PIN AM4 [get_ports {ddr3_addr_o[2]}]

# PadFunction: IO_L12P_T1_MRCC_32
set_property SLEW FAST [get_ports {ddr3_addr_o[1]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr_o[1]}]
set_property PACKAGE_PIN AJ6 [get_ports {ddr3_addr_o[1]}]

# PadFunction: IO_L7N_T1_32
set_property SLEW FAST [get_ports {ddr3_addr_o[0]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr_o[0]}]
set_property PACKAGE_PIN AP4 [get_ports {ddr3_addr_o[0]}]

# PadFunction: IO_L2N_T0_32
set_property SLEW FAST [get_ports {ddr3_ba_o[2]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_ba_o[2]}]
set_property PACKAGE_PIN AK1 [get_ports {ddr3_ba_o[2]}]

# PadFunction: IO_L2P_T0_32
set_property SLEW FAST [get_ports {ddr3_ba_o[1]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_ba_o[1]}]
set_property PACKAGE_PIN AK2 [get_ports {ddr3_ba_o[1]}]

# PadFunction: IO_L3P_T0_DQS_32
set_property SLEW FAST [get_ports {ddr3_ba_o[0]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_ba_o[0]}]
set_property PACKAGE_PIN AM2 [get_ports {ddr3_ba_o[0]}]

# PadFunction: IO_L1P_T0_32
set_property SLEW FAST [get_ports ddr3_ras_n_o]
set_property IOSTANDARD SSTL15 [get_ports ddr3_ras_n_o]
set_property PACKAGE_PIN AN1 [get_ports ddr3_ras_n_o]

# PadFunction: IO_L4P_T0_32
set_property SLEW FAST [get_ports ddr3_cas_n_o]
set_property IOSTANDARD SSTL15 [get_ports ddr3_cas_n_o]
set_property PACKAGE_PIN AL2 [get_ports ddr3_cas_n_o]

# PadFunction: IO_L4N_T0_32
set_property SLEW FAST [get_ports ddr3_we_n_o]
set_property IOSTANDARD SSTL15 [get_ports ddr3_we_n_o]
set_property PACKAGE_PIN AM1 [get_ports ddr3_we_n_o]

# PadFunction: IO_0_32
set_property SLEW FAST [get_ports ddr3_reset_n_o]
set_property IOSTANDARD LVCMOS15 [get_ports ddr3_reset_n_o]
set_property PACKAGE_PIN AJ9 [get_ports ddr3_reset_n_o]

# PadFunction: IO_L8P_T1_32
set_property SLEW FAST [get_ports {ddr3_cke_o[0]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_cke_o[0]}]
set_property PACKAGE_PIN AJ5 [get_ports {ddr3_cke_o[0]}]

# PadFunction: IO_L1N_T0_32
set_property SLEW FAST [get_ports {ddr3_odt_o[0]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_odt_o[0]}]
set_property PACKAGE_PIN AP1 [get_ports {ddr3_odt_o[0]}]

# PadFunction: IO_L5P_T0_32
set_property SLEW FAST [get_ports {ddr3_cs_n_o[0]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_cs_n_o[0]}]
set_property PACKAGE_PIN AN3 [get_ports {ddr3_cs_n_o[0]}]

# PadFunction: IO_L24P_T3_33
set_property SLEW FAST [get_ports {ddr3_dm_o[0]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dm_o[0]}]
set_property PACKAGE_PIN AD10 [get_ports {ddr3_dm_o[0]}]

# PadFunction: IO_L17N_T2_33
set_property SLEW FAST [get_ports {ddr3_dm_o[1]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dm_o[1]}]
set_property PACKAGE_PIN AH6 [get_ports {ddr3_dm_o[1]}]

# PadFunction: IO_L7N_T1_33
set_property SLEW FAST [get_ports {ddr3_dm_o[2]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dm_o[2]}]
set_property PACKAGE_PIN AG4 [get_ports {ddr3_dm_o[2]}]

# PadFunction: IO_L1N_T0_33
set_property SLEW FAST [get_ports {ddr3_dm_o[3]}]
set_property IOSTANDARD SSTL15 [get_ports {ddr3_dm_o[3]}]
set_property PACKAGE_PIN AH1 [get_ports {ddr3_dm_o[3]}]

# PadFunction: IO_L21P_T3_DQS_33
set_property SLEW FAST [get_ports {ddr3_dqs_p_b[0]}]
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dqs_p_b[0]}]
set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_p_b[0]}]

# PadFunction: IO_L21N_T3_DQS_33
set_property SLEW FAST [get_ports {ddr3_dqs_n_b[0]}]
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dqs_n_b[0]}]
set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_n_b[0]}]
set_property PACKAGE_PIN AG9 [get_ports {ddr3_dqs_n_b[0]}]

# PadFunction: IO_L15P_T2_DQS_33
set_property SLEW FAST [get_ports {ddr3_dqs_p_b[1]}]
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dqs_p_b[1]}]
set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_p_b[1]}]

# PadFunction: IO_L15N_T2_DQS_33
set_property SLEW FAST [get_ports {ddr3_dqs_n_b[1]}]
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dqs_n_b[1]}]
set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_n_b[1]}]
set_property PACKAGE_PIN AD8 [get_ports {ddr3_dqs_n_b[1]}]

# PadFunction: IO_L9P_T1_DQS_33
set_property SLEW FAST [get_ports {ddr3_dqs_p_b[2]}]
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dqs_p_b[2]}]
set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_p_b[2]}]

# PadFunction: IO_L9N_T1_DQS_33
set_property SLEW FAST [get_ports {ddr3_dqs_n_b[2]}]
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dqs_n_b[2]}]
set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_n_b[2]}]
set_property PACKAGE_PIN AJ4 [get_ports {ddr3_dqs_n_b[2]}]

# PadFunction: IO_L3P_T0_DQS_33
set_property SLEW FAST [get_ports {ddr3_dqs_p_b[3]}]
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dqs_p_b[3]}]
set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_p_b[3]}]

# PadFunction: IO_L3N_T0_DQS_33
set_property SLEW FAST [get_ports {ddr3_dqs_n_b[3]}]
set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dqs_n_b[3]}]
set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_n_b[3]}]
set_property PACKAGE_PIN AJ1 [get_ports {ddr3_dqs_n_b[3]}]

# PadFunction: IO_L11P_T1_SRCC_32
set_property SLEW FAST [get_ports {ddr3_ck_p_o[0]}]
set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_ck_p_o[0]}]

# PadFunction: IO_L11N_T1_SRCC_32
set_property SLEW FAST [get_ports {ddr3_ck_n_o[0]}]
set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_ck_n_o[0]}]
set_property PACKAGE_PIN AM5 [get_ports {ddr3_ck_n_o[0]}]



set_property LOC PHASER_OUT_PHY_X1Y3 [get_cells  -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out}]
set_property LOC PHASER_OUT_PHY_X1Y2 [get_cells  -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out}]
set_property LOC PHASER_OUT_PHY_X1Y1 [get_cells  -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out}]
set_property LOC PHASER_OUT_PHY_X1Y7 [get_cells  -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out}]
set_property LOC PHASER_OUT_PHY_X1Y6 [get_cells  -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out}]
set_property LOC PHASER_OUT_PHY_X1Y5 [get_cells  -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out}]
set_property LOC PHASER_OUT_PHY_X1Y4 [get_cells  -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out}]

## set_property LOC PHASER_IN_PHY_X1Y3 [get_cells  -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in}]
## set_property LOC PHASER_IN_PHY_X1Y2 [get_cells  -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in}]
## set_property LOC PHASER_IN_PHY_X1Y1 [get_cells  -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_in_gen.phaser_in}]
set_property LOC PHASER_IN_PHY_X1Y7 [get_cells  -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in}]
set_property LOC PHASER_IN_PHY_X1Y6 [get_cells  -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in}]
set_property LOC PHASER_IN_PHY_X1Y5 [get_cells  -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_in_gen.phaser_in}]
set_property LOC PHASER_IN_PHY_X1Y4 [get_cells  -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_in_gen.phaser_in}]



set_property LOC OUT_FIFO_X1Y3 [get_cells  -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo}]
set_property LOC OUT_FIFO_X1Y2 [get_cells  -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo}]
set_property LOC OUT_FIFO_X1Y1 [get_cells  -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo}]
set_property LOC OUT_FIFO_X1Y7 [get_cells  -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo}]
set_property LOC OUT_FIFO_X1Y6 [get_cells  -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo}]
set_property LOC OUT_FIFO_X1Y5 [get_cells  -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo}]
set_property LOC OUT_FIFO_X1Y4 [get_cells  -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo}]

set_property LOC IN_FIFO_X1Y7 [get_cells  -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/in_fifo_gen.in_fifo}]
set_property LOC IN_FIFO_X1Y6 [get_cells  -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/in_fifo_gen.in_fifo}]
set_property LOC IN_FIFO_X1Y5 [get_cells  -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/in_fifo_gen.in_fifo}]
set_property LOC IN_FIFO_X1Y4 [get_cells  -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/in_fifo_gen.in_fifo}]

set_property LOC PHY_CONTROL_X1Y0 [get_cells  -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/phy_control_i}]
set_property LOC PHY_CONTROL_X1Y1 [get_cells  -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i}]

set_property LOC PHASER_REF_X1Y0 [get_cells  -hier -filter {NAME =~ */ddr_phy_4lanes_1.u_ddr_phy_4lanes/phaser_ref_i}]
set_property LOC PHASER_REF_X1Y1 [get_cells  -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/phaser_ref_i}]

set_property LOC OLOGIC_X1Y93 [get_cells  -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/*slave_ts}]
set_property LOC OLOGIC_X1Y81 [get_cells  -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/*slave_ts}]
set_property LOC OLOGIC_X1Y69 [get_cells  -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/*slave_ts}]
set_property LOC OLOGIC_X1Y57 [get_cells  -hier -filter {NAME =~ */ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/*slave_ts}]

set_property LOC PLLE2_ADV_X1Y0 [get_cells -hier -filter {NAME =~ */u_ddr3_infrastructure/plle2_i}]
set_property LOC MMCME2_ADV_X1Y0 [get_cells -hier -filter {NAME =~ */u_ddr3_infrastructure/gen_mmcm.mmcm_i}]


set_multicycle_path -from [get_cells -hier -filter {NAME =~ */mc0/mc_read_idle_r_reg}] \
                    -to   [get_cells -hier -filter {NAME =~ */input_[?].iserdes_dq_.iserdesdq}] \
                    -setup 6

set_multicycle_path -from [get_cells -hier -filter {NAME =~ */mc0/mc_read_idle_r_reg}] \
                    -to   [get_cells -hier -filter {NAME =~ */input_[?].iserdes_dq_.iserdesdq}] \
                    -hold 5



set_false_path -through [get_pins -filter {NAME =~ */DQSFOUND} -of [get_cells -hier -filter {REF_NAME == PHASER_IN_PHY}]]

set_multicycle_path -through [get_pins -filter {NAME =~ */OSERDESRST} -of [get_cells -hier -filter {REF_NAME == PHASER_OUT_PHY}]] -setup 2 -start
set_multicycle_path -through [get_pins -filter {NAME =~ */OSERDESRST} -of [get_cells -hier -filter {REF_NAME == PHASER_OUT_PHY}]] -hold 1 -start

set_max_delay -datapath_only -from [get_cells -hier -filter {NAME =~ *temp_mon_enabled.u_tempmon/* && IS_SEQUENTIAL}] -to [get_cells -hier -filter {NAME =~ *temp_mon_enabled.u_tempmon/device_temp_sync_r1*}] 20
set_max_delay -from [get_cells -hier *rstdiv0_sync_r1_reg*] -to [get_pins -filter {NAME =~ */RESET} -of [get_cells -hier -filter {REF_NAME == PHY_CONTROL}]] -datapath_only 5

set_max_delay -datapath_only -from [get_cells -hier -filter {NAME =~ *ddr3_infrastructure/rstdiv0_sync_r1_reg*}] -to [get_cells -hier -filter {NAME =~ *temp_mon_enabled.u_tempmon/xadc_supplied_temperature.rst_r1*}] 20
