#######################################################################
##                      Artix 7 AMC V3                               ##
#######################################################################

NET  "sys_clk_p_i"				  LOC = AK7 | IOSTANDARD = "DIFF_SSTL15" | IN_TERM = "UNTUNED_SPLIT_50"; // FPGA_CLK1_P
NET  "sys_clk_n_i"				  LOC = AL7 | IOSTANDARD = "DIFF_SSTL15" | IN_TERM = "UNTUNED_SPLIT_50"; // FPGA_CLK1_N

NET  "rs232_txd_o"				  LOC = AB11 | IOSTANDARD = "LVCMOS25";                                  // TXD		IO_25_34
NET  "rs232_rxd_i"				  LOC = Y11  | IOSTANDARD = "LVCMOS25";                                  // VADJ1_RXD	IO_0_34

# System Reset
# Bank 16 VCCO - VADJ_FPGA - IO_25_16. NET = FPGA_RESET_DN, PIN = IO_L19P_T3_13
NET "sys_rst_button_n_i"			  LOC = AG26 | IOSTANDARD = "LVCMOS25" | PULLUP | NODELAY | TIG;

# MMCM Status
###NET "fmc_mmcm_lock_led_o"                      LOC = "AP24"  |  IOSTANDARD = "LVCMOS25"; # GPIO_LED_C, DS16

# LMK clock distribution Status
###NET "fmc_pll_status_led_o"                     LOC = "AD21"  |  IOSTANDARD = "LVCMOS25"; # GPIO_LED_W, DS17

#NET "led_south_o"                                LOC = "AH28"  |  IOSTANDARD = "LVCMOS25"; # GPIO_LED_S, DS18
#NET "led_east_o"                                 LOC = "AE21"  |  IOSTANDARD = "LVCMOS25"; # GPIO_LED_E, DS19
#NET "led_north_o"                                LOC = "AH27"  |  IOSTANDARD = "LVCMOS25"; # GPIO_LED_N, DS20

#NET "board_led1_o"                               LOC = AC22 | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = SLOW; // User led 0
#NET "board_led2_o"                               LOC = AC24 | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = SLOW; // User led 1
#NET "board_led3_o"                               LOC = AE22 | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = SLOW; // User led 2

###NET "clk_swap_o"                              LOC = V34  | IOSTANDARD = LVCMOS25; # USER_SMA_GPIO_P
###NET "clk_swap2x_o"                            LOC = L23  | IOSTANDARD = LVCMOS25; # USER_SMA_CLK_P
###NET "flag1_o"                                 LOC = W34  | IOSTANDARD = LVCMOS25; # USER_SMA_GPIO_N
###NET "flag2_o"                                 LOC = M22  | IOSTANDARD = LVCMOS25; # USER_SMA_CLK_N

#######################################################################
##                      Button/LEDs Contraints                       ##
#######################################################################

###NET "leds_o[0]"                               LOC = AC22 | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = SLOW;
###NET "leds_o[1]"                               LOC = AC24 | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = SLOW;
###NET "leds_o[2]"                               LOC = AE22 | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = SLOW;
###NET "leds_o[3]"                               LOC = AE23 | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = SLOW;
###NET "leds_o[4]"                               LOC = AB23 | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = SLOW;
###NET "leds_o[5]"                               LOC = AG23 | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = SLOW;
###NET "leds_o[6]"                               LOC = AE24 | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = SLOW;
###NET "leds_o[7]"                               LOC = AD24 | IOSTANDARD = LVCMOS25 | DRIVE = 12 | SLEW = SLOW;

#######################################################################
##             Ethernet Contraints. MII 10/100 Mode                  ##
#######################################################################

###NET "mrstn_o"                                 LOC = AH13;
###NET "mcoll_pad_i"                             LOC = AK13;   ## 114 on U80
###NET "mcrs_pad_i"                              LOC = AL13;   ## 115 on U80
#### NET "PHY_INT"                               LOC = AH14;   ## 32  on U80
###NET "mdc_pad_o"                               LOC = AP14;   ## 35  on U80
###NET "md_pad_b"                                LOC = AN14;   ## 33  on U80
#### NET "PHY_RESET"                             LOC = AH13;   ## 36  on U80
###NET "mrx_clk_pad_i"                           LOC = AP11;   ## 7   on U80
###NET "mrxdv_pad_i"                             LOC = AM13;   ## 4   on U80
###NET "mrxd_pad_i[0]"                           LOC = AN13;   ## 3   on U80
###NET "mrxd_pad_i[1]"                           LOC = AF14;   ## 128 on U80
###NET "mrxd_pad_i[2]"                           LOC = AE14;   ## 126 on U80
###NET "mrxd_pad_i[3]"                           LOC = AN12;   ## 125 on U80
#### NET "PHY_RXD4"                              LOC = AM12;   ## 124 on U80
#### NET "PHY_RXD5"                              LOC = AD11;   ## 123 on U80
#### NET "PHY_RXD6"                              LOC = AC12;   ## 121 on U80
#### NET "PHY_RXD7"                              LOC = AC13;   ## 120 on U80
###NET "mrxerr_pad_i"                            LOC = AG12;   ## 9   on U80
###NET "mtx_clk_pad_i"                           LOC = AD12;   ## 10  on U80
###NET "mtxen_pad_o"                             LOC = AJ10;   ## 16  on U80
#### NET "PHY_TXC_GTXCLK"                        LOC = AH12;   ## 14  on U80
###NET "mtxd_pad_o[0]"                           LOC = AM11;   ## 18  on U80
###NET "mtxd_pad_o[1]"                           LOC = AL11;   ## 19  on U80
###NET "mtxd_pad_o[2]"                           LOC = AG10;   ## 20  on U80
###NET "mtxd_pad_o[3]"                           LOC = AG11;   ## 24  on U80
#### NET "PHY_TXD4"                              LOC = AL10;   ## 25  on U80
#### NET "PHY_TXD5"                              LOC = AM10;   ## 26  on U80
#### NET "PHY_TXD6"                              LOC = AE11;   ## 28  on U80
#### NET "PHY_TXD7"                              LOC = AF11;   ## 29  on U80
###NET "mtxerr_pad_o"                            LOC = AH10;   ## 13  on U80

#######################################################################
##                      FMC Connector HPC1                           ##
#######################################################################

###NET  "fmc1_prsnt_i"                            LOC =  | IOSTANDARD = "LVCMOS25";   // Connected to CPU
###NET  "fmc1_pg_m2c_i"                           LOC =  | IOSTANDARD = "LVCMOS25";   // Connected to CPU

// Trigger
NET "fmc1_trig_dir_o"                          LOC = T8   | IOSTANDARD = "LVCMOS25";  // LA28_P
NET "fmc1_trig_term_o"                         LOC = T2   | IOSTANDARD = "LVCMOS25";  // LA26_N
NET "fmc1_trig_val_p_b"                        LOC = R1   | IOSTANDARD = "BLVDS_25";  // LA32_P
NET "fmc1_trig_val_n_b"                        LOC = P1   | IOSTANDARD = "BLVDS_25";  // LA32_N

// Si571 clock gen
NET "fmc1_si571_scl_pad_b"                     LOC = G34  | IOSTANDARD = "LVCMOS25";  // HA12_N
NET "fmc1_si571_sda_pad_b"                     LOC = K25  | IOSTANDARD = "LVCMOS25";  // HA13_P
NET "fmc1_si571_oe_o"                          LOC = H33  | IOSTANDARD = "LVCMOS25";  // HA12_P

// AD9510 clock distribution PLL
NET "fmc1_spi_ad9510_cs_o"                     LOC = G9   | IOSTANDARD = "LVCMOS25";   // LA13_N
NET "fmc1_spi_ad9510_sclk_o"                   LOC = G10  | IOSTANDARD = "LVCMOS25";  // LA13_P
NET "fmc1_spi_ad9510_mosi_o"                   LOC = J3   | IOSTANDARD = "LVCMOS25";  // LA09_N
NET "fmc1_spi_ad9510_miso_i"                   LOC = H9   | IOSTANDARD = "LVCMOS25";  // LA14_P
NET "fmc1_pll_function_o"                      LOC = H8   | IOSTANDARD = "LVCMOS25";  // LA14_N
NET "fmc1_pll_status_i"                        LOC = J4   | IOSTANDARD = "LVCMOS25";  // LA09_P

###NET "fmc1_fpga_clk_p_i"                        LOC = H7  | IOSTANDARD = "LVDS_25";  // CLK0_M2C_P
###NET "fmc1_fpga_clk_n_i"                        LOC = H6  | IOSTANDARD = "LVDS_25";  // CLK0_M2C_N

// Clock reference selection (TS3USB221)
NET "fmc1_clk_sel_o"                           LOC = U7   | IOSTANDARD = "LVCMOS25";  // LA31_P

// EEPROM (multiplexer PCA9548) (Connected to the CPU)
NET "fmc1_eeprom_scl_pad_b"                    LOC = P6   | IOSTANDARD = "LVCMOS25";   # FPGA I2C SCL
NET "fmc1_eeprom_sda_pad_b"                    LOC = R11  | IOSTANDARD = "LVCMOS25";   # FPGA I2C SDA

// LM75 temperature monitor
NET "fmc1_lm75_scl_pad_b"                      LOC = R3   | IOSTANDARD = "LVCMOS25";  // LA27_P
NET "fmc1_lm75_sda_pad_b"                      LOC = R2   | IOSTANDARD = "LVCMOS25";  // LA27_N
NET "fmc1_lm75_temp_alarm_i"                   LOC = T7   | IOSTANDARD = "LVCMOS25";  // LA28_N

// LTC ADC control pins
NET "fmc1_adc_pga_o"                           LOC = L5   | IOSTANDARD = "LVCMOS25";  // LA06_P
NET "fmc1_adc_shdn_o"                          LOC = G2   | IOSTANDARD = "LVCMOS25";  // LA10_N
NET "fmc1_adc_dith_o"                          LOC = H2   | IOSTANDARD = "LVCMOS25";  // LA10_P
NET "fmc1_adc_rand_o"                          LOC = K5   | IOSTANDARD = "LVCMOS25";  // LA06_N

// LEDs
NET "fmc1_led1_o"                              LOC = L9   | IOSTANDARD = "LVCMOS25";  // LA16_N
NET "fmc1_led2_o"                              LOC = L10  | IOSTANDARD = "LVCMOS25";  // LA16_P
NET "fmc1_led3_o"                              LOC = T3   | IOSTANDARD = "LVCMOS25";  // LA26_P

#######################################################################
##                      FMC Connector HPC2                           ##
#######################################################################

###NET  "fmc2_prsnt_i"                            LOC =  | IOSTANDARD = "LVCMOS25";//  Connected to CPU
###NET  "fmc2_pg_m2c_i"                           LOC =  | IOSTANDARD = "LVCMOS25";//  Connected to CPU

// Trigger
NET "fmc2_trig_dir_o"                          LOC = W28  | IOSTANDARD = "LVCMOS25";  // LA28_P
NET "fmc2_trig_term_o"                         LOC = AC32 | IOSTANDARD = "LVCMOS25";  // LA26_N
NET "fmc2_trig_val_p_b"                        LOC = AA34 | IOSTANDARD = "BLVDS_25";  // LA32_P
NET "fmc2_trig_val_n_b"                        LOC = AB34 | IOSTANDARD = "BLVDS_25";  // LA32_N

// Si571 clock gen
NET "fmc2_si571_scl_pad_b"                     LOC = AN29 | IOSTANDARD = "LVCMOS25";  // HA12_N
NET "fmc2_si571_sda_pad_b"                     LOC = AN28 | IOSTANDARD = "LVCMOS25";  // HA13_P
NET "fmc2_si571_oe_o"                          LOC = AM29 | IOSTANDARD = "LVCMOS25";  // HA12_P

// AD9510 clock distribution PLL
NET "fmc2_spi_ad9510_cs_o"                     LOC = AG34 | IOSTANDARD = "LVCMOS25";  // LA13_N
NET "fmc2_spi_ad9510_sclk_o"                   LOC = AF34 | IOSTANDARD = "LVCMOS25";  // LA13_P
NET "fmc2_spi_ad9510_mosi_o"                   LOC = AG25 | IOSTANDARD = "LVCMOS25";  // LA09_N
NET "fmc2_spi_ad9510_miso_i"                   LOC = AE33 | IOSTANDARD = "LVCMOS25";  // LA14_P
NET "fmc2_pll_function_o"                      LOC = AF33 | IOSTANDARD = "LVCMOS25";  // LA14_N
NET "fmc2_pll_status_i"                        LOC = AF25 | IOSTANDARD = "LVCMOS25";  // LA09_P

###NET "fmc2_fpga_clk_p_i"                       LOC = AA30 | IOSTANDARD = "LVDS_25";  // CLK0_M2C_P
###NET "fmc2_fpga_clk_n_i"                       LOC = AB30 | IOSTANDARD = "LVDS_25";  // CLK0_M2C_N

// Clock reference selection (TS3USB221)
NET "fmc2_clk_sel_o"                           LOC = V31  | IOSTANDARD = "LVCMOS25";  // LA31_P

// EEPROM (multiplexer PCA9548) (Connected to the CPU)
###NET "eeprom_scl_pad_b"                        LOC =  | IOSTANDARD ="LVCMOS25"; #  SCL C30
###NET "eeprom_sda_pad_b"                        LOC =  | IOSTANDARD ="LVCMOS25"; #  SDA C31

// LM75 temperature monitor
NET "fmc2_lm75_scl_pad_b"                      LOC = AA27 | IOSTANDARD = "LVCMOS25";  // LA27_P
NET "fmc2_lm75_sda_pad_b"                      LOC = AA28 | IOSTANDARD = "LVCMOS25";  // LA27_N
NET "fmc2_lm75_temp_alarm_i"                   LOC = W29  | IOSTANDARD = "LVCMOS25";  // LA28_N

// LTC ADC control pins
NET "fmc2_adc_pga_o"                           LOC = AE23 | IOSTANDARD = "LVCMOS25";  // LA06_P
NET "fmc2_adc_shdn_o"                          LOC = AH32 | IOSTANDARD = "LVCMOS25";  // LA10_N
NET "fmc2_adc_dith_o"                          LOC = AG32 | IOSTANDARD = "LVCMOS25";  // LA10_P
NET "fmc2_adc_rand_o"                          LOC = AF23 | IOSTANDARD = "LVCMOS25";  // LA06_N

// LEDs
NET "fmc2_led1_o"                              LOC = AD34 | IOSTANDARD = "LVCMOS25";  // LA16_N
NET "fmc2_led2_o"                              LOC = AD33 | IOSTANDARD = "LVCMOS25";  // LA16_P
NET "fmc2_led3_o"                              LOC = AC31 | IOSTANDARD = "LVCMOS25";  // LA26_P

#######################################################################
##                       FMC Connector HPC1                           #
##                         LTC ADC lines                              #
#######################################################################

// ADC0
NET "fmc1_adc0_clk_i"                          LOC = T5   | IOSTANDARD = "LVCMOS25"; // LA17_CC_P

NET "fmc1_adc0_data_i[0]"                      LOC = M11   | IOSTANDARD = "LVCMOS25"; // LA24_P
NET "fmc1_adc0_data_i[1]"                      LOC = M10   | IOSTANDARD = "LVCMOS25"; // LA24_N
NET "fmc1_adc0_data_i[2]"                      LOC = N8    | IOSTANDARD = "LVCMOS25"; // LA25_P
NET "fmc1_adc0_data_i[3]"                      LOC = N7    | IOSTANDARD = "LVCMOS25"; // LA25_N
NET "fmc1_adc0_data_i[4]"                      LOC = M7    | IOSTANDARD = "LVCMOS25"; // LA21_P
NET "fmc1_adc0_data_i[5]"                      LOC = M6    | IOSTANDARD = "LVCMOS25"; // LA21_N
NET "fmc1_adc0_data_i[6]"                      LOC = M5    | IOSTANDARD = "LVCMOS25"; // LA22_P
NET "fmc1_adc0_data_i[7]"                      LOC = M4    | IOSTANDARD = "LVCMOS25"; // LA22_N
NET "fmc1_adc0_data_i[8]"                      LOC = N2    | IOSTANDARD = "LVCMOS25"; // LA23_N
NET "fmc1_adc0_data_i[9]"                      LOC = U4    | IOSTANDARD = "LVCMOS25"; // LA19_N
NET "fmc1_adc0_data_i[10]"                     LOC = P3    | IOSTANDARD = "LVCMOS25"; // LA18_CC_N
NET "fmc1_adc0_data_i[11]"                     LOC = N3    | IOSTANDARD = "LVCMOS25"; // LA23_P
NET "fmc1_adc0_data_i[12]"                     LOC = P10   | IOSTANDARD = "LVCMOS25"; // LA20_N
NET "fmc1_adc0_data_i[13]"                     LOC = U5    | IOSTANDARD = "LVCMOS25"; // LA19_P
NET "fmc1_adc0_data_i[14]"                     LOC = P4    | IOSTANDARD = "LVCMOS25"; // LA18_CC_P
NET "fmc1_adc0_data_i[15]"                     LOC = R10   | IOSTANDARD = "LVCMOS25"; // LA20_P
NET "fmc1_adc0_of_i"                           LOC = P9    | IOSTANDARD = "LVCMOS25"; // LA29_P

// ADC1
NET "fmc1_adc1_clk_i"                          LOC = J28   | IOSTANDARD = "LVCMOS25"; // HA17_CC_P

NET "fmc1_adc1_data_i[15]"                     LOC = H32   | IOSTANDARD = "LVCMOS25"; // HA10_P
NET "fmc1_adc1_data_i[14]"                     LOC = M25   | IOSTANDARD = "LVCMOS25"; // HA11_P
NET "fmc1_adc1_data_i[13]"                     LOC = G32   | IOSTANDARD = "LVCMOS25"; // HA10_N
NET "fmc1_adc1_data_i[12]"                     LOC = L25   | IOSTANDARD = "LVCMOS25"; // HA11_N
NET "fmc1_adc1_data_i[11]"                     LOC = G29   | IOSTANDARD = "LVCMOS25"; // HA15_P
NET "fmc1_adc1_data_i[10]"                     LOC = M24   | IOSTANDARD = "LVCMOS25"; // HA14_P
NET "fmc1_adc1_data_i[9]"                      LOC = G30   | IOSTANDARD = "LVCMOS25"; // HA15_N
NET "fmc1_adc1_data_i[8]"                      LOC = L24   | IOSTANDARD = "LVCMOS25"; // HA14_N
NET "fmc1_adc1_data_i[7]"                      LOC = G27   | IOSTANDARD = "LVCMOS25"; // HA18_N
NET "fmc1_adc1_data_i[6]"                      LOC = H27   | IOSTANDARD = "LVCMOS25"; // HA18_P
NET "fmc1_adc1_data_i[5]"                      LOC = G26   | IOSTANDARD = "LVCMOS25"; // HA19_N
NET "fmc1_adc1_data_i[4]"                      LOC = G24   | IOSTANDARD = "LVCMOS25"; // HA21_P
NET "fmc1_adc1_data_i[3]"                      LOC = J24   | IOSTANDARD = "LVCMOS25"; // HA22_P
NET "fmc1_adc1_data_i[2]"                      LOC = G25   | IOSTANDARD = "LVCMOS25"; // HA21_N
NET "fmc1_adc1_data_i[1]"                      LOC = K23   | IOSTANDARD = "LVCMOS25"; // HA23_P
NET "fmc1_adc1_data_i[0]"                      LOC = H24   | IOSTANDARD = "LVCMOS25"; // HA22_N
NET "fmc1_adc1_of_i"                           LOC = J23   | IOSTANDARD = "LVCMOS25"; // HA23_N

// ADC2
NET "fmc1_adc2_clk_i"                          LOC = K7    | IOSTANDARD = "LVCMOS25"; // LA00_CC_P

NET "fmc1_adc2_data_i[15]"                     LOC = J6    | IOSTANDARD = "LVCMOS25"; // LA01_CC_P
NET "fmc1_adc2_data_i[14]"                     LOC = G7    | IOSTANDARD = "LVCMOS25"; // LA02_P
NET "fmc1_adc2_data_i[13]"                     LOC = J5    | IOSTANDARD = "LVCMOS25"; // LA01_CC_N
NET "fmc1_adc2_data_i[12]"                     LOC = G6    | IOSTANDARD = "LVCMOS25"; // LA02_N
NET "fmc1_adc2_data_i[11]"                     LOC = G1    | IOSTANDARD = "LVCMOS25"; // LA03_N
NET "fmc1_adc2_data_i[10]"                     LOC = H1    | IOSTANDARD = "LVCMOS25"; // LA03_P
NET "fmc1_adc2_data_i[9]"                      LOC = J1    | IOSTANDARD = "LVCMOS25"; // LA04_N
NET "fmc1_adc2_data_i[8]"                      LOC = K1    | IOSTANDARD = "LVCMOS25"; // LA04_P
NET "fmc1_adc2_data_i[7]"                      LOC = H3    | IOSTANDARD = "LVCMOS25"; // LA05_N
NET "fmc1_adc2_data_i[6]"                      LOC = H4    | IOSTANDARD = "LVCMOS25"; // LA05_P
NET "fmc1_adc2_data_i[5]"                      LOC = F2    | IOSTANDARD = "LVCMOS25"; // LA08_N
NET "fmc1_adc2_data_i[4]"                      LOC = F3    | IOSTANDARD = "LVCMOS25"; // LA08_P
NET "fmc1_adc2_data_i[3]"                      LOC = K2    | IOSTANDARD = "LVCMOS25"; // LA07_N
NET "fmc1_adc2_data_i[2]"                      LOC = K3    | IOSTANDARD = "LVCMOS25"; // LA07_P
NET "fmc1_adc2_data_i[1]"                      LOC = K8    | IOSTANDARD = "LVCMOS25"; // LA12_N
NET "fmc1_adc2_data_i[0]"                      LOC = L8    | IOSTANDARD = "LVCMOS25"; // LA12_P
NET "fmc1_adc2_of_i"                           LOC = M2    | IOSTANDARD = "LVCMOS25"; // LA11_P

// ADC3
NET "fmc1_adc3_clk_i"                          LOC = L28   | IOSTANDARD = "LVCMOS25"; // HA01_CC_P

NET "fmc1_adc3_data_i[15]"                     LOC = H29   | IOSTANDARD = "LVCMOS25"; // HA00_CC_N
NET "fmc1_adc3_data_i[14]"                     LOC = J29   | IOSTANDARD = "LVCMOS25"; // HA00_CC_P
NET "fmc1_adc3_data_i[13]"                     LOC = H34   | IOSTANDARD = "LVCMOS25"; // HA05_N
NET "fmc1_adc3_data_i[12]"                     LOC = J33   | IOSTANDARD = "LVCMOS25"; // HA05_P
NET "fmc1_adc3_data_i[11]"                     LOC = L34   | IOSTANDARD = "LVCMOS25"; // HA04_N
NET "fmc1_adc3_data_i[10]"                     LOC = L33   | IOSTANDARD = "LVCMOS25"; // HA04_P
NET "fmc1_adc3_data_i[9]"                      LOC = J31   | IOSTANDARD = "LVCMOS25"; // HA09_N
NET "fmc1_adc3_data_i[8]"                      LOC = K31   | IOSTANDARD = "LVCMOS25"; // HA09_P
NET "fmc1_adc3_data_i[7]"                      LOC = J30   | IOSTANDARD = "LVCMOS25"; // HA03_N
NET "fmc1_adc3_data_i[6]"                      LOC = K30   | IOSTANDARD = "LVCMOS25"; // HA03_P
NET "fmc1_adc3_data_i[5]"                      LOC = L29   | IOSTANDARD = "LVCMOS25"; // HA08_P
NET "fmc1_adc3_data_i[4]"                      LOC = K33   | IOSTANDARD = "LVCMOS25"; // HA02_P
NET "fmc1_adc3_data_i[3]"                      LOC = L32   | IOSTANDARD = "LVCMOS25"; // HA07_P
NET "fmc1_adc3_data_i[2]"                      LOC = J34   | IOSTANDARD = "LVCMOS25"; // HA02_N
NET "fmc1_adc3_data_i[1]"                      LOC = L27   | IOSTANDARD = "LVCMOS25"; // HA06_P
NET "fmc1_adc3_data_i[0]"                      LOC = K32   | IOSTANDARD = "LVCMOS25"; // HA07_N
NET "fmc1_adc3_of_i"                           LOC = K27   | IOSTANDARD = "LVCMOS25"; // HA06_N

#######################################################################
##                       FMC Connector HPC2                           #
##                         LTC ADC lines                              #
#######################################################################

// ADC0
NET "fmc2_adc0_clk_i"                          LOC = AB31  | IOSTANDARD = "LVCMOS25"; // LA17_CC_P

NET "fmc2_adc0_data_i[0]"                      LOC = Y32   | IOSTANDARD = "LVCMOS25"; // LA24_P
NET "fmc2_adc0_data_i[1]"                      LOC = Y33   | IOSTANDARD = "LVCMOS25"; // LA24_N
NET "fmc2_adc0_data_i[2]"                      LOC = AA29  | IOSTANDARD = "LVCMOS25"; // LA25_P
NET "fmc2_adc0_data_i[3]"                      LOC = AB29  | IOSTANDARD = "LVCMOS25"; // LA25_N
NET "fmc2_adc0_data_i[4]"                      LOC = AA32  | IOSTANDARD = "LVCMOS25"; // LA21_P
NET "fmc2_adc0_data_i[5]"                      LOC = AA33  | IOSTANDARD = "LVCMOS25"; // LA21_N
NET "fmc2_adc0_data_i[6]"                      LOC = AA24  | IOSTANDARD = "LVCMOS25"; // LA22_P
NET "fmc2_adc0_data_i[7]"                      LOC = AA25  | IOSTANDARD = "LVCMOS25"; // LA22_N
NET "fmc2_adc0_data_i[8]"                      LOC = Y25   | IOSTANDARD = "LVCMOS25"; // LA23_N
NET "fmc2_adc0_data_i[9]"                      LOC = AB27  | IOSTANDARD = "LVCMOS25"; // LA19_N
NET "fmc2_adc0_data_i[10]"                     LOC = W31   | IOSTANDARD = "LVCMOS25"; // LA18_CC_N
NET "fmc2_adc0_data_i[11]"                     LOC = W25   | IOSTANDARD = "LVCMOS25"; // LA23_P
NET "fmc2_adc0_data_i[12]"                     LOC = AB25  | IOSTANDARD = "LVCMOS25"; // LA20_N
NET "fmc2_adc0_data_i[13]"                     LOC = AB26  | IOSTANDARD = "LVCMOS25"; // LA19_P
NET "fmc2_adc0_data_i[14]"                     LOC = W30   | IOSTANDARD = "LVCMOS25"; // LA18_CC_P
NET "fmc2_adc0_data_i[15]"                     LOC = AB24  | IOSTANDARD = "LVCMOS25"; // LA20_P
NET "fmc2_adc0_of_i"                           LOC = AC33  | IOSTANDARD = "LVCMOS25"; // LA29_P

// ADC1
NET "fmc2_adc1_clk_i"                          LOC = AJ28  | IOSTANDARD = "LVCMOS25"; // HA17_CC_P

NET "fmc2_adc1_data_i[15]"                     LOC = AP25  | IOSTANDARD = "LVCMOS25"; // HA10_P
NET "fmc2_adc1_data_i[14]"                     LOC = AK33  | IOSTANDARD = "LVCMOS25"; // HA11_P
NET "fmc2_adc1_data_i[13]"                     LOC = AP26  | IOSTANDARD = "LVCMOS25"; // HA10_N
NET "fmc2_adc1_data_i[12]"                     LOC = AL33  | IOSTANDARD = "LVCMOS25"; // HA11_N
NET "fmc2_adc1_data_i[11]"                     LOC = AJ29  | IOSTANDARD = "LVCMOS25"; // HA15_P
NET "fmc2_adc1_data_i[10]"                     LOC = AN34  | IOSTANDARD = "LVCMOS25"; // HA14_P
NET "fmc2_adc1_data_i[9]"                      LOC = AK30  | IOSTANDARD = "LVCMOS25"; // HA15_N
NET "fmc2_adc1_data_i[8]"                      LOC = AP34  | IOSTANDARD = "LVCMOS25"; // HA14_N
NET "fmc2_adc1_data_i[7]"                      LOC = AP33  | IOSTANDARD = "LVCMOS25"; // HA18_N
NET "fmc2_adc1_data_i[6]"                      LOC = AN33  | IOSTANDARD = "LVCMOS25"; // HA18_P
NET "fmc2_adc1_data_i[5]"                      LOC = AK31  | IOSTANDARD = "LVCMOS25"; // HA19_N
NET "fmc2_adc1_data_i[4]"                      LOC = AP29  | IOSTANDARD = "LVCMOS25"; // HA21_P
NET "fmc2_adc1_data_i[3]"                      LOC = AL34  | IOSTANDARD = "LVCMOS25"; // HA22_P
NET "fmc2_adc1_data_i[2]"                      LOC = AP30  | IOSTANDARD = "LVCMOS25"; // HA21_N
NET "fmc2_adc1_data_i[1]"                      LOC = AJ33  | IOSTANDARD = "LVCMOS25"; // HA23_P
NET "fmc2_adc1_data_i[0]"                      LOC = AM34  | IOSTANDARD = "LVCMOS25"; // HA22_N
NET "fmc2_adc1_of_i"                           LOC = AJ34  | IOSTANDARD = "LVCMOS25"; // HA23_N

// ADC2
NET "fmc2_adc2_clk_i"                          LOC = AE28  | IOSTANDARD = "LVCMOS25"; // LA00_CC_P

NET "fmc2_adc2_data_i[15]"                     LOC = AF29  | IOSTANDARD = "LVCMOS25"; // LA01_CC_P
NET "fmc2_adc2_data_i[14]"                     LOC = AG31  | IOSTANDARD = "LVCMOS25"; // LA02_P
NET "fmc2_adc2_data_i[13]"                     LOC = AF30  | IOSTANDARD = "LVCMOS25"; // LA01_CC_N
NET "fmc2_adc2_data_i[12]"                     LOC = AH31  | IOSTANDARD = "LVCMOS25"; // LA02_N
NET "fmc2_adc2_data_i[11]"                     LOC = AH24  | IOSTANDARD = "LVCMOS25"; // LA03_N
NET "fmc2_adc2_data_i[10]"                     LOC = AG24  | IOSTANDARD = "LVCMOS25"; // LA03_P
NET "fmc2_adc2_data_i[9]"                      LOC = AC27  | IOSTANDARD = "LVCMOS25"; // LA04_N
NET "fmc2_adc2_data_i[8]"                      LOC = AC26  | IOSTANDARD = "LVCMOS25"; // LA04_P
NET "fmc2_adc2_data_i[7]"                      LOC = AH34  | IOSTANDARD = "LVCMOS25"; // LA05_N
NET "fmc2_adc2_data_i[6]"                      LOC = AH33  | IOSTANDARD = "LVCMOS25"; // LA05_P
NET "fmc2_adc2_data_i[5]"                      LOC = AE25  | IOSTANDARD = "LVCMOS25"; // LA08_N
NET "fmc2_adc2_data_i[4]"                      LOC = AD25  | IOSTANDARD = "LVCMOS25"; // LA08_P
NET "fmc2_adc2_data_i[3]"                      LOC = AH27  | IOSTANDARD = "LVCMOS25"; // LA07_N
NET "fmc2_adc2_data_i[2]"                      LOC = AG27  | IOSTANDARD = "LVCMOS25"; // LA07_P
NET "fmc2_adc2_data_i[1]"                      LOC = AF27  | IOSTANDARD = "LVCMOS25"; // LA12_N
NET "fmc2_adc2_data_i[0]"                      LOC = AE27  | IOSTANDARD = "LVCMOS25"; // LA12_P
NET "fmc2_adc2_of_i"                           LOC = AD30  | IOSTANDARD = "LVCMOS25"; // LA11_P

// ADC3
NET "fmc2_adc3_clk_i"                          LOC = AL28  | IOSTANDARD = "LVCMOS25"; // HA01_CC_P

NET "fmc2_adc3_data_i[15]"                     LOC = AM30  | IOSTANDARD = "LVCMOS25"; // HA00_CC_N
NET "fmc2_adc3_data_i[14]"                     LOC = AL30  | IOSTANDARD = "LVCMOS25"; // HA00_CC_P
NET "fmc2_adc3_data_i[13]"                     LOC = AM25  | IOSTANDARD = "LVCMOS25"; // HA05_N
NET "fmc2_adc3_data_i[12]"                     LOC = AL25  | IOSTANDARD = "LVCMOS25"; // HA05_P
NET "fmc2_adc3_data_i[11]"                     LOC = AK25  | IOSTANDARD = "LVCMOS25"; // HA04_N
NET "fmc2_adc3_data_i[10]"                     LOC = AJ25  | IOSTANDARD = "LVCMOS25"; // HA04_P
NET "fmc2_adc3_data_i[9]"                      LOC = AK26  | IOSTANDARD = "LVCMOS25"; // HA09_N
NET "fmc2_adc3_data_i[8]"                      LOC = AJ26  | IOSTANDARD = "LVCMOS25"; // HA09_P
NET "fmc2_adc3_data_i[7]"                      LOC = AN26  | IOSTANDARD = "LVCMOS25"; // HA03_N
NET "fmc2_adc3_data_i[6]"                      LOC = AM26  | IOSTANDARD = "LVCMOS25"; // HA03_P
NET "fmc2_adc3_data_i[5]"                      LOC = AM27  | IOSTANDARD = "LVCMOS25"; // HA08_P
NET "fmc2_adc3_data_i[4]"                      LOC = AN31  | IOSTANDARD = "LVCMOS25"; // HA02_P
NET "fmc2_adc3_data_i[3]"                      LOC = AM31  | IOSTANDARD = "LVCMOS25"; // HA07_P
NET "fmc2_adc3_data_i[2]"                      LOC = AP31  | IOSTANDARD = "LVCMOS25"; // HA02_N
NET "fmc2_adc3_data_i[1]"                      LOC = AL32  | IOSTANDARD = "LVCMOS25"; // HA06_P
NET "fmc2_adc3_data_i[0]"                      LOC = AN32  | IOSTANDARD = "LVCMOS25"; // HA07_N
NET "fmc2_adc3_of_i"                           LOC = AM32  | IOSTANDARD = "LVCMOS25"; // HA06_N

#######################################################################
##               Pinout and Related I/O Constraints                  ##
#######################################################################

# On ML605 kit, all clock pins are assigned to MRCC pins. However, two of them
# (fmc_adc1_clk and fmc_adc3_clk) are located in the outer left/right column
# I/Os. These locations cannot connect to BUFG primitives, only inner (center)
# left/right column I/Os on the same half top/bottom can!
#
# For 7-series FPGAs there is no such impediment, apparently.

#######################################################################
##                         DIFF TERM                                 ##
#######################################################################

NET "sys_clk_p_i" DIFF_TERM = TRUE;
NET "sys_clk_n_i" DIFF_TERM = TRUE;

NET "fmc1_trig_val_p_b" DIFF_TERM = TRUE;
NET "fmc1_trig_val_n_b" DIFF_TERM = TRUE;

NET "fmc2_trig_val_p_b" DIFF_TERM = TRUE;
NET "fmc2_trig_val_n_b" DIFF_TERM = TRUE;

NET "fmc1_fpga_clk_p_i" DIFF_TERM = TRUE;
NET "fmc1_fpga_clk_n_i" DIFF_TERM = TRUE;

NET "fmc2_fpga_clk_p_i" DIFF_TERM = TRUE;
NET "fmc2_fpga_clk_n_i" DIFF_TERM = TRUE;

#######################################################################
##                    Timing constraints                             ##
#######################################################################

# Overrides default_delay hdl parameter for the VARIABLE mode.
# For Artix7: Average Tap Delay at 200 MHz = 78 ps, at 300 MHz = 52 ps ???
INST "*cmp_fmc_adc_iface/gen_adc_data_chains[0].*.*/gen_adc_data[?].*.cmp_adc_data_iodelay" IDELAY_VALUE = 29;
INST "*cmp_fmc_adc_iface/gen_adc_data_chains[1].*.*/gen_adc_data[?].*.cmp_adc_data_iodelay" IDELAY_VALUE = 31;
INST "*cmp_fmc_adc_iface/gen_adc_data_chains[2].*.*/gen_adc_data[?].*.cmp_adc_data_iodelay" IDELAY_VALUE = 17;
INST "*cmp_fmc_adc_iface/gen_adc_data_chains[3].*.*/gen_adc_data[?].*.cmp_adc_data_iodelay" IDELAY_VALUE = 26;

# Overrides default_delay hdl parameter
INST "*cmp_fmc_adc_iface/gen_clock_chains[0].*.*/*.cmp_ibufds_clk_iodelay" IDELAY_VALUE = 0;
INST "*cmp_fmc_adc_iface/gen_clock_chains[1].*.*/*.cmp_ibufds_clk_iodelay" IDELAY_VALUE = 0;
INST "*cmp_fmc_adc_iface/gen_clock_chains[2].*.*/*.cmp_ibufds_clk_iodelay" IDELAY_VALUE = 0;
INST "*cmp_fmc_adc_iface/gen_clock_chains[3].*.*/*.cmp_ibufds_clk_iodelay" IDELAY_VALUE = 0;

#######################################################################
##                          Clocks                                   ##
#######################################################################

#### 200 MHz onboard input clock
###NET "sys_clk_p_i" TNM_NET = "TNM_clk125mhz";
###TIMESPEC "TS_TNM_clk125mhz" = PERIOD "TNM_clk125mhz" 5 ns HIGH 50%;

# 125 MHz AMC TCLKB input clock
NET "sys_clk_p_i" TNM_NET = "TNM_clk_125mhz";
TIMESPEC "TS_clk_125mhz" = PERIOD "TNM_clk_125mhz" 8 ns HIGH 50%;

## 100 MHz wihsbone clock
NET "clk_sys" TNM_NET = "TNM_clk_100mhz";
TIMESPEC "TS_clk_100mhz" = PERIOD "TNM_clk_100mhz" 10 ns HIGH 50%;

# 200 MHz DDR3 and IDELAY CONTROL clock
NET "clk_200mhz" TNM_NET = "TNM_clk_200mhz";
TIMESPEC "TS_clk_200mhz" = PERIOD "TNM_clk_200mhz" 5 ns HIGH 50%;

# 200 MHz DDR3 UI Clock
#NET "*/u_infrastructure/clk_pll" TNM_NET = "TNM_ddr_sys_clk";
#TIMESPEC "TS_ddr_sys_clk" = PERIOD "TNM_ddr_sys_clk" 5 ns HIGH 50%;
#NET "clk_sys" TNM_NET = "TNM_clk_sys_group_ffs";
#TIMESPEC TS_clk_sys_to_ddr3_ui_clk = FROM "TNM_clk_sys_group_ffs" TO "TNM_ddr_sys_clk" 10 ns DATAPATHONLY;

# real jitter is about 22ps peak-to-peak
NET "fmc1_adc0_clk_i" TNM_NET = fmc1_adc0_clk_i;
TIMESPEC "TS_fmc1_adc0_clk_i" = PERIOD "fmc1_adc0_clk_i" 8.88 ns HIGH 50% INPUT_JITTER 50 ps;
NET "fmc2_adc0_clk_i" TNM_NET = fmc2_adc0_clk_i;
TIMESPEC "TS_fmc2_adc0_clk_i" = PERIOD "fmc2_adc0_clk_i" 8.88 ns HIGH 50% INPUT_JITTER 50 ps;

#INST "cmp1_xwb_fmc130m_4ch/*/*/gen_clock_chains[0].*.*/gen_with_ref_clk.cmp_mmcm_adc_clk" LOC=MMCME2_ADV_X1Y3;

NET "fmc1_adc1_clk_i" TNM_NET = fmc1_adc1_clk_i;
TIMESPEC "TS_fmc1_adc1_clk_i" = PERIOD "fmc1_adc1_clk_i" 8.88 ns HIGH 50% INPUT_JITTER 50 ps;
NET "fmc2_adc1_clk_i" TNM_NET = fmc2_adc1_clk_i;
TIMESPEC "TS_fmc2_adc1_clk_i" = PERIOD "fmc2_adc1_clk_i" 8.88 ns HIGH 50% INPUT_JITTER 50 ps;

NET "fmc1_adc2_clk_i" TNM_NET = fmc1_adc2_clk_i;
TIMESPEC "TS_fmc1_adc2_clk_i" = PERIOD "fmc1_adc2_clk_i" 8.88 ns HIGH 50% INPUT_JITTER 50 ps;
NET "fmc2_adc2_clk_i" TNM_NET = fmc2_adc2_clk_i;
TIMESPEC "TS_fmc2_adc2_clk_i" = PERIOD "fmc2_adc2_clk_i" 8.88 ns HIGH 50% INPUT_JITTER 50 ps;

NET "fmc1_adc3_clk_i" TNM_NET = fmc1_adc3_clk_i;
TIMESPEC "TS_fmc1_adc3_clk_i" = PERIOD "fmc1_adc3_clk_i" 8.88 ns HIGH 50% INPUT_JITTER 50 ps;
NET "fmc2_adc3_clk_i" TNM_NET = fmc2_adc3_clk_i;
TIMESPEC "TS_fmc2_adc3_clk_i" = PERIOD "fmc2_adc3_clk_i" 8.88 ns HIGH 50% INPUT_JITTER 50 ps;

NET "fmc1_fpga_clk_p_i" TNM_NET = fmc1_fpga_clk_p_i;
TIMESPEC "TS_fmc1_fpga_clk_p_i" = PERIOD "fmc1_fpga_clk_p_i" 8.88 ns HIGH 50% INPUT_JITTER 40 ps;
NET "fmc2_fpga_clk_p_i" TNM_NET = fmc2_fpga_clk_p_i;
TIMESPEC "TS_fmc2_fpga_clk_p_i" = PERIOD "fmc2_fpga_clk_p_i" 8.88 ns HIGH 50% INPUT_JITTER 40 ps;

#######################################################################
##                         Cross Clock Constraints		     ##
#######################################################################

# Reset synchronization path
NET "cmp_reset/master_rstn"								TIG;
###NET "cmp_reset/Mshreg_shifters_0_0" TNM_NET = "TNM_reset_clk_0";
#### We relax the reset path here, as we have several FFs pipelined.
#### Here, we are using 2 (125MHz) free_clk clock cycles as the maximum
#### allowed, which is large enough so as to not impose any difficulties by
#### the synthesis tools and still small enough so as to not extrapolate
#### the number of FFs pipelined.
###TIMESPEC "TS_from_reset_free_clk_to_reset_clk_0" = FROM "TNM_reset_free_clk" TO "TNM_reset_clk_0" 16 ns DATAPATHONLY;

#######################################################################
##                                Data                               ##
#######################################################################

#INST "fmc_adc_130m_4ch_i/ltcInterface_adc0_i/IDELAYCTRL_adc0_inst" LOC = IDELAYCTRL_X0Y1;
#INST "fmc_adc_130m_4ch_i/ltcInterface_adc1_i/IDELAYCTRL_adc0_inst" LOC = IDELAYCTRL_X0Y2;
#INST "fmc_adc_130m_4ch_i/ltcInterface_adc2_i/IDELAYCTRL_adc0_inst" LOC = IDELAYCTRL_X0Y0;
#INST "fmc_adc_130m_4ch_i/ltcInterface_adc3_i/IDELAYCTRL_adc0_inst" LOC = IDELAYCTRL_X0Y1; // same as ADC1
#INST "cmp1_xwb_fmc130m_4ch_cmp_wb_fmc130m_4ch_cmp_fmc_adc_iface_cmp_idelayctrl" LOC = IDELAYCTRL_X0Y1;
#INST "cmp2_xwb_fmc130m_4ch_cmp_wb_fmc130m_4ch_cmp_fmc_adc_iface_cmp_idelayctrl" LOC = IDELAYCTRL_X0Y2;

###INST "cmp1_xwb_fmc130m_4ch/*/cmp_fmc_adc_iface/gen_idelayctrl.cmp_idelayctrl" IODELAY_GROUP = fmc1_iodelay_grp;
###INST "cmp2_xwb_fmc130m_4ch/*/cmp_fmc_adc_iface/gen_idelayctrl.cmp_idelayctrl" IODELAY_GROUP = fmc2_iodelay_grp;
###
###INST "cmp1_xwb_fmc130m_4ch/*/cmp_fmc_adc_iface/gen_adc_data_chains[?].*.*/gen_adc_data[?].*.*.cmp_adc_data_iodelay" IODELAY_GROUP = fmc1_iodelay_grp;
###INST "cmp1_xwb_fmc130m_4ch/*/cmp_fmc_adc_iface/gen_clock_chains[?].*.*/*.*.cmp_ibufds_clk_iodelay" IODELAY_GROUP = fmc1_iodelay_grp;
###
###INST "cmp2_xwb_fmc130m_4ch/*/cmp_fmc_adc_iface/gen_adc_data_chains[?].*.*/gen_adc_data[?].*.*.cmp_adc_data_iodelay" IODELAY_GROUP = fmc2_iodelay_grp;
###INST "cmp2_xwb_fmc130m_4ch/*/cmp_fmc_adc_iface/gen_clock_chains[?].*.*/*.*.cmp_ibufds_clk_iodelay" IODELAY_GROUP = fmc2_iodelay_grp;

# The above constraints does not wor with PCIe and DDR cores...
INST "cmp1_xwb_fmc130m_4ch/*/cmp_fmc_adc_iface/gen_adc_data_chains[?].*.*/gen_adc_data[?].*.*.cmp_adc_data_iodelay" IODELAY_GROUP = IODELAY_MIG;
INST "cmp1_xwb_fmc130m_4ch/*/cmp_fmc_adc_iface/gen_clock_chains[?].*.*/*.*.cmp_ibufds_clk_iodelay" IODELAY_GROUP = IODELAY_MIG;

INST "cmp2_xwb_fmc130m_4ch/*/cmp_fmc_adc_iface/gen_adc_data_chains[?].*.*/gen_adc_data[?].*.*.cmp_adc_data_iodelay" IODELAY_GROUP = IODELAY_MIG;
INST "cmp2_xwb_fmc130m_4ch/*/cmp_fmc_adc_iface/gen_clock_chains[?].*.*/*.*.cmp_ibufds_clk_iodelay" IODELAY_GROUP = IODELAY_MIG;

// including 50ps jitter, for 130MHz clock
// since design uses copy of input ADC clock
// there is additional delay for clock/ data (tC)

INST "fmc1_adc0_data_i<*>" TNM = fmc1_adc0_data_i;
INST "fmc1_adc1_data_i<*>" TNM = fmc1_adc1_data_i;
INST "fmc1_adc2_data_i<*>" TNM = fmc1_adc2_data_i;
INST "fmc1_adc3_data_i<*>" TNM = fmc1_adc3_data_i;

TIMEGRP "fmc1_adc0_data_i" OFFSET = IN -0.7 ns VALID 7.6 ns BEFORE "fmc1_adc0_clk_i";
TIMEGRP "fmc1_adc1_data_i" OFFSET = IN -0.7 ns VALID 7.6 ns BEFORE "fmc1_adc1_clk_i";
TIMEGRP "fmc1_adc2_data_i" OFFSET = IN -0.7 ns VALID 7.6 ns BEFORE "fmc1_adc2_clk_i";
TIMEGRP "fmc1_adc3_data_i" OFFSET = IN -0.7 ns VALID 7.6 ns BEFORE "fmc1_adc3_clk_i";

INST "fmc2_adc0_data_i<*>" TNM = fmc2_adc0_data_i;
INST "fmc2_adc1_data_i<*>" TNM = fmc2_adc1_data_i;
INST "fmc2_adc2_data_i<*>" TNM = fmc2_adc2_data_i;
INST "fmc2_adc3_data_i<*>" TNM = fmc2_adc3_data_i;

TIMEGRP "fmc2_adc0_data_i" OFFSET = IN -0.7 ns VALID 7.6 ns BEFORE "fmc2_adc0_clk_i";
TIMEGRP "fmc2_adc1_data_i" OFFSET = IN -0.7 ns VALID 7.6 ns BEFORE "fmc2_adc1_clk_i";
TIMEGRP "fmc2_adc2_data_i" OFFSET = IN -0.7 ns VALID 7.6 ns BEFORE "fmc2_adc2_clk_i";
TIMEGRP "fmc2_adc3_data_i" OFFSET = IN -0.7 ns VALID 7.6 ns BEFORE "fmc2_adc3_clk_i";

#######################################################################
##                          PCIe constraints                        ##
#######################################################################
#
CONFIG PART = xc7a200t-ffg1156-1;

#PCIe clock
NET "pcie_clk_n_i"						 LOC = G18;                             // MGT216_CLK1_N	-> MGTREFCLK0N_216
NET "pcie_clk_p_i"						 LOC = H18;                             // MGT216_CLK1_P	-> MGTREFCLK0P_216
#PCIe lane 0
NET "pci_exp_txp_o[0]"						 LOC = B23;                             // TX216_0_P            -> MGTPTXP0_216
NET "pci_exp_txn_o[0]"						 LOC = A23;                             // TX216_0_N            -> MGTPTXN0_216
NET "pci_exp_rxp_i[0]"						 LOC = F21;                             // RX216_0_P            -> MGTPRXP0_216
NET "pci_exp_rxn_i[0]"						 LOC = E21;                             // RX216_0_N            -> MGTPRXN0_216
#PCIe lane 1
NET "pci_exp_txp_o[1]"						 LOC = D22;                             // TX216_1_P            -> MGTPTXP1_216
NET "pci_exp_txn_o[1]"						 LOC = C22;                             // TX216_1_N            -> MGTPTXN1_216
NET "pci_exp_rxp_i[1]"						 LOC = D20;                             // RX216_1_P            -> MGTPRXP1_216
NET "pci_exp_rxn_i[1]"						 LOC = C20;                             // RX216_1_N            -> MGTPRXN1_216
#PCIe lane 2
NET "pci_exp_txp_o[2]"						 LOC = B21;                             // TX216_2_P            -> MGTPTXP2_216
NET "pci_exp_txn_o[2]"						 LOC = A21;                             // TX216_2_N            -> MGTPTXN2_216
NET "pci_exp_rxp_i[2]"						 LOC = F19;                             // RX216_2_P            -> MGTPRXP2_216
NET "pci_exp_rxn_i[2]"						 LOC = E19;                             // RX216_2_N            -> MGTPRXN2_216
#PCIe lane 3
NET "pci_exp_txp_o[3]"						 LOC = B19;                             // TX216_3_P            -> MGTPTXP3_216
NET "pci_exp_txn_o[3]"						 LOC = A19;                             // TX216_3_N            -> MGTPTXN3_216
NET "pci_exp_rxp_i[3]"						 LOC = D18;                             // RX216_3_P            -> MGTPRXP3_216
NET "pci_exp_rxn_i[3]"						 LOC = C18;                             // RX216_3_N            -> MGTPRXN3_216

#######################################################################
##                         DDR controller                            ##
#######################################################################

NET   "ddr3_dq_b[0]"				LOC = AD11 | IOSTANDARD = SSTL15      | SLEW = FAST | IN_TERM = UNTUNED_SPLIT_50   ; // D0           -> IO_L22P_T3_33
NET   "ddr3_dq_b[1]"				LOC = AE10 | IOSTANDARD = SSTL15      | SLEW = FAST | IN_TERM = UNTUNED_SPLIT_50   ; // D1           -> IO_L24N_T3_33
NET   "ddr3_dq_b[2]"				LOC = AF12 | IOSTANDARD = SSTL15      | SLEW = FAST | IN_TERM = UNTUNED_SPLIT_50   ; // D2           -> IO_L23P_T3_33
NET   "ddr3_dq_b[3]"				LOC = AG11 | IOSTANDARD = SSTL15      | SLEW = FAST | IN_TERM = UNTUNED_SPLIT_50   ; // D3           -> IO_L22N_T3_33
NET   "ddr3_dq_b[4]"				LOC = AE11 | IOSTANDARD = SSTL15      | SLEW = FAST | IN_TERM = UNTUNED_SPLIT_50   ; // D4           -> IO_L20P_T3_33
NET   "ddr3_dq_b[5]"				LOC = AH11 | IOSTANDARD = SSTL15      | SLEW = FAST | IN_TERM = UNTUNED_SPLIT_50   ; // D5           -> IO_L20N_T3_33
NET   "ddr3_dq_b[6]"				LOC = AG12 | IOSTANDARD = SSTL15      | SLEW = FAST | IN_TERM = UNTUNED_SPLIT_50   ; // D6           -> IO_L23N_T3_33
NET   "ddr3_dq_b[7]"				LOC = AH9  | IOSTANDARD = SSTL15      | SLEW = FAST | IN_TERM = UNTUNED_SPLIT_50   ; // D7           -> IO_L19P_T3_33
NET   "ddr3_dq_b[8]"				LOC = AD6  | IOSTANDARD = SSTL15      | SLEW = FAST | IN_TERM = UNTUNED_SPLIT_50   ; // D8           -> IO_L13P_T2_MRCC_33
NET   "ddr3_dq_b[9]"				LOC = AG7  | IOSTANDARD = SSTL15      | SLEW = FAST | IN_TERM = UNTUNED_SPLIT_50   ; // D9           -> IO_L14N_T2_SRCC_33
NET   "ddr3_dq_b[10]"				LOC = AF9  | IOSTANDARD = SSTL15      | SLEW = FAST | IN_TERM = UNTUNED_SPLIT_50   ; // D10          -> IO_L18P_T2_33
NET   "ddr3_dq_b[11]"				LOC = AH7  | IOSTANDARD = SSTL15      | SLEW = FAST | IN_TERM = UNTUNED_SPLIT_50   ; // D11          -> IO_L17P_T2_33
NET   "ddr3_dq_b[12]"				LOC = AE8  | IOSTANDARD = SSTL15      | SLEW = FAST | IN_TERM = UNTUNED_SPLIT_50   ; // D12          -> IO_L16P_T2_33
NET   "ddr3_dq_b[13]"				LOC = AF8  | IOSTANDARD = SSTL15      | SLEW = FAST | IN_TERM = UNTUNED_SPLIT_50   ; // D13          -> IO_L18N_T2_33
NET   "ddr3_dq_b[14]"				LOC = AE7  | IOSTANDARD = SSTL15      | SLEW = FAST | IN_TERM = UNTUNED_SPLIT_50   ; // D14          -> IO_L16N_T2_33
NET   "ddr3_dq_b[15]"				LOC = AF7  | IOSTANDARD = SSTL15      | SLEW = FAST | IN_TERM = UNTUNED_SPLIT_50   ; // D15          -> IO_L14P_T2_SRCC_33
NET   "ddr3_dq_b[16]"				LOC = AF4  | IOSTANDARD = SSTL15      | SLEW = FAST | IN_TERM = UNTUNED_SPLIT_50   ; // D16          -> IO_L7P_T1_33
NET   "ddr3_dq_b[17]"				LOC = AF5  | IOSTANDARD = SSTL15      | SLEW = FAST | IN_TERM = UNTUNED_SPLIT_50   ; // D17          -> IO_L12N_T1_MRCC_33
NET   "ddr3_dq_b[18]"				LOC = AD3  | IOSTANDARD = SSTL15      | SLEW = FAST | IN_TERM = UNTUNED_SPLIT_50   ; // D18          -> IO_L10P_T1_33
NET   "ddr3_dq_b[19]"				LOC = AG5  | IOSTANDARD = SSTL15      | SLEW = FAST | IN_TERM = UNTUNED_SPLIT_50   ; // D19          -> IO_L11N_T1_SRCC_33
NET   "ddr3_dq_b[20]"				LOC = AD5  | IOSTANDARD = SSTL15      | SLEW = FAST | IN_TERM = UNTUNED_SPLIT_50   ; // D20          -> IO_L8P_T1_33
NET   "ddr3_dq_b[21]"				LOC = AG6  | IOSTANDARD = SSTL15      | SLEW = FAST | IN_TERM = UNTUNED_SPLIT_50   ; // D21          -> IO_L11P_T1_SRCC_33
NET   "ddr3_dq_b[22]"				LOC = AD4  | IOSTANDARD = SSTL15      | SLEW = FAST | IN_TERM = UNTUNED_SPLIT_50   ; // D22          -> IO_L8N_T1_33
NET   "ddr3_dq_b[23]"				LOC = AE3  | IOSTANDARD = SSTL15      | SLEW = FAST | IN_TERM = UNTUNED_SPLIT_50   ; // D23          -> IO_L10N_T1_33
NET   "ddr3_dq_b[24]"				LOC = AG1  | IOSTANDARD = SSTL15      | SLEW = FAST | IN_TERM = UNTUNED_SPLIT_50   ; // D24          -> IO_L1P_T0_33
NET   "ddr3_dq_b[25]"				LOC = AG2  | IOSTANDARD = SSTL15      | SLEW = FAST | IN_TERM = UNTUNED_SPLIT_50   ; // D25          -> IO_L5N_T0_33
NET   "ddr3_dq_b[26]"				LOC = AE1  | IOSTANDARD = SSTL15      | SLEW = FAST | IN_TERM = UNTUNED_SPLIT_50   ; // D26          -> IO_L2N_T0_33
NET   "ddr3_dq_b[27]"				LOC = AF3  | IOSTANDARD = SSTL15      | SLEW = FAST | IN_TERM = UNTUNED_SPLIT_50   ; // D27          -> IO_L5P_T0_33
NET   "ddr3_dq_b[28]"				LOC = AE2  | IOSTANDARD = SSTL15      | SLEW = FAST | IN_TERM = UNTUNED_SPLIT_50   ; // D28          -> IO_L4P_T0_33
NET   "ddr3_dq_b[29]"				LOC = AH3  | IOSTANDARD = SSTL15      | SLEW = FAST | IN_TERM = UNTUNED_SPLIT_50   ; // D29          -> IO_L6P_T0_33
NET   "ddr3_dq_b[30]"				LOC = AD1  | IOSTANDARD = SSTL15      | SLEW = FAST | IN_TERM = UNTUNED_SPLIT_50   ; // D30          -> IO_L2P_T0_33
NET   "ddr3_dq_b[31]"				LOC = AF2  | IOSTANDARD = SSTL15      | SLEW = FAST | IN_TERM = UNTUNED_SPLIT_50   ; // D31          -> IO_L4N_T0_33
NET   "ddr3_addr_o[0]"				LOC = AP4  | IOSTANDARD = SSTL15      | SLEW = FAST ;                                // A0           -> IO_L5N_T0_32
NET   "ddr3_addr_o[1]"				LOC = AJ6  | IOSTANDARD = SSTL15      | SLEW = FAST ;                                // A1           -> IO_L15N_T2_DQS_32
NET   "ddr3_addr_o[2]"				LOC = AM4  | IOSTANDARD = SSTL15      | SLEW = FAST ;                                // A2           -> IO_L14P_T2_SRCC_32
NET   "ddr3_addr_o[3]"				LOC = AM6  | IOSTANDARD = SSTL15      | SLEW = FAST ;                                // A3           -> IO_L9N_T1_DQS_32
NET   "ddr3_addr_o[4]"				LOC = AN4  | IOSTANDARD = SSTL15      | SLEW = FAST ;                                // A4           -> IO_L15P_T2_DQS_32
NET   "ddr3_addr_o[5]"				LOC = AK3  | IOSTANDARD = SSTL15      | SLEW = FAST ;                                // A5           -> IO_L3N_T0_DQS_32
NET   "ddr3_addr_o[6]"				LOC = AK5  | IOSTANDARD = SSTL15      | SLEW = FAST ;                                // A6           -> IO_L10P_T1_32
NET   "ddr3_addr_o[7]"				LOC = AP6  | IOSTANDARD = SSTL15      | SLEW = FAST ;                                // A7           -> IO_L12N_T1_MRCC_32
NET   "ddr3_addr_o[8]"				LOC = AK6  | IOSTANDARD = SSTL15      | SLEW = FAST ;                                // A8           -> IO_L9P_T1_DQS_32
NET   "ddr3_addr_o[9]"				LOC = AL4  | IOSTANDARD = SSTL15      | SLEW = FAST ;                                // A9           -> IO_L8N_T1_32
NET   "ddr3_addr_o[10]"				LOC = AN2  | IOSTANDARD = SSTL15      | SLEW = FAST ;                                // A10          -> IO_L6P_T0_32
NET   "ddr3_addr_o[11]"				LOC = AJ8  | IOSTANDARD = SSTL15      | SLEW = FAST ;                                // A11          -> IO_L7P_T1_32
NET   "ddr3_addr_o[12]"				LOC = AP5  | IOSTANDARD = SSTL15      | SLEW = FAST ;                                // A12          -> IO_L14N_T2_SRCC_32
NET   "ddr3_addr_o[13]"				LOC = AM7  | IOSTANDARD = SSTL15      | SLEW = FAST ;                                // A13          -> IO_L10N_T1_32
NET   "ddr3_addr_o[14]"				LOC = AK8  | IOSTANDARD = SSTL15      | SLEW = FAST ;                                // A14          -> IO_L12P_T1_MRCC_32
NET   "ddr3_addr_o[15]"				LOC = AP3  | IOSTANDARD = SSTL15      | SLEW = FAST ;                                // A15          -> IO_L7N_T1_32
NET   "ddr3_ba_o[0]"				LOC = AM2  | IOSTANDARD = SSTL15      | SLEW = FAST ;                                // BA0          -> IO_L2N_T0_32
NET   "ddr3_ba_o[1]"				LOC = AK2  | IOSTANDARD = SSTL15      | SLEW = FAST ;                                // BA1          -> IO_L2P_T0_32
NET   "ddr3_ba_o[2]"				LOC = AK1  | IOSTANDARD = SSTL15      | SLEW = FAST ;                                // BA2          -> IO_L3P_T0_DQS_32
NET   "ddr3_ras_n_o"				LOC = AN1  | IOSTANDARD = SSTL15      | SLEW = FAST ;                                // RAS_N        -> IO_L1P_T0_32
NET   "ddr3_cas_n_o"				LOC = AL2  | IOSTANDARD = SSTL15      | SLEW = FAST ;                                // CAS_N        -> IO_L4P_T0_32
NET   "ddr3_we_n_o"				LOC = AM1  | IOSTANDARD = SSTL15      | SLEW = FAST ;                                // WE_N         -> IO_L4N_T0_32
NET   "ddr3_reset_n_o"				LOC = AJ9  | IOSTANDARD = LVCMOS15    | SLEW = FAST ;                                // RST_N        -> IO_0_32
NET   "ddr3_cke_o[0]"				LOC = AJ5  | IOSTANDARD = SSTL15      | SLEW = FAST ;                                // CKE0         -> IO_L8P_T1_32
NET   "ddr3_odt_o[0]"				LOC = AP1  | IOSTANDARD = SSTL15      | SLEW = FAST ;                                // ODT0         -> IO_L1N_T0_32
NET   "ddr3_cs_n_o[0]"				LOC = AN3  | IOSTANDARD = SSTL15      | SLEW = FAST;                                 // CE0_N        -> IO_L5P_T0_32
NET   "ddr3_dm_o[0]"				LOC = AD10 | IOSTANDARD = SSTL15      | SLEW = FAST ;                                // DM0          -> IO_L24P_T3_33
NET   "ddr3_dm_o[1]"				LOC = AH6  | IOSTANDARD = SSTL15      | SLEW = FAST ;                                // DM1          -> IO_L17N_T2_33
NET   "ddr3_dm_o[2]"				LOC = AG4  | IOSTANDARD = SSTL15      | SLEW = FAST ;                                // DM2          -> IO_L7N_T1_33
NET   "ddr3_dm_o[3]"				LOC = AH1  | IOSTANDARD = SSTL15      | SLEW = FAST ;                                // DM3          -> IO_L1N_T0_33
NET   "ddr3_dqs_p_b[0]"				LOC = AG10 | IOSTANDARD = DIFF_SSTL15 | SLEW = FAST | IN_TERM = UNTUNED_SPLIT_50   ; // DQS0_P       -> IO_L21P_T3_DQS_33
NET   "ddr3_dqs_n_b[0]"				LOC = AG9  | IOSTANDARD = DIFF_SSTL15 | SLEW = FAST | IN_TERM = UNTUNED_SPLIT_50   ; // DQS0_N       -> IO_L21N_T3_DQS_33
NET   "ddr3_dqs_p_b[1]"				LOC = AD9  | IOSTANDARD = DIFF_SSTL15 | SLEW = FAST | IN_TERM = UNTUNED_SPLIT_50   ; // DQS1_P       -> IO_L15P_T2_DQS_33
NET   "ddr3_dqs_n_b[1]"				LOC = AD8  | IOSTANDARD = DIFF_SSTL15 | SLEW = FAST | IN_TERM = UNTUNED_SPLIT_50   ; // DQS1_N       -> IO_L15N_T2_DQS_33
NET   "ddr3_dqs_p_b[2]"				LOC = AH4  | IOSTANDARD = DIFF_SSTL15 | SLEW = FAST | IN_TERM = UNTUNED_SPLIT_50   ; // DQS2_P       -> IO_L9P_T1_DQS_33
NET   "ddr3_dqs_n_b[2]"				LOC = AJ4  | IOSTANDARD = DIFF_SSTL15 | SLEW = FAST | IN_TERM = UNTUNED_SPLIT_50   ; // DQS2_N       -> IO_L9N_T1_DQS_33
NET   "ddr3_dqs_p_b[3]"				LOC = AH2  | IOSTANDARD = DIFF_SSTL15 | SLEW = FAST | IN_TERM = UNTUNED_SPLIT_50   ; // DQS3_P       -> IO_L3P_T0_DQS_33
NET   "ddr3_dqs_n_b[3]"				LOC = AJ1  | IOSTANDARD = DIFF_SSTL15 | SLEW = FAST | IN_TERM = UNTUNED_SPLIT_50   ; // DQS3_N       -> IO_L3N_T0_DQS_33
NET   "ddr3_ck_p_o[0]"				LOC = AL5  | IOSTANDARD = DIFF_SSTL15 | SLEW = FAST ;                                // CLK0_P       -> IO_L11P_T1_SRCC_32
NET   "ddr3_ck_n_o[0]"				LOC = AM5  | IOSTANDARD = DIFF_SSTL15 | SLEW = FAST ;                                // CLK0_N       -> IO_L11N_T1_SRCC_32
# NET   "ddr_sys_clk_p_i"                         LOC =   |   IOSTANDARD = DIFF_SSTL15; # Pad function: IO_L12P_T1_MRCC_33
# NET   "ddr_sys_clk_n_i"                         LOC =   |   IOSTANDARD = DIFF_SSTL15; # Pad function: IO_L12N_T1_MRCC_33

#######################################################################
# Pinout and Related I/O Constraints
#######################################################################

# SYS clock 100 MHz (input) signal. The sys_clk_p and sys_clk_n
# signals are the PCI Express reference clock. Virtex-7 GT
# Transceiver architecture requires the use of a dedicated clock
# resources (FPGA input pins) associated with each GT Transceiver.
# To use these pins an IBUFDS primitive (refclk_ibuf) is
# instantiated in user's design.
# Please refer to the Virtex-7 GT Transceiver User Guide
# (UG) for guidelines regarding clock resource selection.
#

# Already constrained by the pcie_clk_p_i and pcie_clk_n_i LOC constraints
#INST "*pcieclk_ibuf" LOC = IBUFDS_GTE2_X0Y3;

#
# Transceiver instance placement.  This constraint selects the
# transceivers to be used, which also dictates the pinout for the
# transmit and receive differential pairs.  Please refer to the
# Virtex-7 GT Transceiver User Guide (UG) for more information.
#
# PCIe Lane 0
INST "*pcie_core_i/gt_top.gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/gtp_channel.gtpe2_channel_i" LOC = GTPE2_CHANNEL_X0Y4;
# PCIe Lane 1
INST "*pcie_core_i/gt_top.gt_top_i/pipe_wrapper_i/pipe_lane[1].gt_wrapper_i/gtp_channel.gtpe2_channel_i" LOC = GTPE2_CHANNEL_X0Y5;
# PCIe Lane 2
INST "*pcie_core_i/gt_top.gt_top_i/pipe_wrapper_i/pipe_lane[2].gt_wrapper_i/gtp_channel.gtpe2_channel_i" LOC = GTPE2_CHANNEL_X0Y6;
# PCIe Lane 3
INST "*pcie_core_i/gt_top.gt_top_i/pipe_wrapper_i/pipe_lane[3].gt_wrapper_i/gtp_channel.gtpe2_channel_i" LOC = GTPE2_CHANNEL_X0Y7;

# GTP Common Placement
INST "*pcie_core_i/gt_top.gt_top_i/pipe_wrapper_i/pipe_lane[0].pipe_quad.pipe_common.qpll_wrapper_i/gtp_common.gtpe2_common_i" LOC = GTPE2_COMMON_X0Y1;

#
# PCI Express Block placement. This constraint selects the PCI Express
# Block to be used.
#

INST "*pcie_core_i/pcie_top_i/pcie_7x_i/pcie_block_i" LOC = PCIE_X0Y0;

#
# BlockRAM placement
#
INST "*pcie_core_i/pcie_top_i/pcie_7x_i/pcie_bram_top/pcie_brams_rx/brams[3].ram/use_tdp.ramb36/bram36_tdp_bl.bram36_tdp_bl" LOC = RAMB36_X2Y46 ;
INST "*pcie_core_i/pcie_top_i/pcie_7x_i/pcie_bram_top/pcie_brams_rx/brams[2].ram/use_tdp.ramb36/bram36_tdp_bl.bram36_tdp_bl" LOC = RAMB36_X1Y47 ;
INST "*pcie_core_i/pcie_top_i/pcie_7x_i/pcie_bram_top/pcie_brams_rx/brams[1].ram/use_tdp.ramb36/bram36_tdp_bl.bram36_tdp_bl" LOC = RAMB36_X1Y46 ;
INST "*pcie_core_i/pcie_top_i/pcie_7x_i/pcie_bram_top/pcie_brams_rx/brams[0].ram/use_tdp.ramb36/bram36_tdp_bl.bram36_tdp_bl" LOC = RAMB36_X1Y45 ;
INST "*pcie_core_i/pcie_top_i/pcie_7x_i/pcie_bram_top/pcie_brams_tx/brams[0].ram/use_tdp.ramb36/bram36_tdp_bl.bram36_tdp_bl" LOC = RAMB36_X1Y44 ;
INST "*pcie_core_i/pcie_top_i/pcie_7x_i/pcie_bram_top/pcie_brams_tx/brams[1].ram/use_tdp.ramb36/bram36_tdp_bl.bram36_tdp_bl" LOC = RAMB36_X1Y43 ;
INST "*pcie_core_i/pcie_top_i/pcie_7x_i/pcie_bram_top/pcie_brams_tx/brams[2].ram/use_tdp.ramb36/bram36_tdp_bl.bram36_tdp_bl" LOC = RAMB36_X1Y42 ;
INST "*pcie_core_i/pcie_top_i/pcie_7x_i/pcie_bram_top/pcie_brams_tx/brams[3].ram/use_tdp.ramb36/bram36_tdp_bl.bram36_tdp_bl" LOC = RAMB36_X1Y41 ;

#
# DDR controller component placement
# Check it after changing memory controller paramenters
#
INST "*/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out" LOC=PHASER_OUT_PHY_X1Y3;
INST "*/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out" LOC=PHASER_OUT_PHY_X1Y2;
INST "*/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out" LOC=PHASER_OUT_PHY_X1Y1;
INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out" LOC=PHASER_OUT_PHY_X1Y7;
INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out" LOC=PHASER_OUT_PHY_X1Y6;
INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out" LOC=PHASER_OUT_PHY_X1Y5;
INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out" LOC=PHASER_OUT_PHY_X1Y4;

## INST "*/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in" LOC=PHASER_IN_PHY_X1Y3;
## INST "*/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in" LOC=PHASER_IN_PHY_X1Y2;
## INST "*/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_in_gen.phaser_in" LOC=PHASER_IN_PHY_X1Y1;
INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in" LOC=PHASER_IN_PHY_X1Y7;
INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in" LOC=PHASER_IN_PHY_X1Y6;
INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_in_gen.phaser_in" LOC=PHASER_IN_PHY_X1Y5;
INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_in_gen.phaser_in" LOC=PHASER_IN_PHY_X1Y4;

INST "*/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo" LOC=OUT_FIFO_X1Y3;
INST "*/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo" LOC=OUT_FIFO_X1Y2;
INST "*/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo" LOC=OUT_FIFO_X1Y1;
INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo" LOC=OUT_FIFO_X1Y7;
INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo" LOC=OUT_FIFO_X1Y6;
INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo" LOC=OUT_FIFO_X1Y5;
INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo" LOC=OUT_FIFO_X1Y4;

INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/in_fifo_gen.in_fifo" LOC=IN_FIFO_X1Y7;
INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/in_fifo_gen.in_fifo" LOC=IN_FIFO_X1Y6;
INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/in_fifo_gen.in_fifo" LOC=IN_FIFO_X1Y5;
INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/in_fifo_gen.in_fifo" LOC=IN_FIFO_X1Y4;

INST "*/ddr_phy_4lanes_1.u_ddr_phy_4lanes/phy_control_i" LOC=PHY_CONTROL_X1Y0;
INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i" LOC=PHY_CONTROL_X1Y1;

INST "*/ddr_phy_4lanes_1.u_ddr_phy_4lanes/phaser_ref_i" LOC=PHASER_REF_X1Y0;
INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phaser_ref_i" LOC=PHASER_REF_X1Y1;

INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/*slave_ts" LOC=OLOGIC_X1Y93;
INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/*slave_ts" LOC=OLOGIC_X1Y81;
INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/*slave_ts" LOC=OLOGIC_X1Y69;
INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/*slave_ts" LOC=OLOGIC_X1Y57;

INST "*/u_ddr3_infrastructure/plle2_i" LOC=PLLE2_ADV_X1Y0;
INST "*/u_ddr3_infrastructure/gen_mmcm.mmcm_i" LOC=MMCME2_ADV_X1Y0;

#######################################################################
# Timing Constraints
#######################################################################
NET "*bpm_pcie_a7/sys_clk_c"									       TNM_NET = "SYSCLK" ;
NET "*pcie_core_i/gt_top.gt_top_i/pipe_wrapper_i/pipe_clock_int.pipe_clock_i/clk_125mhz"               TNM_NET = "CLK_125" ;
NET "*pcie_core_i/gt_top.gt_top_i/pipe_wrapper_i/pipe_clock_int.pipe_clock_i/clk_250mhz"               TNM_NET = "CLK_250" ;
NET "*pcie_core_i/gt_top.gt_top_i/pipe_wrapper_i/pipe_clock_int.pipe_clock_i/userclk1"                 TNM_NET = "CLK_USERCLK" ;
NET "*pcie_core_i/gt_top.gt_top_i/pipe_wrapper_i/pipe_clock_int.pipe_clock_i/userclk2"                 TNM_NET = "CLK_USERCLK2" ;

TIMESPEC "TS_SYSCLK"                                                                                   = PERIOD "SYSCLK" 100 MHz HIGH 50 % ;
TIMESPEC "TS_CLK_125"                                                                                  = PERIOD "CLK_125" TS_SYSCLK*1.25 HIGH 50 % PRIORITY 1;
#CLK_250 not used, we use Gen1 mode only
#TIMESPEC "TS_CLK_250"                                                                                 = PERIOD "CLK_250" TS_SYSCLK*2.5 HIGH 50 % PRIORITY 2;
TIMESPEC "TS_CLK_USERCLK"                                                                              = PERIOD "CLK_USERCLK" TS_SYSCLK*1.25 HIGH 50 %;
TIMESPEC "TS_CLK_USERCLK2"                                                                             = PERIOD "CLK_USERCLK2" TS_SYSCLK*1.25 HIGH 50 %;

INST "*pcie_core_i/gt_top.gt_top_i/pipe_wrapper_i/pipe_clock_int.pipe_clock_i/mmcm_i"                   LOC = MMCME2_ADV_X0Y2;

PIN "*pcie_core_i/pcie_top_i/pcie_7x_i/pcie_block_i.PLPHYLNKUPN"                                        TIG;
PIN "*pcie_core_i/pcie_top_i/pcie_7x_i/pcie_block_i.PLRECEIVEDHOTRST"                                   TIG;

PIN "*pcie_core_i/gt_top.gt_top_i/pipe_wrapper_i/pipe_clock_int.pipe_clock_i/mmcm_i.RST"                TIG;
NET "*pcie_core_i/gt_top.gt_top_i/pipe_wrapper_i/user_resetdone*"                                       TIG;
NET "*pcie_core_i/gt_top.gt_top_i/pipe_wrapper_i/pipe_clock_int.pipe_clock_i/pclk_sel"                  TIG;
NET "*pcie_core_i/gt_top.gt_top_i/pipe_wrapper_i/pipe_lane[0].gtp_pipe_rate.gtp_pipe_rate_i/*"          TNM_NET = FFS "MC_PIPE";
NET "*pcie_core_i/gt_top.gt_top_i/pipe_wrapper_i/pipe_lane[1].gtp_pipe_rate.gtp_pipe_rate_i/*"          TNM_NET = FFS "MC_PIPE";
NET "*pcie_core_i/gt_top.gt_top_i/pipe_wrapper_i/pipe_lane[2].gtp_pipe_rate.gtp_pipe_rate_i/*"          TNM_NET = FFS "MC_PIPE";
NET "*pcie_core_i/gt_top.gt_top_i/pipe_wrapper_i/pipe_lane[3].gtp_pipe_rate.gtp_pipe_rate_i/*"          TNM_NET = FFS "MC_PIPE";

TIMESPEC "TS_PIPE_RATE"                                                                                 = FROM "MC_PIPE" TS_CLK_USERCLK*0.5;

##########NET "*pcie_core_i/gt_top.gt_top_i/pipe_wrapper_i/gtp_pipe_reset.gtp_pipe_reset_i/pllreset"		TIG;
NET "*pcie_core_i/gt_top.gt_top_i/pipe_wrapper_i/qpll_reset.qpll_reset_i/*"				TIG;

####### DDR ###########
###NET "ddr_sys_clk_p_i" TNM_NET = TNM_ddr_sys_clk;
###TIMESPEC "TS_ddr_sys_clk" = PERIOD "TNM_ddr_sys_clk" 8 ns;

# Note: the following CLOCK_DEDICATED_ROUTE constraint will cause a warning in place similar
# to the following:
#   WARNING:Place:1402 - A clock IOB / PLL clock component pair have been found that are not
#   placed at an optimal clock IOB / PLL site pair.
# This warning can be ignored.  See the Users Guide for more information.
NET "sys_clk_p_i" CLOCK_DEDICATED_ROUTE = BACKBONE;
#NET "ddr_sys_clk_p_i" CLOCK_DEDICATED_ROUTE = BACKBONE;
#PIN "*DDR_int_clk.*.CLKIN1" CLOCK_DEDICATED_ROUTE = BACKBONE;
#PIN "*u_ddr3_infrastructure_plle2_i.CLKIN1" CLOCK_DEDICATED_ROUTE = BACKBONE;

NET "*/iserdes_clk" TNM_NET = "TNM_ISERDES_CLK";
INST "*/mc0/mc_read_idle_r" TNM = "TNM_SOURCE_IDLE";
INST "*/input_[?].iserdes_dq_.iserdesdq" TNM = "TNM_DEST_ISERDES";
TIMESPEC "TS_ISERDES_CLOCK" = PERIOD "TNM_ISERDES_CLK" 2500 ps;
TIMESPEC TS_MULTICYCLEPATH = FROM "TNM_SOURCE_IDLE" TO "TNM_DEST_ISERDES" TS_ISERDES_CLOCK*6;

INST "*/device_temp_sync_r1*" TNM="TNM_MULTICYCLEPATH_DEVICE_TEMP_SYNC";
TIMESPEC "TS_MULTICYCLEPATH_DEVICE_TEMP_SYNC" = TO "TNM_MULTICYCLEPATH_DEVICE_TEMP_SYNC" 20 ns DATAPATHONLY;

#######################################################################
##                      Placement Constraints                        ##
#######################################################################

### Constrain the PCIe core elements placement, so that it won't fail
### timing analysis.
### Comment out because we use nonstandard GTP location
INST "*pcie_core_i/*" AREA_GROUP = "GRP_pcie_core";
AREA_GROUP "GRP_pcie_core" RANGE = CLOCKREGION_X0Y4;
### Place the DMA design not far from PCIe core, otherwise it also breaks timing
INST "*theTlpControl/*" AREA_GROUP = "GRP_tlpControl";
AREA_GROUP "GRP_tlpControl" RANGE = CLOCKREGION_X0Y2:CLOCKREGION_X0Y4;

INST "*u_ddr_core/*" AREA_GROUP = "GRP_ddr_core";
AREA_GROUP "GRP_ddr_core" RANGE = CLOCKREGION_X1Y0:CLOCKREGION_X1Y1;
INST "*u_ddr_core/temp_mon_enabled.u_tempmon/*" AREA_GROUP = "GRP_ddr_core_temp_mon";
AREA_GROUP "GRP_ddr_core_temp_mon" RANGE = CLOCKREGION_X0Y2:CLOCKREGION_X0Y3;
## The FMC #1 is poor placed on PCB, so we constraint it to the rightmost clock regions of the FPGA
#INST "cmp1_xwb_fmc130m_4ch/*" AREA_GROUP = "GRP_fmc1";
#AREA_GROUP "GRP_fmc1" RANGE = CLOCKREGION_X1Y2:CLOCKREGION_X1Y4;
#INST "cmp2_xwb_fmc130m_4ch" AREA_GROUP = "GRP_fmc2";
#AREA_GROUP "GRP_fmc2" RANGE = CLOCKREGION_X0Y0:CLOCKREGION_X0Y2;
INST "cmp1_xwb_position_calc_core_ns/*" AREA_GROUP = "GRP_position_calc_core1";
AREA_GROUP "GRP_position_calc_core1" RANGE = CLOCKREGION_X1Y2:CLOCKREGION_X1Y4;
INST "cmp2_xwb_position_calc_core_ns/*" AREA_GROUP = "GRP_position_calc_core2";
AREA_GROUP "GRP_position_calc_core2" RANGE = CLOCKREGION_X0Y0:CLOCKREGION_X0Y2;

#######################################################################
##                         CE Constraints                            ##
#######################################################################
#
NET "*position_calc_nosysgen/ce_adc*" TNM = "MC_ADC";
TIMESPEC TS_ADC = FROM "MC_ADC" TO "MC_ADC" 8.333 ns;

NET "*position_calc_nosysgen/ce_tbt1*" TNM = "MC_TBT1";
TIMESPEC TS_TBT1 = FROM "MC_TBT1" TO "MC_TBT1" 58.332 ns;       # ADC/7

NET "*position_calc_nosysgen/ce_tbt2*" TNM = "MC_TBT2";
TIMESPEC TS_TBT2 = FROM "MC_TBT2" TO "MC_TBT2" 1.691 us;        # TBT1/29

NET "*position_calc_nosysgen/ce_fofb*" TNM = "MC_FOFB";
TIMESPEC TS_FOFB = FROM "MC_FOFB" TO "MC_FOFB" 8.458 us;        # TBT2/5

NET "*position_calc_nosysgen/ce_monit*" TNM = "MC_MONIT";
TIMESPEC TS_MONIT = FROM "MC_MONIT" TO "MC_MONIT" 17.330 ms;     # FOFB/2049

