NET "buttons_i[0]" LOC = D22;
NET "buttons_i[1]" LOC = C22;
NET "buttons_i[2]" LOC = L21;
NET "buttons_i[3]" LOC = L20;
NET "buttons_i[4]" LOC = C18;
NET "buttons_i[5]" LOC = B18;
NET "buttons_i[6]" LOC = K22;
NET "buttons_i[7]" LOC = K21;
NET "leds_o[0]" LOC = AC22;
NET "leds_o[1]" LOC = AC24;
NET "leds_o[2]" LOC = AE22;
NET "leds_o[3]" LOC = AE23;
NET "leds_o[4]" LOC = AB23;
NET "leds_o[5]" LOC = AG23;
NET "leds_o[6]" LOC = AE24;
NET "leds_o[7]" LOC = AD24;
NET "uart_rxd_i" LOC = J24;
NET "uart_txd_o" LOC = J25;
NET "buttons_i[7]" IOSTANDARD = LVCMOS25;
NET "buttons_i[6]" IOSTANDARD = LVCMOS25;
NET "buttons_i[5]" IOSTANDARD = LVCMOS25;
NET "buttons_i[4]" IOSTANDARD = LVCMOS25;
NET "buttons_i[3]" IOSTANDARD = LVCMOS25;
NET "buttons_i[2]" IOSTANDARD = LVCMOS25;
NET "buttons_i[1]" IOSTANDARD = LVCMOS25;
NET "buttons_i[0]" IOSTANDARD = LVCMOS25;
NET "leds_o[7]" IOSTANDARD = LVCMOS25;
NET "leds_o[7]" DRIVE = 12;
NET "leds_o[7]" SLEW = SLOW;
NET "leds_o[6]" IOSTANDARD = LVCMOS25;
NET "leds_o[6]" DRIVE = 12;
NET "leds_o[6]" SLEW = SLOW;
NET "leds_o[5]" IOSTANDARD = LVCMOS25;
NET "leds_o[5]" DRIVE = 12;
NET "leds_o[5]" SLEW = SLOW;
NET "leds_o[4]" IOSTANDARD = LVCMOS25;
NET "leds_o[4]" DRIVE = 12;
NET "leds_o[4]" SLEW = SLOW;
NET "leds_o[3]" IOSTANDARD = LVCMOS25;
NET "leds_o[3]" DRIVE = 12;
NET "leds_o[3]" SLEW = SLOW;
NET "leds_o[2]" IOSTANDARD = LVCMOS25;
NET "leds_o[2]" DRIVE = 12;
NET "leds_o[2]" SLEW = SLOW;
NET "leds_o[1]" IOSTANDARD = LVCMOS25;
NET "leds_o[1]" DRIVE = 12;
NET "leds_o[1]" SLEW = SLOW;
NET "leds_o[0]" IOSTANDARD = LVCMOS25;
NET "leds_o[0]" DRIVE = 12;
NET "leds_o[0]" SLEW = SLOW;
NET "uart_rxd_i" IOSTANDARD = LVCMOS25;
NET "uart_txd_o" IOSTANDARD = LVCMOS25;

NET "sys_clk_p_i" IOSTANDARD = LVDS_25;
NET "sys_clk_n_i" IOSTANDARD = LVDS_25;
NET "sys_rst_button_i" IOSTANDARD = "SSTL15" | TIG;

NET "sys_rst_button_i" LOC = H10;

# PlanAhead Generated physical constraints 

NET "sys_clk_n_i" LOC = H9;
NET "sys_clk_p_i" LOC = J9;

################################################################################
# Clock constraints
################################################################################
NET "ADC_CLK_AB_P_I" TNM_NET = ADC_CLK_AB_P;

#NET "CLK_TO_FPGA_P" TNM_NET = CLK_TO_FPGA_P;
#TIMESPEC TS_CLK_TO_FPGA_P = PERIOD "CLK_TO_FPGA_P" 246 MHz HIGH 50%;
#NET "EXT_TRIGGER_P" TNM_NET = EXT_TRIGGER_P;
#TIMESPEC TS_EXT_TRIGGER_P = PERIOD "EXT_TRIGGER_P" 246 MHz HIGH 50%;
NET "ADC_CLK_AB_P_I" CLOCK_DEDICATED_ROUTE = FALSE;

################################################################################
# FMC signals (FMC150 on ML605, LPC site)
################################################################################
NET "ADC_N_EN_O" LOC="A33";
NET "ADC_RESET_O" LOC="B32";
NET "ADC_SDO_I" LOC="C32";
NET "CDCE_N_EN_O" LOC="M26";
NET "CDCE_N_PD_O" LOC="L31";
NET "CDCE_N_RESET_O" LOC="M31";
NET "CDCE_SDO_I" LOC="M27";
NET "ADC_CHA_N_I<0>" LOC="E31";
NET "ADC_CHA_N_I<1>" LOC="H30";
NET "ADC_CHA_N_I<2>" LOC="J32";
NET "ADC_CHA_N_I<3>" LOC="J29";
NET "ADC_CHA_N_I<4>" LOC="H33";
NET "ADC_CHA_N_I<5>" LOC="J34";
NET "ADC_CHA_N_I<6>" LOC="H32";
NET "ADC_CHA_P_I<0>" LOC="F31";
NET "ADC_CHA_P_I<1>" LOC="G31";
NET "ADC_CHA_P_I<2>" LOC="J31";
NET "ADC_CHA_P_I<3>" LOC="K28";
NET "ADC_CHA_P_I<4>" LOC="H34";
NET "ADC_CHA_P_I<5>" LOC="K33";
NET "ADC_CHA_P_I<6>" LOC="G32";
NET "ADC_CHB_N_I<0>" LOC="K29";
NET "ADC_CHB_N_I<1>" LOC="L26";
NET "ADC_CHB_N_I<2>" LOC="G30";
NET "ADC_CHB_N_I<3>" LOC="D32";
NET "ADC_CHB_N_I<4>" LOC="E33";
NET "ADC_CHB_N_I<5>" LOC="C34";
NET "ADC_CHB_N_I<6>" LOC="B34";
NET "ADC_CHB_P_I<0>" LOC="J30";
NET "ADC_CHB_P_I<1>" LOC="L25";
NET "ADC_CHB_P_I<2>" LOC="F30";
NET "ADC_CHB_P_I<3>" LOC="D31";
NET "ADC_CHB_P_I<4>" LOC="E32";
NET "ADC_CHB_P_I<5>" LOC="D34";
NET "ADC_CHB_P_I<6>" LOC="C33";
NET "ADC_CLK_AB_N_I" LOC="K27";
NET "ADC_CLK_AB_P_I" LOC="K26";
#NET "CLK_TO_FPGA_N_I" LOC="B10";
#NET "CLK_TO_FPGA_P_I" LOC="A10";
#NET "EXT_TRIGGER_N_I" LOC="G33";
#NET "EXT_TRIGGER_P_I" LOC="F33";
NET "MON_N_EN_O" LOC="R31";
NET "MON_N_INT_I" LOC="M25";
NET "MON_N_RESET_O" LOC="R32";
NET "MON_SDO_I" LOC="N25";
NET "CDCE_PLL_STATUS_I" LOC="K31";
NET "PRSNT_M2C_L_I" LOC="AD9";
NET "CDCE_REF_EN_O" LOC="K32";
NET "SPI_SCLK_O" LOC="N34";
NET "SPI_SDATA_O" LOC="P34";

NET "DAC_DATA_N_O<0>" LOC="M32";
NET "DAC_DATA_N_O<1>" LOC="P30";
NET "DAC_DATA_N_O<2>" LOC="P32";
NET "DAC_DATA_N_O<3>" LOC="R27";
NET "DAC_DATA_N_O<4>" LOC="R29";
NET "DAC_DATA_N_O<5>" LOC="N30";
NET "DAC_DATA_N_O<6>" LOC="L30";
NET "DAC_DATA_N_O<7>" LOC="N29";
NET "DAC_DATA_P_O<0>" LOC="L33";
NET "DAC_DATA_P_O<1>" LOC="P31";
NET "DAC_DATA_P_O<2>" LOC="N32";
NET "DAC_DATA_P_O<3>" LOC="R28";
NET "DAC_DATA_P_O<4>" LOC="P29";
NET "DAC_DATA_P_O<5>" LOC="M30";
NET "DAC_DATA_P_O<6>" LOC="L29";
NET "DAC_DATA_P_O<7>" LOC="N28";
NET "DAC_DCLK_N_O" LOC="T26";
NET "DAC_DCLK_P_O" LOC="R26";
NET "DAC_FRAME_N_O" LOC="P27";
NET "DAC_FRAME_P_O" LOC="N27";
NET "DAC_N_EN_O" LOC="N33";
NET "DAC_SDO_I" LOC="M33";
NET "TXENABLE_O" LOC="B33";

# UP Status MMCM <-> Led signals GPIO_LED_C
#NET "UP_STATUS<2>" LOC="AP24"  |  IOSTANDARD = "LVCMOS25";
# UP Status CDCE_PLL <-> Led signals GPIO_LED_W
#NET "UP_STATUS<1>" LOC="AD21"  |  IOSTANDARD = "LVCMOS25";

################################################################################
# Clock Constraints
################################################################################
NET "adc_clk_ab_n_i" TNM_NET = adc_clk_ab_n_i;
TIMESPEC TS_adc_clk_ab_n_i = PERIOD "adc_clk_ab_n_i" 16.276 ns HIGH 50%;
#TIMESPEC TS_adc_clk_ab_n_i = PERIOD "adc_clk_ab_n_i" 61.44 MHz HIGH 50%;
#TIMESPEC TS_adc_clk_ab_n_i = PERIOD "adc_clk_ab_n_i" 122.88 MHz HIGH 50%;
#TIMESPEC TS_adc_clk_ab_n_i = PERIOD "adc_clk_ab_n_i" 98.304 MHz HIGH 50%;
NET "adc_clk_ab_p_i" TNM_NET = adc_clk_ab_p_i;
TIMESPEC TS_adc_clk_ab_p_i = PERIOD "adc_clk_ab_p_i" 16.276 ns HIGH 50%;
#TIMESPEC TS_adc_clk_ab_p_i = PERIOD "adc_clk_ab_p_i" 61.44 MHz HIGH 50%;
#TIMESPEC TS_adc_clk_ab_p_i = PERIOD "adc_clk_ab_p_i" 122.88 MHz HIGH 50%;
#TIMESPEC TS_adc_clk_ab_p_i = PERIOD "adc_clk_ab_p_i" 98.304 MHz HIGH 50%;

################################################################################
# Timing Constraints
################################################################################
INST "adc_cha_n_i<0>" TNM = TMN_fmc150_adc_cha_n;
INST "adc_cha_n_i<1>" TNM = TMN_fmc150_adc_cha_n;
INST "adc_cha_n_i<2>" TNM = TMN_fmc150_adc_cha_n;
INST "adc_cha_n_i<3>" TNM = TMN_fmc150_adc_cha_n;
INST "adc_cha_n_i<4>" TNM = TMN_fmc150_adc_cha_n;
INST "adc_cha_n_i<5>" TNM = TMN_fmc150_adc_cha_n;
INST "adc_cha_n_i<6>" TNM = TMN_fmc150_adc_cha_n;
TIMEGRP "TMN_fmc150_adc_cha_n" OFFSET = IN 8.138 ns VALID 16.276 ns BEFORE "adc_clk_ab_n_i" RISING;
#TIMEGRP "TMN_fmc150_adc_cha_n" OFFSET = IN 4.069 ns VALID 8.138 ns BEFORE "adc_clk_ab_n_i" RISING;
#TIMEGRP "TMN_fmc150_adc_cha_n" OFFSET = IN 5.087 ns VALID 10.173 ns BEFORE "adc_clk_ab_n_i" RISING;
INST "adc_cha_p_i<0>" TNM = TMN_fmc150_adc_cha_p;
INST "adc_cha_p_i<1>" TNM = TMN_fmc150_adc_cha_p;
INST "adc_cha_p_i<2>" TNM = TMN_fmc150_adc_cha_p;
INST "adc_cha_p_i<3>" TNM = TMN_fmc150_adc_cha_p;
INST "adc_cha_p_i<4>" TNM = TMN_fmc150_adc_cha_p;
INST "adc_cha_p_i<5>" TNM = TMN_fmc150_adc_cha_p;
INST "adc_cha_p_i<6>" TNM = TMN_fmc150_adc_cha_p;
TIMEGRP "TMN_fmc150_adc_cha_p" OFFSET = IN 8.138 ns VALID 16.276 ns BEFORE "adc_clk_ab_p_i" RISING;
#TIMEGRP "TMN_fmc150_adc_cha_p" OFFSET = IN 4.069 ns VALID 8.138 ns BEFORE "adc_clk_ab_p_i" RISING;
#TIMEGRP "TMN_fmc150_adc_cha_p" OFFSET = IN 5.087 ns VALID 10.173 ns BEFORE "adc_clk_ab_p_i" RISING;
INST "adc_chb_n_i<0>" TNM = TMN_fmc150_adc_chb_n;
INST "adc_chb_n_i<1>" TNM = TMN_fmc150_adc_chb_n;
INST "adc_chb_n_i<2>" TNM = TMN_fmc150_adc_chb_n;
INST "adc_chb_n_i<3>" TNM = TMN_fmc150_adc_chb_n;
INST "adc_chb_n_i<4>" TNM = TMN_fmc150_adc_chb_n;
INST "adc_chb_n_i<5>" TNM = TMN_fmc150_adc_chb_n;
INST "adc_chb_n_i<6>" TNM = TMN_fmc150_adc_chb_n;
TIMEGRP "TMN_fmc150_adc_chb_n" OFFSET = IN 8.138 ns VALID 16.276 ns BEFORE "adc_clk_ab_n_i" RISING;
#TIMEGRP "TMN_fmc150_adc_chb_n" OFFSET = IN 4.069 ns VALID 8.138 ns BEFORE "adc_clk_ab_n_i" RISING;
#TIMEGRP "TMN_fmc150_adc_chb_n" OFFSET = IN 5.087 ns VALID 10.173 ns BEFORE "adc_clk_ab_n_i" RISING;
INST "adc_chb_p_i<0>" TNM = TMN_fmc150_adc_chb_p;
INST "adc_chb_p_i<1>" TNM = TMN_fmc150_adc_chb_p;
INST "adc_chb_p_i<2>" TNM = TMN_fmc150_adc_chb_p;
INST "adc_chb_p_i<3>" TNM = TMN_fmc150_adc_chb_p;
INST "adc_chb_p_i<4>" TNM = TMN_fmc150_adc_chb_p;
INST "adc_chb_p_i<5>" TNM = TMN_fmc150_adc_chb_p;
INST "adc_chb_p_i<6>" TNM = TMN_fmc150_adc_chb_p;
TIMEGRP "TMN_fmc150_adc_chb_p" OFFSET = IN 8.138 ns VALID 16.276 ns BEFORE "adc_clk_ab_p_i" RISING;
#TIMEGRP "TMN_fmc150_adc_chb_p" OFFSET = IN 4.069 ns VALID 8.138 ns BEFORE "adc_clk_ab_p_i" RISING;
#TIMEGRP "TMN_fmc150_adc_chb_p" OFFSET = IN 5.087 ns VALID 10.173 ns BEFORE "adc_clk_ab_p_i" RISING;

################################################################################
# Crossing Clock Domain FIFO Constraints
################################################################################

#NET "fmc150_if_dma_0/fmc150_if_dma_0/USER_LOGIC_I/cmp_fmc150_testbench/adc_str_out" TNM_NET = "CLK_ADC_GRP";
#NET "clock_generator_0/clock_generator_0/SIG_MMCM0_CLKOUT2" TNM_NET = "CLK_DMA_GRP";
 
#INST "*/gen_fifo_inst*" TPTHRU = "ASYNC_FIFO";
 
#TIMESPEC TS_CC_AB = FROM "CLK_ADC_GRP" THRU "ASYNC_FIFO" TO "CLK_DMA_GRP" TIG;
#TIMESPEC TS_CC_BA = FROM "CLK_DMA_GRP" THRU "ASYNC_FIFO" TO "CLK_ADC_GRP" TIG;
