echo "project open dbe_bpm_simple.xise" > run.tcl
echo "process run {Generate Programming File} -force rerun_all" >> run.tcl
xtclsh run.tcl
WARNING:ProjectMgmt - File /home/lerwys/Repos/bpm-sw/hdl/syn/dbe_bpm_simple/_ngo
   is missing.
WARNING:ProjectMgmt - File
   /home/lerwys/Repos/bpm-sw/hdl/syn/dbe_bpm_simple/_xmsgs/bitgen.xmsgs is
   missing.
WARNING:ProjectMgmt - File
   /home/lerwys/Repos/bpm-sw/hdl/syn/dbe_bpm_simple/_xmsgs/map.xmsgs is missing.
WARNING:ProjectMgmt - File
   /home/lerwys/Repos/bpm-sw/hdl/syn/dbe_bpm_simple/_xmsgs/ngdbuild.xmsgs is
   missing.
WARNING:ProjectMgmt - File
   /home/lerwys/Repos/bpm-sw/hdl/syn/dbe_bpm_simple/_xmsgs/par.xmsgs is missing.
WARNING:ProjectMgmt - File
   /home/lerwys/Repos/bpm-sw/hdl/syn/dbe_bpm_simple/_xmsgs/trce.xmsgs is
   missing.
WARNING:ProjectMgmt - File
   /home/lerwys/Repos/bpm-sw/hdl/syn/dbe_bpm_simple/_xmsgs/xst.xmsgs is missing.
WARNING:ProjectMgmt - File
   /home/lerwys/Repos/bpm-sw/hdl/syn/dbe_bpm_simple/dbe_bpm_simple_top.bld is
   missing.
WARNING:ProjectMgmt - File
   /home/lerwys/Repos/bpm-sw/hdl/syn/dbe_bpm_simple/dbe_bpm_simple_top.cmd_log
   is missing.
WARNING:ProjectMgmt - File
   /home/lerwys/Repos/bpm-sw/hdl/syn/dbe_bpm_simple/dbe_bpm_simple_top.drc is
   missing.
WARNING:ProjectMgmt - File
   /home/lerwys/Repos/bpm-sw/hdl/syn/dbe_bpm_simple/dbe_bpm_simple_top.lso is
   missing.
WARNING:ProjectMgmt - File
   /home/lerwys/Repos/bpm-sw/hdl/syn/dbe_bpm_simple/dbe_bpm_simple_top.ncd is
   missing.
WARNING:ProjectMgmt - File
   /home/lerwys/Repos/bpm-sw/hdl/syn/dbe_bpm_simple/dbe_bpm_simple_top.ngc is
   missing.
WARNING:ProjectMgmt - File
   /home/lerwys/Repos/bpm-sw/hdl/syn/dbe_bpm_simple/dbe_bpm_simple_top.ngd is
   missing.
WARNING:ProjectMgmt - File
   /home/lerwys/Repos/bpm-sw/hdl/syn/dbe_bpm_simple/dbe_bpm_simple_top.ngr is
   missing.
WARNING:ProjectMgmt - File
   /home/lerwys/Repos/bpm-sw/hdl/syn/dbe_bpm_simple/dbe_bpm_simple_top.pad is
   missing.
WARNING:ProjectMgmt - File
   /home/lerwys/Repos/bpm-sw/hdl/syn/dbe_bpm_simple/dbe_bpm_simple_top.par is
   missing.
WARNING:ProjectMgmt - File
   /home/lerwys/Repos/bpm-sw/hdl/syn/dbe_bpm_simple/dbe_bpm_simple_top.pcf is
   missing.
WARNING:ProjectMgmt - File
   /home/lerwys/Repos/bpm-sw/hdl/syn/dbe_bpm_simple/dbe_bpm_simple_top.prj is
   missing.
WARNING:ProjectMgmt - File
   /home/lerwys/Repos/bpm-sw/hdl/syn/dbe_bpm_simple/dbe_bpm_simple_top.ptwx is
   missing.
WARNING:ProjectMgmt - File
   /home/lerwys/Repos/bpm-sw/hdl/syn/dbe_bpm_simple/dbe_bpm_simple_top.stx is
   missing.
WARNING:ProjectMgmt - File
   /home/lerwys/Repos/bpm-sw/hdl/syn/dbe_bpm_simple/dbe_bpm_simple_top.syr is
   missing.
WARNING:ProjectMgmt - File
   /home/lerwys/Repos/bpm-sw/hdl/syn/dbe_bpm_simple/dbe_bpm_simple_top.twr is
   missing.
WARNING:ProjectMgmt - File
   /home/lerwys/Repos/bpm-sw/hdl/syn/dbe_bpm_simple/dbe_bpm_simple_top.twx is
   missing.
WARNING:ProjectMgmt - File
   /home/lerwys/Repos/bpm-sw/hdl/syn/dbe_bpm_simple/dbe_bpm_simple_top.unroutes
   is missing.
WARNING:ProjectMgmt - File
   /home/lerwys/Repos/bpm-sw/hdl/syn/dbe_bpm_simple/dbe_bpm_simple_top.ut is
   missing.
WARNING:ProjectMgmt - File
   /home/lerwys/Repos/bpm-sw/hdl/syn/dbe_bpm_simple/dbe_bpm_simple_top.xpi is
   missing.
WARNING:ProjectMgmt - File
   /home/lerwys/Repos/bpm-sw/hdl/syn/dbe_bpm_simple/dbe_bpm_simple_top.xst is
   missing.
WARNING:ProjectMgmt - File
   /home/lerwys/Repos/bpm-sw/hdl/syn/dbe_bpm_simple/dbe_bpm_simple_top_guide.ncd
   is missing.
WARNING:ProjectMgmt - File
   /home/lerwys/Repos/bpm-sw/hdl/syn/dbe_bpm_simple/dbe_bpm_simple_top_map.map
   is missing.
WARNING:ProjectMgmt - File
   /home/lerwys/Repos/bpm-sw/hdl/syn/dbe_bpm_simple/dbe_bpm_simple_top_map.mrp
   is missing.
WARNING:ProjectMgmt - File
   /home/lerwys/Repos/bpm-sw/hdl/syn/dbe_bpm_simple/dbe_bpm_simple_top_map.ncd
   is missing.
WARNING:ProjectMgmt - File
   /home/lerwys/Repos/bpm-sw/hdl/syn/dbe_bpm_simple/dbe_bpm_simple_top_map.ngm
   is missing.
WARNING:ProjectMgmt - File
   /home/lerwys/Repos/bpm-sw/hdl/syn/dbe_bpm_simple/dbe_bpm_simple_top_map.xrpt
   is missing.
WARNING:ProjectMgmt - File
   /home/lerwys/Repos/bpm-sw/hdl/syn/dbe_bpm_simple/dbe_bpm_simple_top_ngdbuild.
   xrpt is missing.
WARNING:ProjectMgmt - File
   /home/lerwys/Repos/bpm-sw/hdl/syn/dbe_bpm_simple/dbe_bpm_simple_top_pad.csv
   is missing.
WARNING:ProjectMgmt - File
   /home/lerwys/Repos/bpm-sw/hdl/syn/dbe_bpm_simple/dbe_bpm_simple_top_pad.txt
   is missing.
WARNING:ProjectMgmt - File
   /home/lerwys/Repos/bpm-sw/hdl/syn/dbe_bpm_simple/dbe_bpm_simple_top_par.xrpt
   is missing.
WARNING:ProjectMgmt - File
   /home/lerwys/Repos/bpm-sw/hdl/syn/dbe_bpm_simple/dbe_bpm_simple_top_summary.x
   ml is missing.
WARNING:ProjectMgmt - File
   /home/lerwys/Repos/bpm-sw/hdl/syn/dbe_bpm_simple/dbe_bpm_simple_top_usage.xml
   is missing.
WARNING:ProjectMgmt - File
   /home/lerwys/Repos/bpm-sw/hdl/syn/dbe_bpm_simple/dbe_bpm_simple_top_xst.xrpt
   is missing.
WARNING:ProjectMgmt - File
   /home/lerwys/Repos/bpm-sw/hdl/syn/dbe_bpm_simple/webtalk.log is missing.
WARNING:ProjectMgmt - File
   /home/lerwys/Repos/bpm-sw/hdl/syn/dbe_bpm_simple/webtalk_pn.xml is missing.
WARNING:ProjectMgmt - File
   /home/lerwys/Repos/bpm-sw/hdl/syn/dbe_bpm_simple/xlnx_auto_0_xdb is missing.
WARNING:ProjectMgmt - File /home/lerwys/Repos/bpm-sw/hdl/syn/dbe_bpm_simple/xst
   is missing.

Started : "Synthesize - XST".
Running xst...
Command Line: xst -intstyle ise -ifn "/home/lerwys/Repos/bpm-sw/hdl/syn/dbe_bpm_simple/dbe_bpm_simple_top.xst" -ofn "/home/lerwys/Repos/bpm-sw/hdl/syn/dbe_bpm_simple/dbe_bpm_simple_top.syr"
Reading design: dbe_bpm_simple_top.prj
INFO:Xst - Part-select index evaluated to out of bound value may lead to incorrect synthesis results; it is recommended not to use them in RTL

=========================================================================
*                          HDL Parsing                                  *
=========================================================================
Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v" into library work
Parsing module <sockit_owm>.
Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v" into library work
Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v" included at line 41.
Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" included at line 42.
Parsing module <spi_clgen>.
Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v" into library work
Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v" included at line 41.
Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" included at line 42.
Parsing module <spi_shift>.
Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v" into library work
Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v" included at line 42.
Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v" included at line 43.
Parsing module <spi_top>.
Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" into library work
Parsing module <lm32_top_full_debug>.
Parsing module <lm32_mc_arithmetic_full_debug>.
Parsing module <lm32_cpu_full_debug>.
Parsing module <lm32_load_store_unit_full_debug>.
Parsing module <lm32_decoder_full_debug>.
Parsing module <lm32_icache_full_debug>.
Parsing module <lm32_dcache_full_debug>.
Parsing module <lm32_debug_full_debug>.
Parsing module <lm32_instruction_unit_full_debug>.
Parsing module <lm32_jtag_full_debug>.
Parsing module <lm32_interrupt_full_debug>.
Parsing module <lm32_top_full>.
Parsing module <lm32_mc_arithmetic_full>.
Parsing module <lm32_cpu_full>.
Parsing module <lm32_load_store_unit_full>.
Parsing module <lm32_decoder_full>.
Parsing module <lm32_icache_full>.
Parsing module <lm32_dcache_full>.
Parsing module <lm32_instruction_unit_full>.
Parsing module <lm32_interrupt_full>.
Parsing module <lm32_top_medium_debug>.
Parsing module <lm32_mc_arithmetic_medium_debug>.
Parsing module <lm32_cpu_medium_debug>.
Parsing module <lm32_load_store_unit_medium_debug>.
Parsing module <lm32_decoder_medium_debug>.
Parsing module <lm32_icache_medium_debug>.
Parsing module <lm32_debug_medium_debug>.
Parsing module <lm32_instruction_unit_medium_debug>.
Parsing module <lm32_jtag_medium_debug>.
Parsing module <lm32_interrupt_medium_debug>.
Parsing module <lm32_top_medium_icache_debug>.
Parsing module <lm32_mc_arithmetic_medium_icache_debug>.
Parsing module <lm32_cpu_medium_icache_debug>.
Parsing module <lm32_load_store_unit_medium_icache_debug>.
Parsing module <lm32_decoder_medium_icache_debug>.
Parsing module <lm32_icache_medium_icache_debug>.
Parsing module <lm32_debug_medium_icache_debug>.
Parsing module <lm32_instruction_unit_medium_icache_debug>.
Parsing module <lm32_jtag_medium_icache_debug>.
Parsing module <lm32_interrupt_medium_icache_debug>.
Parsing module <lm32_top_medium_icache>.
Parsing module <lm32_mc_arithmetic_medium_icache>.
Parsing module <lm32_cpu_medium_icache>.
Parsing module <lm32_load_store_unit_medium_icache>.
Parsing module <lm32_decoder_medium_icache>.
Parsing module <lm32_icache_medium_icache>.
Parsing module <lm32_instruction_unit_medium_icache>.
Parsing module <lm32_interrupt_medium_icache>.
Parsing module <lm32_top_medium>.
Parsing module <lm32_mc_arithmetic_medium>.
Parsing module <lm32_cpu_medium>.
Parsing module <lm32_load_store_unit_medium>.
Parsing module <lm32_decoder_medium>.
Parsing module <lm32_instruction_unit_medium>.
Parsing module <lm32_interrupt_medium>.
Parsing module <lm32_top_minimal>.
Parsing module <lm32_mc_arithmetic_minimal>.
Parsing module <lm32_cpu_minimal>.
Parsing module <lm32_load_store_unit_minimal>.
Parsing module <lm32_decoder_minimal>.
Parsing module <lm32_instruction_unit_minimal>.
Parsing module <lm32_interrupt_minimal>.
Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_mc_arithmetic.v" into library work
Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v" included at line 29.
Parsing module <lm32_mc_arithmetic>.
Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v" into library work
Parsing module <jtag_cores>.
Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v" into library work
Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v" included at line 29.
Parsing module <lm32_adder>.
Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v" into library work
Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v" included at line 28.
Parsing module <lm32_addsub>.
Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.v" into library work
Parsing module <lm32_dp_ram>.
Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v" into library work
Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v" included at line 29.
Parsing module <lm32_logic_op>.
Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.v" into library work
Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v" included at line 34.
Parsing module <lm32_ram>.
Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v" into library work
Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v" included at line 29.
Parsing module <lm32_shifter>.
Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic/lm32_multiplier.v" into library work
Parsing verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic/../../src/lm32_include.v" included at line 29.
Parsing module <lm32_multiplier>.
Analyzing Verilog file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic/jtag_tap.v" into library work
Parsing module <jtag_tap>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/genram_pkg.vhd" into library work
Parsing package <genram_pkg>.
Parsing package body <genram_pkg>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd" into library work
Parsing package <wishbone_pkg>.
Parsing package body <wishbone_pkg>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gencores_pkg.vhd" into library work
Parsing package <gencores_pkg>.
Parsing package body <gencores_pkg>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_stream/wb_stream_pkg.vhd" into library work
Parsing package <wb_stream_pkg>.
Parsing package body <wb_stream_pkg>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/dbe_wishbone_pkg.vhd" into library work
Parsing package <dbe_wishbone_pkg>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_simple/dbe_bpm_simple_top.vhd" into library work
Parsing entity <dbe_bpm_simple_top>.
Parsing architecture <rtl> of entity <dbe_bpm_simple_top>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_simple/sys_pll.vhd" into library work
Parsing entity <sys_pll>.
Parsing architecture <syn> of entity <sys_pll>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_simple/clk_gen.vhd" into library work
Parsing entity <clk_gen>.
Parsing architecture <syn> of entity <clk_gen>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_common/dbe_common_pkg.vhd" into library work
Parsing package <dbe_common_pkg>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_stream/xwb_stream_sink.vhd" into library work
Parsing entity <xwb_stream_sink>.
Parsing architecture <rtl> of entity <xwb_stream_sink>.
Parsing entity <wb_stream_sink>.
Parsing architecture <wrapper> of entity <wb_stream_sink>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_stream/xwb_stream_source.vhd" into library work
Parsing entity <xwb_stream_source>.
Parsing architecture <rtl> of entity <xwb_stream_source>.
Parsing entity <wb_stream_source>.
Parsing architecture <wrapper> of entity <wb_stream_source>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/xfmc150_regs_pkg.vhd" into library work
Parsing package <fmc150_wbgen2_pkg>.
Parsing package body <fmc150_wbgen2_pkg>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/wb_fmc150.vhd" into library work
Parsing entity <wb_fmc150>.
Parsing architecture <rtl> of entity <wb_fmc150>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/xwb_fmc150.vhd" into library work
Parsing entity <xwb_fmc150>.
Parsing architecture <rtl> of entity <xwb_fmc150>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/wb_fmc150_port.vhd" into library work
Parsing entity <wb_fmc150_port>.
Parsing architecture <syn> of entity <wb_fmc150_port>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/adc/adc_channel_lvds_ddr.vhd" into library work
Parsing entity <adc_channel_lvds_ddr>.
Parsing architecture <rtl> of entity <adc_channel_lvds_ddr>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/adc/adc_pkg.vhd" into library work
Parsing package <adc_pkg>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/adc/strobe_lvds.vhd" into library work
Parsing entity <strobe_lvds>.
Parsing architecture <rtl> of entity <strobe_lvds>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/fmc150/ads62p49_ctrl.vhd" into library work
Parsing entity <ads62p49_ctrl>.
Parsing architecture <ads62p49_ctrl_syn> of entity <ads62p49_ctrl>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/fmc150/amc7823_ctrl.vhd" into library work
Parsing entity <amc7823_ctrl>.
Parsing architecture <amc7823_ctrl_syn> of entity <amc7823_ctrl>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/fmc150/cdce72010_ctrl.vhd" into library work
Parsing entity <cdce72010_ctrl>.
Parsing architecture <cdce72010_ctrl_syn> of entity <cdce72010_ctrl>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/fmc150/dac3283_ctrl.vhd" into library work
Parsing entity <dac3283_ctrl>.
Parsing architecture <dac3283_ctrl_syn> of entity <dac3283_ctrl>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/fmc150/fmc150_adc_if.vhd" into library work
Parsing entity <fmc150_adc_if>.
Parsing architecture <rtl> of entity <fmc150_adc_if>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/fmc150/fmc150_dac_if.vhd" into library work
Parsing entity <fmc150_dac_if>.
Parsing architecture <rtl> of entity <fmc150_dac_if>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/fmc150/fmc150_pkg.vhd" into library work
Parsing package <fmc150_pkg>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/fmc150/fmc150_spi_ctrl.vhd" into library work
Parsing entity <fmc150_spi_ctrl>.
Parsing architecture <fmc150_spi_ctrl_syn> of entity <fmc150_spi_ctrl>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/fmc150/fmc150_stellar_cmd.vhd" into library work
Parsing entity <fmc150_stellar_cmd>.
Parsing architecture <arch_fmc150_stellar_cmd> of entity <fmc150_stellar_cmd>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/fmc150/fmc150_testbench.vhd" into library work
Parsing entity <fmc150_testbench>.
Parsing architecture <rtl> of entity <fmc150_testbench>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/fmc150/pulse2pulse.vhd" into library work
Parsing entity <pulse2pulse>.
Parsing architecture <syn> of entity <pulse2pulse>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_common/reset_synch/reset_synch.vhd" into library work
Parsing entity <reset_synch>.
Parsing architecture <rtl> of entity <reset_synch>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_crc_gen.vhd" into library work
Parsing entity <gc_crc_gen>.
Parsing architecture <rtl> of entity <gc_crc_gen>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_moving_average.vhd" into library work
Parsing entity <gc_moving_average>.
Parsing architecture <rtl> of entity <gc_moving_average>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_extend_pulse.vhd" into library work
Parsing entity <gc_extend_pulse>.
Parsing architecture <rtl> of entity <gc_extend_pulse>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_delay_gen.vhd" into library work
Parsing entity <gc_delay_gen>.
Parsing architecture <behavioral> of entity <gc_delay_gen>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_dual_pi_controller.vhd" into library work
Parsing entity <gc_dual_pi_controller>.
Parsing architecture <behavioral> of entity <gc_dual_pi_controller>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_reset.vhd" into library work
Parsing entity <gc_reset>.
Parsing architecture <rtl> of entity <gc_reset>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_serial_dac.vhd" into library work
Parsing entity <gc_serial_dac>.
Parsing architecture <syn> of entity <gc_serial_dac>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_sync_ffs.vhd" into library work
Parsing entity <gc_sync_ffs>.
Parsing architecture <behavioral> of entity <gc_sync_ffs>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_arbitrated_mux.vhd" into library work
Parsing entity <gc_arbitrated_mux>.
Parsing architecture <rtl> of entity <gc_arbitrated_mux>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd" into library work
Parsing entity <gc_pulse_synchronizer>.
Parsing architecture <rtl> of entity <gc_pulse_synchronizer>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_frequency_meter.vhd" into library work
Parsing entity <gc_frequency_meter>.
Parsing architecture <behavioral> of entity <gc_frequency_meter>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_dual_clock_ram.vhd" into library work
Parsing entity <gc_dual_clock_ram>.
Parsing architecture <rtl> of entity <gc_dual_clock_ram>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_wfifo.vhd" into library work
Parsing entity <gc_wfifo>.
Parsing architecture <rtl> of entity <gc_wfifo>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd" into library work
Parsing package <memory_loader_pkg>.
Parsing package body <memory_loader_pkg>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/generic_shiftreg_fifo.vhd" into library work
Parsing entity <generic_shiftreg_fifo>.
Parsing architecture <rtl> of entity <generic_shiftreg_fifo>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd" into library work
Parsing entity <generic_dpram>.
Parsing architecture <syn> of entity <generic_dpram>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd" into library work
Parsing entity <generic_dpram_sameclock>.
Parsing architecture <syn> of entity <generic_dpram_sameclock>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd" into library work
Parsing entity <generic_dpram_dualclock>.
Parsing architecture <syn> of entity <generic_dpram_dualclock>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_spram.vhd" into library work
Parsing entity <generic_spram>.
Parsing architecture <syn> of entity <generic_spram>.
WARNING:HDLCompiler:443 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_spram.vhd" Line 58: Function f_bitstring_2_slv does not always return a value.
WARNING:HDLCompiler:443 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_spram.vhd" Line 63: Function f_load_from_file does not always return a value.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_v6_1_pkg.vhd" into library fifo_generator_v6_1
Parsing package <fifo_generator_v6_1_pkg>.
Parsing package body <fifo_generator_v6_1_pkg>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_v6_1_defaults.vhd" into library fifo_generator_v6_1
Parsing package <fifo_generator_v6_1_defaults>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_v6_1_xst_comp.vhd" into library fifo_generator_v6_1
Parsing package <fifo_generator_v6_1_xst_comp>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/input_blk.vhd" into library fifo_generator_v6_1
Parsing entity <input_blk>.
Parsing architecture <xilinx> of entity <input_blk>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/output_blk.vhd" into library fifo_generator_v6_1
Parsing entity <output_blk>.
Parsing architecture <xilinx> of entity <output_blk>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/shft_wrapper.vhd" into library fifo_generator_v6_1
Parsing entity <shft_wrapper>.
Parsing architecture <xilinx> of entity <shft_wrapper>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/shft_ram.vhd" into library fifo_generator_v6_1
Parsing entity <shft_ram>.
Parsing architecture <xilinx> of entity <shft_ram>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/dmem.vhd" into library fifo_generator_v6_1
Parsing entity <dmem>.
Parsing architecture <Xilinx> of entity <dmem>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_v4_1_xst_comp.vhd" into library blk_mem_gen_v4_1
Parsing package <blk_mem_gen_v4_1_xst_comp>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/memory.vhd" into library fifo_generator_v6_1
Parsing entity <memory>.
Parsing architecture <xilinx> of entity <memory>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/compare.vhd" into library fifo_generator_v6_1
Parsing entity <compare>.
Parsing architecture <Xilinx> of entity <compare>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_bin_cntr.vhd" into library fifo_generator_v6_1
Parsing entity <wr_bin_cntr>.
Parsing architecture <xilinx> of entity <wr_bin_cntr>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_bin_cntr.vhd" into library fifo_generator_v6_1
Parsing entity <rd_bin_cntr>.
Parsing architecture <xilinx> of entity <rd_bin_cntr>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/updn_cntr.vhd" into library fifo_generator_v6_1
Parsing entity <updn_cntr>.
Parsing architecture <xilinx> of entity <updn_cntr>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_status_flags_as.vhd" into library fifo_generator_v6_1
Parsing entity <rd_status_flags_as>.
Parsing architecture <xilinx> of entity <rd_status_flags_as>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_status_flags_ss.vhd" into library fifo_generator_v6_1
Parsing entity <rd_status_flags_ss>.
Parsing architecture <xilinx> of entity <rd_status_flags_ss>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_pe_as.vhd" into library fifo_generator_v6_1
Parsing entity <rd_pe_as>.
Parsing architecture <xilinx> of entity <rd_pe_as>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_pe_ss.vhd" into library fifo_generator_v6_1
Parsing entity <rd_pe_ss>.
Parsing architecture <xilinx> of entity <rd_pe_ss>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_handshaking_flags.vhd" into library fifo_generator_v6_1
Parsing entity <rd_handshaking_flags>.
Parsing architecture <xilinx> of entity <rd_handshaking_flags>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_dc_as.vhd" into library fifo_generator_v6_1
Parsing entity <rd_dc_as>.
Parsing architecture <xilinx> of entity <rd_dc_as>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_dc_fwft_ext_as.vhd" into library fifo_generator_v6_1
Parsing entity <rd_dc_fwft_ext_as>.
Parsing architecture <xilinx> of entity <rd_dc_fwft_ext_as>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/dc_ss.vhd" into library fifo_generator_v6_1
Parsing entity <dc_ss>.
Parsing architecture <xilinx> of entity <dc_ss>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/dc_ss_fwft.vhd" into library fifo_generator_v6_1
Parsing entity <dc_ss_fwft>.
Parsing architecture <xilinx> of entity <dc_ss_fwft>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_fwft.vhd" into library fifo_generator_v6_1
Parsing entity <rd_fwft>.
Parsing architecture <xilinx> of entity <rd_fwft>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_logic.vhd" into library fifo_generator_v6_1
Parsing entity <rd_logic>.
Parsing architecture <xilinx> of entity <rd_logic>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/reset_blk_ramfifo.vhd" into library fifo_generator_v6_1
Parsing entity <reset_blk_ramfifo>.
Parsing architecture <xilinx> of entity <reset_blk_ramfifo>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/clk_x_pntrs.vhd" into library fifo_generator_v6_1
Parsing entity <clk_x_pntrs>.
Parsing architecture <xilinx> of entity <clk_x_pntrs>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_status_flags_as.vhd" into library fifo_generator_v6_1
Parsing entity <wr_status_flags_as>.
Parsing architecture <xilinx> of entity <wr_status_flags_as>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_status_flags_ss.vhd" into library fifo_generator_v6_1
Parsing entity <wr_status_flags_ss>.
Parsing architecture <xilinx> of entity <wr_status_flags_ss>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_pf_as.vhd" into library fifo_generator_v6_1
Parsing entity <wr_pf_as>.
Parsing architecture <xilinx> of entity <wr_pf_as>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_pf_ss.vhd" into library fifo_generator_v6_1
Parsing entity <wr_pf_ss>.
Parsing architecture <xilinx> of entity <wr_pf_ss>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_handshaking_flags.vhd" into library fifo_generator_v6_1
Parsing entity <wr_handshaking_flags>.
Parsing architecture <xilinx> of entity <wr_handshaking_flags>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_dc_as.vhd" into library fifo_generator_v6_1
Parsing entity <wr_dc_as>.
Parsing architecture <xilinx> of entity <wr_dc_as>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_dc_fwft_ext_as.vhd" into library fifo_generator_v6_1
Parsing entity <wr_dc_fwft_ext_as>.
Parsing architecture <xilinx> of entity <wr_dc_fwft_ext_as>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_logic.vhd" into library fifo_generator_v6_1
Parsing entity <wr_logic>.
Parsing architecture <xilinx> of entity <wr_logic>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_status_flags_sshft.vhd" into library fifo_generator_v6_1
Parsing entity <wr_status_flags_sshft>.
Parsing architecture <xilinx> of entity <wr_status_flags_sshft>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_status_flags_sshft.vhd" into library fifo_generator_v6_1
Parsing entity <rd_status_flags_sshft>.
Parsing architecture <xilinx> of entity <rd_status_flags_sshft>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_pf_sshft.vhd" into library fifo_generator_v6_1
Parsing entity <wr_pf_sshft>.
Parsing architecture <xilinx> of entity <wr_pf_sshft>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_pe_sshft.vhd" into library fifo_generator_v6_1
Parsing entity <rd_pe_sshft>.
Parsing architecture <xilinx> of entity <rd_pe_sshft>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/logic_sshft.vhd" into library fifo_generator_v6_1
Parsing entity <logic_sshft>.
Parsing architecture <xilinx> of entity <logic_sshft>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_ramfifo.vhd" into library fifo_generator_v6_1
Parsing entity <fifo_generator_ramfifo>.
Parsing architecture <xilinx> of entity <fifo_generator_ramfifo>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_v6_1_comps_builtin.vhd" into library fifo_generator_v6_1
Parsing package <fifo_generator_v6_1_comps_builtin>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/delay.vhd" into library fifo_generator_v6_1
Parsing entity <delay>.
Parsing architecture <xilinx> of entity <delay>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/clk_x_pntrs_builtin.vhd" into library fifo_generator_v6_1
Parsing entity <clk_x_pntrs_builtin>.
Parsing architecture <xilinx> of entity <clk_x_pntrs_builtin>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/bin_cntr.vhd" into library fifo_generator_v6_1
Parsing entity <bin_cntr>.
Parsing architecture <xilinx> of entity <bin_cntr>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/logic_builtin.vhd" into library fifo_generator_v6_1
Parsing entity <logic_builtin>.
Parsing architecture <xilinx> of entity <logic_builtin>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/reset_builtin.vhd" into library fifo_generator_v6_1
Parsing entity <reset_builtin>.
Parsing architecture <xilinx> of entity <reset_builtin>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/builtin_prim.vhd" into library fifo_generator_v6_1
Parsing entity <builtin_prim>.
Parsing architecture <xilinx> of entity <builtin_prim>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/builtin_extdepth.vhd" into library fifo_generator_v6_1
Parsing entity <builtin_extdepth>.
Parsing architecture <xilinx> of entity <builtin_extdepth>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/builtin_top.vhd" into library fifo_generator_v6_1
Parsing entity <builtin_top>.
Parsing architecture <xilinx> of entity <builtin_top>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/builtin_prim_v6.vhd" into library fifo_generator_v6_1
Parsing entity <builtin_prim_v6>.
Parsing architecture <xilinx> of entity <builtin_prim_v6>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/builtin_extdepth_v6.vhd" into library fifo_generator_v6_1
Parsing entity <builtin_extdepth_v6>.
Parsing architecture <xilinx> of entity <builtin_extdepth_v6>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/builtin_top_v6.vhd" into library fifo_generator_v6_1
Parsing entity <builtin_top_v6>.
Parsing architecture <xilinx> of entity <builtin_top_v6>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_v6_1_builtin.vhd" into library fifo_generator_v6_1
Parsing entity <fifo_generator_v6_1_builtin>.
Parsing architecture <xilinx> of entity <fifo_generator_v6_1_builtin>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rgtw.vhd" into library fifo_generator_v6_1
Parsing entity <rgtw>.
Parsing architecture <xilinx> of entity <rgtw>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wgtr.vhd" into library fifo_generator_v6_1
Parsing entity <wgtr>.
Parsing architecture <xilinx> of entity <wgtr>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/input_block_fifo16_patch.vhd" into library fifo_generator_v6_1
Parsing entity <input_block_fifo16_patch>.
Parsing architecture <xilinx> of entity <input_block_fifo16_patch>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/output_block_fifo16_patch.vhd" into library fifo_generator_v6_1
Parsing entity <output_block_fifo16_patch>.
Parsing architecture <xilinx> of entity <output_block_fifo16_patch>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo16_patch_top.vhd" into library fifo_generator_v6_1
Parsing entity <fifo16_patch_top>.
Parsing architecture <xilinx> of entity <fifo16_patch_top>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_v6_1_fifo16_patch.vhd" into library fifo_generator_v6_1
Parsing entity <fifo_generator_v6_1_fifo16_patch>.
Parsing architecture <xilinx> of entity <fifo_generator_v6_1_fifo16_patch>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_v6_1_xst.vhd" into library fifo_generator_v6_1
Parsing entity <fifo_generator_v6_1_xst>.
Parsing architecture <xilinx> of entity <fifo_generator_v6_1_xst>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_async_fifo.vhd" into library work
Parsing entity <generic_async_fifo>.
Parsing architecture <syn> of entity <generic_async_fifo>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/virtex6/generic_sync_fifo.vhd" into library work
Parsing entity <generic_sync_fifo>.
Parsing architecture <syn> of entity <generic_sync_fifo>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd" into library work
Parsing entity <wb_async_bridge>.
Parsing architecture <behavioral> of entity <wb_async_bridge>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_async_bridge/xwb_async_bridge.vhd" into library work
Parsing entity <xwb_async_bridge>.
Parsing architecture <wrapper> of entity <xwb_async_bridge>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd" into library work
Parsing entity <wb_onewire_master>.
Parsing architecture <rtl> of entity <wb_onewire_master>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd" into library work
Parsing entity <xwb_onewire_master>.
Parsing architecture <rtl> of entity <xwb_onewire_master>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd" into library work
Parsing entity <i2c_master_bit_ctrl>.
Parsing architecture <structural> of entity <i2c_master_bit_ctrl>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd" into library work
Parsing entity <i2c_master_byte_ctrl>.
Parsing architecture <structural> of entity <i2c_master_byte_ctrl>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd" into library work
Parsing entity <i2c_master_top>.
Parsing architecture <structural> of entity <i2c_master_top>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" into library work
Parsing entity <wb_i2c_master>.
Parsing architecture <rtl> of entity <wb_i2c_master>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd" into library work
Parsing entity <xwb_i2c_master>.
Parsing architecture <rtl> of entity <xwb_i2c_master>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_bus_fanout/xwb_bus_fanout.vhd" into library work
Parsing entity <xwb_bus_fanout>.
Parsing architecture <rtl> of entity <xwb_bus_fanout>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" into library work
Parsing entity <xwb_dpram>.
Parsing architecture <struct> of entity <xwb_dpram>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" into library work
Parsing entity <wb_gpio_port>.
Parsing architecture <behavioral> of entity <wb_gpio_port>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd" into library work
Parsing entity <xwb_gpio_port>.
Parsing architecture <rtl> of entity <xwb_gpio_port>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd" into library work
Parsing entity <wb_tics>.
Parsing architecture <behaviour> of entity <wb_tics>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_simple_timer/xwb_tics.vhd" into library work
Parsing entity <xwb_tics>.
Parsing architecture <rtl> of entity <xwb_tics>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd" into library work
Parsing entity <uart_async_rx>.
Parsing architecture <behavioral> of entity <uart_async_rx>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd" into library work
Parsing entity <uart_async_tx>.
Parsing architecture <behavioral> of entity <uart_async_tx>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd" into library work
Parsing entity <uart_baud_gen>.
Parsing architecture <behavioral> of entity <uart_baud_gen>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd" into library work
Parsing package <uart_wbgen2_pkg>.
Parsing package body <uart_wbgen2_pkg>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd" into library work
Parsing entity <simple_uart_wb>.
Parsing architecture <syn> of entity <simple_uart_wb>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" into library work
Parsing entity <wb_simple_uart>.
Parsing architecture <syn> of entity <wb_simple_uart>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd" into library work
Parsing entity <xwb_simple_uart>.
Parsing architecture <rtl> of entity <xwb_simple_uart>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_vic/vic_prio_enc.vhd" into library work
Parsing entity <vic_prio_enc>.
Parsing architecture <syn> of entity <vic_prio_enc>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd" into library work
Parsing package <wbgen2_pkg>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd" into library work
Parsing entity <wb_slave_vic>.
Parsing architecture <syn> of entity <wb_slave_vic>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd" into library work
Parsing entity <wb_vic>.
Parsing architecture <syn> of entity <wb_vic>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_vic/xwb_vic.vhd" into library work
Parsing entity <xwb_vic>.
Parsing architecture <wrapper> of entity <xwb_vic>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd" into library work
Parsing entity <wb_spi>.
Parsing architecture <rtl> of entity <wb_spi>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd" into library work
Parsing entity <xwb_spi>.
Parsing architecture <rtl> of entity <xwb_spi>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd" into library work
Parsing entity <sdb_rom>.
Parsing architecture <rtl> of entity <sdb_rom>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd" into library work
Parsing entity <xwb_crossbar>.
Parsing architecture <rtl> of entity <xwb_crossbar>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd" into library work
Parsing entity <xwb_sdb_crossbar>.
Parsing architecture <rtl> of entity <xwb_sdb_crossbar>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" into library work
Parsing entity <xwb_lm32>.
Parsing architecture <rtl> of entity <xwb_lm32>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd" into library work
Parsing entity <wb_slave_adapter>.
Parsing architecture <rtl> of entity <wb_slave_adapter>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd" into library work
Parsing package <xldr_wbgen2_pkg>.
Parsing package body <xldr_wbgen2_pkg>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/wb_xilinx_fpga_loader.vhd" into library work
Parsing entity <wb_xilinx_fpga_loader>.
Parsing architecture <behavioral> of entity <wb_xilinx_fpga_loader>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/xwb_xilinx_fpga_loader.vhd" into library work
Parsing entity <xwb_xilinx_fpga_loader>.
Parsing architecture <rtl> of entity <xwb_xilinx_fpga_loader>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/xloader_wb.vhd" into library work
Parsing entity <xloader_wb>.
Parsing architecture <syn> of entity <xloader_wb>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd" into library work
Parsing entity <xwb_clock_crossing>.
Parsing architecture <rtl> of entity <xwb_clock_crossing>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dma/xwb_dma.vhd" into library work
Parsing entity <xwb_dma>.
Parsing architecture <rtl> of entity <xwb_dma>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd" into library work
Parsing entity <wbgen2_dpssram>.
Parsing architecture <syn> of entity <wbgen2_dpssram>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd" into library work
Parsing entity <wbgen2_eic>.
Parsing architecture <syn> of entity <wbgen2_eic>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd" into library work
Parsing entity <wbgen2_fifo_async>.
Parsing architecture <rtl> of entity <wbgen2_fifo_async>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd" into library work
Parsing entity <wbgen2_fifo_sync>.
Parsing architecture <rtl> of entity <wbgen2_fifo_sync>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_v4_1_defaults.vhd" into library blk_mem_gen_v4_1
Parsing package <blk_mem_gen_v4_1_defaults>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_v4_1_pkg.vhd" into library blk_mem_gen_v4_1
Parsing package <blk_mem_gen_pkg>.
Parsing package body <blk_mem_gen_pkg>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_getinit_pkg.vhd" into library blk_mem_gen_v4_1
Parsing package <blk_mem_gen_getinit_pkg>.
Parsing package body <blk_mem_gen_getinit_pkg>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_min_area_pkg.vhd" into library blk_mem_gen_v4_1
Parsing package <blk_mem_min_area_pkg>.
Parsing package body <blk_mem_min_area_pkg>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_bindec.vhd" into library blk_mem_gen_v4_1
Parsing entity <bindec>.
Parsing architecture <xilinx> of entity <bindec>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_mux.vhd" into library blk_mem_gen_v4_1
Parsing entity <blk_mem_gen_mux>.
Parsing architecture <xilinx> of entity <blk_mem_gen_mux>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s6.vhd" into library blk_mem_gen_v4_1
Parsing entity <blk_mem_gen_prim_wrapper_s6>.
Parsing architecture <xilinx> of entity <blk_mem_gen_prim_wrapper_s6>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s6_init.vhd" into library blk_mem_gen_v4_1
Parsing entity <blk_mem_gen_prim_wrapper_s6_init>.
Parsing architecture <xilinx> of entity <blk_mem_gen_prim_wrapper_s6_init>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3adsp.vhd" into library blk_mem_gen_v4_1
Parsing entity <blk_mem_gen_prim_wrapper_s3adsp>.
Parsing architecture <xilinx> of entity <blk_mem_gen_prim_wrapper_s3adsp>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3adsp_init.vhd" into library blk_mem_gen_v4_1
Parsing entity <blk_mem_gen_prim_wrapper_s3adsp_init>.
Parsing architecture <xilinx> of entity <blk_mem_gen_prim_wrapper_s3adsp_init>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3a.vhd" into library blk_mem_gen_v4_1
Parsing entity <blk_mem_gen_prim_wrapper_s3a>.
Parsing architecture <xilinx> of entity <blk_mem_gen_prim_wrapper_s3a>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3a_init.vhd" into library blk_mem_gen_v4_1
Parsing entity <blk_mem_gen_prim_wrapper_s3a_init>.
Parsing architecture <xilinx> of entity <blk_mem_gen_prim_wrapper_s3a_init>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v6.vhd" into library blk_mem_gen_v4_1
Parsing entity <blk_mem_gen_prim_wrapper_v6>.
Parsing architecture <xilinx> of entity <blk_mem_gen_prim_wrapper_v6>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v6_init.vhd" into library blk_mem_gen_v4_1
Parsing entity <blk_mem_gen_prim_wrapper_v6_init>.
Parsing architecture <xilinx> of entity <blk_mem_gen_prim_wrapper_v6_init>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v5.vhd" into library blk_mem_gen_v4_1
Parsing entity <blk_mem_gen_prim_wrapper_v5>.
Parsing architecture <xilinx> of entity <blk_mem_gen_prim_wrapper_v5>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v5_init.vhd" into library blk_mem_gen_v4_1
Parsing entity <blk_mem_gen_prim_wrapper_v5_init>.
Parsing architecture <xilinx> of entity <blk_mem_gen_prim_wrapper_v5_init>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v4.vhd" into library blk_mem_gen_v4_1
Parsing entity <blk_mem_gen_prim_wrapper_v4>.
Parsing architecture <xilinx> of entity <blk_mem_gen_prim_wrapper_v4>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v4_init.vhd" into library blk_mem_gen_v4_1
Parsing entity <blk_mem_gen_prim_wrapper_v4_init>.
Parsing architecture <xilinx> of entity <blk_mem_gen_prim_wrapper_v4_init>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3.vhd" into library blk_mem_gen_v4_1
Parsing entity <blk_mem_gen_prim_wrapper_s3>.
Parsing architecture <xilinx> of entity <blk_mem_gen_prim_wrapper_s3>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3_init.vhd" into library blk_mem_gen_v4_1
Parsing entity <blk_mem_gen_prim_wrapper_s3_init>.
Parsing architecture <xilinx> of entity <blk_mem_gen_prim_wrapper_s3_init>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_width.vhd" into library blk_mem_gen_v4_1
Parsing entity <blk_mem_gen_prim_width>.
Parsing architecture <xilinx> of entity <blk_mem_gen_prim_width>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_generic_cstr.vhd" into library blk_mem_gen_v4_1
Parsing entity <blk_mem_gen_generic_cstr>.
Parsing architecture <xilinx> of entity <blk_mem_gen_generic_cstr>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_ecc_encoder.vhd" into library blk_mem_gen_v4_1
Parsing entity <blk_mem_gen_ecc_encoder>.
Parsing architecture <xilinx> of entity <blk_mem_gen_ecc_encoder>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_ecc_decoder.vhd" into library blk_mem_gen_v4_1
Parsing entity <blk_mem_gen_ecc_decoder>.
Parsing architecture <xilinx> of entity <blk_mem_gen_ecc_decoder>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_input_block.vhd" into library blk_mem_gen_v4_1
Parsing entity <blk_mem_input_block>.
Parsing architecture <xilinx> of entity <blk_mem_input_block>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_output_block.vhd" into library blk_mem_gen_v4_1
Parsing entity <blk_mem_output_block>.
Parsing architecture <xilinx> of entity <blk_mem_output_block>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_top.vhd" into library blk_mem_gen_v4_1
Parsing entity <blk_mem_gen_top>.
Parsing architecture <xilinx> of entity <blk_mem_gen_top>.
Parsing VHDL file "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_v4_1_xst.vhd" into library blk_mem_gen_v4_1
Parsing entity <blk_mem_gen_v4_1_xst>.
Parsing architecture <xilinx> of entity <blk_mem_gen_v4_1_xst>.

=========================================================================
*                            HDL Elaboration                            *
=========================================================================
WARNING:HDLCompiler:746 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/genram_pkg.vhd" Line 50: Range is empty (null range)

Elaborating entity <dbe_bpm_simple_top> (architecture <rtl>) from library <work>.
WARNING:HDLCompiler:871 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_simple/dbe_bpm_simple_top.vhd" Line 157: Using initial value ("UUUU") for wbs_src_i since it is never assigned

Elaborating entity <clk_gen> (architecture <syn>) from library <work>.

Elaborating entity <sys_pll> (architecture <syn>) with generics from library <work>.

Elaborating entity <gc_reset> (architecture <rtl>) with generics from library <work>.

Elaborating entity <gc_sync_ffs> (architecture <behavioral>) with generics from library <work>.

Elaborating entity <gc_extend_pulse> (architecture <rtl>) with generics from library <work>.
WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_simple/dbe_bpm_simple_top.vhd" Line 376: Assignment to clk_adc_rstn ignored, since the identifier is never used

Elaborating entity <xwb_sdb_crossbar> (architecture <rtl>) with generics from library <work>.
Warning: "Wishbone slave device #1 (WB4-BlockRAM) has an address range that is not a power of 2 minus one (0x15fff). This is not supported by the crossbar."
Warning: "Wishbone slave device #0 (WB4-BlockRAM) has an address range that is not a power of 2 minus one (0x15fff). This is not supported by the crossbar."

Elaborating entity <sdb_rom> (architecture <rtl>) with generics from library <work>.

Elaborating entity <xwb_crossbar> (architecture <rtl>) with generics from library <work>.
Note: "Mapping slave #0[0x0/0xfffe0000]"
Note: "Mapping slave #1[0x10000000/0xfffe0000]"
Note: "Mapping slave #2[0x20000400/0xffffffe0]"
Note: "Mapping slave #3[0x20000500/0xffffff00]"
Note: "Mapping slave #4[0x20000600/0xffffff00]"
Note: "Mapping slave #5[0x20000700/0xffffff00]"
Note: "Mapping slave #6[0x20000800/0xffffff00]"
Note: "Mapping slave #7[0x20000000/0xfffffe00]"

Elaborating entity <xwb_lm32> (architecture <rtl>) with generics from library <work>.
WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" Line 31: Comparison between arrays of unequal length always returns FALSE.
WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" Line 32: Comparison between arrays of unequal length always returns FALSE.
WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" Line 33: Comparison between arrays of unequal length always returns FALSE.
WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" Line 34: Comparison between arrays of unequal length always returns FALSE.
WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" Line 20: Comparison between arrays of unequal length always returns FALSE.
WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" Line 21: Comparison between arrays of unequal length always returns FALSE.
WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" Line 22: Comparison between arrays of unequal length always returns FALSE.
WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" Line 23: Comparison between arrays of unequal length always returns FALSE.
WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" Line 326: Comparison between arrays of unequal length always returns FALSE.
WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" Line 367: Comparison between arrays of unequal length always returns FALSE.
WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" Line 408: Comparison between arrays of unequal length always returns FALSE.
WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" Line 449: Comparison between arrays of unequal length always returns FALSE.
Going to verilog side to elaborate module lm32_top_medium_icache_debug

Elaborating module <lm32_top_medium_icache_debug>.

Elaborating module <lm32_cpu_medium_icache_debug>.

Elaborating module <lm32_instruction_unit_medium_icache_debug(associativity=1,sets=256,bytes_per_line=16,base_address=32'b0,limit=32'b01111111111111111111111111111111)>.

Elaborating module <lm32_icache_medium_icache_debug(associativity=1,sets=256,bytes_per_line=16,base_address=32'b0,limit=32'b01111111111111111111111111111111)>.

Elaborating module <lm32_ram(data_width=32,address_width=32'sb01010)>.

Elaborating module <lm32_ram(data_width=32'sb010100,address_width=32'sb01000)>.
WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" Line 49056: Result of 30-bit expression is truncated to fit in 29-bit target.
WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" Line 41108: Assignment to pc_w ignored, since the identifier is never used

Elaborating module <lm32_decoder_medium_icache_debug>.
WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" Line 45380: Assignment to op_user ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" Line 45414: Assignment to multiply ignored, since the identifier is never used
WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" Line 45624: Result of 32-bit expression is truncated to fit in 29-bit target.

Elaborating module <lm32_load_store_unit_medium_icache_debug(associativity=1,sets=512,bytes_per_line=16,base_address=0,limit=0)>.
"/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" Line 44387. $display Data bus error. Address: 0
"/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" Line 44535. $display Warning: Non-aligned halfword access. Address: 0x0 Time:  $time .
"/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" Line 44537. $display Warning: Non-aligned word access. Address: 0x0 Time:  $time .

Elaborating module <lm32_adder>.

Elaborating module <lm32_addsub>.

Elaborating module <lm32_logic_op>.

Elaborating module <lm32_shifter>.
WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v" Line 128: Result of 64-bit expression is truncated to fit in 32-bit target.

Elaborating module <lm32_multiplier>.

Elaborating module <lm32_interrupt_medium_icache_debug>.
WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" Line 50707: Result of 3-bit expression is truncated to fit in 1-bit target.
WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" Line 50707: Assignment to ie_csr_read_data ignored, since the identifier is never used
WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" Line 50718: Result of 32-bit expression is truncated to fit in 1-bit target.
WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" Line 50718: Assignment to ip_csr_read_data ignored, since the identifier is never used
WARNING:HDLCompiler:413 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" Line 50719: Result of 32-bit expression is truncated to fit in 1-bit target.
WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" Line 50719: Assignment to im_csr_read_data ignored, since the identifier is never used

Elaborating module <lm32_jtag_medium_icache_debug>.

Elaborating module <lm32_debug_medium_icache_debug(breakpoints=0,watchpoints=32'b0100)>.
WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" Line 47797: Net <wp_match_n[4]> does not have a driver.

Elaborating module <lm32_dp_ram(addr_depth=32'sb0100000,addr_width=5,data_width=32)>.
WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" Line 42753: Assignment to x_result_sel_logic_x ignored, since the identifier is never used

Elaborating module <jtag_cores>.

Elaborating module <jtag_tap>.
WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" Line 39170: Assignment to jrstn ignored, since the identifier is never used
Back to vhdl to continue elaboration
WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" Line 531: Comparison between arrays of unequal length always returns FALSE.
WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" Line 572: Comparison between arrays of unequal length always returns FALSE.

Elaborating entity <xwb_dma> (architecture <rtl>) with generics from library <work>.

Elaborating entity <xwb_dpram> (architecture <struct>) with generics from library <work>.

Elaborating entity <wb_slave_adapter> (architecture <rtl>) with generics from library <work>.

Elaborating entity <generic_dpram> (architecture <syn>) with generics from library <work>.

Elaborating entity <generic_dpram_sameclock> (architecture <syn>) with generics from library <work>.
WARNING:HDLCompiler:321 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd" Line 150: Comparison between arrays of unequal length always returns FALSE.
WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" Line 72: Net <slave1_out_int> does not have a driver.
WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" Line 74: Net <slave2_out_int> does not have a driver.

Elaborating entity <xwb_fmc150> (architecture <rtl>) with generics from library <work>.

Elaborating entity <wb_fmc150> (architecture <rtl>) with generics from library <work>.

Elaborating entity <fmc150_testbench> (architecture <rtl>) with generics from library <work>.

Elaborating entity <fmc150_adc_if> (architecture <rtl>) with generics from library <work>.

Elaborating entity <strobe_lvds> (architecture <rtl>) with generics from library <work>.

Elaborating entity <adc_channel_lvds_ddr> (architecture <rtl>) with generics from library <work>.

Elaborating entity <fmc150_dac_if> (architecture <rtl>) from library <work>.

Elaborating entity <fmc150_spi_ctrl> (architecture <fmc150_spi_ctrl_syn>) with generics from library <work>.

Elaborating entity <cdce72010_ctrl> (architecture <cdce72010_ctrl_syn>) with generics from library <work>.

Elaborating entity <fmc150_stellar_cmd> (architecture <arch_fmc150_stellar_cmd>) with generics from library <work>.

Elaborating entity <pulse2pulse> (architecture <syn>) from library <work>.
INFO:HDLCompiler:679 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/fmc150/cdce72010_ctrl.vhd" Line 451. Case statement is complete. others clause is never selected
WARNING:HDLCompiler:89 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/fmc150/cdce72010_ctrl.vhd" Line 114: <cdce72010_init_mem_int> remains a black-box since it has no binding entity.
WARNING:HDLCompiler:89 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/fmc150/cdce72010_ctrl.vhd" Line 122: <cdce72010_init_mem_ext> remains a black-box since it has no binding entity.

Elaborating entity <ads62p49_ctrl> (architecture <ads62p49_ctrl_syn>) with generics from library <work>.
INFO:HDLCompiler:679 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/fmc150/ads62p49_ctrl.vhd" Line 393. Case statement is complete. others clause is never selected
WARNING:HDLCompiler:89 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/fmc150/ads62p49_ctrl.vhd" Line 108: <ads62p49_init_mem> remains a black-box since it has no binding entity.

Elaborating entity <dac3283_ctrl> (architecture <dac3283_ctrl_syn>) with generics from library <work>.
INFO:HDLCompiler:679 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/fmc150/dac3283_ctrl.vhd" Line 383. Case statement is complete. others clause is never selected
WARNING:HDLCompiler:89 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/fmc150/dac3283_ctrl.vhd" Line 106: <dac3283_init_mem> remains a black-box since it has no binding entity.

Elaborating entity <amc7823_ctrl> (architecture <amc7823_ctrl_syn>) with generics from library <work>.
INFO:HDLCompiler:679 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/fmc150/amc7823_ctrl.vhd" Line 398. Case statement is complete. others clause is never selected
WARNING:HDLCompiler:89 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/fmc150/amc7823_ctrl.vhd" Line 109: <amc7823_init_mem> remains a black-box since it has no binding entity.
WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/fmc150/fmc150_testbench.vhd" Line 121: Net <dac_din_c[15]> does not have a driver.
WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/fmc150/fmc150_testbench.vhd" Line 122: Net <dac_din_d[15]> does not have a driver.

Elaborating entity <wb_slave_adapter> (architecture <rtl>) with generics from library <work>.
WARNING:HDLCompiler:92 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd" Line 177: fsm_state should be on the sensitivity list of the process

Elaborating entity <wb_fmc150_port> (architecture <syn>) from library <work>.
WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/wb_fmc150_port.vhd" Line 67: Assignment to bwsel_reg ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/wb_fmc150_port.vhd" Line 68: Assignment to rd_int ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/wb_fmc150_port.vhd" Line 69: Assignment to wr_int ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/wb_fmc150_port.vhd" Line 70: Assignment to allones ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/wb_fmc150_port.vhd" Line 71: Assignment to allzeros ignored, since the identifier is never used
INFO:HDLCompiler:679 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/wb_fmc150_port.vhd" Line 324. Case statement is complete. others clause is never selected

Elaborating entity <reset_synch> (architecture <rtl>) from library <work>.

Elaborating entity <xwb_stream_source> (architecture <rtl>) from library <work>.

Elaborating entity <generic_shiftreg_fifo> (architecture <rtl>) with generics from library <work>.
WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_stream/xwb_stream_source.vhd" Line 77: Net <err_status_is_hp> does not have a driver.
WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/wb_fmc150.vhd" Line 190: Net <wb_out_err> does not have a driver.

Elaborating entity <xwb_simple_uart> (architecture <rtl>) with generics from library <work>.

Elaborating entity <wb_simple_uart> (architecture <syn>) with generics from library <work>.

Elaborating entity <wb_slave_adapter> (architecture <rtl>) with generics from library <work>.
WARNING:HDLCompiler:92 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd" Line 186: fsm_state should be on the sensitivity list of the process
WARNING:HDLCompiler:92 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd" Line 188: stored_we should be on the sensitivity list of the process
WARNING:HDLCompiler:92 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd" Line 194: fsm_state should be on the sensitivity list of the process

Elaborating entity <simple_uart_wb> (architecture <syn>) from library <work>.
WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd" Line 56: Assignment to bwsel_reg ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd" Line 58: Assignment to rd_int ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd" Line 59: Assignment to wr_int ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd" Line 60: Assignment to allones ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd" Line 61: Assignment to allzeros ignored, since the identifier is never used

Elaborating entity <uart_baud_gen> (architecture <behavioral>) with generics from library <work>.

Elaborating entity <uart_async_tx> (architecture <behavioral>) from library <work>.
INFO:HDLCompiler:679 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd" Line 139. Case statement is complete. others clause is never selected

Elaborating entity <uart_async_rx> (architecture <behavioral>) from library <work>.
WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" Line 130: Net <wb_out_err> does not have a driver.
WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" Line 132: Net <regs_in_host_tdr_rdy_i> does not have a driver.

Elaborating entity <xwb_gpio_port> (architecture <rtl>) with generics from library <work>.

Elaborating entity <wb_gpio_port> (architecture <behavioral>) with generics from library <work>.

Elaborating entity <wb_slave_adapter> (architecture <rtl>) with generics from library <work>.
INFO:HDLCompiler:679 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" Line 146. Case statement is complete. others clause is never selected
WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" Line 78: Net <gpio_in_synced[31]> does not have a driver.
WARNING:HDLCompiler:89 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_simple/dbe_bpm_simple_top.vhd" Line 266: <chipscope_icon_2_port> remains a black-box since it has no binding entity.
WARNING:HDLCompiler:89 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_simple/dbe_bpm_simple_top.vhd" Line 274: <chipscope_ila> remains a black-box since it has no binding entity.
WARNING:HDLCompiler:634 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_simple/dbe_bpm_simple_top.vhd" Line 232: Net <TRIG_ILA1_3[31]> does not have a driver.
WARNING:Xst:2972 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_simple/dbe_bpm_simple_top.vhd" line 336. All outputs of instance <cmp_button_adc_ffs> of block <gc_sync_ffs> are unconnected in block <dbe_bpm_simple_top>. Underlying logic will be removed.
WARNING:Xst:2972 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_simple/dbe_bpm_simple_top.vhd" line 359. All outputs of instance <cmp_button_adc_rst> of block <gc_extend_pulse> are unconnected in block <dbe_bpm_simple_top>. Underlying logic will be removed.

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <dbe_bpm_simple_top>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_simple/dbe_bpm_simple_top.vhd".
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_simple/dbe_bpm_simple_top.vhd" line 327: Output port <synced_o> of the instance <cmp_button_sys_ffs> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_simple/dbe_bpm_simple_top.vhd" line 327: Output port <npulse_o> of the instance <cmp_button_sys_ffs> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_simple/dbe_bpm_simple_top.vhd" line 336: Output port <synced_o> of the instance <cmp_button_adc_ffs> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_simple/dbe_bpm_simple_top.vhd" line 336: Output port <npulse_o> of the instance <cmp_button_adc_ffs> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_simple/dbe_bpm_simple_top.vhd" line 359: Output port <extended_o> of the instance <cmp_button_adc_rst> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_simple/dbe_bpm_simple_top.vhd" line 459: Output port <adc_dout_o> of the instance <cmp_xwb_fmc150> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_simple/dbe_bpm_simple_top.vhd" line 557: Output port <desc_o> of the instance <cmp_uart> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_simple/dbe_bpm_simple_top.vhd" line 572: Output port <desc_o> of the instance <cmp_leds> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_simple/dbe_bpm_simple_top.vhd" line 572: Output port <gpio_oen_o> of the instance <cmp_leds> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_simple/dbe_bpm_simple_top.vhd" line 660: Output port <desc_o> of the instance <cmp_buttons> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_simple/dbe_bpm_simple_top.vhd" line 660: Output port <gpio_out_o> of the instance <cmp_buttons> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_simple/dbe_bpm_simple_top.vhd" line 660: Output port <gpio_oen_o> of the instance <cmp_buttons> is unconnected or connected to loadless signal.
WARNING:Xst:653 - Signal <TRIG_ILA1_3> is used but never assigned. This sourceless signal will be automatically connected to value GND.
    Summary:
	no macro.
Unit <dbe_bpm_simple_top> synthesized.

Synthesizing Unit <clk_gen>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_simple/clk_gen.vhd".
    Summary:
	no macro.
Unit <clk_gen> synthesized.

Synthesizing Unit <sys_pll>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_simple/sys_pll.vhd".
        g_clkin_period = 5.0
        g_clkbout_mult_f = 5.0
        g_clk0_divide_f = 10.0
        g_clk1_divide = 5
    Summary:
	no macro.
Unit <sys_pll> synthesized.

Synthesizing Unit <gc_reset>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_reset.vhd".
        g_clocks = 2
        g_logdelay = 10
        g_syncdepth = 3
    Found 10-bit register for signal <locked_count>.
    Found 3-bit register for signal <shifters<1>>.
    Found 3-bit register for signal <shifters<0>>.
    Found 1-bit register for signal <master_rstn>.
    Found 10-bit adder for signal <locked_count[9]_GND_45_o_add_1_OUT> created at line 1241.
    Summary:
	inferred   1 Adder/Subtractor(s).
	inferred  17 D-type flip-flop(s).
Unit <gc_reset> synthesized.

Synthesizing Unit <gc_sync_ffs>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_sync_ffs.vhd".
        g_sync_edge = "positive"
    Register <synced_o> equivalent to <sync2> has been removed
    Found 1-bit register for signal <sync1>.
    Found 1-bit register for signal <sync2>.
    Found 1-bit register for signal <npulse_o>.
    Found 1-bit register for signal <ppulse_o>.
    Found 1-bit register for signal <sync0>.
    Summary:
	inferred   5 D-type flip-flop(s).
Unit <gc_sync_ffs> synthesized.

Synthesizing Unit <gc_extend_pulse>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/common/gc_extend_pulse.vhd".
        g_width = 255
    Found 32-bit register for signal <cntr>.
    Found 1-bit register for signal <extended_int>.
    Found 32-bit subtractor for signal <GND_47_o_GND_47_o_sub_2_OUT<31:0>> created at line 1308.
    Summary:
	inferred   1 Adder/Subtractor(s).
	inferred  33 D-type flip-flop(s).
Unit <gc_extend_pulse> synthesized.

Synthesizing Unit <xwb_sdb_crossbar>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd".
        g_num_masters = 4
        g_num_slaves = 7
        g_registered = true
        g_wraparound = false
        g_layout =
("00000000000000000000000100000000000000000000000000000000000001110000000000000000000000000000000000100000000000000000100000000000000000000000000000000000000000000010000000000000000010001111111100000000000000000000000000000000000000000000000000000110010100010011010110101010011010111001010100000000000000000000000000000001001000000001001000000011000001010100011101010011010010010101111101000111010100000100100101001111010111110011001100110010001000000010000000100000001000000010000000100000001000000010000000000001","000000000000000000000001000000000000000000000000000000000000011100000000000000000000000000000000001000000000000000000111000000000000000000000000000000000000000000100000000000000000011111111111000000000000000000000000000000000000000000000000000001100101000100110101101010100110101110010101000000000000000000000000000000010010000000010010000000110000010101000111010100110100100101011111010001110101000001001001010011110101111100110011001100100010000000100000001000000010000000100000001000000010000000100000000
00001","00000000000000000000000100000000000000000000000000000000000000010000000000000000000000000000000000100000000000000000011000000000000000000000000000000000000000000010000000000000000001101111111100000000000000000000000000000000000000000000000011001110010000101000101001010111000110011010111000000000000000000000000000000001001000000001001000010000000100010100001101000101010100100100111001011111010100110100100101001101010100000100110001000101010111110101010101000001010100100101010000100000001000000010000000000001","000000000000000000000001000000000000000000000000000000000000011100000000000000000000000000000000001000000000000000000101000000000000000000000000000000000000000000100000000000000000010111111111000100000000000000000000000000000000000000000000000100100001010111111000110000010101000011000001000000000000000000000000000000010010000000010010000100000001000001001100010011100100110001010011010111110100011001001101010000110011000100110101001100000010000000100000001000000010000000100000001000000010000000100
00000000001","00000000000000000000000100000000000000000000000000000000000001110000000000000000000000000000000000100000000000000000010000000000000000000000000000000000000000000010000000000000000001000001111100000000000000000000000000000000000000000000000000000110010100011100101010111010101110100101011000000000000000000000000000000001001000000001001000000101000110000101011101000010001101000010110101010011011101000111001001100101011000010110110101101001011011100110011100101101010001000100110101000001010111110011000000000001","000000000000000100000001000000000000000000000000000000000000011100000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000010000000000010101111111111111000000000000000000000000000000000000000000000000110011100100001001100110110011111110101101010010000000000000000000000000000000010010000000010010000000110000010101010111010000100011010000101101010000100110110001101111011000110110101101010010010000010100110100100000001000000010000000100000001000000010000
00010000000000001","00000000000000010000000100000000000000000000000000000000000001110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001010111111111111100000000000000000000000000000000000000000000000011001110010000100110011011001111111010110101001000000000000000000000000000000001001000000001001000000011000001010101011101000010001101000010110101000010011011000110111101100011011010110101001001000001010011010010000000100000001000000010000000100000001000000010000000000001")
        g_sdb_addr = "00100000000000000000000000000000"
    Summary:
	no macro.
Unit <xwb_sdb_crossbar> synthesized.

Synthesizing Unit <sdb_rom>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd".
        g_layout =
("00000000000000000000000100000000000000000000000000000000000001110000000000000000000000000000000000100000000000000000100000000000000000000000000000000000000000000010000000000000000010001111111100000000000000000000000000000000000000000000000000000110010100010011010110101010011010111001010100000000000000000000000000000001001000000001001000000011000001010100011101010011010010010101111101000111010100000100100101001111010111110011001100110010001000000010000000100000001000000010000000100000001000000010000000000001","000000000000000000000001000000000000000000000000000000000000011100000000000000000000000000000000001000000000000000000111000000000000000000000000000000000000000000100000000000000000011111111111000000000000000000000000000000000000000000000000000001100101000100110101101010100110101110010101000000000000000000000000000000010010000000010010000000110000010101000111010100110100100101011111010001110101000001001001010011110101111100110011001100100010000000100000001000000010000000100000001000000010000000100000000
00001","00000000000000000000000100000000000000000000000000000000000000010000000000000000000000000000000000100000000000000000011000000000000000000000000000000000000000000010000000000000000001101111111100000000000000000000000000000000000000000000000011001110010000101000101001010111000110011010111000000000000000000000000000000001001000000001001000010000000100010100001101000101010100100100111001011111010100110100100101001101010100000100110001000101010111110101010101000001010100100101010000100000001000000010000000000001","000000000000000000000001000000000000000000000000000000000000011100000000000000000000000000000000001000000000000000000101000000000000000000000000000000000000000000100000000000000000010111111111000100000000000000000000000000000000000000000000000100100001010111111000110000010101000011000001000000000000000000000000000000010010000000010010000100000001000001001100010011100100110001010011010111110100011001001101010000110011000100110101001100000010000000100000001000000010000000100000001000000010000000100
00000000001","00000000000000000000000100000000000000000000000000000000000001110000000000000000000000000000000000100000000000000000010000000000000000000000000000000000000000000010000000000000000001000001111100000000000000000000000000000000000000000000000000000110010100011100101010111010101110100101011000000000000000000000000000000001001000000001001000000101000110000101011101000010001101000010110101010011011101000111001001100101011000010110110101101001011011100110011100101101010001000100110101000001010111110011000000000001","000000000000000100000001000000000000000000000000000000000000011100000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000010000000000010101111111111111000000000000000000000000000000000000000000000000110011100100001001100110110011111110101101010010000000000000000000000000000000010010000000010010000000110000010101010111010000100011010000101101010000100110110001101111011000110110101101010010010000010100110100100000001000000010000000100000001000000010000
00010000000000001","00000000000000010000000100000000000000000000000000000000000001110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001010111111111111100000000000000000000000000000000000000000000000011001110010000100110011011001111111010110101001000000000000000000000000000000001001000000001001000000011000001010101011101000010001101000010110101000010011011000110111101100011011010110101001001000001010011010010000000100000001000000010000000100000001000000010000000000001")
        g_bus_end = "0000000000000000000000000000000011111111111111111111111111111111"
WARNING:Xst:647 - Input <slave_i_adr<31:9>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <slave_i_adr<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <slave_i_sel<3:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <slave_i_dat<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <slave_i_we> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:2999 - Signal 'rom', unconnected in block 'sdb_rom', is tied to its initial value.
    Found 128x32-bit single-port Read Only RAM <Mram_rom> for signal <rom>.
    Found 1-bit register for signal <slave_o_ack>.
    Found 7-bit register for signal <adr_reg>.
    Summary:
	inferred   1 RAM(s).
	inferred   8 D-type flip-flop(s).
Unit <sdb_rom> synthesized.

Synthesizing Unit <xwb_crossbar>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd".
        g_num_masters = 4
        g_num_slaves = 8
        g_registered = true
        g_address = ("00100000000000000000000000000000","00100000000000000000100000000000","00100000000000000000011100000000","00100000000000000000011000000000","00100000000000000000010100000000","00100000000000000000010000000000","00010000000000000000000000000000","00000000000000000000000000000000")
        g_mask = ("11111111111111111111111000000000","11111111111111111111111100000000","11111111111111111111111100000000","11111111111111111111111100000000","11111111111111111111111100000000","11111111111111111111111111100000","11111111111111100000000000000000","11111111111111100000000000000000")
WARNING:Xst:647 - Input <master_i[7]_int> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <master_i[6]_int> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <master_i[5]_int> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <master_i[4]_int> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <master_i[3]_int> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <master_i[2]_int> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <master_i[1]_int> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <master_i[0]_int> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 9-bit register for signal <matrix_old<3>>.
    Found 9-bit register for signal <matrix_old<2>>.
    Found 9-bit register for signal <matrix_old<1>>.
    Found 9-bit register for signal <matrix_old<0>>.
    Found 1-bit register for signal <virtual_ERR>.
    Summary:
	inferred  37 D-type flip-flop(s).
	inferred  36 Multiplexer(s).
Unit <xwb_crossbar> synthesized.

Synthesizing Unit <xwb_lm32>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd".
        g_profile = "medium_icache_debug"
WARNING:Xst:647 - Input <dwb_i_int> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <iwb_i_int> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" line 491: Output port <I_BTE_O> of the instance <gen_profile_medium_icache_debug.U_Wrapped_LM32> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" line 491: Output port <D_CTI_O> of the instance <gen_profile_medium_icache_debug.U_Wrapped_LM32> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" line 491: Output port <D_BTE_O> of the instance <gen_profile_medium_icache_debug.U_Wrapped_LM32> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" line 491: Output port <I_STB_O> of the instance <gen_profile_medium_icache_debug.U_Wrapped_LM32> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" line 491: Output port <I_LOCK_O> of the instance <gen_profile_medium_icache_debug.U_Wrapped_LM32> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" line 491: Output port <D_STB_O> of the instance <gen_profile_medium_icache_debug.U_Wrapped_LM32> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" line 491: Output port <D_LOCK_O> of the instance <gen_profile_medium_icache_debug.U_Wrapped_LM32> is unconnected or connected to loadless signal.
    Found 3-bit register for signal <inst_remaining>.
    Found 32-bit register for signal <inst_addr_reg>.
    Found 1-bit register for signal <data_was_busy>.
    Found 1-bit register for signal <data_remaining>.
    Found 32-bit register for signal <data_addr_reg>.
    Found 1-bit register for signal <inst_was_busy>.
    Found 2-bit subtractor for signal <n0267> created at line 688.
    Found 32-bit adder for signal <inst_addr_reg[31]_GND_51_o_add_9_OUT> created at line 1241.
    Found 32-bit adder for signal <data_addr_reg[31]_GND_51_o_add_20_OUT> created at line 1241.
    Found 3-bit subtractor for signal <GND_51_o_GND_51_o_sub_11_OUT<2:0>> created at line 650.
    Summary:
	inferred   4 Adder/Subtractor(s).
	inferred  70 D-type flip-flop(s).
	inferred  74 Multiplexer(s).
Unit <xwb_lm32> synthesized.

Synthesizing Unit <lm32_top_medium_icache_debug>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v".
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" line 39161: Output port <jrstn> of the instance <jtag_cores> is unconnected or connected to loadless signal.
    Summary:
	no macro.
Unit <lm32_top_medium_icache_debug> synthesized.

Synthesizing Unit <lm32_cpu_medium_icache_debug>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v".
        eba_reset = 32'b00000000000000000000000000000000
        deba_reset = 32'b00010000000000000000000000000000
        icache_associativity = 1
        icache_sets = 256
        icache_bytes_per_line = 16
        icache_base_address = 32'b00000000000000000000000000000000
        icache_limit = 32'b01111111111111111111111111111111
        dcache_associativity = 1
        dcache_sets = 512
        dcache_bytes_per_line = 16
        dcache_base_address = 0
        dcache_limit = 0
        watchpoints = 32'b00000000000000000000000000000100
        breakpoints = 0
        interrupts = 32
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" line 41044: Output port <pc_w> of the instance <instruction_unit> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" line 41154: Output port <x_result_sel_logic> of the instance <decoder> is unconnected or connected to loadless signal.
    Found 1-bit register for signal <regfile_raw_1>.
    Found 32-bit register for signal <w_result_d>.
    Found 23-bit register for signal <eba>.
    Found 23-bit register for signal <deba>.
    Found 1-bit register for signal <valid_f>.
    Found 1-bit register for signal <valid_d>.
    Found 1-bit register for signal <valid_x>.
    Found 1-bit register for signal <valid_m>.
    Found 1-bit register for signal <valid_w>.
    Found 32-bit register for signal <operand_0_x>.
    Found 32-bit register for signal <operand_1_x>.
    Found 32-bit register for signal <store_operand_x>.
    Found 29-bit register for signal <branch_target_x>.
    Found 1-bit register for signal <x_result_sel_csr_x>.
    Found 1-bit register for signal <x_result_sel_sext_x>.
    Found 1-bit register for signal <x_result_sel_add_x>.
    Found 1-bit register for signal <m_result_sel_compare_x>.
    Found 1-bit register for signal <m_result_sel_shift_x>.
    Found 1-bit register for signal <w_result_sel_load_x>.
    Found 1-bit register for signal <w_result_sel_mul_x>.
    Found 1-bit register for signal <x_bypass_enable_x>.
    Found 1-bit register for signal <m_bypass_enable_x>.
    Found 1-bit register for signal <write_enable_x>.
    Found 5-bit register for signal <write_idx_x>.
    Found 5-bit register for signal <csr_x>.
    Found 1-bit register for signal <load_x>.
    Found 1-bit register for signal <store_x>.
    Found 2-bit register for signal <size_x>.
    Found 1-bit register for signal <sign_extend_x>.
    Found 1-bit register for signal <adder_op_x>.
    Found 1-bit register for signal <adder_op_x_n>.
    Found 4-bit register for signal <logic_op_x>.
    Found 1-bit register for signal <direction_x>.
    Found 1-bit register for signal <branch_x>.
    Found 1-bit register for signal <branch_predict_x>.
    Found 1-bit register for signal <branch_predict_taken_x>.
    Found 3-bit register for signal <condition_x>.
    Found 1-bit register for signal <break_x>.
    Found 1-bit register for signal <system_call_exception>.
    Found 1-bit register for signal <eret_x>.
    Found 1-bit register for signal <bret_x>.
    Found 1-bit register for signal <csr_write_enable_x>.
    Found 32-bit register for signal <operand_m>.
    Found 29-bit register for signal <branch_target_m>.
    Found 1-bit register for signal <m_result_sel_compare_m>.
    Found 1-bit register for signal <m_result_sel_shift_m>.
    Found 1-bit register for signal <w_result_sel_load_m>.
    Found 1-bit register for signal <w_result_sel_mul_m>.
    Found 1-bit register for signal <m_bypass_enable_m>.
    Found 1-bit register for signal <branch_m>.
    Found 1-bit register for signal <branch_predict_m>.
    Found 1-bit register for signal <branch_predict_taken_m>.
    Found 1-bit register for signal <exception_m>.
    Found 1-bit register for signal <load_m>.
    Found 1-bit register for signal <store_m>.
    Found 1-bit register for signal <write_enable_m>.
    Found 5-bit register for signal <write_idx_m>.
    Found 1-bit register for signal <condition_met_m>.
    Found 1-bit register for signal <debug_exception_m>.
    Found 1-bit register for signal <non_debug_exception_m>.
    Found 32-bit register for signal <operand_w>.
    Found 1-bit register for signal <w_result_sel_load_w>.
    Found 1-bit register for signal <w_result_sel_mul_w>.
    Found 5-bit register for signal <write_idx_w>.
    Found 1-bit register for signal <write_enable_w>.
    Found 1-bit register for signal <debug_exception_w>.
    Found 1-bit register for signal <non_debug_exception_w>.
    Found 1-bit register for signal <use_buf>.
    Found 32-bit register for signal <reg_data_buf_0>.
    Found 32-bit register for signal <reg_data_buf_1>.
    Found 1-bit register for signal <regfile_raw_0>.
    Found 29-bit adder for signal <branch_target_d> created at line 41841.
    Found 32-bit 3-to-1 multiplexer for signal <d_result_1> created at line 41852.
    Found 1-bit 8-to-1 multiplexer for signal <condition_met_x> created at line 41889.
    Found 5-bit comparator equal for signal <write_idx_w[4]_instruction_f[25]_equal_1_o> created at line 41592
    Found 5-bit comparator equal for signal <write_idx_w[4]_instruction_f[20]_equal_2_o> created at line 41598
    Found 5-bit comparator equal for signal <write_idx_x[4]_read_idx_0_d[4]_equal_11_o> created at line 41779
    Found 5-bit comparator equal for signal <write_idx_m[4]_read_idx_0_d[4]_equal_13_o> created at line 41780
    Found 5-bit comparator equal for signal <write_idx_w[4]_read_idx_0_d[4]_equal_15_o> created at line 41781
    Found 5-bit comparator equal for signal <write_idx_x[4]_read_idx_1_d[4]_equal_17_o> created at line 41782
    Found 5-bit comparator equal for signal <write_idx_m[4]_read_idx_1_d[4]_equal_19_o> created at line 41783
    Found 5-bit comparator equal for signal <write_idx_w[4]_read_idx_1_d[4]_equal_21_o> created at line 41784
    Found 32-bit comparator equal for signal <cmp_zero> created at line 41883
    Found 1-bit comparator equal for signal <cmp_negative_cmp_overflow_equal_55_o> created at line 41896
    Summary:
	inferred   1 Adder/Subtractor(s).
	inferred 441 D-type flip-flop(s).
	inferred  10 Comparator(s).
	inferred  74 Multiplexer(s).
Unit <lm32_cpu_medium_icache_debug> synthesized.

Synthesizing Unit <lm32_instruction_unit_medium_icache_debug>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v".
        associativity = 1
        sets = 256
        bytes_per_line = 16
        base_address = 32'b00000000000000000000000000000000
        limit = 32'b01111111111111111111111111111111
WARNING:Xst:647 - Input <i_rty_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 29-bit register for signal <pc_d>.
    Found 29-bit register for signal <pc_x>.
    Found 29-bit register for signal <pc_m>.
    Found 29-bit register for signal <pc_w>.
    Found 29-bit register for signal <restart_address>.
    Found 1-bit register for signal <i_cyc_o>.
    Found 1-bit register for signal <i_stb_o>.
    Found 32-bit register for signal <i_adr_o>.
    Found 3-bit register for signal <i_cti_o>.
    Found 1-bit register for signal <i_lock_o>.
    Found 32-bit register for signal <icache_refill_data>.
    Found 1-bit register for signal <icache_refill_ready>.
    Found 1-bit register for signal <i_we_o>.
    Found 4-bit register for signal <i_sel_o>.
    Found 1-bit register for signal <jtag_access>.
    Found 32-bit register for signal <i_dat_o>.
    Found 32-bit register for signal <instruction_d>.
    Found 29-bit register for signal <pc_f>.
    Found 29-bit adder for signal <pc_f[30]_GND_55_o_add_9_OUT> created at line 48969.
    Found 2-bit adder for signal <i_adr_o[3]_GND_55_o_add_58_OUT> created at line 49199.
    Found 8-bit 4-to-1 multiplexer for signal <jtag_read_data> created at line 49131.
    Summary:
	inferred   2 Adder/Subtractor(s).
	inferred 314 D-type flip-flop(s).
	inferred  17 Multiplexer(s).
Unit <lm32_instruction_unit_medium_icache_debug> synthesized.

Synthesizing Unit <lm32_icache_medium_icache_debug>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v".
        associativity = 1
        sets = 256
        bytes_per_line = 16
        base_address = 32'b00000000000000000000000000000000
        limit = 32'b01111111111111111111111111111111
WARNING:Xst:647 - Input <address_a<30:12>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 4-bit register for signal <state>.
    Found 8-bit register for signal <flush_set>.
    Found 29-bit register for signal <refill_address>.
    Found 1-bit register for signal <restart_request>.
    Found 2-bit register for signal <refill_offset>.
    Found 1-bit register for signal <refilling>.
    Found finite state machine <FSM_0> for signal <state>.
    -----------------------------------------------------------------------
    | States             | 4                                              |
    | Transitions        | 18                                             |
    | Inputs             | 11                                             |
    | Outputs            | 8                                              |
    | Clock              | clk_i (rising_edge)                            |
    | Reset              | rst_i (positive)                               |
    | Reset type         | synchronous                                    |
    | Reset State        | 0001                                           |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 8-bit subtractor for signal <flush_set[7]_GND_56_o_sub_22_OUT> created at line 46392.
    Found 2-bit adder for signal <refill_offset[3]_GND_56_o_add_59_OUT> created at line 46469.
    Found 20-bit comparator equal for signal <way_match> created at line 46274
    Summary:
	inferred   2 Adder/Subtractor(s).
	inferred  41 D-type flip-flop(s).
	inferred   1 Comparator(s).
	inferred   8 Multiplexer(s).
	inferred   1 Finite State Machine(s).
Unit <lm32_icache_medium_icache_debug> synthesized.

Synthesizing Unit <lm32_ram_1>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.v".
        data_width = 32
        address_width = 10
WARNING:Xst:647 - Input <reset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 1024x32-bit dual-port RAM <Mram_mem> for signal <mem>.
    Found 10-bit register for signal <ra>.
    Summary:
	inferred   1 RAM(s).
	inferred  10 D-type flip-flop(s).
Unit <lm32_ram_1> synthesized.

Synthesizing Unit <lm32_ram_2>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.v".
        data_width = 20
        address_width = 8
WARNING:Xst:647 - Input <reset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 256x20-bit dual-port RAM <Mram_mem> for signal <mem>.
    Found 8-bit register for signal <ra>.
    Summary:
	inferred   1 RAM(s).
	inferred   8 D-type flip-flop(s).
Unit <lm32_ram_2> synthesized.

Synthesizing Unit <lm32_decoder_medium_icache_debug>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v".
WARNING:Xst:647 - Input <instruction<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Summary:
	inferred  10 Multiplexer(s).
Unit <lm32_decoder_medium_icache_debug> synthesized.

Synthesizing Unit <lm32_load_store_unit_medium_icache_debug>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v".
        associativity = 1
        sets = 512
        bytes_per_line = 16
        base_address = 0
        limit = 0
WARNING:Xst:647 - Input <load_store_address_x<31:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <stall_a> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <kill_x> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <load_x> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <store_x> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <store_q_x> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <d_rty_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 1-bit register for signal <d_stb_o>.
    Found 32-bit register for signal <d_dat_o>.
    Found 32-bit register for signal <d_adr_o>.
    Found 4-bit register for signal <d_sel_o>.
    Found 1-bit register for signal <d_we_o>.
    Found 1-bit register for signal <d_lock_o>.
    Found 32-bit register for signal <wb_data_m>.
    Found 1-bit register for signal <wb_load_complete>.
    Found 1-bit register for signal <stall_wb_load>.
    Found 1-bit register for signal <sign_extend_m>.
    Found 2-bit register for signal <size_m>.
    Found 4-bit register for signal <byte_enable_m>.
    Found 32-bit register for signal <store_data_m>.
    Found 1-bit register for signal <wb_select_m>.
    Found 2-bit register for signal <size_w>.
    Found 32-bit register for signal <data_w>.
    Found 1-bit register for signal <sign_extend_w>.
    Found 1-bit register for signal <d_cyc_o>.
    Found 32-bit 3-to-1 multiplexer for signal <store_data_x> created at line 44142.
    Summary:
	inferred 180 D-type flip-flop(s).
	inferred   2 Multiplexer(s).
Unit <lm32_load_store_unit_medium_icache_debug> synthesized.

Synthesizing Unit <lm32_adder>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v".
    Summary:
	no macro.
Unit <lm32_adder> synthesized.

Synthesizing Unit <lm32_addsub>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v".
    Found 33-bit subtractor for signal <GND_62_o_GND_62_o_sub_3_OUT> created at line 69.
    Found 33-bit subtractor for signal <tmp_subResult> created at line 69.
    Found 33-bit adder for signal <n0025> created at line 68.
    Found 33-bit adder for signal <tmp_addResult> created at line 68.
    Summary:
	inferred   4 Adder/Subtractor(s).
	inferred   2 Multiplexer(s).
Unit <lm32_addsub> synthesized.

Synthesizing Unit <lm32_logic_op>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v".
    Found 1-bit 4-to-1 multiplexer for signal <logic_result_x<0>> created at line 72.
    Found 1-bit 4-to-1 multiplexer for signal <logic_result_x<1>> created at line 72.
    Found 1-bit 4-to-1 multiplexer for signal <logic_result_x<2>> created at line 72.
    Found 1-bit 4-to-1 multiplexer for signal <logic_result_x<3>> created at line 72.
    Found 1-bit 4-to-1 multiplexer for signal <logic_result_x<4>> created at line 72.
    Found 1-bit 4-to-1 multiplexer for signal <logic_result_x<5>> created at line 72.
    Found 1-bit 4-to-1 multiplexer for signal <logic_result_x<6>> created at line 72.
    Found 1-bit 4-to-1 multiplexer for signal <logic_result_x<7>> created at line 72.
    Found 1-bit 4-to-1 multiplexer for signal <logic_result_x<8>> created at line 72.
    Found 1-bit 4-to-1 multiplexer for signal <logic_result_x<9>> created at line 72.
    Found 1-bit 4-to-1 multiplexer for signal <logic_result_x<10>> created at line 72.
    Found 1-bit 4-to-1 multiplexer for signal <logic_result_x<11>> created at line 72.
    Found 1-bit 4-to-1 multiplexer for signal <logic_result_x<12>> created at line 72.
    Found 1-bit 4-to-1 multiplexer for signal <logic_result_x<13>> created at line 72.
    Found 1-bit 4-to-1 multiplexer for signal <logic_result_x<14>> created at line 72.
    Found 1-bit 4-to-1 multiplexer for signal <logic_result_x<15>> created at line 72.
    Found 1-bit 4-to-1 multiplexer for signal <logic_result_x<16>> created at line 72.
    Found 1-bit 4-to-1 multiplexer for signal <logic_result_x<17>> created at line 72.
    Found 1-bit 4-to-1 multiplexer for signal <logic_result_x<18>> created at line 72.
    Found 1-bit 4-to-1 multiplexer for signal <logic_result_x<19>> created at line 72.
    Found 1-bit 4-to-1 multiplexer for signal <logic_result_x<20>> created at line 72.
    Found 1-bit 4-to-1 multiplexer for signal <logic_result_x<21>> created at line 72.
    Found 1-bit 4-to-1 multiplexer for signal <logic_result_x<22>> created at line 72.
    Found 1-bit 4-to-1 multiplexer for signal <logic_result_x<23>> created at line 72.
    Found 1-bit 4-to-1 multiplexer for signal <logic_result_x<24>> created at line 72.
    Found 1-bit 4-to-1 multiplexer for signal <logic_result_x<25>> created at line 72.
    Found 1-bit 4-to-1 multiplexer for signal <logic_result_x<26>> created at line 72.
    Found 1-bit 4-to-1 multiplexer for signal <logic_result_x<27>> created at line 72.
    Found 1-bit 4-to-1 multiplexer for signal <logic_result_x<28>> created at line 72.
    Found 1-bit 4-to-1 multiplexer for signal <logic_result_x<29>> created at line 72.
    Found 1-bit 4-to-1 multiplexer for signal <logic_result_x<30>> created at line 72.
    Found 1-bit 4-to-1 multiplexer for signal <logic_result_x<31>> created at line 72.
    Summary:
	inferred  32 Multiplexer(s).
Unit <lm32_logic_op> synthesized.

Synthesizing Unit <lm32_shifter>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v".
WARNING:Xst:647 - Input <operand_1_x<31:5>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 1-bit register for signal <direction_m>.
    Found 32-bit register for signal <right_shift_result>.
    Found 64-bit shifter logical right for signal <n0028> created at line 128
    Summary:
	inferred  33 D-type flip-flop(s).
	inferred   3 Multiplexer(s).
	inferred   1 Combinational logic shifter(s).
Unit <lm32_shifter> synthesized.

Synthesizing Unit <lm32_multiplier>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic/lm32_multiplier.v".
    Found 16-bit register for signal <a1>.
    Found 16-bit register for signal <b0>.
    Found 16-bit register for signal <b1>.
    Found 16-bit register for signal <c0>.
    Found 16-bit register for signal <c1>.
    Found 16-bit register for signal <d1>.
    Found 16-bit register for signal <e1>.
    Found 16-bit register for signal <result0>.
    Found 16-bit register for signal <result1>.
    Found 16-bit register for signal <a0>.
    Found 16-bit adder for signal <n0077> created at line 115.
    Found 16-bit adder for signal <c1[15]_e1[15]_add_17_OUT> created at line 115.
    Found 16x16-bit multiplier for signal <a0[15]_b0[15]_MuLt_9_OUT> created at line 109.
    Found 16x16-bit multiplier for signal <n0055> created at line 110.
    Found 16x16-bit multiplier for signal <n0056> created at line 111.
    Summary:
	inferred   3 Multiplier(s).
	inferred   2 Adder/Subtractor(s).
	inferred 160 D-type flip-flop(s).
Unit <lm32_multiplier> synthesized.

Synthesizing Unit <lm32_interrupt_medium_icache_debug>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v".
        interrupts = 32
WARNING:Xst:647 - Input <csr_write_data<3:31>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 1-bit register for signal <eie>.
    Found 1-bit register for signal <bie>.
    Found 32-bit register for signal <im>.
    Found 32-bit register for signal <ip>.
    Found 11-bit register for signal <eie_delay>.
    Found 1-bit register for signal <ie>.
    Found 32-bit 3-to-1 multiplexer for signal <csr_read_data> created at line 50671.
    Summary:
	inferred  78 D-type flip-flop(s).
	inferred  17 Multiplexer(s).
Unit <lm32_interrupt_medium_icache_debug> synthesized.

Synthesizing Unit <lm32_jtag_medium_icache_debug>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v".
WARNING:Xst:647 - Input <csr_write_data<31:8>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <jtag_clk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 1-bit register for signal <rx_update_r>.
    Found 1-bit register for signal <rx_update_r_r>.
    Found 1-bit register for signal <rx_update_r_r_r>.
    Found 4-bit register for signal <state>.
    Found 4-bit register for signal <command>.
    Found 8-bit register for signal <jtag_reg_d>.
    Found 1-bit register for signal <processing>.
    Found 1-bit register for signal <jtag_csr_write_enable>.
    Found 1-bit register for signal <jtag_read_enable>.
    Found 1-bit register for signal <jtag_write_enable>.
    Found 1-bit register for signal <jtag_break>.
    Found 1-bit register for signal <jtag_reset>.
    Found 8-bit register for signal <uart_tx_byte>.
    Found 1-bit register for signal <uart_tx_valid>.
    Found 8-bit register for signal <uart_rx_byte>.
    Found 1-bit register for signal <uart_rx_valid>.
    Found 8-bit register for signal <jtag_byte_4>.
    Found 8-bit register for signal <jtag_byte_3>.
    Found 8-bit register for signal <jtag_byte_2>.
    Found 8-bit register for signal <jtag_byte_1>.
    Found 8-bit register for signal <jtag_byte_0>.
    Found 1-bit register for signal <rx_update>.
    Found finite state machine <FSM_1> for signal <state>.
    -----------------------------------------------------------------------
    | States             | 9                                              |
    | Transitions        | 36                                             |
    | Inputs             | 13                                             |
    | Outputs            | 8                                              |
    | Clock              | clk_i (rising_edge)                            |
    | Reset              | rst_i (positive)                               |
    | Reset type         | synchronous                                    |
    | Reset State        | 0000                                           |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 16-bit adder for signal <jtag_byte_2[7]_GND_68_o_add_22_OUT> created at line 50090.
    Summary:
	inferred   1 Adder/Subtractor(s).
	inferred  80 D-type flip-flop(s).
	inferred  13 Multiplexer(s).
	inferred   1 Finite State Machine(s).
Unit <lm32_jtag_medium_icache_debug> synthesized.

Synthesizing Unit <lm32_debug_medium_icache_debug>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v".
        breakpoints = 0
        watchpoints = 32'b00000000000000000000000000000100
WARNING:Xst:647 - Input <pc_x<30:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:653 - Signal <wp_match_n<4>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
    Found 1-bit register for signal <wp<0><30>>.
    Found 1-bit register for signal <wp<0><29>>.
    Found 1-bit register for signal <wp<0><28>>.
    Found 1-bit register for signal <wp<0><27>>.
    Found 1-bit register for signal <wp<0><26>>.
    Found 1-bit register for signal <wp<0><25>>.
    Found 1-bit register for signal <wp<0><24>>.
    Found 1-bit register for signal <wp<0><23>>.
    Found 1-bit register for signal <wp<0><22>>.
    Found 1-bit register for signal <wp<0><21>>.
    Found 1-bit register for signal <wp<0><20>>.
    Found 1-bit register for signal <wp<0><19>>.
    Found 1-bit register for signal <wp<0><18>>.
    Found 1-bit register for signal <wp<0><17>>.
    Found 1-bit register for signal <wp<0><16>>.
    Found 1-bit register for signal <wp<0><15>>.
    Found 1-bit register for signal <wp<0><14>>.
    Found 1-bit register for signal <wp<0><13>>.
    Found 1-bit register for signal <wp<0><12>>.
    Found 1-bit register for signal <wp<0><11>>.
    Found 1-bit register for signal <wp<0><10>>.
    Found 1-bit register for signal <wp<0><9>>.
    Found 1-bit register for signal <wp<0><8>>.
    Found 1-bit register for signal <wp<0><7>>.
    Found 1-bit register for signal <wp<0><6>>.
    Found 1-bit register for signal <wp<0><5>>.
    Found 1-bit register for signal <wp<0><4>>.
    Found 1-bit register for signal <wp<0><3>>.
    Found 1-bit register for signal <wp<0><2>>.
    Found 1-bit register for signal <wp<0><1>>.
    Found 1-bit register for signal <wp<0><0>>.
    Found 1-bit register for signal <wpc_c<0><1>>.
    Found 1-bit register for signal <wpc_c<0><0>>.
    Found 1-bit register for signal <wp<1><31>>.
    Found 1-bit register for signal <wp<1><30>>.
    Found 1-bit register for signal <wp<1><29>>.
    Found 1-bit register for signal <wp<1><28>>.
    Found 1-bit register for signal <wp<1><27>>.
    Found 1-bit register for signal <wp<1><26>>.
    Found 1-bit register for signal <wp<1><25>>.
    Found 1-bit register for signal <wp<1><24>>.
    Found 1-bit register for signal <wp<1><23>>.
    Found 1-bit register for signal <wp<1><22>>.
    Found 1-bit register for signal <wp<1><21>>.
    Found 1-bit register for signal <wp<1><20>>.
    Found 1-bit register for signal <wp<1><19>>.
    Found 1-bit register for signal <wp<1><18>>.
    Found 1-bit register for signal <wp<1><17>>.
    Found 1-bit register for signal <wp<1><16>>.
    Found 1-bit register for signal <wp<1><15>>.
    Found 1-bit register for signal <wp<1><14>>.
    Found 1-bit register for signal <wp<1><13>>.
    Found 1-bit register for signal <wp<1><12>>.
    Found 1-bit register for signal <wp<1><11>>.
    Found 1-bit register for signal <wp<1><10>>.
    Found 1-bit register for signal <wp<1><9>>.
    Found 1-bit register for signal <wp<1><8>>.
    Found 1-bit register for signal <wp<1><7>>.
    Found 1-bit register for signal <wp<1><6>>.
    Found 1-bit register for signal <wp<1><5>>.
    Found 1-bit register for signal <wp<1><4>>.
    Found 1-bit register for signal <wp<1><3>>.
    Found 1-bit register for signal <wp<1><2>>.
    Found 1-bit register for signal <wp<1><1>>.
    Found 1-bit register for signal <wp<1><0>>.
    Found 1-bit register for signal <wpc_c<1><1>>.
    Found 1-bit register for signal <wpc_c<1><0>>.
    Found 1-bit register for signal <wp<2><31>>.
    Found 1-bit register for signal <wp<2><30>>.
    Found 1-bit register for signal <wp<2><29>>.
    Found 1-bit register for signal <wp<2><28>>.
    Found 1-bit register for signal <wp<2><27>>.
    Found 1-bit register for signal <wp<2><26>>.
    Found 1-bit register for signal <wp<2><25>>.
    Found 1-bit register for signal <wp<2><24>>.
    Found 1-bit register for signal <wp<2><23>>.
    Found 1-bit register for signal <wp<2><22>>.
    Found 1-bit register for signal <wp<2><21>>.
    Found 1-bit register for signal <wp<2><20>>.
    Found 1-bit register for signal <wp<2><19>>.
    Found 1-bit register for signal <wp<2><18>>.
    Found 1-bit register for signal <wp<2><17>>.
    Found 1-bit register for signal <wp<2><16>>.
    Found 1-bit register for signal <wp<2><15>>.
    Found 1-bit register for signal <wp<2><14>>.
    Found 1-bit register for signal <wp<2><13>>.
    Found 1-bit register for signal <wp<2><12>>.
    Found 1-bit register for signal <wp<2><11>>.
    Found 1-bit register for signal <wp<2><10>>.
    Found 1-bit register for signal <wp<2><9>>.
    Found 1-bit register for signal <wp<2><8>>.
    Found 1-bit register for signal <wp<2><7>>.
    Found 1-bit register for signal <wp<2><6>>.
    Found 1-bit register for signal <wp<2><5>>.
    Found 1-bit register for signal <wp<2><4>>.
    Found 1-bit register for signal <wp<2><3>>.
    Found 1-bit register for signal <wp<2><2>>.
    Found 1-bit register for signal <wp<2><1>>.
    Found 1-bit register for signal <wp<2><0>>.
    Found 1-bit register for signal <wpc_c<2><1>>.
    Found 1-bit register for signal <wpc_c<2><0>>.
    Found 1-bit register for signal <wp<3><31>>.
    Found 1-bit register for signal <wp<3><30>>.
    Found 1-bit register for signal <wp<3><29>>.
    Found 1-bit register for signal <wp<3><28>>.
    Found 1-bit register for signal <wp<3><27>>.
    Found 1-bit register for signal <wp<3><26>>.
    Found 1-bit register for signal <wp<3><25>>.
    Found 1-bit register for signal <wp<3><24>>.
    Found 1-bit register for signal <wp<3><23>>.
    Found 1-bit register for signal <wp<3><22>>.
    Found 1-bit register for signal <wp<3><21>>.
    Found 1-bit register for signal <wp<3><20>>.
    Found 1-bit register for signal <wp<3><19>>.
    Found 1-bit register for signal <wp<3><18>>.
    Found 1-bit register for signal <wp<3><17>>.
    Found 1-bit register for signal <wp<3><16>>.
    Found 1-bit register for signal <wp<3><15>>.
    Found 1-bit register for signal <wp<3><14>>.
    Found 1-bit register for signal <wp<3><13>>.
    Found 1-bit register for signal <wp<3><12>>.
    Found 1-bit register for signal <wp<3><11>>.
    Found 1-bit register for signal <wp<3><10>>.
    Found 1-bit register for signal <wp<3><9>>.
    Found 1-bit register for signal <wp<3><8>>.
    Found 1-bit register for signal <wp<3><7>>.
    Found 1-bit register for signal <wp<3><6>>.
    Found 1-bit register for signal <wp<3><5>>.
    Found 1-bit register for signal <wp<3><4>>.
    Found 1-bit register for signal <wp<3><3>>.
    Found 1-bit register for signal <wp<3><2>>.
    Found 1-bit register for signal <wp<3><1>>.
    Found 1-bit register for signal <wp<3><0>>.
    Found 1-bit register for signal <wpc_c<3><1>>.
    Found 1-bit register for signal <wpc_c<3><0>>.
    Found 1-bit register for signal <dc_re>.
    Found 3-bit register for signal <state>.
    Found 1-bit register for signal <dc_ss>.
    Found 1-bit register for signal <wp<0><31>>.
    Found finite state machine <FSM_2> for signal <state>.
    -----------------------------------------------------------------------
    | States             | 5                                              |
    | Transitions        | 36                                             |
    | Inputs             | 8                                              |
    | Outputs            | 4                                              |
    | Clock              | clk_i (rising_edge)                            |
    | Reset              | rst_i (positive)                               |
    | Reset type         | synchronous                                    |
    | Reset State        | 000                                            |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 32-bit comparator equal for signal <wp[0][31]_load_store_address_x[31]_equal_2_o> created at line 47900
    Found 32-bit comparator equal for signal <wp[1][31]_load_store_address_x[31]_equal_3_o> created at line 47900
    Found 32-bit comparator equal for signal <wp[2][31]_load_store_address_x[31]_equal_4_o> created at line 47900
    Found 32-bit comparator equal for signal <wp[3][31]_load_store_address_x[31]_equal_5_o> created at line 47900
    Summary:
	inferred 138 D-type flip-flop(s).
	inferred   4 Comparator(s).
	inferred  35 Multiplexer(s).
	inferred   1 Finite State Machine(s).
Unit <lm32_debug_medium_icache_debug> synthesized.

Synthesizing Unit <lm32_dp_ram>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.v".
        addr_width = 5
        addr_depth = 32
        data_width = 32
WARNING:Xst:647 - Input <rst_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 32x32-bit dual-port RAM <Mram_ram> for signal <ram>.
    Found 5-bit register for signal <raddr_r>.
    Summary:
	inferred   1 RAM(s).
	inferred   5 D-type flip-flop(s).
Unit <lm32_dp_ram> synthesized.

Synthesizing Unit <jtag_cores>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v".
    Found 11-bit register for signal <jtag_latched>.
    Found 11-bit register for signal <jtag_shift>.
    Summary:
	inferred  22 D-type flip-flop(s).
	inferred   1 Multiplexer(s).
Unit <jtag_cores> synthesized.

Synthesizing Unit <jtag_tap>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic/jtag_tap.v".
WARNING:Xst:647 - Input <tdo> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Summary:
	no macro.
Unit <jtag_tap> synthesized.

Synthesizing Unit <xwb_dma>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dma/xwb_dma.vhd".
        logRingLen = 4
WARNING:Xst:647 - Input <slave_i_adr<31:5>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <slave_i_adr<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <w_master_i_dat<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <r_master_i_int> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <w_master_i_int> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:653 - Signal <slave_o_int> is used but never assigned. This sourceless signal will be automatically connected to value GND.
    Found 16x32-bit dual-port RAM <Mram_ring> for signal <ring>.
    Found 5-bit register for signal <read_result_offset>.
    Found 5-bit register for signal <write_issue_offset>.
    Found 5-bit register for signal <write_result_offset>.
    Found 32-bit register for signal <read_issue_address>.
    Found 32-bit register for signal <write_issue_address>.
    Found 32-bit register for signal <read_stride>.
    Found 32-bit register for signal <write_stride>.
    Found 32-bit register for signal <transfer_count>.
    Found 1-bit register for signal <r_master_o_CYC>.
    Found 1-bit register for signal <w_master_o_CYC>.
    Found 1-bit register for signal <r_master_o_STB>.
    Found 1-bit register for signal <w_master_o_STB>.
    Found 1-bit register for signal <slave_o_ACK>.
    Found 32-bit register for signal <slave_o_DAT>.
    Found 1-bit register for signal <interrupt_o>.
    Found 5-bit register for signal <read_issue_offset>.
    Found 32-bit adder for signal <read_issue_address[31]_read_stride[31]_add_8_OUT> created at line 197.
    Found 5-bit adder for signal <read_issue_offset[4]_GND_73_o_add_9_OUT> created at line 1241.
    Found 5-bit adder for signal <read_result_offset[4]_GND_73_o_add_15_OUT> created at line 1241.
    Found 32-bit adder for signal <write_issue_address[31]_write_stride[31]_add_17_OUT> created at line 213.
    Found 5-bit adder for signal <write_issue_offset[4]_GND_73_o_add_18_OUT> created at line 1241.
    Found 5-bit adder for signal <write_result_offset[4]_GND_73_o_add_21_OUT> created at line 1241.
    Found 32-bit subtractor for signal <GND_73_o_GND_73_o_sub_11_OUT<31:0>> created at line 1308.
    Found 32-bit 7-to-1 multiplexer for signal <slave_i_adr[4]_GND_73_o_wide_mux_7_OUT> created at line 180.
    Found 4-bit comparator equal for signal <write_result_offset[4]_read_issue_offset[4]_equal_24_o> created at line 224
    Found 5-bit comparator not equal for signal <n0052> created at line 236
    Found 5-bit comparator not equal for signal <n0055> created at line 237
    Found 5-bit comparator not equal for signal <n0057> created at line 238
    Summary:
	inferred   1 RAM(s).
	inferred   7 Adder/Subtractor(s).
	inferred 218 D-type flip-flop(s).
	inferred   4 Comparator(s).
	inferred 175 Multiplexer(s).
Unit <xwb_dma> synthesized.

Synthesizing Unit <xwb_dpram>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd".
        g_size = 22528
        g_init_file = "../../../embedded-sw/dbe.ram"
        g_init_value = ""
        g_must_have_init_file = true
        g_slave1_interface_mode = pipelined
        g_slave2_interface_mode = pipelined
        g_slave1_granularity = byte
        g_slave2_granularity = byte
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 80: Output port <sl_dat_o> of the instance <U_Adapter1> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 80: Output port <ma_adr_o> of the instance <U_Adapter1> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 80: Output port <ma_dat_o> of the instance <U_Adapter1> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 80: Output port <ma_sel_o> of the instance <U_Adapter1> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 80: Output port <sl_err_o> of the instance <U_Adapter1> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 80: Output port <sl_rty_o> of the instance <U_Adapter1> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 80: Output port <sl_ack_o> of the instance <U_Adapter1> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 80: Output port <sl_stall_o> of the instance <U_Adapter1> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 80: Output port <sl_int_o> of the instance <U_Adapter1> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 80: Output port <ma_cyc_o> of the instance <U_Adapter1> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 80: Output port <ma_stb_o> of the instance <U_Adapter1> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 80: Output port <ma_we_o> of the instance <U_Adapter1> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 96: Output port <sl_dat_o> of the instance <U_Adapter2> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 96: Output port <ma_adr_o> of the instance <U_Adapter2> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 96: Output port <ma_dat_o> of the instance <U_Adapter2> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 96: Output port <ma_sel_o> of the instance <U_Adapter2> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 96: Output port <sl_err_o> of the instance <U_Adapter2> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 96: Output port <sl_rty_o> of the instance <U_Adapter2> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 96: Output port <sl_ack_o> of the instance <U_Adapter2> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 96: Output port <sl_stall_o> of the instance <U_Adapter2> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 96: Output port <sl_int_o> of the instance <U_Adapter2> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 96: Output port <ma_cyc_o> of the instance <U_Adapter2> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 96: Output port <ma_stb_o> of the instance <U_Adapter2> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" line 96: Output port <ma_we_o> of the instance <U_Adapter2> is unconnected or connected to loadless signal.
WARNING:Xst:653 - Signal <slave1_out_int> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <slave2_out_int> is used but never assigned. This sourceless signal will be automatically connected to value GND.
    Found 1-bit register for signal <slave2_out_ack>.
    Found 1-bit register for signal <slave1_out_ack>.
    Summary:
	inferred   2 D-type flip-flop(s).
	inferred   2 Multiplexer(s).
Unit <xwb_dpram> synthesized.

Synthesizing Unit <wb_slave_adapter_1>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd".
        g_master_use_struct = true
        g_master_mode = pipelined
        g_master_granularity = word
        g_slave_use_struct = true
        g_slave_mode = pipelined
        g_slave_granularity = byte
WARNING:Xst:647 - Input <sl_adr_i<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <sl_dat_i<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <sl_sel_i<3:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ma_dat_i<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clk_sys_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <rst_n_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <sl_cyc_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <sl_stb_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <sl_we_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ma_err_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ma_rty_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ma_ack_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ma_stall_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ma_int_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:653 - Signal <ma_adr_o> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <ma_dat_o> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <ma_sel_o> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <ma_cyc_o> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <ma_stb_o> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <ma_we_o> is used but never assigned. This sourceless signal will be automatically connected to value GND.
    Summary:
	no macro.
Unit <wb_slave_adapter_1> synthesized.

Synthesizing Unit <generic_dpram>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd".
        g_data_width = 32
        g_size = 22528
        g_with_byte_enable = true
        g_addr_conflict_resolution = "read_first"
        g_init_file = "../../../embedded-sw/dbe.ram"
        g_init_value = ""
        g_dual_clock = false
        g_fail_if_file_not_found = true
WARNING:Xst:647 - Input <clkb_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Summary:
	no macro.
Unit <generic_dpram> synthesized.

Synthesizing Unit <generic_dpram_sameclock>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd".
        g_data_width = 32
        g_size = 22528
        g_with_byte_enable = true
        g_addr_conflict_resolution = "read_first"
        g_init_file = "../../../embedded-sw/dbe.ram"
        g_init_value = ""
        g_fail_if_file_not_found = true
WARNING:Xst:647 - Input <rst_n_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:3035 - Index value(s) does not match array range for signal <ram>, simulation mismatch.
    Found 22528x32-bit dual-port RAM <Mram_ram> for signal <ram>.
    Found 32-bit register for signal <qb_o>.
    Found 32-bit register for signal <qa_o>.
    Summary:
	inferred   1 RAM(s).
	inferred  64 D-type flip-flop(s).
	inferred   8 Multiplexer(s).
Unit <generic_dpram_sameclock> synthesized.

Synthesizing Unit <xwb_fmc150>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/xwb_fmc150.vhd".
        g_interface_mode = classic
        g_address_granularity = byte
        g_packet_size = 32
        g_sim = 0
    Summary:
	no macro.
Unit <xwb_fmc150> synthesized.

Synthesizing Unit <wb_fmc150>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/wb_fmc150.vhd".
        g_interface_mode = classic
        g_address_granularity = byte
        g_packet_size = 32
        g_sim = 0
WARNING:Xst:647 - Input <sim_adc_data_valid> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/wb_fmc150.vhd" line 296: Output port <adc_str_cntvalueout_o> of the instance <cmp_fmc150_testbench> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/wb_fmc150.vhd" line 390: Output port <slave_o_dat> of the instance <cmp_adapter> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/wb_fmc150.vhd" line 390: Output port <ma_adr_o> of the instance <cmp_adapter> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/wb_fmc150.vhd" line 390: Output port <ma_dat_o> of the instance <cmp_adapter> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/wb_fmc150.vhd" line 390: Output port <ma_sel_o> of the instance <cmp_adapter> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/wb_fmc150.vhd" line 390: Output port <sl_err_o> of the instance <cmp_adapter> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/wb_fmc150.vhd" line 390: Output port <sl_rty_o> of the instance <cmp_adapter> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/wb_fmc150.vhd" line 390: Output port <sl_int_o> of the instance <cmp_adapter> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/wb_fmc150.vhd" line 390: Output port <slave_o_ack> of the instance <cmp_adapter> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/wb_fmc150.vhd" line 390: Output port <slave_o_err> of the instance <cmp_adapter> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/wb_fmc150.vhd" line 390: Output port <slave_o_rty> of the instance <cmp_adapter> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/wb_fmc150.vhd" line 390: Output port <slave_o_stall> of the instance <cmp_adapter> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/wb_fmc150.vhd" line 390: Output port <slave_o_int> of the instance <cmp_adapter> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/wb_fmc150.vhd" line 390: Output port <ma_cyc_o> of the instance <cmp_adapter> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/wb_fmc150.vhd" line 390: Output port <ma_stb_o> of the instance <cmp_adapter> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/wb_fmc150.vhd" line 390: Output port <ma_we_o> of the instance <cmp_adapter> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/wb_fmc150.vhd" line 448: Output port <src_o_stb> of the instance <cmp_wb_source_if> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/wb_fmc150.vhd" line 448: Output port <dreq_o> of the instance <cmp_wb_source_if> is unconnected or connected to loadless signal.
WARNING:Xst:653 - Signal <wb_out_err> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <wb_out_rty> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <wb_out_int> is used but never assigned. This sourceless signal will be automatically connected to value GND.
    Found 5-bit register for signal <s_wbs_packet_counter>.
    Found 5-bit adder for signal <s_wbs_packet_counter[4]_GND_99_o_add_3_OUT> created at line 1241.
    Summary:
	inferred   1 Adder/Subtractor(s).
	inferred   5 D-type flip-flop(s).
Unit <wb_fmc150> synthesized.

Synthesizing Unit <fmc150_testbench>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/fmc150/fmc150_testbench.vhd".
        g_sim = 0
WARNING:Xst:647 - Input <sim_adc_cha_data_i<13:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <sim_adc_chb_data_i<13:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <sim_adc_clk_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <sim_adc_clk2x_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:653 - Signal <dac_din_c> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <dac_din_d> is used but never assigned. This sourceless signal will be automatically connected to value GND.
    Found 16-bit register for signal <adc_dout_b>.
    Found 16-bit register for signal <adc_dout_a>.
    Summary:
	inferred  32 D-type flip-flop(s).
Unit <fmc150_testbench> synthesized.

Synthesizing Unit <fmc150_adc_if>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/fmc150/fmc150_adc_if.vhd".
        g_sim = 0
WARNING:Xst:647 - Input <rst_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clk_adc_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Summary:
	no macro.
Unit <fmc150_adc_if> synthesized.

Synthesizing Unit <strobe_lvds>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/adc/strobe_lvds.vhd".
        C_DEFAULT_DELAY = 0
    Summary:
	no macro.
Unit <strobe_lvds> synthesized.

Synthesizing Unit <adc_channel_lvds_ddr>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/adc/adc_channel_lvds_ddr.vhd".
        C_NBITS = 14
        C_DEFAULT_DELAY = 15
    Summary:
	no macro.
Unit <adc_channel_lvds_ddr> synthesized.

Synthesizing Unit <fmc150_dac_if>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/fmc150/fmc150_dac_if.vhd".
    Found 10-bit register for signal <cnt>.
    Found 1-bit register for signal <io_rst>.
    Found 1-bit register for signal <frame>.
    Found 1-bit register for signal <txenable_o>.
    Found 10-bit adder for signal <cnt[9]_GND_199_o_add_1_OUT> created at line 53.
    Found 10-bit comparator greater for signal <cnt[9]_PWR_84_o_LessThan_1_o> created at line 52
    Summary:
	inferred   1 Adder/Subtractor(s).
	inferred  13 D-type flip-flop(s).
	inferred   1 Comparator(s).
	inferred   1 Multiplexer(s).
Unit <fmc150_dac_if> synthesized.

Synthesizing Unit <fmc150_spi_ctrl>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/fmc150/fmc150_spi_ctrl.vhd".
        g_sim = 0
WARNING:Xst:647 - Input <prsnt_m2c_l> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/fmc150/fmc150_spi_ctrl.vhd" line 416: Output port <init_done> of the instance <amc7823_ctrl_inst> is unconnected or connected to loadless signal.
    Found 1-bit register for signal <ads62p49_valid_prev>.
    Found 1-bit register for signal <dac3283_valid_prev>.
    Found 1-bit register for signal <amc7823_valid_prev>.
    Found 1-bit register for signal <cdce72010_in_cmd_val>.
    Found 1-bit register for signal <ads62p49_in_cmd_val>.
    Found 1-bit register for signal <dac3283_in_cmd_val>.
    Found 1-bit register for signal <amc7823_in_cmd_val>.
    Found 1-bit register for signal <busy>.
    Found 32-bit register for signal <odata>.
    Found 1-bit register for signal <cdce72010_valid_prev>.
    Found 62-bit register for signal <in_cmd>.
    WARNING:Xst:2404 -  FFs/Latches <in_cmd<63:62>> (without init value) have a constant value of 0 in block <fmc150_spi_ctrl>.
    Summary:
	inferred 103 D-type flip-flop(s).
	inferred  11 Multiplexer(s).
Unit <fmc150_spi_ctrl> synthesized.

Synthesizing Unit <cdce72010_ctrl>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/fmc150/cdce72010_ctrl.vhd".
        START_ADDR = "0000000000000000000000000000"
        STOP_ADDR = "1111111111111111111111111111"
        g_sim = 0
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/fmc150/cdce72010_ctrl.vhd" line 360: Output port <inbusy> of the instance <pulse2pulse_inst0> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/fmc150/cdce72010_ctrl.vhd" line 513: Output port <inbusy> of the instance <pulse2pulse_inst1> is unconnected or connected to loadless signal.
    Found 1-bit register for signal <ncs_int>.
    Found 32-bit register for signal <in_reg>.
    Found 32-bit register for signal <sh_counter>.
    Found 32-bit register for signal <shift_reg>.
    Found 4-bit register for signal <inst_reg>.
    Found 4-bit register for signal <init_address>.
    Found 28-bit register for signal <data_reg>.
    Found 28-bit register for signal <data_read>.
    Found 3-bit register for signal <sh_state>.
    Found 1-bit register for signal <init_done>.
    Found 1-bit register for signal <init_done_tmp>.
    Found 1-bit register for signal <init_done_prev>.
    Found 1-bit register for signal <init>.
    Found 1-bit register for signal <cdce_reset>.
    Found 1-bit register for signal <cdce_pd>.
    Found 1-bit register for signal <ref_dis>.
    Found 1-bit register for signal <in_reg_val>.
    Found 1-bit register for signal <inst_val>.
    Found 1-bit register for signal <inst_rw>.
    Found 1-bit register for signal <init_tmp>.
    Found 1-bit register for signal <init_reg>.
    Found 1-bit register for signal <shifting>.
    Found 1-bit register for signal <read_n_write>.
    Found 1-bit register for signal <done_sclk>.
    Found 1-bit register for signal <init_done_sclk>.
    Found 1-bit register for signal <read_byte_val>.
    Found 1-bit register for signal <sclk_ext>.
    Found 1-bit register for signal <serial_clk>.
    Found 1-bit register for signal <sdi>.
    Found 4-bit register for signal <gen_serial_clk.clk_div>.
    Found finite state machine <FSM_3> for signal <sh_state>.
    -----------------------------------------------------------------------
    | States             | 5                                              |
    | Transitions        | 9                                              |
    | Inputs             | 3                                              |
    | Outputs            | 8                                              |
    | Clock              | serial_clk (rising_edge)                       |
    | Reset              | rst (positive)                                 |
    | Reset type         | asynchronous                                   |
    | Reset State        | idle                                           |
    | Power Up State     | idle                                           |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 4-bit adder for signal <gen_serial_clk.clk_div[3]_GND_306_o_add_0_OUT> created at line 222.
    Found 4-bit adder for signal <init_address[3]_GND_306_o_add_37_OUT> created at line 485.
    Found 32-bit subtractor for signal <sh_counter[31]_GND_306_o_sub_26_OUT<31:0>> created at line 445.
    Found 1-bit tristate buffer for signal <spi_sdo> created at line 595
    Found 28-bit comparator greater for signal <n0018> created at line 328
    Found 28-bit comparator lessequal for signal <n0024> created at line 337
    Summary:
	inferred   3 Adder/Subtractor(s).
	inferred 185 D-type flip-flop(s).
	inferred   2 Comparator(s).
	inferred  23 Multiplexer(s).
	inferred   1 Tristate(s).
	inferred   1 Finite State Machine(s).
Unit <cdce72010_ctrl> synthesized.

Synthesizing Unit <fmc150_stellar_cmd>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/fmc150/fmc150_stellar_cmd.vhd".
        START_ADDR = "0000000000000000000000000000"
        STOP_ADDR = "1111111111111111111111111111"
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/fmc150/fmc150_stellar_cmd.vhd" line 109: Output port <inbusy> of the instance <p2p0> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/fmc150/fmc150_stellar_cmd.vhd" line 119: Output port <inbusy> of the instance <p2p1> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/fmc150/fmc150_stellar_cmd.vhd" line 129: Output port <inbusy> of the instance <p2p2> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/fmc150/fmc150_stellar_cmd.vhd" line 139: Output port <inbusy> of the instance <p2p3> is unconnected or connected to loadless signal.
    Found 64-bit register for signal <out_cmd>.
    Found 28-bit register for signal <out_reg_addr>.
    Found 28-bit register for signal <in_reg_addr_sig>.
    Found 32-bit register for signal <out_reg>.
    Found 1-bit register for signal <register_rd>.
    Found 1-bit register for signal <mbx_received>.
    Found 1-bit register for signal <out_cmd_val>.
    Found 1-bit register for signal <register_wr>.
    Summary:
	inferred 156 D-type flip-flop(s).
	inferred   3 Multiplexer(s).
Unit <fmc150_stellar_cmd> synthesized.

Synthesizing Unit <pulse2pulse>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/fmc150/pulse2pulse.vhd".
    Found 1-bit register for signal <in_reset_prev>.
    Found 1-bit register for signal <in_reset_prev2>.
    Found 1-bit register for signal <in_set>.
    Found 1-bit register for signal <out_set>.
    Found 1-bit register for signal <out_set_prev>.
    Found 1-bit register for signal <out_set_prev2>.
    Found 1-bit register for signal <outreset>.
    Found 1-bit register for signal <pulseout>.
    Found 1-bit register for signal <in_reset>.
    Summary:
	inferred   9 D-type flip-flop(s).
Unit <pulse2pulse> synthesized.

Synthesizing Unit <ads62p49_ctrl>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/fmc150/ads62p49_ctrl.vhd".
        START_ADDR = "0000000000000000000000000000"
        STOP_ADDR = "1111111111111111111111111111"
        g_sim = 0
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/fmc150/ads62p49_ctrl.vhd" line 311: Output port <inbusy> of the instance <pulse2pulse_inst0> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/fmc150/ads62p49_ctrl.vhd" line 455: Output port <inbusy> of the instance <pulse2pulse_inst1> is unconnected or connected to loadless signal.
    Found 1-bit register for signal <ncs_int>.
    Found 1-bit register for signal <reset>.
    Found 32-bit register for signal <in_reg>.
    Found 32-bit register for signal <sh_counter>.
    Found 8-bit register for signal <inst_reg>.
    Found 8-bit register for signal <data_reg>.
    Found 8-bit register for signal <data_read>.
    Found 2-bit register for signal <sh_state>.
    Found 16-bit register for signal <shift_reg>.
    Found 5-bit register for signal <init_address>.
    Found 1-bit register for signal <init_done>.
    Found 1-bit register for signal <init_done_tmp>.
    Found 1-bit register for signal <init_done_prev>.
    Found 1-bit register for signal <init>.
    Found 1-bit register for signal <in_reg_val>.
    Found 1-bit register for signal <inst_val>.
    Found 1-bit register for signal <inst_rw>.
    Found 1-bit register for signal <init_tmp>.
    Found 1-bit register for signal <init_reg>.
    Found 1-bit register for signal <shifting>.
    Found 1-bit register for signal <read_n_write>.
    Found 1-bit register for signal <done_sclk>.
    Found 1-bit register for signal <init_done_sclk>.
    Found 1-bit register for signal <read_byte_val>.
    Found 1-bit register for signal <serial_clk>.
    Found 1-bit register for signal <sclk_ext>.
    Found 1-bit register for signal <sdi>.
    Found 4-bit register for signal <gen_serial_clk.clk_div>.
    Found finite state machine <FSM_4> for signal <sh_state>.
    -----------------------------------------------------------------------
    | States             | 4                                              |
    | Transitions        | 8                                              |
    | Inputs             | 3                                              |
    | Outputs            | 5                                              |
    | Clock              | serial_clk (rising_edge)                       |
    | Reset              | rst (positive)                                 |
    | Reset type         | asynchronous                                   |
    | Reset State        | idle                                           |
    | Power Up State     | idle                                           |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 4-bit adder for signal <gen_serial_clk.clk_div[3]_GND_344_o_add_0_OUT> created at line 180.
    Found 5-bit adder for signal <init_address[4]_GND_344_o_add_36_OUT> created at line 427.
    Found 32-bit subtractor for signal <sh_counter[31]_GND_344_o_sub_25_OUT<31:0>> created at line 387.
    Found 1-bit tristate buffer for signal <spi_sdo> created at line 496
    Found 28-bit comparator greater for signal <n0016> created at line 279
    Found 28-bit comparator lessequal for signal <n0022> created at line 288
    Summary:
	inferred   3 Adder/Subtractor(s).
	inferred 132 D-type flip-flop(s).
	inferred   2 Comparator(s).
	inferred  18 Multiplexer(s).
	inferred   1 Tristate(s).
	inferred   1 Finite State Machine(s).
Unit <ads62p49_ctrl> synthesized.

Synthesizing Unit <dac3283_ctrl>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/fmc150/dac3283_ctrl.vhd".
        START_ADDR = "0000000000000000000000000000"
        STOP_ADDR = "1111111111111111111111111111"
        g_sim = 0
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/fmc150/dac3283_ctrl.vhd" line 300: Output port <inbusy> of the instance <pulse2pulse_inst0> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/fmc150/dac3283_ctrl.vhd" line 446: Output port <inbusy> of the instance <pulse2pulse_inst1> is unconnected or connected to loadless signal.
    Found 1-bit register for signal <ncs_int>.
    Found 32-bit register for signal <in_reg>.
    Found 32-bit register for signal <sh_counter>.
    Found 5-bit register for signal <inst_reg>.
    Found 5-bit register for signal <init_address>.
    Found 8-bit register for signal <data_reg>.
    Found 8-bit register for signal <data_read>.
    Found 2-bit register for signal <sh_state>.
    Found 16-bit register for signal <shift_reg>.
    Found 1-bit register for signal <init_done>.
    Found 1-bit register for signal <init_done_tmp>.
    Found 1-bit register for signal <init_done_prev>.
    Found 1-bit register for signal <init>.
    Found 1-bit register for signal <in_reg_val>.
    Found 1-bit register for signal <inst_val>.
    Found 1-bit register for signal <inst_rw>.
    Found 1-bit register for signal <init_tmp>.
    Found 1-bit register for signal <init_reg>.
    Found 1-bit register for signal <shifting>.
    Found 1-bit register for signal <read_n_write>.
    Found 1-bit register for signal <done_sclk>.
    Found 1-bit register for signal <init_done_sclk>.
    Found 1-bit register for signal <read_byte_val>.
    Found 1-bit register for signal <sclk_ext>.
    Found 1-bit register for signal <serial_clk>.
    Found 1-bit register for signal <sdi>.
    Found 4-bit register for signal <gen_serial_clk.clk_div>.
    Found finite state machine <FSM_5> for signal <sh_state>.
    -----------------------------------------------------------------------
    | States             | 4                                              |
    | Transitions        | 8                                              |
    | Inputs             | 3                                              |
    | Outputs            | 5                                              |
    | Clock              | serial_clk (rising_edge)                       |
    | Reset              | rst (positive)                                 |
    | Reset type         | asynchronous                                   |
    | Reset State        | idle                                           |
    | Power Up State     | idle                                           |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 4-bit adder for signal <gen_serial_clk.clk_div[3]_GND_380_o_add_0_OUT> created at line 177.
    Found 5-bit adder for signal <init_address[4]_GND_380_o_add_35_OUT> created at line 417.
    Found 32-bit subtractor for signal <sh_counter[31]_GND_380_o_sub_24_OUT<31:0>> created at line 377.
    Found 1-bit tristate buffer for signal <spi_sdo> created at line 488
    Found 28-bit comparator greater for signal <n0015> created at line 268
    Found 28-bit comparator lessequal for signal <n0021> created at line 277
    Summary:
	inferred   3 Adder/Subtractor(s).
	inferred 128 D-type flip-flop(s).
	inferred   2 Comparator(s).
	inferred  17 Multiplexer(s).
	inferred   1 Tristate(s).
	inferred   1 Finite State Machine(s).
Unit <dac3283_ctrl> synthesized.

Synthesizing Unit <amc7823_ctrl>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/fmc150/amc7823_ctrl.vhd".
        START_ADDR = "0000000000000000000000000000"
        STOP_ADDR = "1111111111111111111111111111"
        g_sim = 0
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/fmc150/amc7823_ctrl.vhd" line 316: Output port <inbusy> of the instance <pulse2pulse_inst0> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/fmc150/amc7823_ctrl.vhd" line 462: Output port <inbusy> of the instance <pulse2pulse_inst1> is unconnected or connected to loadless signal.
    Found 1-bit register for signal <ncs_int>.
    Found 1-bit register for signal <mon_reset>.
    Found 32-bit register for signal <in_reg>.
    Found 32-bit register for signal <sh_counter>.
    Found 32-bit register for signal <shift_reg>.
    Found 2-bit register for signal <page_reg>.
    Found 2-bit register for signal <sh_state>.
    Found 5-bit register for signal <inst_reg>.
    Found 5-bit register for signal <init_address>.
    Found 16-bit register for signal <data_reg>.
    Found 16-bit register for signal <data_read>.
    Found 1-bit register for signal <init_done>.
    Found 1-bit register for signal <init_done_tmp>.
    Found 1-bit register for signal <init_done_prev>.
    Found 1-bit register for signal <init>.
    Found 1-bit register for signal <in_reg_val>.
    Found 1-bit register for signal <inst_val>.
    Found 1-bit register for signal <inst_rw>.
    Found 1-bit register for signal <init_tmp>.
    Found 1-bit register for signal <init_reg>.
    Found 1-bit register for signal <shifting>.
    Found 1-bit register for signal <read_n_write>.
    Found 1-bit register for signal <done_sclk>.
    Found 1-bit register for signal <init_done_sclk>.
    Found 1-bit register for signal <read_byte_val>.
    Found 1-bit register for signal <sclk_ext>.
    Found 1-bit register for signal <serial_clk>.
    Found 4-bit register for signal <gen_serial_clk.clk_div>.
    Found finite state machine <FSM_6> for signal <sh_state>.
    -----------------------------------------------------------------------
    | States             | 4                                              |
    | Transitions        | 8                                              |
    | Inputs             | 3                                              |
    | Outputs            | 5                                              |
    | Clock              | serial_clk (rising_edge)                       |
    | Reset              | rst (positive)                                 |
    | Reset type         | asynchronous                                   |
    | Reset State        | idle                                           |
    | Power Up State     | idle                                           |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 4-bit adder for signal <gen_serial_clk.clk_div[3]_GND_416_o_add_0_OUT> created at line 182.
    Found 5-bit adder for signal <init_address[4]_GND_416_o_add_39_OUT> created at line 433.
    Found 32-bit subtractor for signal <sh_counter[31]_GND_416_o_sub_28_OUT<31:0>> created at line 392.
    Found 1-bit tristate buffer for signal <spi_sdo> created at line 503
    Found 28-bit comparator greater for signal <n0017> created at line 282
    Found 28-bit comparator lessequal for signal <n0023> created at line 291
    Summary:
	inferred   3 Adder/Subtractor(s).
	inferred 162 D-type flip-flop(s).
	inferred   2 Comparator(s).
	inferred  19 Multiplexer(s).
	inferred   1 Tristate(s).
	inferred   1 Finite State Machine(s).
Unit <amc7823_ctrl> synthesized.

Synthesizing Unit <wb_slave_adapter_2>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd".
        g_master_use_struct = true
        g_master_mode = pipelined
        g_master_granularity = word
        g_slave_use_struct = false
        g_slave_mode = classic
        g_slave_granularity = byte
WARNING:Xst:647 - Input <slave_i_adr<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <slave_i_sel<3:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <slave_i_dat<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ma_dat_i<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <slave_i_cyc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <slave_i_stb> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <slave_i_we> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ma_err_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ma_rty_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ma_ack_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ma_stall_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ma_int_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:653 - Signal <ma_adr_o> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <ma_dat_o> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <ma_sel_o> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <ma_cyc_o> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <ma_stb_o> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <ma_we_o> is used but never assigned. This sourceless signal will be automatically connected to value GND.
    Found 1-bit register for signal <fsm_state>.
    Summary:
	inferred   1 D-type flip-flop(s).
	inferred   1 Multiplexer(s).
Unit <wb_slave_adapter_2> synthesized.

Synthesizing Unit <wb_fmc150_port>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_fmc150/wb_fmc150_port.vhd".
WARNING:Xst:647 - Input <wb_sel_i<3:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 6-bit register for signal <ack_sreg>.
    Found 32-bit register for signal <rddata_reg>.
    Found 32-bit register for signal <fmc150_data_in_int>.
    Found 16-bit register for signal <fmc150_addr_int>.
    Found 5-bit register for signal <fmc150_adc_dly_str_int>.
    Found 5-bit register for signal <fmc150_adc_dly_cha_int>.
    Found 5-bit register for signal <fmc150_adc_dly_chb_int>.
    Found 1-bit register for signal <ack_in_progress>.
    Found 1-bit register for signal <fmc150_flgs_pulse_int>.
    Found 1-bit register for signal <fmc150_flgs_in_spi_rw_int>.
    Found 1-bit register for signal <fmc150_flgs_in_ext_clk_int>.
    Found 1-bit register for signal <fmc150_cs_cdce72010_int>.
    Found 1-bit register for signal <fmc150_cs_ads62p49_int>.
    Found 1-bit register for signal <fmc150_cs_dac3283_int>.
    Found 1-bit register for signal <fmc150_cs_amc7823_int>.
    Found 1-bit register for signal <fmc150_flgs_pulse_dly0>.
    Found 1-bit register for signal <regs_o_flgs_pulse_o>.
    Found 32-bit 7-to-1 multiplexer for signal <rwaddr_reg[2]_X_73_o_wide_mux_10_OUT> created at line 104.
    WARNING:Xst:2404 -  FFs/Latches <ack_sreg<9:9>> (without init value) have a constant value of 0 in block <wb_fmc150_port>.
    WARNING:Xst:2404 -  FFs/Latches <ack_sreg<8:8>> (without init value) have a constant value of 0 in block <wb_fmc150_port>.
    WARNING:Xst:2404 -  FFs/Latches <ack_sreg<7:7>> (without init value) have a constant value of 0 in block <wb_fmc150_port>.
    WARNING:Xst:2404 -  FFs/Latches <ack_sreg<6:6>> (without init value) have a constant value of 0 in block <wb_fmc150_port>.
    Summary:
	inferred 111 D-type flip-flop(s).
	inferred   8 Multiplexer(s).
Unit <wb_fmc150_port> synthesized.

Synthesizing Unit <reset_synch>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_common/reset_synch/reset_synch.vhd".
    Found 1-bit register for signal <rst_n_o>.
    Found 1-bit register for signal <s_ff>.
    Summary:
	inferred   2 D-type flip-flop(s).
Unit <reset_synch> synthesized.

Synthesizing Unit <xwb_stream_source>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_stream/xwb_stream_source.vhd".
WARNING:Xst:647 - Input <src_i_ack> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <src_i_err> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <src_i_rty> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/modules/dbe_wishbone/wb_stream/xwb_stream_source.vhd" line 96: Output port <full_o> of the instance <cmp_fifo> is unconnected or connected to loadless signal.
WARNING:Xst:653 - Signal <err_status_match_class> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <err_status_is_hp> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <err_status_has_smac> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <err_status_has_crc> is used but never assigned. This sourceless signal will be automatically connected to value GND.
    Found 1-bit register for signal <cyc_int>.
    Summary:
	inferred   1 D-type flip-flop(s).
	inferred   1 Multiplexer(s).
Unit <xwb_stream_source> synthesized.

Synthesizing Unit <generic_shiftreg_fifo>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/genrams/generic_shiftreg_fifo.vhd".
        g_data_width = 43
        g_size = 32
    Found 43-bit register for signal <fifo_store<30>>.
    Found 43-bit register for signal <fifo_store<29>>.
    Found 43-bit register for signal <fifo_store<28>>.
    Found 43-bit register for signal <fifo_store<27>>.
    Found 43-bit register for signal <fifo_store<26>>.
    Found 43-bit register for signal <fifo_store<25>>.
    Found 43-bit register for signal <fifo_store<24>>.
    Found 43-bit register for signal <fifo_store<23>>.
    Found 43-bit register for signal <fifo_store<22>>.
    Found 43-bit register for signal <fifo_store<21>>.
    Found 43-bit register for signal <fifo_store<20>>.
    Found 43-bit register for signal <fifo_store<19>>.
    Found 43-bit register for signal <fifo_store<18>>.
    Found 43-bit register for signal <fifo_store<17>>.
    Found 43-bit register for signal <fifo_store<16>>.
    Found 43-bit register for signal <fifo_store<15>>.
    Found 43-bit register for signal <fifo_store<14>>.
    Found 43-bit register for signal <fifo_store<13>>.
    Found 43-bit register for signal <fifo_store<12>>.
    Found 43-bit register for signal <fifo_store<11>>.
    Found 43-bit register for signal <fifo_store<10>>.
    Found 43-bit register for signal <fifo_store<9>>.
    Found 43-bit register for signal <fifo_store<8>>.
    Found 43-bit register for signal <fifo_store<7>>.
    Found 43-bit register for signal <fifo_store<6>>.
    Found 43-bit register for signal <fifo_store<5>>.
    Found 43-bit register for signal <fifo_store<4>>.
    Found 43-bit register for signal <fifo_store<3>>.
    Found 43-bit register for signal <fifo_store<2>>.
    Found 43-bit register for signal <fifo_store<1>>.
    Found 43-bit register for signal <fifo_store<0>>.
    Found 1-bit register for signal <empty>.
    Found 5-bit register for signal <pointer>.
    Found 43-bit register for signal <fifo_store<31>>.
    Found 5-bit adder for signal <pointer[4]_GND_462_o_add_65_OUT> created at line 142.
    Found 5-bit subtractor for signal <GND_462_o_GND_462_o_sub_67_OUT<4:0>> created at line 144.
INFO:Xst:3019 - HDL ADVISOR - 1376 flip-flops were inferred for signal <fifo_store>. You may be trying to describe a RAM in a way that is incompatible with block and distributed RAM resources available on Xilinx devices, or with a specific template that is not supported. Please review the Xilinx resources documentation and the XST user manual for coding guidelines. Taking advantage of RAM resources will lead to improved device usage and reduced synthesis time.
    Found 43-bit 32-to-1 multiplexer for signal <q_o> created at line 109.
    Summary:
	inferred   1 Adder/Subtractor(s).
	inferred 1382 D-type flip-flop(s).
	inferred   1 Multiplexer(s).
Unit <generic_shiftreg_fifo> synthesized.

Synthesizing Unit <xwb_simple_uart>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd".
        g_with_virtual_uart = false
        g_with_physical_uart = true
        g_interface_mode = pipelined
        g_address_granularity = byte
WARNING:Xst:647 - Input <slave_i_adr<31:5>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:653 - Signal <desc_o> is used but never assigned. This sourceless signal will be automatically connected to value GND.
    Summary:
	no macro.
Unit <xwb_simple_uart> synthesized.

Synthesizing Unit <wb_simple_uart>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd".
        g_with_virtual_uart = false
        g_with_physical_uart = true
        g_interface_mode = pipelined
        g_address_granularity = byte
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 152: Output port <slave_o_dat> of the instance <U_Adapter> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 152: Output port <ma_adr_o> of the instance <U_Adapter> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 152: Output port <ma_dat_o> of the instance <U_Adapter> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 152: Output port <ma_sel_o> of the instance <U_Adapter> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 152: Output port <sl_err_o> of the instance <U_Adapter> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 152: Output port <sl_rty_o> of the instance <U_Adapter> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 152: Output port <sl_int_o> of the instance <U_Adapter> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 152: Output port <slave_o_ack> of the instance <U_Adapter> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 152: Output port <slave_o_err> of the instance <U_Adapter> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 152: Output port <slave_o_rty> of the instance <U_Adapter> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 152: Output port <slave_o_stall> of the instance <U_Adapter> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 152: Output port <slave_o_int> of the instance <U_Adapter> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 152: Output port <ma_cyc_o> of the instance <U_Adapter> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 152: Output port <ma_stb_o> of the instance <U_Adapter> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 152: Output port <ma_we_o> of the instance <U_Adapter> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 175: Output port <regs_o_host_tdr_data_o> of the instance <U_WB_SLAVE> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 175: Output port <host_rack_o> of the instance <U_WB_SLAVE> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" line 226: Output port <rx_error_o> of the instance <gen_phys_uart.U_RX> is unconnected or connected to loadless signal.
WARNING:Xst:653 - Signal <regs_in_host_rdr_data_i> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <regs_in_host_rdr_count_i> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <wb_out_err> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <wb_out_rty> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <wb_out_stall> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <wb_out_int> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <regs_in_host_tdr_rdy_i> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <regs_in_host_rdr_rdy_i> is used but never assigned. This sourceless signal will be automatically connected to value GND.
    Found 1-bit register for signal <regs_in_sr_rx_rdy_i>.
    Found 8-bit register for signal <regs_in_rdr_rx_data_i>.
    Found 32-bit register for signal <uart_bcr>.
    Summary:
	inferred  41 D-type flip-flop(s).
Unit <wb_simple_uart> synthesized.

Synthesizing Unit <wb_slave_adapter_3>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd".
        g_master_use_struct = true
        g_master_mode = classic
        g_master_granularity = word
        g_slave_use_struct = false
        g_slave_mode = pipelined
        g_slave_granularity = byte
WARNING:Xst:647 - Input <slave_i_adr<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <slave_i_sel<3:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <slave_i_dat<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ma_dat_i<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <slave_i_cyc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <slave_i_stb> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <slave_i_we> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ma_err_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ma_rty_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ma_ack_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ma_stall_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ma_int_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <master_i_stall> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:653 - Signal <ma_adr_o> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <ma_dat_o> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <ma_sel_o> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <ma_cyc_o> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <ma_stb_o> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <ma_we_o> is used but never assigned. This sourceless signal will be automatically connected to value GND.
    Found 1-bit register for signal <stored_we>.
    Found 1-bit register for signal <fsm_state>.
    Summary:
	inferred   2 D-type flip-flop(s).
	inferred   3 Multiplexer(s).
Unit <wb_slave_adapter_3> synthesized.

Synthesizing Unit <simple_uart_wb>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd".
WARNING:Xst:647 - Input <wb_sel_i<3:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 7-bit register for signal <ack_sreg>.
    Found 32-bit register for signal <rddata_reg>.
    Found 1-bit register for signal <ack_in_progress>.
    Found 1-bit register for signal <regs_o_bcr_wr_o>.
    Found 1-bit register for signal <regs_o_tdr_tx_data_wr_o>.
    Found 1-bit register for signal <regs_o_host_tdr_data_wr_o>.
    Found 1-bit register for signal <rdr_rack_o>.
    Found 1-bit register for signal <host_rack_o>.
    WARNING:Xst:2404 -  FFs/Latches <ack_sreg<9:9>> (without init value) have a constant value of 0 in block <simple_uart_wb>.
    WARNING:Xst:2404 -  FFs/Latches <ack_sreg<8:8>> (without init value) have a constant value of 0 in block <simple_uart_wb>.
    WARNING:Xst:2404 -  FFs/Latches <ack_sreg<7:7>> (without init value) have a constant value of 0 in block <simple_uart_wb>.
    Summary:
	inferred  45 D-type flip-flop(s).
	inferred   8 Multiplexer(s).
Unit <simple_uart_wb> synthesized.

Synthesizing Unit <uart_baud_gen>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd".
        g_baud_acc_width = 16
    Found 8-bit register for signal <Baud_sreg>.
    Found 17-bit register for signal <Baud8GeneratorAcc>.
    Found 17-bit adder for signal <GND_505_o_Baud8GeneratorInc[16]_add_1_OUT> created at line 39.
    Summary:
	inferred   1 Adder/Subtractor(s).
	inferred  25 D-type flip-flop(s).
	inferred   1 Multiplexer(s).
Unit <uart_baud_gen> synthesized.

Synthesizing Unit <uart_async_tx>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd".
    Found 4-bit register for signal <state>.
    Found 1-bit register for signal <TxD>.
    Found 8-bit register for signal <TxD_dataReg>.
    Found finite state machine <FSM_7> for signal <state>.
    -----------------------------------------------------------------------
    | States             | 13                                             |
    | Transitions        | 26                                             |
    | Inputs             | 2                                              |
    | Outputs            | 6                                              |
    | Clock              | clk_sys_i (rising_edge)                        |
    | Reset              | rst_n_i_INV_518_o (positive)                   |
    | Reset type         | synchronous                                    |
    | Reset State        | 0000                                           |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 1-bit 8-to-1 multiplexer for signal <muxbit> created at line 130.
    Summary:
	inferred   9 D-type flip-flop(s).
	inferred   1 Multiplexer(s).
	inferred   1 Finite State Machine(s).
Unit <uart_async_tx> synthesized.

Synthesizing Unit <uart_async_rx>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd".
    Found 1-bit register for signal <RxD_bit_inv>.
    Found 2-bit register for signal <RxD_cnt_inv>.
    Found 4-bit register for signal <bit_spacing>.
    Found 4-bit register for signal <state>.
    Found 8-bit register for signal <RxD_data>.
    Found 1-bit register for signal <RxD_data_error>.
    Found 1-bit register for signal <RxD_data_ready>.
    Found 2-bit register for signal <RxD_sync_inv>.
    Found finite state machine <FSM_8> for signal <state>.
    -----------------------------------------------------------------------
    | States             | 10                                             |
    | Transitions        | 30                                             |
    | Inputs             | 3                                              |
    | Outputs            | 3                                              |
    | Clock              | clk_sys_i (rising_edge)                        |
    | Reset              | rst_n_i_INV_528_o (positive)                   |
    | Reset type         | synchronous                                    |
    | Reset State        | 0000                                           |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 2-bit adder for signal <RxD_cnt_inv[1]_GND_507_o_add_4_OUT> created at line 1241.
    Found 4-bit adder for signal <GND_507_o_GND_507_o_add_16_OUT> created at line 1241.
    Found 2-bit subtractor for signal <GND_507_o_GND_507_o_sub_7_OUT<1:0>> created at line 1308.
    Summary:
	inferred   2 Adder/Subtractor(s).
	inferred  19 D-type flip-flop(s).
	inferred   1 Multiplexer(s).
	inferred   1 Finite State Machine(s).
Unit <uart_async_rx> synthesized.

Synthesizing Unit <xwb_gpio_port>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd".
        g_interface_mode = classic
        g_address_granularity = byte
        g_num_pins = 8
        g_with_builtin_tristates = false
WARNING:Xst:647 - Input <slave_i_adr<31:8>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:653 - Signal <desc_o> is used but never assigned. This sourceless signal will be automatically connected to value GND.
    Summary:
	no macro.
Unit <xwb_gpio_port> synthesized.

Synthesizing Unit <wb_gpio_port>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd".
        g_interface_mode = classic
        g_address_granularity = byte
        g_num_pins = 8
        g_with_builtin_tristates = false
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 97: Output port <slave_o_dat> of the instance <U_Adapter> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 97: Output port <ma_adr_o> of the instance <U_Adapter> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 97: Output port <ma_dat_o> of the instance <U_Adapter> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 97: Output port <ma_sel_o> of the instance <U_Adapter> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 97: Output port <sl_err_o> of the instance <U_Adapter> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 97: Output port <sl_rty_o> of the instance <U_Adapter> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 97: Output port <sl_int_o> of the instance <U_Adapter> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 97: Output port <slave_o_ack> of the instance <U_Adapter> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 97: Output port <slave_o_err> of the instance <U_Adapter> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 97: Output port <slave_o_rty> of the instance <U_Adapter> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 97: Output port <slave_o_stall> of the instance <U_Adapter> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 97: Output port <slave_o_int> of the instance <U_Adapter> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 97: Output port <ma_cyc_o> of the instance <U_Adapter> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 97: Output port <ma_stb_o> of the instance <U_Adapter> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 97: Output port <ma_we_o> of the instance <U_Adapter> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 123: Output port <npulse_o> of the instance <GEN_SYNC_FFS[0].INPUT_SYNC> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 123: Output port <ppulse_o> of the instance <GEN_SYNC_FFS[0].INPUT_SYNC> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 123: Output port <npulse_o> of the instance <GEN_SYNC_FFS[1].INPUT_SYNC> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 123: Output port <ppulse_o> of the instance <GEN_SYNC_FFS[1].INPUT_SYNC> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 123: Output port <npulse_o> of the instance <GEN_SYNC_FFS[2].INPUT_SYNC> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 123: Output port <ppulse_o> of the instance <GEN_SYNC_FFS[2].INPUT_SYNC> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 123: Output port <npulse_o> of the instance <GEN_SYNC_FFS[3].INPUT_SYNC> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 123: Output port <ppulse_o> of the instance <GEN_SYNC_FFS[3].INPUT_SYNC> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 123: Output port <npulse_o> of the instance <GEN_SYNC_FFS[4].INPUT_SYNC> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 123: Output port <ppulse_o> of the instance <GEN_SYNC_FFS[4].INPUT_SYNC> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 123: Output port <npulse_o> of the instance <GEN_SYNC_FFS[5].INPUT_SYNC> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 123: Output port <ppulse_o> of the instance <GEN_SYNC_FFS[5].INPUT_SYNC> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 123: Output port <npulse_o> of the instance <GEN_SYNC_FFS[6].INPUT_SYNC> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 123: Output port <ppulse_o> of the instance <GEN_SYNC_FFS[6].INPUT_SYNC> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 123: Output port <npulse_o> of the instance <GEN_SYNC_FFS[7].INPUT_SYNC> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" line 123: Output port <ppulse_o> of the instance <GEN_SYNC_FFS[7].INPUT_SYNC> is unconnected or connected to loadless signal.
WARNING:Xst:2563 - Inout <gpio_b> is never assigned. Tied to value Z.
WARNING:Xst:653 - Signal <gpio_in_synced<31:8>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
    Found 32-bit register for signal <out_reg>.
    Found 32-bit register for signal <wb_out_dat>.
    Found 1-bit register for signal <ack_int>.
    Found 32-bit register for signal <dir_reg>.
    Found 8x1-bit Read Only RAM for signal <write_mask<0>>
    Found 8-bit tristate buffer for signal <gpio_b> created at line 56
    Summary:
	inferred   1 RAM(s).
	inferred  97 D-type flip-flop(s).
	inferred   8 Multiplexer(s).
	inferred   1 Tristate(s).
Unit <wb_gpio_port> synthesized.

Synthesizing Unit <wb_slave_adapter_4>.
    Related source file is "/home/lerwys/Repos/bpm-sw/hdl/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd".
        g_master_use_struct = true
        g_master_mode = classic
        g_master_granularity = word
        g_slave_use_struct = false
        g_slave_mode = classic
        g_slave_granularity = byte
WARNING:Xst:647 - Input <slave_i_adr<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <slave_i_sel<3:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <slave_i_dat<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ma_dat_i<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clk_sys_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <rst_n_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <slave_i_cyc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <slave_i_stb> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <slave_i_we> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ma_err_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ma_rty_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ma_ack_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ma_stall_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ma_int_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:653 - Signal <ma_adr_o> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <ma_dat_o> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <ma_sel_o> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <ma_cyc_o> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <ma_stb_o> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <ma_we_o> is used but never assigned. This sourceless signal will be automatically connected to value GND.
    Summary:
	no macro.
Unit <wb_slave_adapter_4> synthesized.

=========================================================================
HDL Synthesis Report

Macro Statistics
# RAMs                                                 : 9
 1024x32-bit dual-port RAM                             : 1
 128x32-bit single-port Read Only RAM                  : 1
 16x32-bit dual-port RAM                               : 1
 22528x32-bit dual-port RAM                            : 1
 256x20-bit dual-port RAM                              : 1
 32x32-bit dual-port RAM                               : 2
 8x1-bit single-port Read Only RAM                     : 2
# Multipliers                                          : 3
 16x16-bit multiplier                                  : 3
# Adders/Subtractors                                   : 43
 10-bit adder                                          : 2
 16-bit adder                                          : 3
 17-bit adder                                          : 1
 2-bit adder                                           : 2
 2-bit addsub                                          : 1
 2-bit subtractor                                      : 1
 29-bit adder                                          : 2
 3-bit subtractor                                      : 1
 32-bit adder                                          : 4
 32-bit subtractor                                     : 6
 33-bit adder                                          : 2
 33-bit subtractor                                     : 2
 4-bit adder                                           : 6
 5-bit adder                                           : 8
 5-bit addsub                                          : 1
 8-bit subtractor                                      : 1
# Registers                                            : 752
 1-bit register                                        : 543
 10-bit register                                       : 3
 11-bit register                                       : 3
 16-bit register                                       : 11
 17-bit register                                       : 1
 2-bit register                                        : 7
 23-bit register                                       : 2
 28-bit register                                       : 10
 29-bit register                                       : 9
 3-bit register                                        : 5
 32-bit register                                       : 63
 4-bit register                                        : 12
 43-bit register                                       : 32
 5-bit register                                        : 20
 6-bit register                                        : 1
 62-bit register                                       : 1
 64-bit register                                       : 4
 7-bit register                                        : 2
 8-bit register                                        : 19
 9-bit register                                        : 4
# Comparators                                          : 28
 1-bit comparator equal                                : 1
 10-bit comparator greater                             : 1
 20-bit comparator equal                               : 1
 28-bit comparator greater                             : 4
 28-bit comparator lessequal                           : 4
 32-bit comparator equal                               : 5
 4-bit comparator equal                                : 1
 5-bit comparator equal                                : 8
 5-bit comparator not equal                            : 3
# Multiplexers                                         : 651
 1-bit 2-to-1 multiplexer                              : 435
 1-bit 4-to-1 multiplexer                              : 32
 1-bit 8-to-1 multiplexer                              : 2
 10-bit 2-to-1 multiplexer                             : 1
 11-bit 2-to-1 multiplexer                             : 2
 16-bit 2-to-1 multiplexer                             : 4
 2-bit 2-to-1 multiplexer                              : 5
 23-bit 2-to-1 multiplexer                             : 2
 28-bit 2-to-1 multiplexer                             : 1
 29-bit 2-to-1 multiplexer                             : 7
 3-bit 2-to-1 multiplexer                              : 6
 32-bit 2-to-1 multiplexer                             : 102
 32-bit 3-to-1 multiplexer                             : 3
 32-bit 7-to-1 multiplexer                             : 2
 4-bit 2-to-1 multiplexer                              : 6
 43-bit 32-to-1 multiplexer                            : 1
 5-bit 2-to-1 multiplexer                              : 13
 64-bit 2-to-1 multiplexer                             : 8
 8-bit 2-to-1 multiplexer                              : 14
 8-bit 4-to-1 multiplexer                              : 1
 9-bit 2-to-1 multiplexer                              : 4
# Logic shifters                                       : 1
 64-bit shifter logical right                          : 1
# Tristates                                            : 6
 1-bit tristate buffer                                 : 4
 8-bit tristate buffer                                 : 2
# FSMs                                                 : 9
# Xors                                                 : 101
 1-bit xor2                                            : 69
 32-bit xor2                                           : 32

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Reading core <../../platform/virtex6/chipscope/chipscope_ila.ngc>.
Reading core <../../platform/virtex6/chipscope/icon_2_port/chipscope_icon_2_port.ngc>.
Reading core <../../modules/dbe_wishbone/wb_fmc150/netlist/cdce72010_init_mem_int.ngc>.
Reading core <../../modules/dbe_wishbone/wb_fmc150/netlist/cdce72010_init_mem_ext.ngc>.
Reading core <../../modules/dbe_wishbone/wb_fmc150/netlist/ads62p49_init_mem.ngc>.
Reading core <../../modules/dbe_wishbone/wb_fmc150/netlist/dac3283_init_mem.ngc>.
Reading core <../../modules/dbe_wishbone/wb_fmc150/netlist/amc7823_init_mem.ngc>.
Loading core <chipscope_ila> for timing and area information for instance <cmp_chipscope_ila_0>.
Loading core <chipscope_ila> for timing and area information for instance <cmp_chipscope_ila_1>.
Loading core <chipscope_icon_2_port> for timing and area information for instance <cmp_chipscope_icon_0>.
Loading core <cdce72010_init_mem_int> for timing and area information for instance <cdce72010_init_mem_int_inst>.
Loading core <cdce72010_init_mem_ext> for timing and area information for instance <cdce72010_init_mem_ext_inst>.
Loading core <ads62p49_init_mem> for timing and area information for instance <ads62p49_init_mem_inst>.
Loading core <dac3283_init_mem> for timing and area information for instance <dac3283_init_mem_inst>.
Loading core <amc7823_init_mem> for timing and area information for instance <amc7823_init_mem_inst>.
INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1
INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1
INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1
INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1
INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1
INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1
INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1
INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1
INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1
INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1
INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1
INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1
INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1
INFO:Xst:1901 - Instance U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36 in unit U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36 of type RAMB36 has been replaced by RAMB36E1
INFO:Xst:2261 - The FF/Latch <gen_serial_clk.clk_div_3> in Unit <cdce72010_ctrl_inst> is equivalent to the following FF/Latch, which will be removed : <sclk_ext> 
INFO:Xst:2261 - The FF/Latch <gen_serial_clk.clk_div_3> in Unit <ads62p49_ctrl_inst> is equivalent to the following FF/Latch, which will be removed : <serial_clk> 
INFO:Xst:2261 - The FF/Latch <gen_serial_clk.clk_div_3> in Unit <dac3283_ctrl_inst> is equivalent to the following FF/Latch, which will be removed : <sclk_ext> 
INFO:Xst:2261 - The FF/Latch <gen_serial_clk.clk_div_3> in Unit <amc7823_ctrl_inst> is equivalent to the following FF/Latch, which will be removed : <sclk_ext> 
INFO:Xst:2261 - The FF/Latch <in_cmd_48> in Unit <cmp_fmc150_ctrl> is equivalent to the following 11 FFs/Latches, which will be removed : <in_cmd_49> <in_cmd_50> <in_cmd_51> <in_cmd_52> <in_cmd_53> <in_cmd_54> <in_cmd_55> <in_cmd_56> <in_cmd_57> <in_cmd_58> <in_cmd_59> 
INFO:Xst:2261 - The FF/Latch <adc_dout_b_13> in Unit <cmp_fmc150_testbench> is equivalent to the following 2 FFs/Latches, which will be removed : <adc_dout_b_14> <adc_dout_b_15> 
INFO:Xst:2261 - The FF/Latch <adc_dout_a_13> in Unit <cmp_fmc150_testbench> is equivalent to the following 2 FFs/Latches, which will be removed : <adc_dout_a_14> <adc_dout_a_15> 
INFO:Xst:2261 - The FF/Latch <i_dat_o_0> in Unit <instruction_unit> is equivalent to the following 3 FFs/Latches, which will be removed : <i_dat_o_8> <i_dat_o_16> <i_dat_o_24> 
INFO:Xst:2261 - The FF/Latch <i_dat_o_1> in Unit <instruction_unit> is equivalent to the following 3 FFs/Latches, which will be removed : <i_dat_o_9> <i_dat_o_17> <i_dat_o_25> 
INFO:Xst:2261 - The FF/Latch <i_dat_o_2> in Unit <instruction_unit> is equivalent to the following 3 FFs/Latches, which will be removed : <i_dat_o_10> <i_dat_o_18> <i_dat_o_26> 
INFO:Xst:2261 - The FF/Latch <i_dat_o_3> in Unit <instruction_unit> is equivalent to the following 3 FFs/Latches, which will be removed : <i_dat_o_11> <i_dat_o_19> <i_dat_o_27> 
INFO:Xst:2261 - The FF/Latch <i_dat_o_4> in Unit <instruction_unit> is equivalent to the following 3 FFs/Latches, which will be removed : <i_dat_o_12> <i_dat_o_20> <i_dat_o_28> 
INFO:Xst:2261 - The FF/Latch <i_dat_o_5> in Unit <instruction_unit> is equivalent to the following 3 FFs/Latches, which will be removed : <i_dat_o_13> <i_dat_o_21> <i_dat_o_29> 
INFO:Xst:2261 - The FF/Latch <i_dat_o_6> in Unit <instruction_unit> is equivalent to the following 3 FFs/Latches, which will be removed : <i_dat_o_14> <i_dat_o_22> <i_dat_o_30> 
INFO:Xst:2261 - The FF/Latch <i_dat_o_7> in Unit <instruction_unit> is equivalent to the following 3 FFs/Latches, which will be removed : <i_dat_o_15> <i_dat_o_23> <i_dat_o_31> 
WARNING:Xst:1710 - FF/Latch <fifo_store_0_39> (without init value) has a constant value of 1 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <fifo_store_0_40> (without init value) has a constant value of 1 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <jtag_shift_10> (without init value) has a constant value of 0 in block <jtag_cores>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <jtag_shift_9> (without init value) has a constant value of 0 in block <jtag_cores>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <jtag_shift_8> (without init value) has a constant value of 0 in block <jtag_cores>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <jtag_shift_7> (without init value) has a constant value of 0 in block <jtag_cores>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <jtag_shift_6> (without init value) has a constant value of 0 in block <jtag_cores>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <jtag_shift_5> (without init value) has a constant value of 0 in block <jtag_cores>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <jtag_shift_4> (without init value) has a constant value of 0 in block <jtag_cores>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <jtag_shift_3> (without init value) has a constant value of 0 in block <jtag_cores>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <jtag_shift_2> (without init value) has a constant value of 0 in block <jtag_cores>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <jtag_shift_1> (without init value) has a constant value of 0 in block <jtag_cores>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <jtag_shift_0> (without init value) has a constant value of 0 in block <jtag_cores>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <i_dat_o_7> (without init value) has a constant value of 0 in block <instruction_unit>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <i_dat_o_6> (without init value) has a constant value of 0 in block <instruction_unit>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <i_dat_o_5> (without init value) has a constant value of 0 in block <instruction_unit>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <i_dat_o_4> (without init value) has a constant value of 0 in block <instruction_unit>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <i_dat_o_3> (without init value) has a constant value of 0 in block <instruction_unit>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <i_dat_o_2> (without init value) has a constant value of 0 in block <instruction_unit>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <i_dat_o_1> (without init value) has a constant value of 0 in block <instruction_unit>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <in_reg_addr_sig_27> (without init value) has a constant value of 0 in block <fmc150_stellar_cmd_inst>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <out_reg_addr_16> (without init value) has a constant value of 0 in block <fmc150_stellar_cmd_inst>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <out_reg_addr_17> (without init value) has a constant value of 0 in block <fmc150_stellar_cmd_inst>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <out_reg_addr_18> (without init value) has a constant value of 0 in block <fmc150_stellar_cmd_inst>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <out_reg_addr_19> (without init value) has a constant value of 0 in block <fmc150_stellar_cmd_inst>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <out_reg_addr_20> (without init value) has a constant value of 0 in block <fmc150_stellar_cmd_inst>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <out_reg_addr_21> (without init value) has a constant value of 0 in block <fmc150_stellar_cmd_inst>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <out_reg_addr_22> (without init value) has a constant value of 0 in block <fmc150_stellar_cmd_inst>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <out_reg_addr_23> (without init value) has a constant value of 0 in block <fmc150_stellar_cmd_inst>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <out_reg_addr_24> (without init value) has a constant value of 0 in block <fmc150_stellar_cmd_inst>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <out_reg_addr_25> (without init value) has a constant value of 0 in block <fmc150_stellar_cmd_inst>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <out_reg_addr_26> (without init value) has a constant value of 0 in block <fmc150_stellar_cmd_inst>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <out_reg_addr_27> (without init value) has a constant value of 0 in block <fmc150_stellar_cmd_inst>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <in_cmd_48> (without init value) has a constant value of 0 in block <cmp_fmc150_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ack_sreg_5> (without init value) has a constant value of 0 in block <cmp_wb_fmc150_port>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <fifo_store_0_32> (without init value) has a constant value of 0 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <fifo_store_0_33> (without init value) has a constant value of 0 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <fifo_store_0_34> (without init value) has a constant value of 0 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <fifo_store_0_35> (without init value) has a constant value of 0 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <fifo_store_0_37> (without init value) has a constant value of 1 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <fifo_store_0_38> (without init value) has a constant value of 1 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <jtag_byte_1_2> (without init value) has a constant value of 0 in block <jtag>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <jtag_byte_1_1> (without init value) has a constant value of 0 in block <jtag>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <jtag_byte_1_0> (without init value) has a constant value of 0 in block <jtag>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <jtag_byte_4_7> (without init value) has a constant value of 0 in block <jtag>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <jtag_byte_4_6> (without init value) has a constant value of 0 in block <jtag>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <jtag_byte_4_5> (without init value) has a constant value of 0 in block <jtag>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <jtag_byte_4_4> (without init value) has a constant value of 0 in block <jtag>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <jtag_byte_4_3> (without init value) has a constant value of 0 in block <jtag>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <jtag_byte_4_2> (without init value) has a constant value of 0 in block <jtag>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <jtag_byte_4_1> (without init value) has a constant value of 0 in block <jtag>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <jtag_byte_4_0> (without init value) has a constant value of 0 in block <jtag>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <jtag_byte_0_7> (without init value) has a constant value of 0 in block <jtag>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <jtag_byte_0_6> (without init value) has a constant value of 0 in block <jtag>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <jtag_byte_0_5> (without init value) has a constant value of 0 in block <jtag>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <jtag_byte_0_4> (without init value) has a constant value of 0 in block <jtag>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <jtag_byte_0_3> (without init value) has a constant value of 0 in block <jtag>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <jtag_byte_0_2> (without init value) has a constant value of 0 in block <jtag>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <jtag_byte_0_1> (without init value) has a constant value of 0 in block <jtag>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <jtag_byte_0_0> (without init value) has a constant value of 0 in block <jtag>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ack_sreg_6> (without init value) has a constant value of 0 in block <U_WB_SLAVE>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <i_dat_o_0> (without init value) has a constant value of 0 in block <instruction_unit>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <jtag_reset> (without init value) has a constant value of 0 in block <jtag>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <jtag_break> (without init value) has a constant value of 0 in block <jtag>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <command_3> (without init value) has a constant value of 0 in block <jtag>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <command_2> (without init value) has a constant value of 0 in block <jtag>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <command_1> (without init value) has a constant value of 0 in block <jtag>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <command_0> (without init value) has a constant value of 0 in block <jtag>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <rx_update> (without init value) has a constant value of 0 in block <jtag>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <uart_rx_byte_7> (without init value) has a constant value of 0 in block <jtag>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <uart_rx_byte_6> (without init value) has a constant value of 0 in block <jtag>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <uart_rx_byte_5> (without init value) has a constant value of 0 in block <jtag>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <uart_rx_byte_4> (without init value) has a constant value of 0 in block <jtag>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <uart_rx_byte_3> (without init value) has a constant value of 0 in block <jtag>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <uart_rx_byte_2> (without init value) has a constant value of 0 in block <jtag>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <uart_rx_byte_1> (without init value) has a constant value of 0 in block <jtag>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <uart_rx_byte_0> (without init value) has a constant value of 0 in block <jtag>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <jtag_byte_1_7> (without init value) has a constant value of 0 in block <jtag>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <jtag_byte_1_6> (without init value) has a constant value of 0 in block <jtag>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <jtag_byte_1_5> (without init value) has a constant value of 0 in block <jtag>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <jtag_byte_1_4> (without init value) has a constant value of 0 in block <jtag>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <jtag_byte_1_3> (without init value) has a constant value of 0 in block <jtag>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <in_reg_addr_sig_16> (without init value) has a constant value of 0 in block <fmc150_stellar_cmd_inst>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <in_reg_addr_sig_17> (without init value) has a constant value of 0 in block <fmc150_stellar_cmd_inst>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <in_reg_addr_sig_18> (without init value) has a constant value of 0 in block <fmc150_stellar_cmd_inst>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <in_reg_addr_sig_19> (without init value) has a constant value of 0 in block <fmc150_stellar_cmd_inst>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <in_reg_addr_sig_20> (without init value) has a constant value of 0 in block <fmc150_stellar_cmd_inst>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <in_reg_addr_sig_21> (without init value) has a constant value of 0 in block <fmc150_stellar_cmd_inst>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <in_reg_addr_sig_22> (without init value) has a constant value of 0 in block <fmc150_stellar_cmd_inst>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <in_reg_addr_sig_23> (without init value) has a constant value of 0 in block <fmc150_stellar_cmd_inst>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <in_reg_addr_sig_24> (without init value) has a constant value of 0 in block <fmc150_stellar_cmd_inst>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <in_reg_addr_sig_25> (without init value) has a constant value of 0 in block <fmc150_stellar_cmd_inst>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <in_reg_addr_sig_26> (without init value) has a constant value of 0 in block <fmc150_stellar_cmd_inst>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <in_reg_addr_sig_27> (without init value) has a constant value of 0 in block <fmc150_stellar_cmd_inst>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <out_reg_addr_16> (without init value) has a constant value of 0 in block <fmc150_stellar_cmd_inst>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <out_reg_addr_17> (without init value) has a constant value of 0 in block <fmc150_stellar_cmd_inst>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <out_reg_addr_18> (without init value) has a constant value of 0 in block <fmc150_stellar_cmd_inst>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <out_reg_addr_19> (without init value) has a constant value of 0 in block <fmc150_stellar_cmd_inst>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <out_reg_addr_20> (without init value) has a constant value of 0 in block <fmc150_stellar_cmd_inst>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <out_reg_addr_21> (without init value) has a constant value of 0 in block <fmc150_stellar_cmd_inst>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <out_reg_addr_22> (without init value) has a constant value of 0 in block <fmc150_stellar_cmd_inst>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <out_reg_addr_23> (without init value) has a constant value of 0 in block <fmc150_stellar_cmd_inst>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <out_reg_addr_24> (without init value) has a constant value of 0 in block <fmc150_stellar_cmd_inst>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <out_reg_addr_25> (without init value) has a constant value of 0 in block <fmc150_stellar_cmd_inst>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <out_reg_addr_26> (without init value) has a constant value of 0 in block <fmc150_stellar_cmd_inst>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <in_reg_addr_sig_16> (without init value) has a constant value of 0 in block <fmc150_stellar_cmd_inst>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <in_reg_addr_sig_17> (without init value) has a constant value of 0 in block <fmc150_stellar_cmd_inst>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <in_reg_addr_sig_18> (without init value) has a constant value of 0 in block <fmc150_stellar_cmd_inst>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <in_reg_addr_sig_19> (without init value) has a constant value of 0 in block <fmc150_stellar_cmd_inst>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <in_reg_addr_sig_20> (without init value) has a constant value of 0 in block <fmc150_stellar_cmd_inst>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <in_reg_addr_sig_21> (without init value) has a constant value of 0 in block <fmc150_stellar_cmd_inst>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <in_reg_addr_sig_22> (without init value) has a constant value of 0 in block <fmc150_stellar_cmd_inst>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <in_reg_addr_sig_23> (without init value) has a constant value of 0 in block <fmc150_stellar_cmd_inst>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <in_reg_addr_sig_24> (without init value) has a constant value of 0 in block <fmc150_stellar_cmd_inst>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <in_reg_addr_sig_25> (without init value) has a constant value of 0 in block <fmc150_stellar_cmd_inst>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <in_reg_addr_sig_26> (without init value) has a constant value of 0 in block <fmc150_stellar_cmd_inst>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <in_reg_addr_sig_27> (without init value) has a constant value of 0 in block <fmc150_stellar_cmd_inst>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <out_reg_addr_16> (without init value) has a constant value of 0 in block <fmc150_stellar_cmd_inst>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <out_reg_addr_17> (without init value) has a constant value of 0 in block <fmc150_stellar_cmd_inst>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <out_reg_addr_18> (without init value) has a constant value of 0 in block <fmc150_stellar_cmd_inst>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <out_reg_addr_19> (without init value) has a constant value of 0 in block <fmc150_stellar_cmd_inst>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <out_reg_addr_20> (without init value) has a constant value of 0 in block <fmc150_stellar_cmd_inst>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <out_reg_addr_21> (without init value) has a constant value of 0 in block <fmc150_stellar_cmd_inst>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <out_reg_addr_22> (without init value) has a constant value of 0 in block <fmc150_stellar_cmd_inst>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <out_reg_addr_23> (without init value) has a constant value of 0 in block <fmc150_stellar_cmd_inst>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <out_reg_addr_24> (without init value) has a constant value of 0 in block <fmc150_stellar_cmd_inst>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <out_reg_addr_25> (without init value) has a constant value of 0 in block <fmc150_stellar_cmd_inst>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <out_reg_addr_26> (without init value) has a constant value of 0 in block <fmc150_stellar_cmd_inst>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <out_reg_addr_27> (without init value) has a constant value of 0 in block <fmc150_stellar_cmd_inst>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <out_reg_addr_16> (without init value) has a constant value of 0 in block <fmc150_stellar_cmd_inst>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <out_reg_addr_17> (without init value) has a constant value of 0 in block <fmc150_stellar_cmd_inst>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <out_reg_addr_18> (without init value) has a constant value of 0 in block <fmc150_stellar_cmd_inst>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <out_reg_addr_19> (without init value) has a constant value of 0 in block <fmc150_stellar_cmd_inst>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <out_reg_addr_20> (without init value) has a constant value of 0 in block <fmc150_stellar_cmd_inst>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <out_reg_addr_21> (without init value) has a constant value of 0 in block <fmc150_stellar_cmd_inst>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <out_reg_addr_22> (without init value) has a constant value of 0 in block <fmc150_stellar_cmd_inst>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <out_reg_addr_23> (without init value) has a constant value of 0 in block <fmc150_stellar_cmd_inst>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <out_reg_addr_24> (without init value) has a constant value of 0 in block <fmc150_stellar_cmd_inst>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <out_reg_addr_25> (without init value) has a constant value of 0 in block <fmc150_stellar_cmd_inst>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <out_reg_addr_26> (without init value) has a constant value of 0 in block <fmc150_stellar_cmd_inst>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <out_reg_addr_27> (without init value) has a constant value of 0 in block <fmc150_stellar_cmd_inst>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <in_reg_addr_sig_16> (without init value) has a constant value of 0 in block <fmc150_stellar_cmd_inst>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <in_reg_addr_sig_17> (without init value) has a constant value of 0 in block <fmc150_stellar_cmd_inst>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <in_reg_addr_sig_18> (without init value) has a constant value of 0 in block <fmc150_stellar_cmd_inst>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <in_reg_addr_sig_19> (without init value) has a constant value of 0 in block <fmc150_stellar_cmd_inst>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <in_reg_addr_sig_20> (without init value) has a constant value of 0 in block <fmc150_stellar_cmd_inst>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <in_reg_addr_sig_21> (without init value) has a constant value of 0 in block <fmc150_stellar_cmd_inst>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <in_reg_addr_sig_22> (without init value) has a constant value of 0 in block <fmc150_stellar_cmd_inst>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <in_reg_addr_sig_23> (without init value) has a constant value of 0 in block <fmc150_stellar_cmd_inst>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <in_reg_addr_sig_24> (without init value) has a constant value of 0 in block <fmc150_stellar_cmd_inst>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <in_reg_addr_sig_25> (without init value) has a constant value of 0 in block <fmc150_stellar_cmd_inst>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <in_reg_addr_sig_26> (without init value) has a constant value of 0 in block <fmc150_stellar_cmd_inst>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <out_reg_addr_27> (without init value) has a constant value of 0 in block <fmc150_stellar_cmd_inst>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <in_reg_addr_sig_16> (without init value) has a constant value of 0 in block <fmc150_stellar_cmd_inst>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <in_reg_addr_sig_17> (without init value) has a constant value of 0 in block <fmc150_stellar_cmd_inst>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <in_reg_addr_sig_18> (without init value) has a constant value of 0 in block <fmc150_stellar_cmd_inst>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <in_reg_addr_sig_19> (without init value) has a constant value of 0 in block <fmc150_stellar_cmd_inst>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <in_reg_addr_sig_20> (without init value) has a constant value of 0 in block <fmc150_stellar_cmd_inst>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <in_reg_addr_sig_21> (without init value) has a constant value of 0 in block <fmc150_stellar_cmd_inst>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <in_reg_addr_sig_22> (without init value) has a constant value of 0 in block <fmc150_stellar_cmd_inst>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <in_reg_addr_sig_23> (without init value) has a constant value of 0 in block <fmc150_stellar_cmd_inst>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <in_reg_addr_sig_24> (without init value) has a constant value of 0 in block <fmc150_stellar_cmd_inst>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <in_reg_addr_sig_25> (without init value) has a constant value of 0 in block <fmc150_stellar_cmd_inst>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <in_reg_addr_sig_26> (without init value) has a constant value of 0 in block <fmc150_stellar_cmd_inst>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <in_reg_addr_sig_27> (without init value) has a constant value of 0 in block <fmc150_stellar_cmd_inst>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <jtag_latched_0> (without init value) has a constant value of 0 in block <jtag_cores>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <jtag_latched_1> (without init value) has a constant value of 0 in block <jtag_cores>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <jtag_latched_10> (without init value) has a constant value of 0 in block <jtag_cores>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <jtag_latched_9> (without init value) has a constant value of 0 in block <jtag_cores>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <jtag_latched_2> (without init value) has a constant value of 0 in block <jtag_cores>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rx_update_r> (without init value) has a constant value of 0 in block <jtag>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <jtag_latched_3> (without init value) has a constant value of 0 in block <jtag_cores>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <jtag_latched_4> (without init value) has a constant value of 0 in block <jtag_cores>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <jtag_latched_5> (without init value) has a constant value of 0 in block <jtag_cores>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <jtag_latched_6> (without init value) has a constant value of 0 in block <jtag_cores>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <jtag_latched_7> (without init value) has a constant value of 0 in block <jtag_cores>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <jtag_latched_8> (without init value) has a constant value of 0 in block <jtag_cores>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_5> (without init value) has a constant value of 0 in block <U_WB_SLAVE>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_4> (without init value) has a constant value of 0 in block <cmp_wb_fmc150_port>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_1_32> (without init value) has a constant value of 0 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_1_33> (without init value) has a constant value of 0 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_1_34> (without init value) has a constant value of 0 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_1_35> (without init value) has a constant value of 0 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_1_37> (without init value) has a constant value of 1 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_1_38> (without init value) has a constant value of 1 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_1_39> (without init value) has a constant value of 1 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_1_40> (without init value) has a constant value of 1 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rx_update_r_r> (without init value) has a constant value of 0 in block <jtag>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_4> (without init value) has a constant value of 0 in block <U_WB_SLAVE>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_2_40> (without init value) has a constant value of 1 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_2_39> (without init value) has a constant value of 1 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_2_38> (without init value) has a constant value of 1 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_2_37> (without init value) has a constant value of 1 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_2_35> (without init value) has a constant value of 0 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_2_34> (without init value) has a constant value of 0 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_2_33> (without init value) has a constant value of 0 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_2_32> (without init value) has a constant value of 0 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_3> (without init value) has a constant value of 0 in block <cmp_wb_fmc150_port>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_3> (without init value) has a constant value of 0 in block <U_WB_SLAVE>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rx_update_r_r_r> (without init value) has a constant value of 0 in block <jtag>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_3_40> (without init value) has a constant value of 1 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_3_39> (without init value) has a constant value of 1 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_3_38> (without init value) has a constant value of 1 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_3_37> (without init value) has a constant value of 1 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_3_32> (without init value) has a constant value of 0 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_3_33> (without init value) has a constant value of 0 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_3_35> (without init value) has a constant value of 0 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_3_34> (without init value) has a constant value of 0 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_2> (without init value) has a constant value of 0 in block <U_WB_SLAVE>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_4_40> (without init value) has a constant value of 1 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_4_39> (without init value) has a constant value of 1 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_4_38> (without init value) has a constant value of 1 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_4_37> (without init value) has a constant value of 1 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_4_35> (without init value) has a constant value of 0 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_4_34> (without init value) has a constant value of 0 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_4_33> (without init value) has a constant value of 0 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_4_32> (without init value) has a constant value of 0 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ack_sreg_1> (without init value) has a constant value of 0 in block <U_WB_SLAVE>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_5_40> (without init value) has a constant value of 1 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_5_39> (without init value) has a constant value of 1 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_5_32> (without init value) has a constant value of 0 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_5_33> (without init value) has a constant value of 0 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_5_34> (without init value) has a constant value of 0 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_5_35> (without init value) has a constant value of 0 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_5_38> (without init value) has a constant value of 1 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_5_37> (without init value) has a constant value of 1 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_6_32> (without init value) has a constant value of 0 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_6_33> (without init value) has a constant value of 0 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_6_40> (without init value) has a constant value of 1 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_6_34> (without init value) has a constant value of 0 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_6_35> (without init value) has a constant value of 0 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_6_37> (without init value) has a constant value of 1 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_6_38> (without init value) has a constant value of 1 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_6_39> (without init value) has a constant value of 1 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_7_32> (without init value) has a constant value of 0 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_7_33> (without init value) has a constant value of 0 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_7_34> (without init value) has a constant value of 0 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_7_35> (without init value) has a constant value of 0 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_7_37> (without init value) has a constant value of 1 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_7_38> (without init value) has a constant value of 1 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_7_39> (without init value) has a constant value of 1 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_7_40> (without init value) has a constant value of 1 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_8_35> (without init value) has a constant value of 0 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_8_37> (without init value) has a constant value of 1 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_8_38> (without init value) has a constant value of 1 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_8_39> (without init value) has a constant value of 1 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_8_40> (without init value) has a constant value of 1 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_8_34> (without init value) has a constant value of 0 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_8_33> (without init value) has a constant value of 0 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_8_32> (without init value) has a constant value of 0 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_9_32> (without init value) has a constant value of 0 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_9_33> (without init value) has a constant value of 0 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_9_34> (without init value) has a constant value of 0 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_9_35> (without init value) has a constant value of 0 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_9_37> (without init value) has a constant value of 1 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_9_38> (without init value) has a constant value of 1 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_9_39> (without init value) has a constant value of 1 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_9_40> (without init value) has a constant value of 1 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_10_32> (without init value) has a constant value of 0 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_10_33> (without init value) has a constant value of 0 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_10_34> (without init value) has a constant value of 0 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_10_35> (without init value) has a constant value of 0 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_10_37> (without init value) has a constant value of 1 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_10_38> (without init value) has a constant value of 1 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_10_39> (without init value) has a constant value of 1 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_10_40> (without init value) has a constant value of 1 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_11_40> (without init value) has a constant value of 1 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_11_39> (without init value) has a constant value of 1 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_11_38> (without init value) has a constant value of 1 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_11_37> (without init value) has a constant value of 1 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_11_35> (without init value) has a constant value of 0 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_11_34> (without init value) has a constant value of 0 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_11_33> (without init value) has a constant value of 0 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_11_32> (without init value) has a constant value of 0 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_12_40> (without init value) has a constant value of 1 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_12_39> (without init value) has a constant value of 1 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_12_38> (without init value) has a constant value of 1 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_12_37> (without init value) has a constant value of 1 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_12_35> (without init value) has a constant value of 0 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_12_34> (without init value) has a constant value of 0 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_12_33> (without init value) has a constant value of 0 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_12_32> (without init value) has a constant value of 0 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_13_32> (without init value) has a constant value of 0 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_13_33> (without init value) has a constant value of 0 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_13_34> (without init value) has a constant value of 0 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_13_35> (without init value) has a constant value of 0 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_13_37> (without init value) has a constant value of 1 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_13_38> (without init value) has a constant value of 1 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_13_39> (without init value) has a constant value of 1 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_13_40> (without init value) has a constant value of 1 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_14_40> (without init value) has a constant value of 1 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_14_39> (without init value) has a constant value of 1 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_14_38> (without init value) has a constant value of 1 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_14_37> (without init value) has a constant value of 1 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_14_35> (without init value) has a constant value of 0 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_14_34> (without init value) has a constant value of 0 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_14_33> (without init value) has a constant value of 0 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_14_32> (without init value) has a constant value of 0 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_15_32> (without init value) has a constant value of 0 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_15_33> (without init value) has a constant value of 0 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_15_34> (without init value) has a constant value of 0 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_15_35> (without init value) has a constant value of 0 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_15_37> (without init value) has a constant value of 1 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_15_38> (without init value) has a constant value of 1 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_15_39> (without init value) has a constant value of 1 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_15_40> (without init value) has a constant value of 1 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_16_40> (without init value) has a constant value of 1 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_16_39> (without init value) has a constant value of 1 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_16_38> (without init value) has a constant value of 1 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_16_37> (without init value) has a constant value of 1 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_16_35> (without init value) has a constant value of 0 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_16_34> (without init value) has a constant value of 0 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_16_33> (without init value) has a constant value of 0 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_16_32> (without init value) has a constant value of 0 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_17_40> (without init value) has a constant value of 1 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_17_39> (without init value) has a constant value of 1 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_17_38> (without init value) has a constant value of 1 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_17_37> (without init value) has a constant value of 1 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_17_35> (without init value) has a constant value of 0 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_17_34> (without init value) has a constant value of 0 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_17_33> (without init value) has a constant value of 0 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_17_32> (without init value) has a constant value of 0 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_18_32> (without init value) has a constant value of 0 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_18_33> (without init value) has a constant value of 0 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_18_34> (without init value) has a constant value of 0 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_18_35> (without init value) has a constant value of 0 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_18_37> (without init value) has a constant value of 1 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_18_38> (without init value) has a constant value of 1 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_18_39> (without init value) has a constant value of 1 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_18_40> (without init value) has a constant value of 1 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_19_32> (without init value) has a constant value of 0 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_19_33> (without init value) has a constant value of 0 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_19_34> (without init value) has a constant value of 0 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_19_35> (without init value) has a constant value of 0 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_19_37> (without init value) has a constant value of 1 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_19_38> (without init value) has a constant value of 1 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_19_39> (without init value) has a constant value of 1 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_19_40> (without init value) has a constant value of 1 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_20_32> (without init value) has a constant value of 0 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_20_33> (without init value) has a constant value of 0 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_20_34> (without init value) has a constant value of 0 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_20_35> (without init value) has a constant value of 0 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_20_37> (without init value) has a constant value of 1 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_20_38> (without init value) has a constant value of 1 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_20_39> (without init value) has a constant value of 1 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_20_40> (without init value) has a constant value of 1 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_21_40> (without init value) has a constant value of 1 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_21_39> (without init value) has a constant value of 1 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_21_38> (without init value) has a constant value of 1 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_21_37> (without init value) has a constant value of 1 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_21_35> (without init value) has a constant value of 0 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_21_34> (without init value) has a constant value of 0 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_21_33> (without init value) has a constant value of 0 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_21_32> (without init value) has a constant value of 0 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_22_40> (without init value) has a constant value of 1 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_22_39> (without init value) has a constant value of 1 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_22_38> (without init value) has a constant value of 1 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_22_37> (without init value) has a constant value of 1 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_22_35> (without init value) has a constant value of 0 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_22_34> (without init value) has a constant value of 0 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_22_33> (without init value) has a constant value of 0 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_22_32> (without init value) has a constant value of 0 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_23_32> (without init value) has a constant value of 0 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_23_33> (without init value) has a constant value of 0 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_23_34> (without init value) has a constant value of 0 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_23_35> (without init value) has a constant value of 0 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_23_37> (without init value) has a constant value of 1 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_23_38> (without init value) has a constant value of 1 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_23_39> (without init value) has a constant value of 1 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_23_40> (without init value) has a constant value of 1 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_24_40> (without init value) has a constant value of 1 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_24_39> (without init value) has a constant value of 1 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_24_38> (without init value) has a constant value of 1 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_24_37> (without init value) has a constant value of 1 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_24_35> (without init value) has a constant value of 0 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_24_34> (without init value) has a constant value of 0 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_24_33> (without init value) has a constant value of 0 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_24_32> (without init value) has a constant value of 0 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_25_32> (without init value) has a constant value of 0 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_25_33> (without init value) has a constant value of 0 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_25_34> (without init value) has a constant value of 0 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_25_35> (without init value) has a constant value of 0 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_25_37> (without init value) has a constant value of 1 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_25_38> (without init value) has a constant value of 1 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_25_39> (without init value) has a constant value of 1 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_25_40> (without init value) has a constant value of 1 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_26_32> (without init value) has a constant value of 0 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_26_33> (without init value) has a constant value of 0 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_26_34> (without init value) has a constant value of 0 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_26_35> (without init value) has a constant value of 0 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_26_37> (without init value) has a constant value of 1 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_26_38> (without init value) has a constant value of 1 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_26_39> (without init value) has a constant value of 1 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_26_40> (without init value) has a constant value of 1 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_27_40> (without init value) has a constant value of 1 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_27_39> (without init value) has a constant value of 1 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_27_38> (without init value) has a constant value of 1 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_27_37> (without init value) has a constant value of 1 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_27_35> (without init value) has a constant value of 0 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_27_34> (without init value) has a constant value of 0 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_27_33> (without init value) has a constant value of 0 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_27_32> (without init value) has a constant value of 0 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_28_40> (without init value) has a constant value of 1 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_28_39> (without init value) has a constant value of 1 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_28_38> (without init value) has a constant value of 1 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_28_37> (without init value) has a constant value of 1 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_28_35> (without init value) has a constant value of 0 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_28_34> (without init value) has a constant value of 0 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_28_33> (without init value) has a constant value of 0 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_28_32> (without init value) has a constant value of 0 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_29_34> (without init value) has a constant value of 0 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_29_35> (without init value) has a constant value of 0 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_29_37> (without init value) has a constant value of 1 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_29_38> (without init value) has a constant value of 1 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_29_39> (without init value) has a constant value of 1 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_29_40> (without init value) has a constant value of 1 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_29_32> (without init value) has a constant value of 0 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_29_33> (without init value) has a constant value of 0 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_30_32> (without init value) has a constant value of 0 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_30_33> (without init value) has a constant value of 0 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_30_34> (without init value) has a constant value of 0 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_30_35> (without init value) has a constant value of 0 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_30_37> (without init value) has a constant value of 1 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_30_38> (without init value) has a constant value of 1 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_30_39> (without init value) has a constant value of 1 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_30_40> (without init value) has a constant value of 1 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_31_32> (without init value) has a constant value of 0 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_31_33> (without init value) has a constant value of 0 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_31_37> (without init value) has a constant value of 1 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_31_38> (without init value) has a constant value of 1 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_31_39> (without init value) has a constant value of 1 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_31_40> (without init value) has a constant value of 1 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_31_34> (without init value) has a constant value of 0 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fifo_store_31_35> (without init value) has a constant value of 0 in block <cmp_fifo>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:2677 - Node <out_cmd_32> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_cmd_33> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_cmd_34> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_cmd_35> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_cmd_36> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_cmd_37> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_cmd_38> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_cmd_39> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_cmd_40> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_cmd_41> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_cmd_42> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_cmd_43> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_cmd_44> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_cmd_45> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_cmd_46> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_cmd_47> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_cmd_48> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_cmd_49> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_cmd_50> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_cmd_51> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_cmd_52> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_cmd_53> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_cmd_54> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_cmd_55> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_cmd_56> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_cmd_57> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_cmd_58> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_cmd_59> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_cmd_60> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_cmd_61> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_cmd_62> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_cmd_63> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_reg_8> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_reg_9> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_reg_10> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_reg_11> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_reg_12> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_reg_13> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_reg_14> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_reg_15> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_reg_16> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_reg_17> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_reg_18> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_reg_19> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_reg_20> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_reg_21> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_reg_22> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_reg_23> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_reg_24> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_reg_25> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_reg_26> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_reg_27> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_reg_28> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_reg_29> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_reg_30> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_reg_31> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_cmd_32> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_cmd_33> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_cmd_34> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_cmd_35> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_cmd_36> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_cmd_37> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_cmd_38> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_cmd_39> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_cmd_40> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_cmd_41> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_cmd_42> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_cmd_43> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_cmd_44> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_cmd_45> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_cmd_46> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_cmd_47> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_cmd_48> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_cmd_49> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_cmd_50> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_cmd_51> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_cmd_52> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_cmd_53> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_cmd_54> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_cmd_55> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_cmd_56> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_cmd_57> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_cmd_58> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_cmd_59> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_cmd_60> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_cmd_61> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_cmd_62> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_cmd_63> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_reg_8> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_reg_9> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_reg_10> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_reg_11> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_reg_12> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_reg_13> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_reg_14> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_reg_15> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_reg_16> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_reg_17> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_reg_18> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_reg_19> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_reg_20> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_reg_21> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_reg_22> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_reg_23> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_reg_24> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_reg_25> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_reg_26> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_reg_27> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_reg_28> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_reg_29> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_reg_30> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_reg_31> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_cmd_32> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_cmd_33> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_cmd_34> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_cmd_35> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_cmd_36> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_cmd_37> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_cmd_38> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_cmd_39> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_cmd_40> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_cmd_41> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_cmd_42> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_cmd_43> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_cmd_44> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_cmd_45> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_cmd_46> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_cmd_47> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_cmd_48> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_cmd_49> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_cmd_50> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_cmd_51> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_cmd_52> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_cmd_53> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_cmd_54> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_cmd_55> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_cmd_56> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_cmd_57> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_cmd_58> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_cmd_59> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_cmd_60> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_cmd_61> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_cmd_62> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_cmd_63> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_reg_16> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_reg_17> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_reg_18> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_reg_19> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_reg_20> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_reg_21> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_reg_22> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_reg_23> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_reg_24> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_reg_25> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_reg_26> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_reg_27> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_reg_28> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_reg_29> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_reg_30> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_reg_31> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_cmd_32> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_cmd_33> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_cmd_34> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_cmd_35> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_cmd_36> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_cmd_37> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_cmd_38> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_cmd_39> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_cmd_40> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_cmd_41> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_cmd_42> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_cmd_43> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_cmd_44> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_cmd_45> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_cmd_46> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_cmd_47> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_cmd_48> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_cmd_49> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_cmd_50> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_cmd_51> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_cmd_52> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_cmd_53> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_cmd_54> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_cmd_55> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_cmd_56> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_cmd_57> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_cmd_58> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_cmd_59> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_cmd_60> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_cmd_61> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_cmd_62> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <out_cmd_63> of sequential type is unconnected in block <fmc150_stellar_cmd_inst>.
WARNING:Xst:2677 - Node <uart_bcr_17> of sequential type is unconnected in block <U_Wrapped_UART>.
WARNING:Xst:2677 - Node <uart_bcr_18> of sequential type is unconnected in block <U_Wrapped_UART>.
WARNING:Xst:2677 - Node <uart_bcr_19> of sequential type is unconnected in block <U_Wrapped_UART>.
WARNING:Xst:2677 - Node <uart_bcr_20> of sequential type is unconnected in block <U_Wrapped_UART>.
WARNING:Xst:2677 - Node <uart_bcr_21> of sequential type is unconnected in block <U_Wrapped_UART>.
WARNING:Xst:2677 - Node <uart_bcr_22> of sequential type is unconnected in block <U_Wrapped_UART>.
WARNING:Xst:2677 - Node <uart_bcr_23> of sequential type is unconnected in block <U_Wrapped_UART>.
WARNING:Xst:2677 - Node <uart_bcr_24> of sequential type is unconnected in block <U_Wrapped_UART>.
WARNING:Xst:2677 - Node <uart_bcr_25> of sequential type is unconnected in block <U_Wrapped_UART>.
WARNING:Xst:2677 - Node <uart_bcr_26> of sequential type is unconnected in block <U_Wrapped_UART>.
WARNING:Xst:2677 - Node <uart_bcr_27> of sequential type is unconnected in block <U_Wrapped_UART>.
WARNING:Xst:2677 - Node <uart_bcr_28> of sequential type is unconnected in block <U_Wrapped_UART>.
WARNING:Xst:2677 - Node <uart_bcr_29> of sequential type is unconnected in block <U_Wrapped_UART>.
WARNING:Xst:2677 - Node <uart_bcr_30> of sequential type is unconnected in block <U_Wrapped_UART>.
WARNING:Xst:2677 - Node <uart_bcr_31> of sequential type is unconnected in block <U_Wrapped_UART>.
WARNING:Xst:1898 - Due to constant pushing, FF/Latch <processing> is unconnected in block <jtag>.
WARNING:Xst:1898 - Due to constant pushing, FF/Latch <jtag_reg_d_0> is unconnected in block <jtag>.
WARNING:Xst:1898 - Due to constant pushing, FF/Latch <jtag_reg_d_1> is unconnected in block <jtag>.
WARNING:Xst:1898 - Due to constant pushing, FF/Latch <jtag_reg_d_2> is unconnected in block <jtag>.
WARNING:Xst:1898 - Due to constant pushing, FF/Latch <jtag_reg_d_3> is unconnected in block <jtag>.
WARNING:Xst:1898 - Due to constant pushing, FF/Latch <jtag_reg_d_4> is unconnected in block <jtag>.
WARNING:Xst:1898 - Due to constant pushing, FF/Latch <jtag_reg_d_5> is unconnected in block <jtag>.
WARNING:Xst:1898 - Due to constant pushing, FF/Latch <jtag_reg_d_6> is unconnected in block <jtag>.
WARNING:Xst:1898 - Due to constant pushing, FF/Latch <uart_tx_byte_0> is unconnected in block <jtag>.
WARNING:Xst:1898 - Due to constant pushing, FF/Latch <uart_tx_byte_1> is unconnected in block <jtag>.
WARNING:Xst:1898 - Due to constant pushing, FF/Latch <uart_tx_byte_2> is unconnected in block <jtag>.
WARNING:Xst:1898 - Due to constant pushing, FF/Latch <uart_tx_byte_3> is unconnected in block <jtag>.
WARNING:Xst:1898 - Due to constant pushing, FF/Latch <uart_tx_byte_4> is unconnected in block <jtag>.
WARNING:Xst:1898 - Due to constant pushing, FF/Latch <uart_tx_byte_5> is unconnected in block <jtag>.
WARNING:Xst:1898 - Due to constant pushing, FF/Latch <uart_tx_byte_6> is unconnected in block <jtag>.
WARNING:Xst:1898 - Due to constant pushing, FF/Latch <uart_tx_byte_7> is unconnected in block <jtag>.
WARNING:Xst:1898 - Due to constant pushing, FF/Latch <jtag_reg_d_7> is unconnected in block <jtag>.
WARNING:Xst:1290 - Hierarchical block <jtag_tap> is unconnected in block <jtag_cores>.
   It will be removed from the design.
WARNING:Xst:1710 - FF/Latch <jtag_byte_3_0> (without init value) has a constant value of 0 in block <jtag>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <jtag_byte_3_1> (without init value) has a constant value of 0 in block <jtag>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <jtag_byte_3_2> (without init value) has a constant value of 0 in block <jtag>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <jtag_byte_3_3> (without init value) has a constant value of 0 in block <jtag>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <jtag_byte_3_4> (without init value) has a constant value of 0 in block <jtag>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <jtag_byte_3_5> (without init value) has a constant value of 0 in block <jtag>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <jtag_byte_3_6> (without init value) has a constant value of 0 in block <jtag>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <jtag_byte_3_7> (without init value) has a constant value of 0 in block <jtag>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <jtag_byte_2_0> (without init value) has a constant value of 0 in block <jtag>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <jtag_byte_2_1> (without init value) has a constant value of 0 in block <jtag>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <jtag_byte_2_2> (without init value) has a constant value of 0 in block <jtag>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <jtag_byte_2_3> (without init value) has a constant value of 0 in block <jtag>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <jtag_byte_2_4> (without init value) has a constant value of 0 in block <jtag>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <jtag_byte_2_5> (without init value) has a constant value of 0 in block <jtag>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <jtag_byte_2_6> (without init value) has a constant value of 0 in block <jtag>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <jtag_byte_2_7> (without init value) has a constant value of 0 in block <jtag>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:2404 -  FFs/Latches <ack_sreg<5:3>> (without init value) have a constant value of 0 in block <wb_fmc150_port>.
WARNING:Xst:2404 -  FFs/Latches <ack_sreg<6:1>> (without init value) have a constant value of 0 in block <simple_uart_wb>.

Synthesizing (advanced) Unit <ads62p49_ctrl>.
The following registers are absorbed into counter <gen_serial_clk.clk_div>: 1 register on signal <gen_serial_clk.clk_div>.
The following registers are absorbed into counter <init_address>: 1 register on signal <init_address>.
Unit <ads62p49_ctrl> synthesized (advanced).

Synthesizing (advanced) Unit <amc7823_ctrl>.
The following registers are absorbed into counter <gen_serial_clk.clk_div>: 1 register on signal <gen_serial_clk.clk_div>.
The following registers are absorbed into counter <init_address>: 1 register on signal <init_address>.
Unit <amc7823_ctrl> synthesized (advanced).

Synthesizing (advanced) Unit <cdce72010_ctrl>.
The following registers are absorbed into counter <gen_serial_clk.clk_div>: 1 register on signal <gen_serial_clk.clk_div>.
The following registers are absorbed into counter <init_address>: 1 register on signal <init_address>.
Unit <cdce72010_ctrl> synthesized (advanced).

Synthesizing (advanced) Unit <dac3283_ctrl>.
The following registers are absorbed into counter <gen_serial_clk.clk_div>: 1 register on signal <gen_serial_clk.clk_div>.
The following registers are absorbed into counter <init_address>: 1 register on signal <init_address>.
Unit <dac3283_ctrl> synthesized (advanced).

Synthesizing (advanced) Unit <fmc150_dac_if>.
The following registers are absorbed into counter <cnt>: 1 register on signal <cnt>.
Unit <fmc150_dac_if> synthesized (advanced).

Synthesizing (advanced) Unit <gc_extend_pulse>.
The following registers are absorbed into counter <cntr>: 1 register on signal <cntr>.
Unit <gc_extend_pulse> synthesized (advanced).

Synthesizing (advanced) Unit <gc_reset>.
The following registers are absorbed into counter <locked_count>: 1 register on signal <locked_count>.
Unit <gc_reset> synthesized (advanced).

Synthesizing (advanced) Unit <generic_dpram_sameclock>.
INFO:Xst:3226 - The RAM <Mram_ram> will be implemented as a BLOCK RAM, absorbing the following register(s): <qa_o> <qb_o>
    -----------------------------------------------------------------------
    | ram_type           | Block                               |          |
    -----------------------------------------------------------------------
    | Port A                                                              |
    |     aspect ratio   | 22528-word x 32-bit                 |          |
    |     mode           | read-first                          |          |
    |     clkA           | connected to signal <clk_i>         | rise     |
    |     weA<3>         | connected to signal <s_we_a<3>>     | high     |
    |     weA<2>         | connected to signal <s_we_a<2>>     | high     |
    |     weA<1>         | connected to signal <s_we_a<1>>     | high     |
    |     weA<0>         | connected to signal <s_we_a<0>>     | high     |
    |     addrA          | connected to signal <aa_i>          |          |
    |     diA            | connected to signal <da_i>          |          |
    |     doA            | connected to signal <qa_o>          |          |
    -----------------------------------------------------------------------
    | optimization       | speed                               |          |
    -----------------------------------------------------------------------
    | Port B                                                              |
    |     aspect ratio   | 22528-word x 32-bit                 |          |
    |     mode           | read-first                          |          |
    |     clkB           | connected to signal <clk_i>         | rise     |
    |     weB<3>         | connected to signal <s_we_b<3>>     | high     |
    |     weB<2>         | connected to signal <s_we_b<2>>     | high     |
    |     weB<1>         | connected to signal <s_we_b<1>>     | high     |
    |     weB<0>         | connected to signal <s_we_b<0>>     | high     |
    |     addrB          | connected to signal <ab_i>          |          |
    |     diB            | connected to signal <db_i>          |          |
    |     doB            | connected to signal <qb_o>          |          |
    -----------------------------------------------------------------------
    | optimization       | speed                               |          |
    -----------------------------------------------------------------------
Unit <generic_dpram_sameclock> synthesized (advanced).

Synthesizing (advanced) Unit <generic_shiftreg_fifo>.
The following registers are absorbed into counter <pointer>: 1 register on signal <pointer>.
Unit <generic_shiftreg_fifo> synthesized (advanced).

Synthesizing (advanced) Unit <lm32_cpu_medium_icache_debug>.
INFO:Xst:3226 - The RAM <reg_0/Mram_ram> will be implemented as a BLOCK RAM, absorbing the following register(s): <reg_0/raddr_r>
    -----------------------------------------------------------------------
    | ram_type           | Block                               |          |
    -----------------------------------------------------------------------
    | Port A                                                              |
    |     aspect ratio   | 32-word x 32-bit                    |          |
    |     mode           | read-first                          |          |
    |     clkA           | connected to signal <clk_i>         | rise     |
    |     weA            | connected to signal <reg_write_enable_q_w> | high     |
    |     addrA          | connected to signal <write_idx_w>   |          |
    |     diA            | connected to signal <w_result>      |          |
    -----------------------------------------------------------------------
    | optimization       | speed                               |          |
    -----------------------------------------------------------------------
    | Port B                                                              |
    |     aspect ratio   | 32-word x 32-bit                    |          |
    |     mode           | read-first                          |          |
    |     clkB           | connected to signal <clk_i>         | rise     |
    |     addrB          | connected to signal <instruction_f<25:21>> |          |
    |     doB            | connected to signal <regfile_data_0> |          |
    -----------------------------------------------------------------------
    | optimization       | speed                               |          |
    -----------------------------------------------------------------------
INFO:Xst:3226 - The RAM <reg_1/Mram_ram> will be implemented as a BLOCK RAM, absorbing the following register(s): <reg_1/raddr_r>
    -----------------------------------------------------------------------
    | ram_type           | Block                               |          |
    -----------------------------------------------------------------------
    | Port A                                                              |
    |     aspect ratio   | 32-word x 32-bit                    |          |
    |     mode           | read-first                          |          |
    |     clkA           | connected to signal <clk_i>         | rise     |
    |     weA            | connected to signal <reg_write_enable_q_w> | high     |
    |     addrA          | connected to signal <write_idx_w>   |          |
    |     diA            | connected to signal <w_result>      |          |
    -----------------------------------------------------------------------
    | optimization       | speed                               |          |
    -----------------------------------------------------------------------
    | Port B                                                              |
    |     aspect ratio   | 32-word x 32-bit                    |          |
    |     mode           | read-first                          |          |
    |     clkB           | connected to signal <clk_i>         | rise     |
    |     addrB          | connected to signal <instruction_f<20:16>> |          |
    |     doB            | connected to signal <regfile_data_1> |          |
    -----------------------------------------------------------------------
    | optimization       | speed                               |          |
    -----------------------------------------------------------------------
Unit <lm32_cpu_medium_icache_debug> synthesized (advanced).

Synthesizing (advanced) Unit <lm32_icache_medium_icache_debug>.
The following registers are absorbed into counter <flush_set>: 1 register on signal <flush_set>.
INFO:Xst:3226 - The RAM <memories[0].way_0_data_ram/Mram_mem> will be implemented as a BLOCK RAM, absorbing the following register(s): <memories[0].way_0_data_ram/ra>
    -----------------------------------------------------------------------
    | ram_type           | Block                               |          |
    -----------------------------------------------------------------------
    | Port A                                                              |
    |     aspect ratio   | 1024-word x 32-bit                  |          |
    |     mode           | read-first                          |          |
    |     clkA           | connected to signal <clk_i>         | rise     |
    |     weA            | connected to signal <way_mem_we>    | high     |
    |     addrA          | connected to signal <(refill_address<11:4>,refill_offset)> |          |
    |     diA            | connected to signal <refill_data>   |          |
    -----------------------------------------------------------------------
    | optimization       | speed                               |          |
    -----------------------------------------------------------------------
    | Port B                                                              |
    |     aspect ratio   | 1024-word x 32-bit                  |          |
    |     mode           | write-first                         |          |
    |     clkB           | connected to signal <clk_i>         | rise     |
    |     addrB          | connected to signal <address_a>     |          |
    |     doB            | connected to signal <way_data<0>>   |          |
    -----------------------------------------------------------------------
    | optimization       | speed                               |          |
    -----------------------------------------------------------------------
Unit <lm32_icache_medium_icache_debug> synthesized (advanced).

Synthesizing (advanced) Unit <lm32_multiplier>.
	Multiplier <Mmult_n0056> in block <lm32_multiplier> and adder/subtractor <Madd_c1[15]_e1[15]_add_17_OUT> in block <lm32_multiplier> are combined into a MAC<Maddsub_n0056>.
	The following registers are also absorbed by the MAC: <e1> in block <lm32_multiplier>, <result1,result0> in block <lm32_multiplier>.
	Multiplier <Mmult_n0055> in block <lm32_multiplier> and adder/subtractor <Madd_n0077> in block <lm32_multiplier> are combined into a MAC<Maddsub_n0055>.
	The following registers are also absorbed by the MAC: <d1> in block <lm32_multiplier>.
	Found pipelined multiplier on signal <a0[15]_b0[15]_MuLt_9_OUT>:
		- 1 pipeline level(s) found in a register connected to the multiplier macro output.
		Pushing register(s) into the multiplier macro.
INFO:Xst:2385 - HDL ADVISOR - You can improve the performance of the multiplier Mmult_a0[15]_b0[15]_MuLt_9_OUT by adding 1 register level(s).
Unit <lm32_multiplier> synthesized (advanced).

Synthesizing (advanced) Unit <lm32_ram_2>.
INFO:Xst:3226 - The RAM <Mram_mem> will be implemented as a BLOCK RAM, absorbing the following register(s): <ra>
    -----------------------------------------------------------------------
    | ram_type           | Block                               |          |
    -----------------------------------------------------------------------
    | Port A                                                              |
    |     aspect ratio   | 256-word x 20-bit                   |          |
    |     mode           | write-first                         |          |
    |     clkA           | connected to signal <write_clk>     | rise     |
    |     weA            | connected to signal <write_enable>  | high     |
    |     addrA          | connected to signal <write_address> |          |
    |     diA            | connected to signal <write_data>    |          |
    -----------------------------------------------------------------------
    | optimization       | speed                               |          |
    -----------------------------------------------------------------------
    | Port B                                                              |
    |     aspect ratio   | 256-word x 20-bit                   |          |
    |     mode           | write-first                         |          |
    |     clkB           | connected to signal <read_clk>      | rise     |
    |     addrB          | connected to signal <read_address>  |          |
    |     doB            | connected to internal node          |          |
    -----------------------------------------------------------------------
    | optimization       | speed                               |          |
    -----------------------------------------------------------------------
Unit <lm32_ram_2> synthesized (advanced).

Synthesizing (advanced) Unit <sdb_rom>.
INFO:Xst:3226 - The RAM <Mram_rom> will be implemented as a BLOCK RAM, absorbing the following register(s): <adr_reg>
    -----------------------------------------------------------------------
    | ram_type           | Block                               |          |
    -----------------------------------------------------------------------
    | Port A                                                              |
    |     aspect ratio   | 128-word x 32-bit                   |          |
    |     mode           | write-first                         |          |
    |     clkA           | connected to signal <clk_sys_i>     | rise     |
    |     weA            | connected to signal <GND>           | high     |
    |     addrA          | connected to signal <slave_i_adr>   |          |
    |     diA            | connected to signal <GND>           |          |
    |     doA            | connected to internal node          |          |
    -----------------------------------------------------------------------
    | optimization       | speed                               |          |
    -----------------------------------------------------------------------
Unit <sdb_rom> synthesized (advanced).

Synthesizing (advanced) Unit <uart_async_rx>.
The following registers are absorbed into counter <RxD_cnt_inv>: 1 register on signal <RxD_cnt_inv>.
Unit <uart_async_rx> synthesized (advanced).

Synthesizing (advanced) Unit <wb_fmc150>.
The following registers are absorbed into counter <s_wbs_packet_counter>: 1 register on signal <s_wbs_packet_counter>.
Unit <wb_fmc150> synthesized (advanced).

Synthesizing (advanced) Unit <wb_gpio_port>.
INFO:Xst:3218 - HDL ADVISOR - The RAM <Mram_write_mask<0>> will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
    -----------------------------------------------------------------------
    | ram_type           | Distributed                         |          |
    -----------------------------------------------------------------------
    | Port A                                                              |
    |     aspect ratio   | 8-word x 1-bit                      |          |
    |     weA            | connected to signal <GND>           | high     |
    |     addrA          | connected to signal <wb_in_adr<5:3>> |          |
    |     diA            | connected to signal <GND>           |          |
    |     doA            | connected to signal <write_mask>    |          |
    -----------------------------------------------------------------------
Unit <wb_gpio_port> synthesized (advanced).

Synthesizing (advanced) Unit <xwb_dma>.
The following registers are absorbed into counter <read_result_offset>: 1 register on signal <read_result_offset>.
The following registers are absorbed into counter <write_issue_offset>: 1 register on signal <write_issue_offset>.
The following registers are absorbed into counter <write_result_offset>: 1 register on signal <write_result_offset>.
The following registers are absorbed into counter <read_issue_offset>: 1 register on signal <read_issue_offset>.
INFO:Xst:3218 - HDL ADVISOR - The RAM <Mram_ring> will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
    -----------------------------------------------------------------------
    | ram_type           | Distributed                         |          |
    -----------------------------------------------------------------------
    | Port A                                                              |
    |     aspect ratio   | 16-word x 32-bit                    |          |
    |     clkA           | connected to signal <clk_i>         | rise     |
    |     weA            | connected to internal node          | high     |
    |     addrA          | connected to signal <read_result_offset<3:0>> |          |
    |     diA            | connected to signal <r_master_i_dat> |          |
    -----------------------------------------------------------------------
    | Port B                                                              |
    |     aspect ratio   | 16-word x 32-bit                    |          |
    |     addrB          | connected to signal <write_issue_offset<3:0>> |          |
    |     doB            | connected to internal node          |          |
    -----------------------------------------------------------------------
Unit <xwb_dma> synthesized (advanced).

Synthesizing (advanced) Unit <generic_shiftreg_fifo>.
	Found 32-bit dynamic shift register for signal <q_o<0>>.
	Found 32-bit dynamic shift register for signal <q_o<1>>.
	Found 32-bit dynamic shift register for signal <q_o<2>>.
	Found 32-bit dynamic shift register for signal <q_o<3>>.
	Found 32-bit dynamic shift register for signal <q_o<4>>.
	Found 32-bit dynamic shift register for signal <q_o<5>>.
	Found 32-bit dynamic shift register for signal <q_o<6>>.
	Found 32-bit dynamic shift register for signal <q_o<7>>.
	Found 32-bit dynamic shift register for signal <q_o<8>>.
	Found 32-bit dynamic shift register for signal <q_o<9>>.
	Found 32-bit dynamic shift register for signal <q_o<10>>.
	Found 32-bit dynamic shift register for signal <q_o<11>>.
	Found 32-bit dynamic shift register for signal <q_o<12>>.
	Found 32-bit dynamic shift register for signal <q_o<13>>.
	Found 32-bit dynamic shift register for signal <q_o<14>>.
	Found 32-bit dynamic shift register for signal <q_o<15>>.
	Found 32-bit dynamic shift register for signal <q_o<16>>.
	Found 32-bit dynamic shift register for signal <q_o<17>>.
	Found 32-bit dynamic shift register for signal <q_o<18>>.
	Found 32-bit dynamic shift register for signal <q_o<19>>.
	Found 32-bit dynamic shift register for signal <q_o<20>>.
	Found 32-bit dynamic shift register for signal <q_o<21>>.
	Found 32-bit dynamic shift register for signal <q_o<22>>.
	Found 32-bit dynamic shift register for signal <q_o<23>>.
	Found 32-bit dynamic shift register for signal <q_o<24>>.
	Found 32-bit dynamic shift register for signal <q_o<25>>.
	Found 32-bit dynamic shift register for signal <q_o<26>>.
	Found 32-bit dynamic shift register for signal <q_o<27>>.
	Found 32-bit dynamic shift register for signal <q_o<28>>.
	Found 32-bit dynamic shift register for signal <q_o<29>>.
	Found 32-bit dynamic shift register for signal <q_o<30>>.
	Found 32-bit dynamic shift register for signal <q_o<31>>.
	Found 32-bit dynamic shift register for signal <q_o<32>>.
	Found 32-bit dynamic shift register for signal <q_o<33>>.
	Found 32-bit dynamic shift register for signal <q_o<34>>.
	Found 32-bit dynamic shift register for signal <q_o<35>>.
	Found 32-bit dynamic shift register for signal <q_o<36>>.
	Found 32-bit dynamic shift register for signal <q_o<37>>.
	Found 32-bit dynamic shift register for signal <q_o<38>>.
	Found 32-bit dynamic shift register for signal <q_o<39>>.
	Found 32-bit dynamic shift register for signal <q_o<40>>.
	Found 32-bit dynamic shift register for signal <q_o<41>>.
	Found 32-bit dynamic shift register for signal <q_o<42>>.
Unit <generic_shiftreg_fifo> synthesized (advanced).
WARNING:Xst:2677 - Node <uart_bcr_17> of sequential type is unconnected in block <wb_simple_uart>.
WARNING:Xst:2677 - Node <uart_bcr_18> of sequential type is unconnected in block <wb_simple_uart>.
WARNING:Xst:2677 - Node <uart_bcr_19> of sequential type is unconnected in block <wb_simple_uart>.
WARNING:Xst:2677 - Node <uart_bcr_20> of sequential type is unconnected in block <wb_simple_uart>.
WARNING:Xst:2677 - Node <uart_bcr_21> of sequential type is unconnected in block <wb_simple_uart>.
WARNING:Xst:2677 - Node <uart_bcr_22> of sequential type is unconnected in block <wb_simple_uart>.
WARNING:Xst:2677 - Node <uart_bcr_23> of sequential type is unconnected in block <wb_simple_uart>.
WARNING:Xst:2677 - Node <uart_bcr_24> of sequential type is unconnected in block <wb_simple_uart>.
WARNING:Xst:2677 - Node <uart_bcr_25> of sequential type is unconnected in block <wb_simple_uart>.
WARNING:Xst:2677 - Node <uart_bcr_26> of sequential type is unconnected in block <wb_simple_uart>.
WARNING:Xst:2677 - Node <uart_bcr_27> of sequential type is unconnected in block <wb_simple_uart>.
WARNING:Xst:2677 - Node <uart_bcr_28> of sequential type is unconnected in block <wb_simple_uart>.
WARNING:Xst:2677 - Node <uart_bcr_29> of sequential type is unconnected in block <wb_simple_uart>.
WARNING:Xst:2677 - Node <uart_bcr_30> of sequential type is unconnected in block <wb_simple_uart>.
WARNING:Xst:2677 - Node <uart_bcr_31> of sequential type is unconnected in block <wb_simple_uart>.

=========================================================================
Advanced HDL Synthesis Report

Macro Statistics
# RAMs                                                 : 9
 1024x32-bit dual-port block RAM                       : 1
 128x32-bit single-port block Read Only RAM            : 1
 16x32-bit dual-port distributed RAM                   : 1
 22528x32-bit dual-port block RAM                      : 1
 256x20-bit dual-port block RAM                        : 1
 32x32-bit dual-port block RAM                         : 2
 8x1-bit single-port distributed Read Only RAM         : 2
# MACs                                                 : 2
 16x16-to-16-bit MAC                                   : 2
# Multipliers                                          : 1
 16x16-bit registered multiplier                       : 1
# Adders/Subtractors                                   : 29
 1-bit subtractor                                      : 1
 10-bit adder                                          : 1
 16-bit adder                                          : 1
 17-bit adder                                          : 1
 2-bit adder                                           : 2
 29-bit adder                                          : 2
 3-bit subtractor                                      : 1
 32-bit adder                                          : 4
 32-bit subtractor                                     : 5
 33-bit adder carry in                                 : 1
 33-bit subtractor borrow in                           : 1
 4-bit adder                                           : 5
 5-bit adder                                           : 4
# Counters                                             : 19
 10-bit up counter                                     : 2
 2-bit updown counter                                  : 1
 32-bit down counter                                   : 1
 4-bit up counter                                      : 5
 5-bit up counter                                      : 8
 5-bit updown counter                                  : 1
 8-bit down counter                                    : 1
# Registers                                            : 3793
 Flip-Flops                                            : 3793
# Shift Registers                                      : 43
 32-bit dynamic shift register                         : 43
# Comparators                                          : 28
 1-bit comparator equal                                : 1
 10-bit comparator greater                             : 1
 20-bit comparator equal                               : 1
 28-bit comparator greater                             : 4
 28-bit comparator lessequal                           : 4
 32-bit comparator equal                               : 5
 4-bit comparator equal                                : 1
 5-bit comparator equal                                : 8
 5-bit comparator not equal                            : 3
# Multiplexers                                         : 941
 1-bit 2-to-1 multiplexer                              : 751
 1-bit 4-to-1 multiplexer                              : 32
 1-bit 8-to-1 multiplexer                              : 2
 10-bit 2-to-1 multiplexer                             : 1
 11-bit 2-to-1 multiplexer                             : 1
 16-bit 2-to-1 multiplexer                             : 3
 2-bit 2-to-1 multiplexer                              : 5
 23-bit 2-to-1 multiplexer                             : 2
 28-bit 2-to-1 multiplexer                             : 1
 29-bit 2-to-1 multiplexer                             : 7
 3-bit 2-to-1 multiplexer                              : 5
 32-bit 2-to-1 multiplexer                             : 92
 32-bit 3-to-1 multiplexer                             : 3
 32-bit 7-to-1 multiplexer                             : 2
 4-bit 2-to-1 multiplexer                              : 5
 5-bit 2-to-1 multiplexer                              : 10
 64-bit 2-to-1 multiplexer                             : 8
 8-bit 2-to-1 multiplexer                              : 6
 8-bit 4-to-1 multiplexer                              : 1
 9-bit 2-to-1 multiplexer                              : 4
# Logic shifters                                       : 1
 64-bit shifter logical right                          : 1
# FSMs                                                 : 9
# Xors                                                 : 101
 1-bit xor2                                            : 69
 32-bit xor2                                           : 32

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1710 - FF/Latch <in_cmd_48> (without init value) has a constant value of 0 in block <fmc150_spi_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <in_cmd_49> (without init value) has a constant value of 0 in block <fmc150_spi_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <in_cmd_50> (without init value) has a constant value of 0 in block <fmc150_spi_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <in_cmd_51> (without init value) has a constant value of 0 in block <fmc150_spi_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <in_cmd_52> (without init value) has a constant value of 0 in block <fmc150_spi_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <in_cmd_53> (without init value) has a constant value of 0 in block <fmc150_spi_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <in_cmd_54> (without init value) has a constant value of 0 in block <fmc150_spi_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <in_cmd_55> (without init value) has a constant value of 0 in block <fmc150_spi_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <in_cmd_56> (without init value) has a constant value of 0 in block <fmc150_spi_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <in_cmd_57> (without init value) has a constant value of 0 in block <fmc150_spi_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <in_cmd_58> (without init value) has a constant value of 0 in block <fmc150_spi_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <in_cmd_59> (without init value) has a constant value of 0 in block <fmc150_spi_ctrl>. This FF/Latch will be trimmed during the optimization process.
INFO:Xst:2261 - The FF/Latch <adc_dout_b_13> in Unit <fmc150_testbench> is equivalent to the following 2 FFs/Latches, which will be removed : <adc_dout_b_14> <adc_dout_b_15> 
INFO:Xst:2261 - The FF/Latch <adc_dout_a_13> in Unit <fmc150_testbench> is equivalent to the following 2 FFs/Latches, which will be removed : <adc_dout_a_14> <adc_dout_a_15> 
INFO:Xst:2261 - The FF/Latch <i_dat_o_0> in Unit <lm32_instruction_unit_medium_icache_debug> is equivalent to the following 3 FFs/Latches, which will be removed : <i_dat_o_8> <i_dat_o_16> <i_dat_o_24> 
INFO:Xst:2261 - The FF/Latch <i_dat_o_1> in Unit <lm32_instruction_unit_medium_icache_debug> is equivalent to the following 3 FFs/Latches, which will be removed : <i_dat_o_9> <i_dat_o_17> <i_dat_o_25> 
INFO:Xst:2261 - The FF/Latch <i_dat_o_2> in Unit <lm32_instruction_unit_medium_icache_debug> is equivalent to the following 3 FFs/Latches, which will be removed : <i_dat_o_10> <i_dat_o_18> <i_dat_o_26> 
INFO:Xst:2261 - The FF/Latch <i_dat_o_3> in Unit <lm32_instruction_unit_medium_icache_debug> is equivalent to the following 3 FFs/Latches, which will be removed : <i_dat_o_11> <i_dat_o_19> <i_dat_o_27> 
INFO:Xst:2261 - The FF/Latch <i_dat_o_4> in Unit <lm32_instruction_unit_medium_icache_debug> is equivalent to the following 3 FFs/Latches, which will be removed : <i_dat_o_12> <i_dat_o_20> <i_dat_o_28> 
INFO:Xst:2261 - The FF/Latch <i_dat_o_5> in Unit <lm32_instruction_unit_medium_icache_debug> is equivalent to the following 3 FFs/Latches, which will be removed : <i_dat_o_13> <i_dat_o_21> <i_dat_o_29> 
INFO:Xst:2261 - The FF/Latch <i_dat_o_6> in Unit <lm32_instruction_unit_medium_icache_debug> is equivalent to the following 3 FFs/Latches, which will be removed : <i_dat_o_14> <i_dat_o_22> <i_dat_o_30> 
INFO:Xst:2261 - The FF/Latch <i_dat_o_7> in Unit <lm32_instruction_unit_medium_icache_debug> is equivalent to the following 3 FFs/Latches, which will be removed : <i_dat_o_15> <i_dat_o_23> <i_dat_o_31> 
INFO:Xst:2261 - The FF/Latch <i_cyc_o> in Unit <lm32_instruction_unit_medium_icache_debug> is equivalent to the following FF/Latch, which will be removed : <i_stb_o> 
INFO:Xst:2261 - The FF/Latch <d_stb_o> in Unit <lm32_load_store_unit_medium_icache_debug> is equivalent to the following FF/Latch, which will be removed : <d_cyc_o> 
INFO:Xst:2261 - The FF/Latch <fmc150_stellar_cmd_inst/out_reg_addr_27> in Unit <cdce72010_ctrl> is equivalent to the following 11 FFs/Latches, which will be removed : <fmc150_stellar_cmd_inst/out_reg_addr_26> <fmc150_stellar_cmd_inst/out_reg_addr_25> <fmc150_stellar_cmd_inst/out_reg_addr_24> <fmc150_stellar_cmd_inst/out_reg_addr_23> <fmc150_stellar_cmd_inst/out_reg_addr_22> <fmc150_stellar_cmd_inst/out_reg_addr_21> <fmc150_stellar_cmd_inst/out_reg_addr_20> <fmc150_stellar_cmd_inst/out_reg_addr_19> <fmc150_stellar_cmd_inst/out_reg_addr_18> <fmc150_stellar_cmd_inst/out_reg_addr_17> <fmc150_stellar_cmd_inst/out_reg_addr_16> 
INFO:Xst:2261 - The FF/Latch <fmc150_stellar_cmd_inst/in_reg_addr_sig_27> in Unit <cdce72010_ctrl> is equivalent to the following 11 FFs/Latches, which will be removed : <fmc150_stellar_cmd_inst/in_reg_addr_sig_26> <fmc150_stellar_cmd_inst/in_reg_addr_sig_25> <fmc150_stellar_cmd_inst/in_reg_addr_sig_24> <fmc150_stellar_cmd_inst/in_reg_addr_sig_23> <fmc150_stellar_cmd_inst/in_reg_addr_sig_22> <fmc150_stellar_cmd_inst/in_reg_addr_sig_21> <fmc150_stellar_cmd_inst/in_reg_addr_sig_20> <fmc150_stellar_cmd_inst/in_reg_addr_sig_19> <fmc150_stellar_cmd_inst/in_reg_addr_sig_18> <fmc150_stellar_cmd_inst/in_reg_addr_sig_17> <fmc150_stellar_cmd_inst/in_reg_addr_sig_16> 
INFO:Xst:2261 - The FF/Latch <fmc150_stellar_cmd_inst/out_reg_addr_27> in Unit <ads62p49_ctrl> is equivalent to the following 11 FFs/Latches, which will be removed : <fmc150_stellar_cmd_inst/out_reg_addr_26> <fmc150_stellar_cmd_inst/out_reg_addr_25> <fmc150_stellar_cmd_inst/out_reg_addr_24> <fmc150_stellar_cmd_inst/out_reg_addr_23> <fmc150_stellar_cmd_inst/out_reg_addr_22> <fmc150_stellar_cmd_inst/out_reg_addr_21> <fmc150_stellar_cmd_inst/out_reg_addr_20> <fmc150_stellar_cmd_inst/out_reg_addr_19> <fmc150_stellar_cmd_inst/out_reg_addr_18> <fmc150_stellar_cmd_inst/out_reg_addr_17> <fmc150_stellar_cmd_inst/out_reg_addr_16> 
INFO:Xst:2261 - The FF/Latch <fmc150_stellar_cmd_inst/in_reg_addr_sig_27> in Unit <ads62p49_ctrl> is equivalent to the following 11 FFs/Latches, which will be removed : <fmc150_stellar_cmd_inst/in_reg_addr_sig_26> <fmc150_stellar_cmd_inst/in_reg_addr_sig_25> <fmc150_stellar_cmd_inst/in_reg_addr_sig_24> <fmc150_stellar_cmd_inst/in_reg_addr_sig_23> <fmc150_stellar_cmd_inst/in_reg_addr_sig_22> <fmc150_stellar_cmd_inst/in_reg_addr_sig_21> <fmc150_stellar_cmd_inst/in_reg_addr_sig_20> <fmc150_stellar_cmd_inst/in_reg_addr_sig_19> <fmc150_stellar_cmd_inst/in_reg_addr_sig_18> <fmc150_stellar_cmd_inst/in_reg_addr_sig_17> <fmc150_stellar_cmd_inst/in_reg_addr_sig_16> 
INFO:Xst:2261 - The FF/Latch <fmc150_stellar_cmd_inst/out_reg_addr_27> in Unit <dac3283_ctrl> is equivalent to the following 11 FFs/Latches, which will be removed : <fmc150_stellar_cmd_inst/out_reg_addr_26> <fmc150_stellar_cmd_inst/out_reg_addr_25> <fmc150_stellar_cmd_inst/out_reg_addr_24> <fmc150_stellar_cmd_inst/out_reg_addr_23> <fmc150_stellar_cmd_inst/out_reg_addr_22> <fmc150_stellar_cmd_inst/out_reg_addr_21> <fmc150_stellar_cmd_inst/out_reg_addr_20> <fmc150_stellar_cmd_inst/out_reg_addr_19> <fmc150_stellar_cmd_inst/out_reg_addr_18> <fmc150_stellar_cmd_inst/out_reg_addr_17> <fmc150_stellar_cmd_inst/out_reg_addr_16> 
INFO:Xst:2261 - The FF/Latch <fmc150_stellar_cmd_inst/in_reg_addr_sig_27> in Unit <dac3283_ctrl> is equivalent to the following 11 FFs/Latches, which will be removed : <fmc150_stellar_cmd_inst/in_reg_addr_sig_26> <fmc150_stellar_cmd_inst/in_reg_addr_sig_25> <fmc150_stellar_cmd_inst/in_reg_addr_sig_24> <fmc150_stellar_cmd_inst/in_reg_addr_sig_23> <fmc150_stellar_cmd_inst/in_reg_addr_sig_22> <fmc150_stellar_cmd_inst/in_reg_addr_sig_21> <fmc150_stellar_cmd_inst/in_reg_addr_sig_20> <fmc150_stellar_cmd_inst/in_reg_addr_sig_19> <fmc150_stellar_cmd_inst/in_reg_addr_sig_18> <fmc150_stellar_cmd_inst/in_reg_addr_sig_17> <fmc150_stellar_cmd_inst/in_reg_addr_sig_16> 
INFO:Xst:2261 - The FF/Latch <fmc150_stellar_cmd_inst/out_reg_addr_27> in Unit <amc7823_ctrl> is equivalent to the following 11 FFs/Latches, which will be removed : <fmc150_stellar_cmd_inst/out_reg_addr_26> <fmc150_stellar_cmd_inst/out_reg_addr_25> <fmc150_stellar_cmd_inst/out_reg_addr_24> <fmc150_stellar_cmd_inst/out_reg_addr_23> <fmc150_stellar_cmd_inst/out_reg_addr_22> <fmc150_stellar_cmd_inst/out_reg_addr_21> <fmc150_stellar_cmd_inst/out_reg_addr_20> <fmc150_stellar_cmd_inst/out_reg_addr_19> <fmc150_stellar_cmd_inst/out_reg_addr_18> <fmc150_stellar_cmd_inst/out_reg_addr_17> <fmc150_stellar_cmd_inst/out_reg_addr_16> 
INFO:Xst:2261 - The FF/Latch <fmc150_stellar_cmd_inst/in_reg_addr_sig_27> in Unit <amc7823_ctrl> is equivalent to the following 11 FFs/Latches, which will be removed : <fmc150_stellar_cmd_inst/in_reg_addr_sig_26> <fmc150_stellar_cmd_inst/in_reg_addr_sig_25> <fmc150_stellar_cmd_inst/in_reg_addr_sig_24> <fmc150_stellar_cmd_inst/in_reg_addr_sig_23> <fmc150_stellar_cmd_inst/in_reg_addr_sig_22> <fmc150_stellar_cmd_inst/in_reg_addr_sig_21> <fmc150_stellar_cmd_inst/in_reg_addr_sig_20> <fmc150_stellar_cmd_inst/in_reg_addr_sig_19> <fmc150_stellar_cmd_inst/in_reg_addr_sig_18> <fmc150_stellar_cmd_inst/in_reg_addr_sig_17> <fmc150_stellar_cmd_inst/in_reg_addr_sig_16> 
WARNING:Xst:1710 - FF/Latch <fmc150_stellar_cmd_inst/in_reg_addr_sig_27> (without init value) has a constant value of 0 in block <cdce72010_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fmc150_stellar_cmd_inst/out_reg_addr_27> (without init value) has a constant value of 0 in block <cdce72010_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <fmc150_stellar_cmd_inst/in_reg_addr_sig_27> (without init value) has a constant value of 0 in block <ads62p49_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fmc150_stellar_cmd_inst/out_reg_addr_27> (without init value) has a constant value of 0 in block <ads62p49_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:2677 - Node <fmc150_stellar_cmd_inst/out_reg_31> of sequential type is unconnected in block <ads62p49_ctrl>.
WARNING:Xst:2677 - Node <fmc150_stellar_cmd_inst/out_reg_30> of sequential type is unconnected in block <ads62p49_ctrl>.
WARNING:Xst:2677 - Node <fmc150_stellar_cmd_inst/out_reg_29> of sequential type is unconnected in block <ads62p49_ctrl>.
WARNING:Xst:2677 - Node <fmc150_stellar_cmd_inst/out_reg_28> of sequential type is unconnected in block <ads62p49_ctrl>.
WARNING:Xst:2677 - Node <fmc150_stellar_cmd_inst/out_reg_27> of sequential type is unconnected in block <ads62p49_ctrl>.
WARNING:Xst:2677 - Node <fmc150_stellar_cmd_inst/out_reg_26> of sequential type is unconnected in block <ads62p49_ctrl>.
WARNING:Xst:2677 - Node <fmc150_stellar_cmd_inst/out_reg_25> of sequential type is unconnected in block <ads62p49_ctrl>.
WARNING:Xst:2677 - Node <fmc150_stellar_cmd_inst/out_reg_24> of sequential type is unconnected in block <ads62p49_ctrl>.
WARNING:Xst:2677 - Node <fmc150_stellar_cmd_inst/out_reg_23> of sequential type is unconnected in block <ads62p49_ctrl>.
WARNING:Xst:2677 - Node <fmc150_stellar_cmd_inst/out_reg_22> of sequential type is unconnected in block <ads62p49_ctrl>.
WARNING:Xst:2677 - Node <fmc150_stellar_cmd_inst/out_reg_21> of sequential type is unconnected in block <ads62p49_ctrl>.
WARNING:Xst:2677 - Node <fmc150_stellar_cmd_inst/out_reg_20> of sequential type is unconnected in block <ads62p49_ctrl>.
WARNING:Xst:2677 - Node <fmc150_stellar_cmd_inst/out_reg_19> of sequential type is unconnected in block <ads62p49_ctrl>.
WARNING:Xst:2677 - Node <fmc150_stellar_cmd_inst/out_reg_18> of sequential type is unconnected in block <ads62p49_ctrl>.
WARNING:Xst:2677 - Node <fmc150_stellar_cmd_inst/out_reg_17> of sequential type is unconnected in block <ads62p49_ctrl>.
WARNING:Xst:2677 - Node <fmc150_stellar_cmd_inst/out_reg_16> of sequential type is unconnected in block <ads62p49_ctrl>.
WARNING:Xst:2677 - Node <fmc150_stellar_cmd_inst/out_reg_15> of sequential type is unconnected in block <ads62p49_ctrl>.
WARNING:Xst:2677 - Node <fmc150_stellar_cmd_inst/out_reg_14> of sequential type is unconnected in block <ads62p49_ctrl>.
WARNING:Xst:2677 - Node <fmc150_stellar_cmd_inst/out_reg_13> of sequential type is unconnected in block <ads62p49_ctrl>.
WARNING:Xst:2677 - Node <fmc150_stellar_cmd_inst/out_reg_12> of sequential type is unconnected in block <ads62p49_ctrl>.
WARNING:Xst:2677 - Node <fmc150_stellar_cmd_inst/out_reg_11> of sequential type is unconnected in block <ads62p49_ctrl>.
WARNING:Xst:2677 - Node <fmc150_stellar_cmd_inst/out_reg_10> of sequential type is unconnected in block <ads62p49_ctrl>.
WARNING:Xst:2677 - Node <fmc150_stellar_cmd_inst/out_reg_9> of sequential type is unconnected in block <ads62p49_ctrl>.
WARNING:Xst:2677 - Node <fmc150_stellar_cmd_inst/out_reg_8> of sequential type is unconnected in block <ads62p49_ctrl>.
WARNING:Xst:1710 - FF/Latch <fmc150_stellar_cmd_inst/in_reg_addr_sig_27> (without init value) has a constant value of 0 in block <dac3283_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fmc150_stellar_cmd_inst/out_reg_addr_27> (without init value) has a constant value of 0 in block <dac3283_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:2677 - Node <fmc150_stellar_cmd_inst/out_reg_31> of sequential type is unconnected in block <dac3283_ctrl>.
WARNING:Xst:2677 - Node <fmc150_stellar_cmd_inst/out_reg_30> of sequential type is unconnected in block <dac3283_ctrl>.
WARNING:Xst:2677 - Node <fmc150_stellar_cmd_inst/out_reg_29> of sequential type is unconnected in block <dac3283_ctrl>.
WARNING:Xst:2677 - Node <fmc150_stellar_cmd_inst/out_reg_28> of sequential type is unconnected in block <dac3283_ctrl>.
WARNING:Xst:2677 - Node <fmc150_stellar_cmd_inst/out_reg_27> of sequential type is unconnected in block <dac3283_ctrl>.
WARNING:Xst:2677 - Node <fmc150_stellar_cmd_inst/out_reg_26> of sequential type is unconnected in block <dac3283_ctrl>.
WARNING:Xst:2677 - Node <fmc150_stellar_cmd_inst/out_reg_25> of sequential type is unconnected in block <dac3283_ctrl>.
WARNING:Xst:2677 - Node <fmc150_stellar_cmd_inst/out_reg_24> of sequential type is unconnected in block <dac3283_ctrl>.
WARNING:Xst:2677 - Node <fmc150_stellar_cmd_inst/out_reg_23> of sequential type is unconnected in block <dac3283_ctrl>.
WARNING:Xst:2677 - Node <fmc150_stellar_cmd_inst/out_reg_22> of sequential type is unconnected in block <dac3283_ctrl>.
WARNING:Xst:2677 - Node <fmc150_stellar_cmd_inst/out_reg_21> of sequential type is unconnected in block <dac3283_ctrl>.
WARNING:Xst:2677 - Node <fmc150_stellar_cmd_inst/out_reg_20> of sequential type is unconnected in block <dac3283_ctrl>.
WARNING:Xst:2677 - Node <fmc150_stellar_cmd_inst/out_reg_19> of sequential type is unconnected in block <dac3283_ctrl>.
WARNING:Xst:2677 - Node <fmc150_stellar_cmd_inst/out_reg_18> of sequential type is unconnected in block <dac3283_ctrl>.
WARNING:Xst:2677 - Node <fmc150_stellar_cmd_inst/out_reg_17> of sequential type is unconnected in block <dac3283_ctrl>.
WARNING:Xst:2677 - Node <fmc150_stellar_cmd_inst/out_reg_16> of sequential type is unconnected in block <dac3283_ctrl>.
WARNING:Xst:2677 - Node <fmc150_stellar_cmd_inst/out_reg_15> of sequential type is unconnected in block <dac3283_ctrl>.
WARNING:Xst:2677 - Node <fmc150_stellar_cmd_inst/out_reg_14> of sequential type is unconnected in block <dac3283_ctrl>.
WARNING:Xst:2677 - Node <fmc150_stellar_cmd_inst/out_reg_13> of sequential type is unconnected in block <dac3283_ctrl>.
WARNING:Xst:2677 - Node <fmc150_stellar_cmd_inst/out_reg_12> of sequential type is unconnected in block <dac3283_ctrl>.
WARNING:Xst:2677 - Node <fmc150_stellar_cmd_inst/out_reg_11> of sequential type is unconnected in block <dac3283_ctrl>.
WARNING:Xst:2677 - Node <fmc150_stellar_cmd_inst/out_reg_10> of sequential type is unconnected in block <dac3283_ctrl>.
WARNING:Xst:2677 - Node <fmc150_stellar_cmd_inst/out_reg_9> of sequential type is unconnected in block <dac3283_ctrl>.
WARNING:Xst:2677 - Node <fmc150_stellar_cmd_inst/out_reg_8> of sequential type is unconnected in block <dac3283_ctrl>.
WARNING:Xst:1710 - FF/Latch <fmc150_stellar_cmd_inst/in_reg_addr_sig_27> (without init value) has a constant value of 0 in block <amc7823_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fmc150_stellar_cmd_inst/out_reg_addr_27> (without init value) has a constant value of 0 in block <amc7823_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:2677 - Node <fmc150_stellar_cmd_inst/out_reg_31> of sequential type is unconnected in block <amc7823_ctrl>.
WARNING:Xst:2677 - Node <fmc150_stellar_cmd_inst/out_reg_30> of sequential type is unconnected in block <amc7823_ctrl>.
WARNING:Xst:2677 - Node <fmc150_stellar_cmd_inst/out_reg_29> of sequential type is unconnected in block <amc7823_ctrl>.
WARNING:Xst:2677 - Node <fmc150_stellar_cmd_inst/out_reg_28> of sequential type is unconnected in block <amc7823_ctrl>.
WARNING:Xst:2677 - Node <fmc150_stellar_cmd_inst/out_reg_27> of sequential type is unconnected in block <amc7823_ctrl>.
WARNING:Xst:2677 - Node <fmc150_stellar_cmd_inst/out_reg_26> of sequential type is unconnected in block <amc7823_ctrl>.
WARNING:Xst:2677 - Node <fmc150_stellar_cmd_inst/out_reg_25> of sequential type is unconnected in block <amc7823_ctrl>.
WARNING:Xst:2677 - Node <fmc150_stellar_cmd_inst/out_reg_24> of sequential type is unconnected in block <amc7823_ctrl>.
WARNING:Xst:2677 - Node <fmc150_stellar_cmd_inst/out_reg_23> of sequential type is unconnected in block <amc7823_ctrl>.
WARNING:Xst:2677 - Node <fmc150_stellar_cmd_inst/out_reg_22> of sequential type is unconnected in block <amc7823_ctrl>.
WARNING:Xst:2677 - Node <fmc150_stellar_cmd_inst/out_reg_21> of sequential type is unconnected in block <amc7823_ctrl>.
WARNING:Xst:2677 - Node <fmc150_stellar_cmd_inst/out_reg_20> of sequential type is unconnected in block <amc7823_ctrl>.
WARNING:Xst:2677 - Node <fmc150_stellar_cmd_inst/out_reg_19> of sequential type is unconnected in block <amc7823_ctrl>.
WARNING:Xst:2677 - Node <fmc150_stellar_cmd_inst/out_reg_18> of sequential type is unconnected in block <amc7823_ctrl>.
WARNING:Xst:2677 - Node <fmc150_stellar_cmd_inst/out_reg_17> of sequential type is unconnected in block <amc7823_ctrl>.
WARNING:Xst:2677 - Node <fmc150_stellar_cmd_inst/out_reg_16> of sequential type is unconnected in block <amc7823_ctrl>.
WARNING:Xst:1710 - FF/Latch <jtag_shift_0> (without init value) has a constant value of 0 in block <jtag_cores>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <jtag_shift_1> (without init value) has a constant value of 0 in block <jtag_cores>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <jtag_shift_2> (without init value) has a constant value of 0 in block <jtag_cores>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <jtag_shift_3> (without init value) has a constant value of 0 in block <jtag_cores>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <jtag_shift_4> (without init value) has a constant value of 0 in block <jtag_cores>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <jtag_shift_5> (without init value) has a constant value of 0 in block <jtag_cores>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <jtag_shift_6> (without init value) has a constant value of 0 in block <jtag_cores>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <jtag_shift_7> (without init value) has a constant value of 0 in block <jtag_cores>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <jtag_shift_8> (without init value) has a constant value of 0 in block <jtag_cores>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <jtag_shift_9> (without init value) has a constant value of 0 in block <jtag_cores>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <jtag_shift_10> (without init value) has a constant value of 0 in block <jtag_cores>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <jtag_latched_10> (without init value) has a constant value of 0 in block <jtag_cores>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <jtag_latched_9> (without init value) has a constant value of 0 in block <jtag_cores>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <jtag_latched_8> (without init value) has a constant value of 0 in block <jtag_cores>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <jtag_latched_7> (without init value) has a constant value of 0 in block <jtag_cores>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <jtag_latched_6> (without init value) has a constant value of 0 in block <jtag_cores>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <jtag_latched_5> (without init value) has a constant value of 0 in block <jtag_cores>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <jtag_latched_4> (without init value) has a constant value of 0 in block <jtag_cores>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <jtag_latched_3> (without init value) has a constant value of 0 in block <jtag_cores>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <jtag_latched_2> (without init value) has a constant value of 0 in block <jtag_cores>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <jtag_latched_1> (without init value) has a constant value of 0 in block <jtag_cores>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <jtag_latched_0> (without init value) has a constant value of 0 in block <jtag_cores>. This FF/Latch will be trimmed during the optimization process.
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/cdce72010_ctrl_inst/FSM_3> on signal <sh_state[1:3]> with user encoding.
----------------------------
 State          | Encoding
----------------------------
 idle           | 000
 reg_write      | 001
 start_reg_read | 010
 reg_read       | 011
 data_valid     | 100
----------------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/ads62p49_ctrl_inst/FSM_4> on signal <sh_state[1:2]> with user encoding.
------------------------
 State      | Encoding
------------------------
 idle       | 00
 instruct   | 01
 data_io    | 10
 data_valid | 11
------------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/dac3283_ctrl_inst/FSM_5> on signal <sh_state[1:2]> with user encoding.
------------------------
 State      | Encoding
------------------------
 idle       | 00
 instruct   | 01
 data_io    | 10
 data_valid | 11
------------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/amc7823_ctrl_inst/FSM_6> on signal <sh_state[1:2]> with user encoding.
------------------------
 State      | Encoding
------------------------
 idle       | 00
 instruct   | 01
 data_io    | 10
 data_valid | 11
------------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <cmp_uart/U_Wrapped_UART/gen_phys_uart.U_TX/FSM_7> on signal <state[1:4]> with user encoding.
-------------------
 State | Encoding
-------------------
 0000  | 0000
 0001  | 0001
 0100  | 0100
 0011  | 0011
 1000  | 1000
 1001  | 1001
 1010  | 1010
 1011  | 1011
 1100  | 1100
 1101  | 1101
 1110  | 1110
 1111  | 1111
 0010  | 0010
-------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <cmp_uart/U_Wrapped_UART/gen_phys_uart.U_RX/FSM_8> on signal <state[1:4]> with sequential encoding.
-------------------
 State | Encoding
-------------------
 0000  | 0000
 1000  | 0001
 1001  | 0010
 1010  | 0011
 1011  | 0100
 1100  | 0101
 1101  | 0110
 1110  | 0111
 1111  | 1000
 0001  | 1001
-------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/FSM_1> on signal <state[1:4]> with sequential encoding.
-------------------
 State | Encoding
-------------------
 0000  | 0000
 0001  | 0001
 0110  | 0010
 0101  | 0011
 0010  | 0100
 0011  | 0101
 0100  | 0110
 0111  | 0111
 1000  | 1000
-------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/FSM_0> on signal <state[1:2]> with gray encoding.
-------------------
 State | Encoding
-------------------
 0001  | 00
 0010  | 01
 0100  | 11
 1000  | 10
-------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/hw_debug/FSM_2> on signal <state[1:3]> with user encoding.
-------------------
 State | Encoding
-------------------
 000   | 000
 001   | 001
 010   | 010
 011   | 011
 100   | 100
-------------------
INFO:Xst:2146 - In block <generic_shiftreg_fifo>, Shifter <Mshreg_fifo_store<30><32>> <Mshreg_fifo_store<30><35>> <Mshreg_fifo_store<30><33>> <Mshreg_fifo_store<30><34>> are equivalent, XST will keep only <Mshreg_fifo_store<30><32>>.
INFO:Xst:2146 - In block <generic_shiftreg_fifo>, Shifter <Mshreg_fifo_store<30><38>> <Mshreg_fifo_store<30><37>> <Mshreg_fifo_store<30><39>> <Mshreg_fifo_store<30><40>> are equivalent, XST will keep only <Mshreg_fifo_store<30><38>>.
WARNING:Xst:1710 - FF/Latch <fmc150_stellar_cmd_inst/out_cmd_63> (without init value) has a constant value of 0 in block <cdce72010_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fmc150_stellar_cmd_inst/out_cmd_61> (without init value) has a constant value of 0 in block <cdce72010_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fmc150_stellar_cmd_inst/out_cmd_60> (without init value) has a constant value of 0 in block <cdce72010_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fmc150_stellar_cmd_inst/out_cmd_59> (without init value) has a constant value of 0 in block <cdce72010_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fmc150_stellar_cmd_inst/out_cmd_58> (without init value) has a constant value of 0 in block <cdce72010_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fmc150_stellar_cmd_inst/out_cmd_57> (without init value) has a constant value of 0 in block <cdce72010_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fmc150_stellar_cmd_inst/out_cmd_56> (without init value) has a constant value of 0 in block <cdce72010_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fmc150_stellar_cmd_inst/out_cmd_55> (without init value) has a constant value of 0 in block <cdce72010_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fmc150_stellar_cmd_inst/out_cmd_54> (without init value) has a constant value of 0 in block <cdce72010_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fmc150_stellar_cmd_inst/out_cmd_53> (without init value) has a constant value of 0 in block <cdce72010_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fmc150_stellar_cmd_inst/out_cmd_52> (without init value) has a constant value of 0 in block <cdce72010_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fmc150_stellar_cmd_inst/out_cmd_51> (without init value) has a constant value of 0 in block <cdce72010_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fmc150_stellar_cmd_inst/out_cmd_50> (without init value) has a constant value of 0 in block <cdce72010_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fmc150_stellar_cmd_inst/out_cmd_49> (without init value) has a constant value of 0 in block <cdce72010_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fmc150_stellar_cmd_inst/out_cmd_48> (without init value) has a constant value of 0 in block <cdce72010_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <fmc150_stellar_cmd_inst/out_cmd_54> (without init value) has a constant value of 0 in block <ads62p49_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fmc150_stellar_cmd_inst/out_cmd_53> (without init value) has a constant value of 0 in block <ads62p49_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fmc150_stellar_cmd_inst/out_cmd_52> (without init value) has a constant value of 0 in block <ads62p49_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fmc150_stellar_cmd_inst/out_cmd_51> (without init value) has a constant value of 0 in block <ads62p49_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fmc150_stellar_cmd_inst/out_cmd_50> (without init value) has a constant value of 0 in block <ads62p49_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fmc150_stellar_cmd_inst/out_cmd_49> (without init value) has a constant value of 0 in block <ads62p49_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fmc150_stellar_cmd_inst/out_cmd_48> (without init value) has a constant value of 0 in block <ads62p49_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fmc150_stellar_cmd_inst/out_cmd_31> (without init value) has a constant value of 0 in block <ads62p49_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fmc150_stellar_cmd_inst/out_cmd_30> (without init value) has a constant value of 0 in block <ads62p49_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fmc150_stellar_cmd_inst/out_cmd_29> (without init value) has a constant value of 0 in block <ads62p49_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fmc150_stellar_cmd_inst/out_cmd_28> (without init value) has a constant value of 0 in block <ads62p49_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fmc150_stellar_cmd_inst/out_cmd_27> (without init value) has a constant value of 0 in block <ads62p49_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fmc150_stellar_cmd_inst/out_cmd_26> (without init value) has a constant value of 0 in block <ads62p49_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fmc150_stellar_cmd_inst/out_cmd_25> (without init value) has a constant value of 0 in block <ads62p49_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fmc150_stellar_cmd_inst/out_cmd_24> (without init value) has a constant value of 0 in block <ads62p49_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fmc150_stellar_cmd_inst/out_cmd_23> (without init value) has a constant value of 0 in block <ads62p49_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fmc150_stellar_cmd_inst/out_cmd_22> (without init value) has a constant value of 0 in block <ads62p49_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fmc150_stellar_cmd_inst/out_cmd_21> (without init value) has a constant value of 0 in block <ads62p49_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fmc150_stellar_cmd_inst/out_cmd_20> (without init value) has a constant value of 0 in block <ads62p49_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fmc150_stellar_cmd_inst/out_cmd_19> (without init value) has a constant value of 0 in block <ads62p49_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fmc150_stellar_cmd_inst/out_cmd_18> (without init value) has a constant value of 0 in block <ads62p49_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fmc150_stellar_cmd_inst/out_cmd_17> (without init value) has a constant value of 0 in block <ads62p49_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fmc150_stellar_cmd_inst/out_cmd_16> (without init value) has a constant value of 0 in block <ads62p49_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fmc150_stellar_cmd_inst/out_cmd_15> (without init value) has a constant value of 0 in block <ads62p49_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fmc150_stellar_cmd_inst/out_cmd_14> (without init value) has a constant value of 0 in block <ads62p49_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fmc150_stellar_cmd_inst/out_cmd_13> (without init value) has a constant value of 0 in block <ads62p49_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fmc150_stellar_cmd_inst/out_cmd_12> (without init value) has a constant value of 0 in block <ads62p49_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fmc150_stellar_cmd_inst/out_cmd_11> (without init value) has a constant value of 0 in block <ads62p49_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fmc150_stellar_cmd_inst/out_cmd_10> (without init value) has a constant value of 0 in block <ads62p49_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fmc150_stellar_cmd_inst/out_cmd_9> (without init value) has a constant value of 0 in block <ads62p49_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fmc150_stellar_cmd_inst/out_cmd_8> (without init value) has a constant value of 0 in block <ads62p49_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <in_reg_8> (without init value) has a constant value of 0 in block <ads62p49_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <in_reg_9> (without init value) has a constant value of 0 in block <ads62p49_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <in_reg_10> (without init value) has a constant value of 0 in block <ads62p49_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <in_reg_11> (without init value) has a constant value of 0 in block <ads62p49_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <in_reg_12> (without init value) has a constant value of 0 in block <ads62p49_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <in_reg_13> (without init value) has a constant value of 0 in block <ads62p49_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <in_reg_14> (without init value) has a constant value of 0 in block <ads62p49_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <in_reg_15> (without init value) has a constant value of 0 in block <ads62p49_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <in_reg_16> (without init value) has a constant value of 0 in block <ads62p49_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <in_reg_17> (without init value) has a constant value of 0 in block <ads62p49_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <in_reg_18> (without init value) has a constant value of 0 in block <ads62p49_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <in_reg_19> (without init value) has a constant value of 0 in block <ads62p49_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <in_reg_20> (without init value) has a constant value of 0 in block <ads62p49_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <in_reg_21> (without init value) has a constant value of 0 in block <ads62p49_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <in_reg_22> (without init value) has a constant value of 0 in block <ads62p49_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <in_reg_23> (without init value) has a constant value of 0 in block <ads62p49_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <in_reg_24> (without init value) has a constant value of 0 in block <ads62p49_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <in_reg_25> (without init value) has a constant value of 0 in block <ads62p49_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <in_reg_26> (without init value) has a constant value of 0 in block <ads62p49_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <in_reg_27> (without init value) has a constant value of 0 in block <ads62p49_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <in_reg_28> (without init value) has a constant value of 0 in block <ads62p49_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <in_reg_29> (without init value) has a constant value of 0 in block <ads62p49_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <in_reg_30> (without init value) has a constant value of 0 in block <ads62p49_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <in_reg_31> (without init value) has a constant value of 0 in block <ads62p49_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fmc150_stellar_cmd_inst/out_cmd_63> (without init value) has a constant value of 0 in block <ads62p49_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fmc150_stellar_cmd_inst/out_cmd_61> (without init value) has a constant value of 0 in block <ads62p49_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fmc150_stellar_cmd_inst/out_cmd_60> (without init value) has a constant value of 0 in block <ads62p49_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fmc150_stellar_cmd_inst/out_cmd_59> (without init value) has a constant value of 0 in block <ads62p49_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fmc150_stellar_cmd_inst/out_cmd_58> (without init value) has a constant value of 0 in block <ads62p49_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fmc150_stellar_cmd_inst/out_cmd_57> (without init value) has a constant value of 0 in block <ads62p49_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fmc150_stellar_cmd_inst/out_cmd_56> (without init value) has a constant value of 0 in block <ads62p49_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fmc150_stellar_cmd_inst/out_cmd_55> (without init value) has a constant value of 0 in block <ads62p49_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <fmc150_stellar_cmd_inst/out_cmd_54> (without init value) has a constant value of 0 in block <dac3283_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fmc150_stellar_cmd_inst/out_cmd_53> (without init value) has a constant value of 0 in block <dac3283_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fmc150_stellar_cmd_inst/out_cmd_52> (without init value) has a constant value of 0 in block <dac3283_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fmc150_stellar_cmd_inst/out_cmd_51> (without init value) has a constant value of 0 in block <dac3283_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fmc150_stellar_cmd_inst/out_cmd_50> (without init value) has a constant value of 0 in block <dac3283_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fmc150_stellar_cmd_inst/out_cmd_49> (without init value) has a constant value of 0 in block <dac3283_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fmc150_stellar_cmd_inst/out_cmd_48> (without init value) has a constant value of 0 in block <dac3283_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fmc150_stellar_cmd_inst/out_cmd_31> (without init value) has a constant value of 0 in block <dac3283_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fmc150_stellar_cmd_inst/out_cmd_30> (without init value) has a constant value of 0 in block <dac3283_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fmc150_stellar_cmd_inst/out_cmd_29> (without init value) has a constant value of 0 in block <dac3283_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fmc150_stellar_cmd_inst/out_cmd_28> (without init value) has a constant value of 0 in block <dac3283_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fmc150_stellar_cmd_inst/out_cmd_27> (without init value) has a constant value of 0 in block <dac3283_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fmc150_stellar_cmd_inst/out_cmd_26> (without init value) has a constant value of 0 in block <dac3283_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fmc150_stellar_cmd_inst/out_cmd_25> (without init value) has a constant value of 0 in block <dac3283_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fmc150_stellar_cmd_inst/out_cmd_24> (without init value) has a constant value of 0 in block <dac3283_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fmc150_stellar_cmd_inst/out_cmd_23> (without init value) has a constant value of 0 in block <dac3283_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fmc150_stellar_cmd_inst/out_cmd_22> (without init value) has a constant value of 0 in block <dac3283_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fmc150_stellar_cmd_inst/out_cmd_21> (without init value) has a constant value of 0 in block <dac3283_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fmc150_stellar_cmd_inst/out_cmd_20> (without init value) has a constant value of 0 in block <dac3283_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fmc150_stellar_cmd_inst/out_cmd_19> (without init value) has a constant value of 0 in block <dac3283_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fmc150_stellar_cmd_inst/out_cmd_18> (without init value) has a constant value of 0 in block <dac3283_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fmc150_stellar_cmd_inst/out_cmd_17> (without init value) has a constant value of 0 in block <dac3283_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fmc150_stellar_cmd_inst/out_cmd_16> (without init value) has a constant value of 0 in block <dac3283_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fmc150_stellar_cmd_inst/out_cmd_15> (without init value) has a constant value of 0 in block <dac3283_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fmc150_stellar_cmd_inst/out_cmd_14> (without init value) has a constant value of 0 in block <dac3283_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fmc150_stellar_cmd_inst/out_cmd_13> (without init value) has a constant value of 0 in block <dac3283_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fmc150_stellar_cmd_inst/out_cmd_12> (without init value) has a constant value of 0 in block <dac3283_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fmc150_stellar_cmd_inst/out_cmd_11> (without init value) has a constant value of 0 in block <dac3283_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fmc150_stellar_cmd_inst/out_cmd_10> (without init value) has a constant value of 0 in block <dac3283_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fmc150_stellar_cmd_inst/out_cmd_9> (without init value) has a constant value of 0 in block <dac3283_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fmc150_stellar_cmd_inst/out_cmd_8> (without init value) has a constant value of 0 in block <dac3283_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <in_reg_8> (without init value) has a constant value of 0 in block <dac3283_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <in_reg_9> (without init value) has a constant value of 0 in block <dac3283_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <in_reg_10> (without init value) has a constant value of 0 in block <dac3283_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <in_reg_11> (without init value) has a constant value of 0 in block <dac3283_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <in_reg_12> (without init value) has a constant value of 0 in block <dac3283_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <in_reg_13> (without init value) has a constant value of 0 in block <dac3283_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <in_reg_14> (without init value) has a constant value of 0 in block <dac3283_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <in_reg_15> (without init value) has a constant value of 0 in block <dac3283_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <in_reg_16> (without init value) has a constant value of 0 in block <dac3283_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <in_reg_17> (without init value) has a constant value of 0 in block <dac3283_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <in_reg_18> (without init value) has a constant value of 0 in block <dac3283_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <in_reg_19> (without init value) has a constant value of 0 in block <dac3283_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <in_reg_20> (without init value) has a constant value of 0 in block <dac3283_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <in_reg_21> (without init value) has a constant value of 0 in block <dac3283_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <in_reg_22> (without init value) has a constant value of 0 in block <dac3283_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <in_reg_23> (without init value) has a constant value of 0 in block <dac3283_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <in_reg_24> (without init value) has a constant value of 0 in block <dac3283_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <in_reg_25> (without init value) has a constant value of 0 in block <dac3283_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <in_reg_26> (without init value) has a constant value of 0 in block <dac3283_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <in_reg_27> (without init value) has a constant value of 0 in block <dac3283_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <in_reg_28> (without init value) has a constant value of 0 in block <dac3283_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <in_reg_29> (without init value) has a constant value of 0 in block <dac3283_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <in_reg_30> (without init value) has a constant value of 0 in block <dac3283_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <in_reg_31> (without init value) has a constant value of 0 in block <dac3283_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fmc150_stellar_cmd_inst/out_cmd_63> (without init value) has a constant value of 0 in block <dac3283_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fmc150_stellar_cmd_inst/out_cmd_61> (without init value) has a constant value of 0 in block <dac3283_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fmc150_stellar_cmd_inst/out_cmd_60> (without init value) has a constant value of 0 in block <dac3283_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fmc150_stellar_cmd_inst/out_cmd_59> (without init value) has a constant value of 0 in block <dac3283_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fmc150_stellar_cmd_inst/out_cmd_58> (without init value) has a constant value of 0 in block <dac3283_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fmc150_stellar_cmd_inst/out_cmd_57> (without init value) has a constant value of 0 in block <dac3283_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fmc150_stellar_cmd_inst/out_cmd_56> (without init value) has a constant value of 0 in block <dac3283_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fmc150_stellar_cmd_inst/out_cmd_55> (without init value) has a constant value of 0 in block <dac3283_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <fmc150_stellar_cmd_inst/out_cmd_54> (without init value) has a constant value of 0 in block <amc7823_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fmc150_stellar_cmd_inst/out_cmd_53> (without init value) has a constant value of 0 in block <amc7823_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fmc150_stellar_cmd_inst/out_cmd_52> (without init value) has a constant value of 0 in block <amc7823_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fmc150_stellar_cmd_inst/out_cmd_51> (without init value) has a constant value of 0 in block <amc7823_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fmc150_stellar_cmd_inst/out_cmd_50> (without init value) has a constant value of 0 in block <amc7823_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fmc150_stellar_cmd_inst/out_cmd_49> (without init value) has a constant value of 0 in block <amc7823_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fmc150_stellar_cmd_inst/out_cmd_48> (without init value) has a constant value of 0 in block <amc7823_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fmc150_stellar_cmd_inst/out_cmd_31> (without init value) has a constant value of 0 in block <amc7823_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fmc150_stellar_cmd_inst/out_cmd_30> (without init value) has a constant value of 0 in block <amc7823_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fmc150_stellar_cmd_inst/out_cmd_29> (without init value) has a constant value of 0 in block <amc7823_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fmc150_stellar_cmd_inst/out_cmd_28> (without init value) has a constant value of 0 in block <amc7823_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fmc150_stellar_cmd_inst/out_cmd_27> (without init value) has a constant value of 0 in block <amc7823_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fmc150_stellar_cmd_inst/out_cmd_26> (without init value) has a constant value of 0 in block <amc7823_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fmc150_stellar_cmd_inst/out_cmd_25> (without init value) has a constant value of 0 in block <amc7823_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fmc150_stellar_cmd_inst/out_cmd_24> (without init value) has a constant value of 0 in block <amc7823_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fmc150_stellar_cmd_inst/out_cmd_23> (without init value) has a constant value of 0 in block <amc7823_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fmc150_stellar_cmd_inst/out_cmd_22> (without init value) has a constant value of 0 in block <amc7823_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fmc150_stellar_cmd_inst/out_cmd_21> (without init value) has a constant value of 0 in block <amc7823_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fmc150_stellar_cmd_inst/out_cmd_20> (without init value) has a constant value of 0 in block <amc7823_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fmc150_stellar_cmd_inst/out_cmd_19> (without init value) has a constant value of 0 in block <amc7823_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fmc150_stellar_cmd_inst/out_cmd_18> (without init value) has a constant value of 0 in block <amc7823_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fmc150_stellar_cmd_inst/out_cmd_17> (without init value) has a constant value of 0 in block <amc7823_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fmc150_stellar_cmd_inst/out_cmd_16> (without init value) has a constant value of 0 in block <amc7823_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <in_reg_16> (without init value) has a constant value of 0 in block <amc7823_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <in_reg_17> (without init value) has a constant value of 0 in block <amc7823_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <in_reg_18> (without init value) has a constant value of 0 in block <amc7823_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <in_reg_19> (without init value) has a constant value of 0 in block <amc7823_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <in_reg_20> (without init value) has a constant value of 0 in block <amc7823_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <in_reg_21> (without init value) has a constant value of 0 in block <amc7823_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <in_reg_22> (without init value) has a constant value of 0 in block <amc7823_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <in_reg_23> (without init value) has a constant value of 0 in block <amc7823_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <in_reg_24> (without init value) has a constant value of 0 in block <amc7823_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <in_reg_25> (without init value) has a constant value of 0 in block <amc7823_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <in_reg_26> (without init value) has a constant value of 0 in block <amc7823_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <in_reg_27> (without init value) has a constant value of 0 in block <amc7823_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <in_reg_28> (without init value) has a constant value of 0 in block <amc7823_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <in_reg_29> (without init value) has a constant value of 0 in block <amc7823_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <in_reg_30> (without init value) has a constant value of 0 in block <amc7823_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <in_reg_31> (without init value) has a constant value of 0 in block <amc7823_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fmc150_stellar_cmd_inst/out_cmd_63> (without init value) has a constant value of 0 in block <amc7823_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fmc150_stellar_cmd_inst/out_cmd_61> (without init value) has a constant value of 0 in block <amc7823_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fmc150_stellar_cmd_inst/out_cmd_60> (without init value) has a constant value of 0 in block <amc7823_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fmc150_stellar_cmd_inst/out_cmd_59> (without init value) has a constant value of 0 in block <amc7823_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fmc150_stellar_cmd_inst/out_cmd_58> (without init value) has a constant value of 0 in block <amc7823_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fmc150_stellar_cmd_inst/out_cmd_57> (without init value) has a constant value of 0 in block <amc7823_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fmc150_stellar_cmd_inst/out_cmd_56> (without init value) has a constant value of 0 in block <amc7823_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <fmc150_stellar_cmd_inst/out_cmd_55> (without init value) has a constant value of 0 in block <amc7823_ctrl>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:2677 - Node <out_reg_8> of sequential type is unconnected in block <wb_gpio_port>.
WARNING:Xst:2677 - Node <out_reg_9> of sequential type is unconnected in block <wb_gpio_port>.
WARNING:Xst:2677 - Node <out_reg_10> of sequential type is unconnected in block <wb_gpio_port>.
WARNING:Xst:2677 - Node <out_reg_11> of sequential type is unconnected in block <wb_gpio_port>.
WARNING:Xst:2677 - Node <out_reg_12> of sequential type is unconnected in block <wb_gpio_port>.
WARNING:Xst:2677 - Node <out_reg_13> of sequential type is unconnected in block <wb_gpio_port>.
WARNING:Xst:2677 - Node <out_reg_14> of sequential type is unconnected in block <wb_gpio_port>.
WARNING:Xst:2677 - Node <out_reg_15> of sequential type is unconnected in block <wb_gpio_port>.
WARNING:Xst:2677 - Node <out_reg_16> of sequential type is unconnected in block <wb_gpio_port>.
WARNING:Xst:2677 - Node <out_reg_17> of sequential type is unconnected in block <wb_gpio_port>.
WARNING:Xst:2677 - Node <out_reg_18> of sequential type is unconnected in block <wb_gpio_port>.
WARNING:Xst:2677 - Node <out_reg_19> of sequential type is unconnected in block <wb_gpio_port>.
WARNING:Xst:2677 - Node <out_reg_20> of sequential type is unconnected in block <wb_gpio_port>.
WARNING:Xst:2677 - Node <out_reg_21> of sequential type is unconnected in block <wb_gpio_port>.
WARNING:Xst:2677 - Node <out_reg_22> of sequential type is unconnected in block <wb_gpio_port>.
WARNING:Xst:2677 - Node <out_reg_23> of sequential type is unconnected in block <wb_gpio_port>.
WARNING:Xst:2677 - Node <out_reg_24> of sequential type is unconnected in block <wb_gpio_port>.
WARNING:Xst:2677 - Node <out_reg_25> of sequential type is unconnected in block <wb_gpio_port>.
WARNING:Xst:2677 - Node <out_reg_26> of sequential type is unconnected in block <wb_gpio_port>.
WARNING:Xst:2677 - Node <out_reg_27> of sequential type is unconnected in block <wb_gpio_port>.
WARNING:Xst:2677 - Node <out_reg_28> of sequential type is unconnected in block <wb_gpio_port>.
WARNING:Xst:2677 - Node <out_reg_29> of sequential type is unconnected in block <wb_gpio_port>.
WARNING:Xst:2677 - Node <out_reg_30> of sequential type is unconnected in block <wb_gpio_port>.
WARNING:Xst:2677 - Node <out_reg_31> of sequential type is unconnected in block <wb_gpio_port>.
WARNING:Xst:1710 - FF/Latch <rddata_reg_8> (without init value) has a constant value of 0 in block <simple_uart_wb>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <i_cti_o_1> (without init value) has a constant value of 1 in block <lm32_instruction_unit_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
INFO:Xst:1901 - Instance gen_adc_lvds_ddr[0].cmp_iddr in unit adc_channel_lvds_ddr of type IDDR has been replaced by IDDR_2CLK
INFO:Xst:1901 - Instance gen_adc_lvds_ddr[1].cmp_iddr in unit adc_channel_lvds_ddr of type IDDR has been replaced by IDDR_2CLK
INFO:Xst:1901 - Instance gen_adc_lvds_ddr[2].cmp_iddr in unit adc_channel_lvds_ddr of type IDDR has been replaced by IDDR_2CLK
INFO:Xst:1901 - Instance gen_adc_lvds_ddr[3].cmp_iddr in unit adc_channel_lvds_ddr of type IDDR has been replaced by IDDR_2CLK
INFO:Xst:1901 - Instance gen_adc_lvds_ddr[4].cmp_iddr in unit adc_channel_lvds_ddr of type IDDR has been replaced by IDDR_2CLK
INFO:Xst:1901 - Instance gen_adc_lvds_ddr[5].cmp_iddr in unit adc_channel_lvds_ddr of type IDDR has been replaced by IDDR_2CLK
INFO:Xst:1901 - Instance gen_adc_lvds_ddr[6].cmp_iddr in unit adc_channel_lvds_ddr of type IDDR has been replaced by IDDR_2CLK
INFO:Xst:1901 - Instance oserdes_clock in unit fmc150_dac_if of type OSERDES has been replaced by OSERDESE1
INFO:Xst:1901 - Instance dac_data[0].oserdes_data in unit fmc150_dac_if of type OSERDES has been replaced by OSERDESE1
INFO:Xst:1901 - Instance dac_data[1].oserdes_data in unit fmc150_dac_if of type OSERDES has been replaced by OSERDESE1
INFO:Xst:1901 - Instance dac_data[2].oserdes_data in unit fmc150_dac_if of type OSERDES has been replaced by OSERDESE1
INFO:Xst:1901 - Instance dac_data[3].oserdes_data in unit fmc150_dac_if of type OSERDES has been replaced by OSERDESE1
INFO:Xst:1901 - Instance dac_data[4].oserdes_data in unit fmc150_dac_if of type OSERDES has been replaced by OSERDESE1
INFO:Xst:1901 - Instance dac_data[5].oserdes_data in unit fmc150_dac_if of type OSERDES has been replaced by OSERDESE1
INFO:Xst:1901 - Instance dac_data[6].oserdes_data in unit fmc150_dac_if of type OSERDES has been replaced by OSERDESE1
INFO:Xst:1901 - Instance dac_data[7].oserdes_data in unit fmc150_dac_if of type OSERDES has been replaced by OSERDESE1
INFO:Xst:1901 - Instance oserdes_frame in unit fmc150_dac_if of type OSERDES has been replaced by OSERDESE1
INFO:Xst:2261 - The FF/Latch <gen_serial_clk.clk_div_3> in Unit <cdce72010_ctrl> is equivalent to the following FF/Latch, which will be removed : <sclk_ext> 
INFO:Xst:2261 - The FF/Latch <gen_serial_clk.clk_div_3> in Unit <ads62p49_ctrl> is equivalent to the following FF/Latch, which will be removed : <serial_clk> 
INFO:Xst:2261 - The FF/Latch <gen_serial_clk.clk_div_3> in Unit <dac3283_ctrl> is equivalent to the following FF/Latch, which will be removed : <sclk_ext> 
INFO:Xst:2261 - The FF/Latch <gen_serial_clk.clk_div_3> in Unit <amc7823_ctrl> is equivalent to the following FF/Latch, which will be removed : <sclk_ext> 
INFO:Xst:2261 - The FF/Latch <i_cti_o_0> in Unit <lm32_instruction_unit_medium_icache_debug> is equivalent to the following FF/Latch, which will be removed : <i_cti_o_2> 
WARNING:Xst:2042 - Unit wb_gpio_port: 8 internal tristates are replaced by logic (pull-up yes): gpio_b<0>, gpio_b<1>, gpio_b<2>, gpio_b<3>, gpio_b<4>, gpio_b<5>, gpio_b<6>, gpio_b<7>.
WARNING:Xst:2041 - Unit cdce72010_ctrl: 1 internal tristate is replaced by logic (pull-up yes): spi_sdo.
WARNING:Xst:2041 - Unit ads62p49_ctrl: 1 internal tristate is replaced by logic (pull-up yes): spi_sdo.
WARNING:Xst:2041 - Unit dac3283_ctrl: 1 internal tristate is replaced by logic (pull-up yes): spi_sdo.
WARNING:Xst:2041 - Unit amc7823_ctrl: 1 internal tristate is replaced by logic (pull-up yes): spi_sdo.

Optimizing unit <fmc150_testbench> ...

Optimizing unit <dbe_bpm_simple_top> ...

Optimizing unit <wb_fmc150> ...

Optimizing unit <adc_channel_lvds_ddr> ...

Optimizing unit <fmc150_spi_ctrl> ...

Optimizing unit <cdce72010_ctrl> ...

Optimizing unit <pulse2pulse> ...

Optimizing unit <ads62p49_ctrl> ...

Optimizing unit <dac3283_ctrl> ...

Optimizing unit <amc7823_ctrl> ...

Optimizing unit <fmc150_dac_if> ...

Optimizing unit <wb_fmc150_port> ...

Optimizing unit <xwb_stream_source> ...

Optimizing unit <generic_shiftreg_fifo> ...

Optimizing unit <wb_gpio_port> ...

Optimizing unit <gc_sync_ffs> ...

Optimizing unit <wb_simple_uart> ...

Optimizing unit <wb_slave_adapter_3> ...

Optimizing unit <simple_uart_wb> ...
WARNING:Xst:1710 - FF/Latch <rddata_reg_31> (without init value) has a constant value of 0 in block <simple_uart_wb>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_30> (without init value) has a constant value of 0 in block <simple_uart_wb>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_29> (without init value) has a constant value of 0 in block <simple_uart_wb>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_28> (without init value) has a constant value of 0 in block <simple_uart_wb>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_27> (without init value) has a constant value of 0 in block <simple_uart_wb>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_26> (without init value) has a constant value of 0 in block <simple_uart_wb>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_25> (without init value) has a constant value of 0 in block <simple_uart_wb>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_24> (without init value) has a constant value of 0 in block <simple_uart_wb>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_23> (without init value) has a constant value of 0 in block <simple_uart_wb>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_22> (without init value) has a constant value of 0 in block <simple_uart_wb>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_21> (without init value) has a constant value of 0 in block <simple_uart_wb>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_20> (without init value) has a constant value of 0 in block <simple_uart_wb>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_19> (without init value) has a constant value of 0 in block <simple_uart_wb>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_18> (without init value) has a constant value of 0 in block <simple_uart_wb>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_17> (without init value) has a constant value of 0 in block <simple_uart_wb>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_16> (without init value) has a constant value of 0 in block <simple_uart_wb>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_15> (without init value) has a constant value of 0 in block <simple_uart_wb>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_14> (without init value) has a constant value of 0 in block <simple_uart_wb>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_13> (without init value) has a constant value of 0 in block <simple_uart_wb>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_12> (without init value) has a constant value of 0 in block <simple_uart_wb>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_11> (without init value) has a constant value of 0 in block <simple_uart_wb>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_10> (without init value) has a constant value of 0 in block <simple_uart_wb>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_9> (without init value) has a constant value of 0 in block <simple_uart_wb>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <rddata_reg_31> (without init value) has a constant value of 0 in block <simple_uart_wb>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_30> (without init value) has a constant value of 0 in block <simple_uart_wb>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_29> (without init value) has a constant value of 0 in block <simple_uart_wb>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_28> (without init value) has a constant value of 0 in block <simple_uart_wb>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_27> (without init value) has a constant value of 0 in block <simple_uart_wb>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_26> (without init value) has a constant value of 0 in block <simple_uart_wb>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_25> (without init value) has a constant value of 0 in block <simple_uart_wb>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_24> (without init value) has a constant value of 0 in block <simple_uart_wb>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_23> (without init value) has a constant value of 0 in block <simple_uart_wb>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_22> (without init value) has a constant value of 0 in block <simple_uart_wb>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_21> (without init value) has a constant value of 0 in block <simple_uart_wb>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_20> (without init value) has a constant value of 0 in block <simple_uart_wb>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_19> (without init value) has a constant value of 0 in block <simple_uart_wb>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_18> (without init value) has a constant value of 0 in block <simple_uart_wb>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_17> (without init value) has a constant value of 0 in block <simple_uart_wb>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_16> (without init value) has a constant value of 0 in block <simple_uart_wb>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_15> (without init value) has a constant value of 0 in block <simple_uart_wb>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_14> (without init value) has a constant value of 0 in block <simple_uart_wb>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_13> (without init value) has a constant value of 0 in block <simple_uart_wb>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_12> (without init value) has a constant value of 0 in block <simple_uart_wb>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_11> (without init value) has a constant value of 0 in block <simple_uart_wb>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_10> (without init value) has a constant value of 0 in block <simple_uart_wb>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <rddata_reg_9> (without init value) has a constant value of 0 in block <simple_uart_wb>. This FF/Latch will be trimmed during the optimization process.

Optimizing unit <uart_baud_gen> ...

Optimizing unit <uart_async_tx> ...

Optimizing unit <uart_async_rx> ...

Optimizing unit <xwb_crossbar> ...

Optimizing unit <gc_reset> ...

Optimizing unit <xwb_dma> ...

Optimizing unit <xwb_lm32> ...

Optimizing unit <lm32_cpu_medium_icache_debug> ...

Optimizing unit <lm32_interrupt_medium_icache_debug> ...
WARNING:Xst:1710 - FF/Latch <ip_31> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_30> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_29> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_28> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_27> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_26> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_25> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_24> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_23> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_22> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_21> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_20> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_19> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_18> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_17> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_16> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_15> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_14> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_13> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_12> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_11> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_10> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_9> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_8> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_7> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_6> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_5> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_4> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_3> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_2> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_1> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <ip_31> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_30> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_29> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_28> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_27> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_26> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_25> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_24> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_23> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_22> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_21> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_20> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_19> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_18> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_17> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_16> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_15> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_14> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_13> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_12> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_11> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_10> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_9> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_8> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_7> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_6> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_5> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_4> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_3> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_2> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ip_1> (without init value) has a constant value of 0 in block <lm32_interrupt_medium_icache_debug>. This FF/Latch will be trimmed during the optimization process.

Optimizing unit <lm32_jtag_medium_icache_debug> ...

Optimizing unit <lm32_instruction_unit_medium_icache_debug> ...

Optimizing unit <lm32_icache_medium_icache_debug> ...

Optimizing unit <lm32_ram_2> ...

Optimizing unit <lm32_load_store_unit_medium_icache_debug> ...

Optimizing unit <lm32_shifter> ...

Optimizing unit <lm32_multiplier> ...

Optimizing unit <lm32_debug_medium_icache_debug> ...

Optimizing unit <lm32_decoder_medium_icache_debug> ...

Optimizing unit <xwb_dpram> ...

Optimizing unit <generic_dpram_sameclock> ...
WARNING:Xst:1710 - FF/Latch <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_byte_1_6> (without init value) has a constant value of 0 in block <dbe_bpm_simple_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_byte_1_5> (without init value) has a constant value of 0 in block <dbe_bpm_simple_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_byte_1_4> (without init value) has a constant value of 0 in block <dbe_bpm_simple_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_byte_1_3> (without init value) has a constant value of 0 in block <dbe_bpm_simple_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_byte_1_2> (without init value) has a constant value of 0 in block <dbe_bpm_simple_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_byte_1_1> (without init value) has a constant value of 0 in block <dbe_bpm_simple_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_byte_1_0> (without init value) has a constant value of 0 in block <dbe_bpm_simple_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_byte_4_7> (without init value) has a constant value of 0 in block <dbe_bpm_simple_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_byte_4_6> (without init value) has a constant value of 0 in block <dbe_bpm_simple_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_byte_4_5> (without init value) has a constant value of 0 in block <dbe_bpm_simple_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_byte_4_4> (without init value) has a constant value of 0 in block <dbe_bpm_simple_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_byte_4_3> (without init value) has a constant value of 0 in block <dbe_bpm_simple_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_byte_4_2> (without init value) has a constant value of 0 in block <dbe_bpm_simple_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_byte_4_1> (without init value) has a constant value of 0 in block <dbe_bpm_simple_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_byte_4_0> (without init value) has a constant value of 0 in block <dbe_bpm_simple_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_byte_0_7> (without init value) has a constant value of 0 in block <dbe_bpm_simple_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_byte_0_6> (without init value) has a constant value of 0 in block <dbe_bpm_simple_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_byte_0_5> (without init value) has a constant value of 0 in block <dbe_bpm_simple_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_byte_0_4> (without init value) has a constant value of 0 in block <dbe_bpm_simple_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_byte_0_3> (without init value) has a constant value of 0 in block <dbe_bpm_simple_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_byte_0_2> (without init value) has a constant value of 0 in block <dbe_bpm_simple_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_byte_0_1> (without init value) has a constant value of 0 in block <dbe_bpm_simple_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_byte_0_0> (without init value) has a constant value of 0 in block <dbe_bpm_simple_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/i_adr_o_31> (without init value) has a constant value of 0 in block <dbe_bpm_simple_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/jtag_access> (without init value) has a constant value of 0 in block <dbe_bpm_simple_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/i_we_o> (without init value) has a constant value of 0 in block <dbe_bpm_simple_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/i_dat_o_2> (without init value) has a constant value of 0 in block <dbe_bpm_simple_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/state_FSM_FFd2> (without init value) has a constant value of 0 in block <dbe_bpm_simple_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/state_FSM_FFd3> (without init value) has a constant value of 0 in block <dbe_bpm_simple_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/state_FSM_FFd4> (without init value) has a constant value of 0 in block <dbe_bpm_simple_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_write_enable> (without init value) has a constant value of 0 in block <dbe_bpm_simple_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_csr_write_enable> (without init value) has a constant value of 0 in block <dbe_bpm_simple_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_read_enable> (without init value) has a constant value of 0 in block <dbe_bpm_simple_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/uart_rx_valid> (without init value) has a constant value of 0 in block <dbe_bpm_simple_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/state_FSM_FFd1> (without init value) has a constant value of 0 in block <dbe_bpm_simple_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_reset> (without init value) has a constant value of 0 in block <dbe_bpm_simple_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_break> (without init value) has a constant value of 0 in block <dbe_bpm_simple_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/command_3> (without init value) has a constant value of 0 in block <dbe_bpm_simple_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/command_2> (without init value) has a constant value of 0 in block <dbe_bpm_simple_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/command_1> (without init value) has a constant value of 0 in block <dbe_bpm_simple_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/command_0> (without init value) has a constant value of 0 in block <dbe_bpm_simple_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/rx_update> (without init value) has a constant value of 0 in block <dbe_bpm_simple_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/uart_rx_byte_7> (without init value) has a constant value of 0 in block <dbe_bpm_simple_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/uart_rx_byte_6> (without init value) has a constant value of 0 in block <dbe_bpm_simple_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/uart_rx_byte_5> (without init value) has a constant value of 0 in block <dbe_bpm_simple_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/uart_rx_byte_4> (without init value) has a constant value of 0 in block <dbe_bpm_simple_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/uart_rx_byte_3> (without init value) has a constant value of 0 in block <dbe_bpm_simple_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/uart_rx_byte_2> (without init value) has a constant value of 0 in block <dbe_bpm_simple_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/uart_rx_byte_1> (without init value) has a constant value of 0 in block <dbe_bpm_simple_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/uart_rx_byte_0> (without init value) has a constant value of 0 in block <dbe_bpm_simple_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_byte_1_7> (without init value) has a constant value of 0 in block <dbe_bpm_simple_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/i_dat_o_0> (without init value) has a constant value of 0 in block <dbe_bpm_simple_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/i_dat_o_1> (without init value) has a constant value of 0 in block <dbe_bpm_simple_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/i_dat_o_3> (without init value) has a constant value of 0 in block <dbe_bpm_simple_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/i_dat_o_4> (without init value) has a constant value of 0 in block <dbe_bpm_simple_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/i_dat_o_5> (without init value) has a constant value of 0 in block <dbe_bpm_simple_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/i_dat_o_6> (without init value) has a constant value of 0 in block <dbe_bpm_simple_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/i_dat_o_7> (without init value) has a constant value of 0 in block <dbe_bpm_simple_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/rx_update_r> (without init value) has a constant value of 0 in block <dbe_bpm_simple_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/rx_update_r_r> (without init value) has a constant value of 0 in block <dbe_bpm_simple_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/rx_update_r_r_r> (without init value) has a constant value of 0 in block <dbe_bpm_simple_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:2677 - Node <cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/cdce72010_ctrl_inst/fmc150_stellar_cmd_inst/out_cmd_32> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/cdce72010_ctrl_inst/fmc150_stellar_cmd_inst/out_cmd_33> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/cdce72010_ctrl_inst/fmc150_stellar_cmd_inst/out_cmd_34> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/cdce72010_ctrl_inst/fmc150_stellar_cmd_inst/out_cmd_35> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/cdce72010_ctrl_inst/fmc150_stellar_cmd_inst/out_cmd_36> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/cdce72010_ctrl_inst/fmc150_stellar_cmd_inst/out_cmd_37> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/cdce72010_ctrl_inst/fmc150_stellar_cmd_inst/out_cmd_38> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/cdce72010_ctrl_inst/fmc150_stellar_cmd_inst/out_cmd_39> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/cdce72010_ctrl_inst/fmc150_stellar_cmd_inst/out_cmd_40> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/cdce72010_ctrl_inst/fmc150_stellar_cmd_inst/out_cmd_41> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/cdce72010_ctrl_inst/fmc150_stellar_cmd_inst/out_cmd_42> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/cdce72010_ctrl_inst/fmc150_stellar_cmd_inst/out_cmd_43> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/cdce72010_ctrl_inst/fmc150_stellar_cmd_inst/out_cmd_44> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/cdce72010_ctrl_inst/fmc150_stellar_cmd_inst/out_cmd_45> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/cdce72010_ctrl_inst/fmc150_stellar_cmd_inst/out_cmd_46> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/cdce72010_ctrl_inst/fmc150_stellar_cmd_inst/out_cmd_47> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/cdce72010_ctrl_inst/fmc150_stellar_cmd_inst/out_cmd_62> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/ads62p49_ctrl_inst/fmc150_stellar_cmd_inst/out_cmd_32> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/ads62p49_ctrl_inst/fmc150_stellar_cmd_inst/out_cmd_33> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/ads62p49_ctrl_inst/fmc150_stellar_cmd_inst/out_cmd_34> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/ads62p49_ctrl_inst/fmc150_stellar_cmd_inst/out_cmd_35> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/ads62p49_ctrl_inst/fmc150_stellar_cmd_inst/out_cmd_36> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/ads62p49_ctrl_inst/fmc150_stellar_cmd_inst/out_cmd_37> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/ads62p49_ctrl_inst/fmc150_stellar_cmd_inst/out_cmd_38> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/ads62p49_ctrl_inst/fmc150_stellar_cmd_inst/out_cmd_39> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/ads62p49_ctrl_inst/fmc150_stellar_cmd_inst/out_cmd_40> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/ads62p49_ctrl_inst/fmc150_stellar_cmd_inst/out_cmd_41> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/ads62p49_ctrl_inst/fmc150_stellar_cmd_inst/out_cmd_42> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/ads62p49_ctrl_inst/fmc150_stellar_cmd_inst/out_cmd_43> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/ads62p49_ctrl_inst/fmc150_stellar_cmd_inst/out_cmd_44> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/ads62p49_ctrl_inst/fmc150_stellar_cmd_inst/out_cmd_45> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/ads62p49_ctrl_inst/fmc150_stellar_cmd_inst/out_cmd_46> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/ads62p49_ctrl_inst/fmc150_stellar_cmd_inst/out_cmd_47> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/ads62p49_ctrl_inst/fmc150_stellar_cmd_inst/out_cmd_62> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/dac3283_ctrl_inst/fmc150_stellar_cmd_inst/out_cmd_32> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/dac3283_ctrl_inst/fmc150_stellar_cmd_inst/out_cmd_33> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/dac3283_ctrl_inst/fmc150_stellar_cmd_inst/out_cmd_34> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/dac3283_ctrl_inst/fmc150_stellar_cmd_inst/out_cmd_35> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/dac3283_ctrl_inst/fmc150_stellar_cmd_inst/out_cmd_36> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/dac3283_ctrl_inst/fmc150_stellar_cmd_inst/out_cmd_37> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/dac3283_ctrl_inst/fmc150_stellar_cmd_inst/out_cmd_38> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/dac3283_ctrl_inst/fmc150_stellar_cmd_inst/out_cmd_39> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/dac3283_ctrl_inst/fmc150_stellar_cmd_inst/out_cmd_40> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/dac3283_ctrl_inst/fmc150_stellar_cmd_inst/out_cmd_41> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/dac3283_ctrl_inst/fmc150_stellar_cmd_inst/out_cmd_42> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/dac3283_ctrl_inst/fmc150_stellar_cmd_inst/out_cmd_43> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/dac3283_ctrl_inst/fmc150_stellar_cmd_inst/out_cmd_44> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/dac3283_ctrl_inst/fmc150_stellar_cmd_inst/out_cmd_45> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/dac3283_ctrl_inst/fmc150_stellar_cmd_inst/out_cmd_46> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/dac3283_ctrl_inst/fmc150_stellar_cmd_inst/out_cmd_47> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/dac3283_ctrl_inst/fmc150_stellar_cmd_inst/out_cmd_62> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/amc7823_ctrl_inst/fmc150_stellar_cmd_inst/out_cmd_32> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/amc7823_ctrl_inst/fmc150_stellar_cmd_inst/out_cmd_33> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/amc7823_ctrl_inst/fmc150_stellar_cmd_inst/out_cmd_34> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/amc7823_ctrl_inst/fmc150_stellar_cmd_inst/out_cmd_35> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/amc7823_ctrl_inst/fmc150_stellar_cmd_inst/out_cmd_36> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/amc7823_ctrl_inst/fmc150_stellar_cmd_inst/out_cmd_37> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/amc7823_ctrl_inst/fmc150_stellar_cmd_inst/out_cmd_38> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/amc7823_ctrl_inst/fmc150_stellar_cmd_inst/out_cmd_39> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/amc7823_ctrl_inst/fmc150_stellar_cmd_inst/out_cmd_40> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/amc7823_ctrl_inst/fmc150_stellar_cmd_inst/out_cmd_41> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/amc7823_ctrl_inst/fmc150_stellar_cmd_inst/out_cmd_42> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/amc7823_ctrl_inst/fmc150_stellar_cmd_inst/out_cmd_43> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/amc7823_ctrl_inst/fmc150_stellar_cmd_inst/out_cmd_44> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/amc7823_ctrl_inst/fmc150_stellar_cmd_inst/out_cmd_45> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/amc7823_ctrl_inst/fmc150_stellar_cmd_inst/out_cmd_46> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/amc7823_ctrl_inst/fmc150_stellar_cmd_inst/out_cmd_47> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/amc7823_ctrl_inst/fmc150_stellar_cmd_inst/out_cmd_62> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/amc7823_ctrl_inst/init_done> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/amc7823_ctrl_inst/init_done_sclk> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_xwb_fmc150/cmp_wb_fmc150/cmp_wb_source_if/cmp_fifo/Mshreg_q_o_36_0> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_buttons/Wrapped_GPIO/out_reg_7> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_buttons/Wrapped_GPIO/out_reg_6> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_buttons/Wrapped_GPIO/out_reg_5> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_buttons/Wrapped_GPIO/out_reg_4> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_buttons/Wrapped_GPIO/out_reg_3> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_buttons/Wrapped_GPIO/out_reg_2> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_buttons/Wrapped_GPIO/out_reg_1> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_buttons/Wrapped_GPIO/out_reg_0> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_leds/Wrapped_GPIO/GEN_SYNC_FFS[7].INPUT_SYNC/ppulse_o> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_leds/Wrapped_GPIO/GEN_SYNC_FFS[7].INPUT_SYNC/npulse_o> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_leds/Wrapped_GPIO/GEN_SYNC_FFS[6].INPUT_SYNC/ppulse_o> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_leds/Wrapped_GPIO/GEN_SYNC_FFS[6].INPUT_SYNC/npulse_o> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_leds/Wrapped_GPIO/GEN_SYNC_FFS[5].INPUT_SYNC/ppulse_o> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_leds/Wrapped_GPIO/GEN_SYNC_FFS[5].INPUT_SYNC/npulse_o> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_leds/Wrapped_GPIO/GEN_SYNC_FFS[4].INPUT_SYNC/ppulse_o> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_leds/Wrapped_GPIO/GEN_SYNC_FFS[4].INPUT_SYNC/npulse_o> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_leds/Wrapped_GPIO/GEN_SYNC_FFS[3].INPUT_SYNC/ppulse_o> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_leds/Wrapped_GPIO/GEN_SYNC_FFS[3].INPUT_SYNC/npulse_o> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_leds/Wrapped_GPIO/GEN_SYNC_FFS[2].INPUT_SYNC/ppulse_o> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_leds/Wrapped_GPIO/GEN_SYNC_FFS[2].INPUT_SYNC/npulse_o> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_leds/Wrapped_GPIO/GEN_SYNC_FFS[1].INPUT_SYNC/ppulse_o> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_leds/Wrapped_GPIO/GEN_SYNC_FFS[1].INPUT_SYNC/npulse_o> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_leds/Wrapped_GPIO/GEN_SYNC_FFS[0].INPUT_SYNC/ppulse_o> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_leds/Wrapped_GPIO/GEN_SYNC_FFS[0].INPUT_SYNC/npulse_o> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_buttons/Wrapped_GPIO/GEN_SYNC_FFS[7].INPUT_SYNC/ppulse_o> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_buttons/Wrapped_GPIO/GEN_SYNC_FFS[7].INPUT_SYNC/npulse_o> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_buttons/Wrapped_GPIO/GEN_SYNC_FFS[6].INPUT_SYNC/ppulse_o> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_buttons/Wrapped_GPIO/GEN_SYNC_FFS[6].INPUT_SYNC/npulse_o> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_buttons/Wrapped_GPIO/GEN_SYNC_FFS[5].INPUT_SYNC/ppulse_o> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_buttons/Wrapped_GPIO/GEN_SYNC_FFS[5].INPUT_SYNC/npulse_o> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_buttons/Wrapped_GPIO/GEN_SYNC_FFS[4].INPUT_SYNC/ppulse_o> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_buttons/Wrapped_GPIO/GEN_SYNC_FFS[4].INPUT_SYNC/npulse_o> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_buttons/Wrapped_GPIO/GEN_SYNC_FFS[3].INPUT_SYNC/ppulse_o> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_buttons/Wrapped_GPIO/GEN_SYNC_FFS[3].INPUT_SYNC/npulse_o> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_buttons/Wrapped_GPIO/GEN_SYNC_FFS[2].INPUT_SYNC/ppulse_o> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_buttons/Wrapped_GPIO/GEN_SYNC_FFS[2].INPUT_SYNC/npulse_o> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_buttons/Wrapped_GPIO/GEN_SYNC_FFS[1].INPUT_SYNC/ppulse_o> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_buttons/Wrapped_GPIO/GEN_SYNC_FFS[1].INPUT_SYNC/npulse_o> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_buttons/Wrapped_GPIO/GEN_SYNC_FFS[0].INPUT_SYNC/ppulse_o> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_buttons/Wrapped_GPIO/GEN_SYNC_FFS[0].INPUT_SYNC/npulse_o> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_button_sys_ffs/npulse_o> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_uart/U_Wrapped_UART/U_WB_SLAVE/host_rack_o> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_uart/U_Wrapped_UART/gen_phys_uart.U_RX/RxD_data_error> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_reset/shifters_1_2> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_reset/shifters_1_1> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_reset/shifters_1_0> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_reg_d_7> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_reg_d_6> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_reg_d_5> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_reg_d_4> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_reg_d_3> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_reg_d_2> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_reg_d_1> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_reg_d_0> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/processing> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/uart_tx_byte_7> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/uart_tx_byte_6> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/uart_tx_byte_5> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/uart_tx_byte_4> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/uart_tx_byte_3> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/uart_tx_byte_2> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/uart_tx_byte_1> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/uart_tx_byte_0> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_w_30> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_w_29> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_w_28> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_w_27> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_w_26> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_w_25> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_w_24> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_w_23> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_w_22> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_w_21> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_w_20> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_w_19> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_w_18> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_w_17> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_w_16> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_w_15> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_w_14> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_w_13> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_w_12> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_w_11> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_w_10> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_w_9> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_w_8> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_w_7> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_w_6> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_w_5> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_w_4> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_w_3> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:2677 - Node <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/pc_w_2> of sequential type is unconnected in block <dbe_bpm_simple_top>.
WARNING:Xst:1710 - FF/Latch <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/i_sel_o_3> (without init value) has a constant value of 1 in block <dbe_bpm_simple_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/i_adr_o_0> (without init value) has a constant value of 0 in block <dbe_bpm_simple_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/i_adr_o_1> (without init value) has a constant value of 0 in block <dbe_bpm_simple_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_byte_3_0> (without init value) has a constant value of 0 in block <dbe_bpm_simple_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_byte_3_1> (without init value) has a constant value of 0 in block <dbe_bpm_simple_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_byte_3_2> (without init value) has a constant value of 0 in block <dbe_bpm_simple_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_byte_3_3> (without init value) has a constant value of 0 in block <dbe_bpm_simple_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_byte_3_4> (without init value) has a constant value of 0 in block <dbe_bpm_simple_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_byte_3_5> (without init value) has a constant value of 0 in block <dbe_bpm_simple_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_byte_3_6> (without init value) has a constant value of 0 in block <dbe_bpm_simple_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_byte_3_7> (without init value) has a constant value of 0 in block <dbe_bpm_simple_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_byte_2_0> (without init value) has a constant value of 0 in block <dbe_bpm_simple_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_byte_2_1> (without init value) has a constant value of 0 in block <dbe_bpm_simple_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_byte_2_2> (without init value) has a constant value of 0 in block <dbe_bpm_simple_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_byte_2_3> (without init value) has a constant value of 0 in block <dbe_bpm_simple_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_byte_2_4> (without init value) has a constant value of 0 in block <dbe_bpm_simple_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_byte_2_5> (without init value) has a constant value of 0 in block <dbe_bpm_simple_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_byte_2_6> (without init value) has a constant value of 0 in block <dbe_bpm_simple_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/jtag/jtag_byte_2_7> (without init value) has a constant value of 0 in block <dbe_bpm_simple_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_lm32/inst_addr_reg_0> (without init value) has a constant value of 0 in block <dbe_bpm_simple_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_lm32/inst_addr_reg_1> (without init value) has a constant value of 0 in block <dbe_bpm_simple_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/cdce72010_ctrl_inst/fmc150_stellar_cmd_inst/p2p3/outreset> (without init value) has a constant value of 0 in block <dbe_bpm_simple_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/cdce72010_ctrl_inst/fmc150_stellar_cmd_inst/p2p3/pulseout> (without init value) has a constant value of 0 in block <dbe_bpm_simple_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/cdce72010_ctrl_inst/fmc150_stellar_cmd_inst/p2p3/in_set> (without init value) has a constant value of 0 in block <dbe_bpm_simple_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/ads62p49_ctrl_inst/fmc150_stellar_cmd_inst/p2p3/in_set> (without init value) has a constant value of 0 in block <dbe_bpm_simple_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/ads62p49_ctrl_inst/fmc150_stellar_cmd_inst/p2p3/pulseout> (without init value) has a constant value of 0 in block <dbe_bpm_simple_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/ads62p49_ctrl_inst/fmc150_stellar_cmd_inst/p2p3/outreset> (without init value) has a constant value of 0 in block <dbe_bpm_simple_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/ads62p49_ctrl_inst/fmc150_stellar_cmd_inst/p2p3/out_set_prev2> (without init value) has a constant value of 0 in block <dbe_bpm_simple_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/ads62p49_ctrl_inst/fmc150_stellar_cmd_inst/mbx_received> (without init value) has a constant value of 0 in block <dbe_bpm_simple_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/ads62p49_ctrl_inst/inst_reg_7> (without init value) has a constant value of 0 in block <dbe_bpm_simple_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/dac3283_ctrl_inst/fmc150_stellar_cmd_inst/p2p3/in_set> (without init value) has a constant value of 0 in block <dbe_bpm_simple_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/dac3283_ctrl_inst/fmc150_stellar_cmd_inst/p2p3/pulseout> (without init value) has a constant value of 0 in block <dbe_bpm_simple_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/dac3283_ctrl_inst/fmc150_stellar_cmd_inst/p2p3/outreset> (without init value) has a constant value of 0 in block <dbe_bpm_simple_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/dac3283_ctrl_inst/fmc150_stellar_cmd_inst/p2p3/out_set_prev2> (without init value) has a constant value of 0 in block <dbe_bpm_simple_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/dac3283_ctrl_inst/fmc150_stellar_cmd_inst/mbx_received> (without init value) has a constant value of 0 in block <dbe_bpm_simple_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/amc7823_ctrl_inst/fmc150_stellar_cmd_inst/p2p3/in_set> (without init value) has a constant value of 0 in block <dbe_bpm_simple_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/amc7823_ctrl_inst/fmc150_stellar_cmd_inst/p2p3/pulseout> (without init value) has a constant value of 0 in block <dbe_bpm_simple_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/amc7823_ctrl_inst/fmc150_stellar_cmd_inst/p2p3/outreset> (without init value) has a constant value of 0 in block <dbe_bpm_simple_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/amc7823_ctrl_inst/fmc150_stellar_cmd_inst/p2p3/out_set_prev2> (without init value) has a constant value of 0 in block <dbe_bpm_simple_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/amc7823_ctrl_inst/fmc150_stellar_cmd_inst/mbx_received> (without init value) has a constant value of 0 in block <dbe_bpm_simple_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/amc7823_ctrl_inst/page_reg_1> (without init value) has a constant value of 0 in block <dbe_bpm_simple_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <cmp_xwb_fmc150/cmp_wb_fmc150/cmp_wb_source_if/cmp_fifo/pointer_4> has a constant value of 0 in block <dbe_bpm_simple_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <cmp_xwb_fmc150/cmp_wb_fmc150/cmp_wb_source_if/cmp_fifo/pointer_3> has a constant value of 0 in block <dbe_bpm_simple_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <cmp_xwb_fmc150/cmp_wb_fmc150/cmp_wb_source_if/cmp_fifo/pointer_2> has a constant value of 0 in block <dbe_bpm_simple_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <cmp_xwb_fmc150/cmp_wb_fmc150/cmp_wb_source_if/cmp_fifo/pointer_1> has a constant value of 0 in block <dbe_bpm_simple_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <cmp_xwb_fmc150/cmp_wb_fmc150/cmp_wb_source_if/cmp_fifo/pointer_0> has a constant value of 0 in block <dbe_bpm_simple_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/i_sel_o_2> (without init value) has a constant value of 1 in block <dbe_bpm_simple_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/i_sel_o_1> (without init value) has a constant value of 1 in block <dbe_bpm_simple_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/i_sel_o_0> (without init value) has a constant value of 1 in block <dbe_bpm_simple_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_button_sys_rst/cntr_17> (without init value) has a constant value of 0 in block <dbe_bpm_simple_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_button_sys_rst/cntr_16> (without init value) has a constant value of 0 in block <dbe_bpm_simple_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_button_sys_rst/cntr_19> (without init value) has a constant value of 0 in block <dbe_bpm_simple_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_button_sys_rst/cntr_20> (without init value) has a constant value of 0 in block <dbe_bpm_simple_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_button_sys_rst/cntr_21> (without init value) has a constant value of 0 in block <dbe_bpm_simple_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_button_sys_rst/cntr_22> (without init value) has a constant value of 0 in block <dbe_bpm_simple_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_button_sys_rst/cntr_25> (without init value) has a constant value of 0 in block <dbe_bpm_simple_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_button_sys_rst/cntr_18> (without init value) has a constant value of 0 in block <dbe_bpm_simple_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_button_sys_rst/cntr_14> (without init value) has a constant value of 0 in block <dbe_bpm_simple_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_button_sys_rst/cntr_13> (without init value) has a constant value of 0 in block <dbe_bpm_simple_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_button_sys_rst/cntr_23> (without init value) has a constant value of 0 in block <dbe_bpm_simple_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_button_sys_rst/cntr_24> (without init value) has a constant value of 0 in block <dbe_bpm_simple_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_button_sys_rst/cntr_28> (without init value) has a constant value of 0 in block <dbe_bpm_simple_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_button_sys_rst/cntr_26> (without init value) has a constant value of 0 in block <dbe_bpm_simple_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_button_sys_rst/cntr_27> (without init value) has a constant value of 0 in block <dbe_bpm_simple_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_button_sys_rst/cntr_8> (without init value) has a constant value of 0 in block <dbe_bpm_simple_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_button_sys_rst/cntr_9> (without init value) has a constant value of 0 in block <dbe_bpm_simple_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_button_sys_rst/cntr_12> (without init value) has a constant value of 0 in block <dbe_bpm_simple_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/cdce72010_ctrl_inst/fmc150_stellar_cmd_inst/p2p3/out_set_prev2> (without init value) has a constant value of 0 in block <dbe_bpm_simple_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/cdce72010_ctrl_inst/fmc150_stellar_cmd_inst/mbx_received> (without init value) has a constant value of 0 in block <dbe_bpm_simple_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_button_sys_rst/cntr_30> (without init value) has a constant value of 0 in block <dbe_bpm_simple_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_button_sys_rst/cntr_29> (without init value) has a constant value of 0 in block <dbe_bpm_simple_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_button_sys_rst/cntr_10> (without init value) has a constant value of 0 in block <dbe_bpm_simple_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_button_sys_rst/cntr_11> (without init value) has a constant value of 0 in block <dbe_bpm_simple_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_button_sys_rst/cntr_15> (without init value) has a constant value of 0 in block <dbe_bpm_simple_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <cmp_button_sys_rst/cntr_31> (without init value) has a constant value of 0 in block <dbe_bpm_simple_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/ads62p49_ctrl_inst/fmc150_stellar_cmd_inst/p2p3/in_reset> (without init value) has a constant value of 0 in block <dbe_bpm_simple_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/dac3283_ctrl_inst/fmc150_stellar_cmd_inst/p2p3/out_set> (without init value) has a constant value of 0 in block <dbe_bpm_simple_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/dac3283_ctrl_inst/fmc150_stellar_cmd_inst/p2p3/in_reset> (without init value) has a constant value of 0 in block <dbe_bpm_simple_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/ads62p49_ctrl_inst/fmc150_stellar_cmd_inst/p2p3/out_set> (without init value) has a constant value of 0 in block <dbe_bpm_simple_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/cdce72010_ctrl_inst/fmc150_stellar_cmd_inst/p2p3/in_reset> (without init value) has a constant value of 0 in block <dbe_bpm_simple_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/amc7823_ctrl_inst/fmc150_stellar_cmd_inst/p2p3/in_reset> (without init value) has a constant value of 0 in block <dbe_bpm_simple_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/amc7823_ctrl_inst/fmc150_stellar_cmd_inst/p2p3/out_set> (without init value) has a constant value of 0 in block <dbe_bpm_simple_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/cdce72010_ctrl_inst/fmc150_stellar_cmd_inst/p2p3/out_set> (without init value) has a constant value of 0 in block <dbe_bpm_simple_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/amc7823_ctrl_inst/fmc150_stellar_cmd_inst/p2p3/out_set_prev> (without init value) has a constant value of 0 in block <dbe_bpm_simple_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/amc7823_ctrl_inst/fmc150_stellar_cmd_inst/p2p3/in_reset_prev> (without init value) has a constant value of 0 in block <dbe_bpm_simple_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/dac3283_ctrl_inst/fmc150_stellar_cmd_inst/p2p3/out_set_prev> (without init value) has a constant value of 0 in block <dbe_bpm_simple_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/dac3283_ctrl_inst/fmc150_stellar_cmd_inst/p2p3/in_reset_prev> (without init value) has a constant value of 0 in block <dbe_bpm_simple_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/ads62p49_ctrl_inst/fmc150_stellar_cmd_inst/p2p3/out_set_prev> (without init value) has a constant value of 0 in block <dbe_bpm_simple_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/ads62p49_ctrl_inst/fmc150_stellar_cmd_inst/p2p3/in_reset_prev> (without init value) has a constant value of 0 in block <dbe_bpm_simple_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/cdce72010_ctrl_inst/fmc150_stellar_cmd_inst/p2p3/out_set_prev> (without init value) has a constant value of 0 in block <dbe_bpm_simple_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/cdce72010_ctrl_inst/fmc150_stellar_cmd_inst/p2p3/in_reset_prev> (without init value) has a constant value of 0 in block <dbe_bpm_simple_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/amc7823_ctrl_inst/fmc150_stellar_cmd_inst/p2p3/in_reset_prev2> (without init value) has a constant value of 0 in block <dbe_bpm_simple_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/dac3283_ctrl_inst/fmc150_stellar_cmd_inst/p2p3/in_reset_prev2> (without init value) has a constant value of 0 in block <dbe_bpm_simple_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/ads62p49_ctrl_inst/fmc150_stellar_cmd_inst/p2p3/in_reset_prev2> (without init value) has a constant value of 0 in block <dbe_bpm_simple_top>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/cdce72010_ctrl_inst/fmc150_stellar_cmd_inst/p2p3/in_reset_prev2> (without init value) has a constant value of 0 in block <dbe_bpm_simple_top>. This FF/Latch will be trimmed during the optimization process.
INFO:Xst:2261 - The FF/Latch <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/logic_op_x_3> in Unit <dbe_bpm_simple_top> is equivalent to the following FF/Latch, which will be removed : <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/direction_x> 
INFO:Xst:2261 - The FF/Latch <cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/cdce72010_ctrl_inst/serial_clk> in Unit <dbe_bpm_simple_top> is equivalent to the following 3 FFs/Latches, which will be removed : <cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/ads62p49_ctrl_inst/sclk_ext> <cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/dac3283_ctrl_inst/serial_clk> <cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/amc7823_ctrl_inst/serial_clk> 
INFO:Xst:2261 - The FF/Latch <cmp_uart/U_Wrapped_UART/U_WB_SLAVE/ack_sreg> in Unit <dbe_bpm_simple_top> is equivalent to the following FF/Latch, which will be removed : <cmp_uart/U_Wrapped_UART/U_WB_SLAVE/ack_in_progress> 
INFO:Xst:2261 - The FF/Latch <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/memories[0].way_0_data_ram/ra_2> in Unit <dbe_bpm_simple_top> is equivalent to the following FF/Latch, which will be removed : <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/memories[0].way_0_tag_ram/ra_0> 
INFO:Xst:2261 - The FF/Latch <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/memories[0].way_0_data_ram/ra_3> in Unit <dbe_bpm_simple_top> is equivalent to the following FF/Latch, which will be removed : <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/memories[0].way_0_tag_ram/ra_1> 
INFO:Xst:2261 - The FF/Latch <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/memories[0].way_0_data_ram/ra_4> in Unit <dbe_bpm_simple_top> is equivalent to the following FF/Latch, which will be removed : <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/memories[0].way_0_tag_ram/ra_2> 
INFO:Xst:2261 - The FF/Latch <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/memories[0].way_0_data_ram/ra_5> in Unit <dbe_bpm_simple_top> is equivalent to the following FF/Latch, which will be removed : <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/memories[0].way_0_tag_ram/ra_3> 
INFO:Xst:2261 - The FF/Latch <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/memories[0].way_0_data_ram/ra_6> in Unit <dbe_bpm_simple_top> is equivalent to the following FF/Latch, which will be removed : <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/memories[0].way_0_tag_ram/ra_4> 
INFO:Xst:2261 - The FF/Latch <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/memories[0].way_0_data_ram/ra_7> in Unit <dbe_bpm_simple_top> is equivalent to the following FF/Latch, which will be removed : <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/memories[0].way_0_tag_ram/ra_5> 
INFO:Xst:2261 - The FF/Latch <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/memories[0].way_0_data_ram/ra_8> in Unit <dbe_bpm_simple_top> is equivalent to the following FF/Latch, which will be removed : <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/memories[0].way_0_tag_ram/ra_6> 
INFO:Xst:2261 - The FF/Latch <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/memories[0].way_0_data_ram/ra_9> in Unit <dbe_bpm_simple_top> is equivalent to the following FF/Latch, which will be removed : <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/memories[0].way_0_tag_ram/ra_7> 
INFO:Xst:2261 - The FF/Latch <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/load_x> in Unit <dbe_bpm_simple_top> is equivalent to the following FF/Latch, which will be removed : <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/w_result_sel_load_x> 
INFO:Xst:2261 - The FF/Latch <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/condition_x_0> in Unit <dbe_bpm_simple_top> is equivalent to the following 2 FFs/Latches, which will be removed : <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/logic_op_x_0> <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/size_x_0> 
INFO:Xst:2261 - The FF/Latch <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/condition_x_1> in Unit <dbe_bpm_simple_top> is equivalent to the following 2 FFs/Latches, which will be removed : <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/logic_op_x_1> <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/size_x_1> 
INFO:Xst:2261 - The FF/Latch <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/condition_x_2> in Unit <dbe_bpm_simple_top> is equivalent to the following 2 FFs/Latches, which will be removed : <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/logic_op_x_2> <cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/sign_extend_x> 
INFO:Xst:2261 - The FF/Latch <cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/cdce72010_ctrl_inst/gen_serial_clk.clk_div_0> in Unit <dbe_bpm_simple_top> is equivalent to the following 3 FFs/Latches, which will be removed : <cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/ads62p49_ctrl_inst/gen_serial_clk.clk_div_0> <cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/dac3283_ctrl_inst/gen_serial_clk.clk_div_0> <cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/amc7823_ctrl_inst/gen_serial_clk.clk_div_0> 
INFO:Xst:2261 - The FF/Latch <cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/cdce72010_ctrl_inst/gen_serial_clk.clk_div_1> in Unit <dbe_bpm_simple_top> is equivalent to the following 3 FFs/Latches, which will be removed : <cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/ads62p49_ctrl_inst/gen_serial_clk.clk_div_1> <cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/dac3283_ctrl_inst/gen_serial_clk.clk_div_1> <cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/amc7823_ctrl_inst/gen_serial_clk.clk_div_1> 
INFO:Xst:2261 - The FF/Latch <cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/cdce72010_ctrl_inst/gen_serial_clk.clk_div_2> in Unit <dbe_bpm_simple_top> is equivalent to the following 3 FFs/Latches, which will be removed : <cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/ads62p49_ctrl_inst/gen_serial_clk.clk_div_2> <cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/dac3283_ctrl_inst/gen_serial_clk.clk_div_2> <cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/amc7823_ctrl_inst/gen_serial_clk.clk_div_2> 
INFO:Xst:2261 - The FF/Latch <cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/cdce72010_ctrl_inst/gen_serial_clk.clk_div_3> in Unit <dbe_bpm_simple_top> is equivalent to the following 3 FFs/Latches, which will be removed : <cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/ads62p49_ctrl_inst/gen_serial_clk.clk_div_3> <cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/dac3283_ctrl_inst/gen_serial_clk.clk_div_3> <cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/amc7823_ctrl_inst/gen_serial_clk.clk_div_3> 
INFO:Xst:3203 - The FF/Latch <cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/cdce72010_ctrl_inst/ncs_int> in Unit <dbe_bpm_simple_top> is the opposite to the following FF/Latch, which will be removed : <cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/cdce72010_ctrl_inst/shifting> 
INFO:Xst:3203 - The FF/Latch <cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/amc7823_ctrl_inst/ncs_int> in Unit <dbe_bpm_simple_top> is the opposite to the following FF/Latch, which will be removed : <cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/amc7823_ctrl_inst/shifting> 

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block dbe_bpm_simple_top, actual ratio is 4.

Final Macro Processing ...

Processing Unit <dbe_bpm_simple_top> :
	Found 3-bit shift register for signal <cmp_reset/shifters_0_0>.
	Found 2-bit shift register for signal <cmp_button_sys_ffs/sync1>.
Unit <dbe_bpm_simple_top> processed.

=========================================================================
Final Register Report

Macro Statistics
# Registers                                            : 3014
 Flip-Flops                                            : 3014
# Shift Registers                                      : 2
 2-bit shift register                                  : 1
 3-bit shift register                                  : 1

=========================================================================

=========================================================================
*                           Partition Report                            *
=========================================================================

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

=========================================================================
*                            Design Summary                             *
=========================================================================

Clock Information:
------------------
--------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------+-------+
Clock Signal                                                                                                  | Clock buffer(FF name)                                          | Load  |
--------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------+-------+
sys_clk_p_i                                                                                                   | MMCM_ADV:CLKOUT0                                               | 3395  |
cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_adc_if/gen_adc_clk.cmp_adc_str/s_strobe_dly             | MMCM_ADV:CLKOUT0                                               | 868   |
cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/cdce72010_ctrl_inst/serial_clk              | BUFG                                                           | 303   |
cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/cdce72010_ctrl_inst/gen_serial_clk.clk_div_3| BUFG                                                           | 82    |
sys_clk_p_i                                                                                                   | IBUFGDS+BUFG                                                   | 11    |
cmp_chipscope_icon_0/U0/U_ICON/I_YES_BSCAN.U_BS/iDRCK_LOCAL                                                   | BUFG                                                           | 379   |
cmp_chipscope_icon_0/CONTROL1<13>(cmp_chipscope_icon_0/U0/U_ICON/U_CTRL_OUT/F_NCP[1].F_CMD[9].U_LCE:O)        | NONE(*)(cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_STAT/U_DIRTY_LDC)| 1     |
cmp_chipscope_icon_0/CONTROL0<13>(cmp_chipscope_icon_0/U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[9].U_LCE:O)        | NONE(*)(cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_STAT/U_DIRTY_LDC)| 1     |
cmp_chipscope_icon_0/U0/iUPDATE_OUT                                                                           | NONE(cmp_chipscope_icon_0/U0/U_ICON/U_iDATA_CMD)               | 1     |
--------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------+-------+
(*) These 2 clock signal(s) are generated by combinatorial logic,
and XST is not able to identify which are the primary clock signals.
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.

Asynchronous Control Signals Information:
----------------------------------------
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------+
Control Signal                                                                                                                                                                                                                                                                                                                                                                    | Buffer(FF name)                                                                                                                                                                                                                                                                                                                                      | Load  |
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------+
cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/XST_VCC:P)  | NONE(cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36)  | 124   |
cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36)| 124   |
cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36)| 124   |
cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36)| 124   |
cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36)| 124   |
cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/XST_VCC:P)  | NONE(cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36)  | 124   |
cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/XST_VCC:P)  | NONE(cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36)  | 124   |
cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/XST_VCC:P)  | NONE(cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36)  | 124   |
cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/XST_VCC:P)  | NONE(cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36)  | 124   |
cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/XST_VCC:P)  | NONE(cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36)  | 124   |
cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/XST_VCC:P)  | NONE(cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36)  | 124   |
cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/XST_VCC:P)  | NONE(cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36)  | 124   |
cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/XST_VCC:P)  | NONE(cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36)  | 124   |
cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/XST_VCC:P)  | NONE(cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36)  | 124   |
cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/XST_VCC:P)  | NONE(cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36)  | 124   |
cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36)| 124   |
cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36)| 124   |
cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36)| 124   |
cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/XST_VCC:P)| NONE(cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36)| 124   |
cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/XST_VCC:P)  | NONE(cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36)  | 124   |
cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/XST_VCC:P)  | NONE(cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36)  | 124   |
cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/XST_VCC:P)  | NONE(cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36)  | 124   |
cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/XST_VCC:P)  | NONE(cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36)  | 124   |
cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/XST_VCC:P)  | NONE(cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36)  | 124   |
cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/XST_VCC:P)  | NONE(cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36)  | 124   |
cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/XST_VCC:P)  | NONE(cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36)  | 124   |
cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/XST_VCC:P)  | NONE(cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36)  | 124   |
cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/N11(cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/XST_VCC:P)  | NONE(cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36)  | 124   |
cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/XST_GND:G)   | NONE(cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36)  | 72    |
cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36)| 72    |
cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36)| 72    |
cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36)| 72    |
cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36)| 72    |
cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/XST_GND:G)   | NONE(cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36)  | 72    |
cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/XST_GND:G)   | NONE(cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36)  | 72    |
cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/XST_GND:G)   | NONE(cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36)  | 72    |
cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/XST_GND:G)   | NONE(cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36)  | 72    |
cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/XST_GND:G)   | NONE(cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36)  | 72    |
cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/XST_GND:G)   | NONE(cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36)  | 72    |
cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/XST_GND:G)   | NONE(cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36)  | 72    |
cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/XST_GND:G)   | NONE(cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36)  | 72    |
cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/XST_GND:G)   | NONE(cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36)  | 72    |
cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/XST_GND:G)   | NONE(cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[0].u_ramb36/U_RAMB36)  | 72    |
cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[10].u_ramb36/U_RAMB36)| 72    |
cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[11].u_ramb36/U_RAMB36)| 72    |
cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36)| 72    |
cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/XST_GND:G) | NONE(cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[13].u_ramb36/U_RAMB36)| 72    |
cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/XST_GND:G)   | NONE(cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[1].u_ramb36/U_RAMB36)  | 72    |
cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/XST_GND:G)   | NONE(cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[2].u_ramb36/U_RAMB36)  | 72    |
cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/XST_GND:G)   | NONE(cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[3].u_ramb36/U_RAMB36)  | 72    |
cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/XST_GND:G)   | NONE(cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[4].u_ramb36/U_RAMB36)  | 72    |
cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/XST_GND:G)   | NONE(cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[5].u_ramb36/U_RAMB36)  | 72    |
cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/XST_GND:G)   | NONE(cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[6].u_ramb36/U_RAMB36)  | 72    |
cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/XST_GND:G)   | NONE(cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[7].u_ramb36/U_RAMB36)  | 72    |
cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/XST_GND:G)   | NONE(cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36)  | 72    |
cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/N0(cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/XST_GND:G)   | NONE(cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[9].u_ramb36/U_RAMB36)  | 72    |
cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_STAT/U_ECR_glue_set(cmp_chipscope_ila_0/XST_VCC:P)                                                                                                                                                                                                                                                                                          | NONE(cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[8].u_ramb36/U_RAMB36)  | 56    |
cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_STAT/U_ECR_glue_set(cmp_chipscope_ila_1/XST_VCC:P)                                                                                                                                                                                                                                                                                          | NONE(cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B36KGT0.G_RAMB36[12].u_ramb36/U_RAMB36)| 56    |
cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/iCAP_WR_EN(cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_INTCAP_F.U_CAPWE1:Q)                                                                                                                                                                                                                                                       | NONE(cmp_chipscope_ila_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B18KGT0.u_ramb18/U_RAMB18E1)                                                                                                                                                                         | 8     |
cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/iCAP_WR_EN(cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/I_INTCAP_F.U_CAPWE1:Q)                                                                                                                                                                                                                                                       | NONE(cmp_chipscope_ila_1/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_V6.U_CS_BRAM_CASCADE_V6/I_DEPTH_LTEQ_32K.U_SBRAM_0/I_B18KGT0.u_ramb18/U_RAMB18E1)                                                                                                                                                                         | 8     |
cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/reg_write_enable_q_w(cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/reg_write_enable_q_w1:O)                                                                                                                                                                                                             | NONE(cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/reg_0/Mram_ram)                                                                                                                                                                                                                                                                     | 8     |
cmp_button_sys_ffs/rst_n_i_inv(XST_GND:G)                                                                                                                                                                                                                                                                                                                                         | NONE(cmp_interconnect/rom/Mram_rom1)                                                                                                                                                                                                                                                                                                                 | 6     |
cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/way_mem_we[0]_flushing_OR_4271_o(cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/way_mem_we[0]_flushing_OR_4271_o1:O)                                                                                                                                     | NONE(cmp_lm32/gen_profile_medium_icache_debug.U_Wrapped_LM32/cpu/instruction_unit/icache/memories[0].way_0_tag_ram/Mram_mem)                                                                                                                                                                                                                         | 4     |
cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/ads62p49_ctrl_inst/ads62p49_init_mem_inst/N1(cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/ads62p49_ctrl_inst/ads62p49_init_mem_inst/XST_GND:G)                                                                                                                                             | NONE(cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/ads62p49_ctrl_inst/ads62p49_init_mem_inst/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_init.ram/SP.WIDE_PRIM18.ram)                                                                                                                  | 4     |
cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/amc7823_ctrl_inst/amc7823_init_mem_inst/N1(cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/amc7823_ctrl_inst/amc7823_init_mem_inst/XST_GND:G)                                                                                                                                                 | NONE(cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/amc7823_ctrl_inst/amc7823_init_mem_inst/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_init.ram/SP.WIDE_PRIM18.ram)                                                                                                                    | 4     |
cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/cdce72010_ctrl_inst/cdce72010_init_mem_ext_inst/N1(cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/cdce72010_ctrl_inst/cdce72010_init_mem_ext_inst/XST_GND:G)                                                                                                                                 | NONE(cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/cdce72010_ctrl_inst/cdce72010_init_mem_ext_inst/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_init.ram/SP.WIDE_PRIM18.ram)                                                                                                            | 4     |
cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/cdce72010_ctrl_inst/cdce72010_init_mem_int_inst/N1(cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/cdce72010_ctrl_inst/cdce72010_init_mem_int_inst/XST_GND:G)                                                                                                                                 | NONE(cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/cdce72010_ctrl_inst/cdce72010_init_mem_int_inst/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_init.ram/SP.WIDE_PRIM18.ram)                                                                                                            | 4     |
cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/dac3283_ctrl_inst/dac3283_init_mem_inst/N1(cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/dac3283_ctrl_inst/dac3283_init_mem_inst/XST_GND:G)                                                                                                                                                 | NONE(cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_fmc150_ctrl/dac3283_ctrl_inst/dac3283_init_mem_inst/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v6_init.ram/SP.WIDE_PRIM18.ram)                                                                                                                    | 4     |
cbar_slave_i[1]_sel<0>(XST_VCC:P)                                                                                                                                                                                                                                                                                                                                                 | NONE(cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_adc_if/gen_adc_clk.cmp_adc_str/cmp_bufr)                                                                                                                                                                                                                                                  | 2     |
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------+

Timing Summary:
---------------
Speed Grade: -1

   Minimum period: 6.594ns (Maximum Frequency: 151.653MHz)
   Minimum input arrival time before clock: 4.763ns
   Maximum output required time after clock: 3.092ns
   Maximum combinational path delay: 2.230ns

=========================================================================

Process "Synthesize - XST" completed successfully

Started : "Translate".
Running ngdbuild...
Command Line: ngdbuild -intstyle ise -dd _ngo -sd ../../platform/virtex6/chipscope/icon_1_port -sd ../../platform/virtex6/chipscope/icon_2_port -sd ../../platform/virtex6/chipscope -sd ../../modules/dbe_wishbone/wb_fmc150/netlist -nt timestamp -uc /home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_simple/dbe_bpm_simple_top.ucf -p xc6vlx240t-ff1156-1 dbe_bpm_simple_top.ngc dbe_bpm_simple_top.ngd

Command Line: /opt/Xilinx/13.4/ISE_DS/ISE/bin/lin64/unwrapped/ngdbuild -intstyle
ise -dd _ngo -sd ../../platform/virtex6/chipscope/icon_1_port -sd
../../platform/virtex6/chipscope/icon_2_port -sd
../../platform/virtex6/chipscope -sd
../../modules/dbe_wishbone/wb_fmc150/netlist -nt timestamp -uc
/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_simple/dbe_bpm_simple_top.ucf
-p xc6vlx240t-ff1156-1 dbe_bpm_simple_top.ngc dbe_bpm_simple_top.ngd

Reading NGO file
"/home/lerwys/Repos/bpm-sw/hdl/syn/dbe_bpm_simple/dbe_bpm_simple_top.ngc" ...
Loading design module "../../platform/virtex6/chipscope/chipscope_ila.ngc"...
Loading design module
"../../platform/virtex6/chipscope/icon_2_port/chipscope_icon_2_port.ngc"...
Loading design module
"../../modules/dbe_wishbone/wb_fmc150/netlist/cdce72010_init_mem_int.ngc"...
Loading design module
"../../modules/dbe_wishbone/wb_fmc150/netlist/cdce72010_init_mem_ext.ngc"...
Loading design module
"../../modules/dbe_wishbone/wb_fmc150/netlist/ads62p49_init_mem.ngc"...
Loading design module
"../../modules/dbe_wishbone/wb_fmc150/netlist/dac3283_init_mem.ngc"...
Loading design module
"../../modules/dbe_wishbone/wb_fmc150/netlist/amc7823_init_mem.ngc"...
	/dbe_bpm_simple_top/dbe_bpm_simple_top
	/dbe_bpm_simple_top/cmp_chipscope_ila_1
	/dbe_bpm_simple_top/cmp_chipscope_ila_0

-----------------------------------------------
WARNING:Security:42 - Your software subscription period has lapsed. Your current
version of Xilinx tools will continue to function, but you no longer qualify for
Xilinx software updates or new releases.

-----------------------------------------------

-----------------------------------------------
Gathering constraint information from source properties...
Done.

Annotating constraints to design from ucf file
"/home/lerwys/Repos/bpm-sw/hdl/top/ml_605/dbe_bpm_simple/dbe_bpm_simple_top.ucf"
...
Resolving constraint associations...
Checking Constraint Associations...




Done...

Checking expanded design ...

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Writing NGD file "dbe_bpm_simple_top.ngd" ...
Total REAL time to NGDBUILD completion:  21 sec
Total CPU time to NGDBUILD completion:   21 sec

Writing NGDBUILD log file "dbe_bpm_simple_top.bld"...

NGDBUILD done.

Process "Translate" completed successfully

Started : "Map".
Running map...
Command Line: map -intstyle ise -p xc6vlx240t-ff1156-1 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt 2 -ir off -pr off -lc off -power off -o dbe_bpm_simple_top_map.ncd dbe_bpm_simple_top.ngd dbe_bpm_simple_top.pcf
Using target part "6vlx240tff1156-1".
INFO:Map:284 - Map is running with the multi-threading option on. Map currently
   supports the use of up to 2 processors. Based on the the user options and
   machine load, Map will use 2 processors during this run.
vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv
INFO:Security:56 - Part 'xc6vlx240t' is not a WebPack part.
WARNING:Security:9b - No 'ISE' feature version 2012.01 was available for part
'xc6vlx240t'.
WARNING:Security:42 - Your software subscription period has lapsed. Your current
version of Xilinx tools will continue to function, but you no longer qualify for
Xilinx software updates or new releases.
WARNING:Security:42 - Your software subscription period has lapsed. Your current
version of Xilinx tools will continue to function, but you no longer qualify for
Xilinx software updates or new releases.
----------------------------------------------------------------------
Mapping design into LUTs...
Running directed packing...
Running delay-based LUT packing...
Updating timing models...
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
   (.mrp).
Running timing-driven placement...
Total REAL time at the beginning of Placer: 1 mins 4 secs 
Total CPU  time at the beginning of Placer: 1 mins 4 secs 

Phase 1.1  Initial Placement Analysis
Phase 1.1  Initial Placement Analysis (Checksum:15e7a8a3) REAL time: 1 mins 16 secs 

Phase 2.7  Design Feasibility Check
Phase 2.7  Design Feasibility Check (Checksum:15e7a8a3) REAL time: 1 mins 18 secs 

Phase 3.31  Local Placement Optimization
Phase 3.31  Local Placement Optimization (Checksum:f61fec8f) REAL time: 1 mins 18 secs 

Phase 4.37  Local Placement Optimization
Phase 4.37  Local Placement Optimization (Checksum:f61fec8f) REAL time: 1 mins 18 secs 

Phase 5.2  Initial Placement for Architecture Specific Features

......


There are 12 clock regions on the target FPGA device:
|------------------------------------------|------------------------------------------|
| CLOCKREGION_X0Y5:                        | CLOCKREGION_X1Y5:                        |
|   4 BUFRs available, 0 in use            |   2 BUFRs available, 0 in use            |
|   6 Regional Clock Spines, 0 in use      |   6 Regional Clock Spines, 0 in use      |
|   4 edge BUFIOs available, 0 in use      |   0 edge BUFIOs available, 0 in use      |
|   4 center BUFIOs available, 0 in use    |   4 center BUFIOs available, 0 in use    |
|                                          |                                          |
|------------------------------------------|------------------------------------------|
| CLOCKREGION_X0Y4:                        | CLOCKREGION_X1Y4:                        |
|   4 BUFRs available, 0 in use            |   2 BUFRs available, 0 in use            |
|   6 Regional Clock Spines, 1 in use      |   6 Regional Clock Spines, 0 in use      |
|   4 edge BUFIOs available, 0 in use      |   0 edge BUFIOs available, 0 in use      |
|   4 center BUFIOs available, 0 in use    |   4 center BUFIOs available, 0 in use    |
|                                          |                                          |
|------------------------------------------|------------------------------------------|
| CLOCKREGION_X0Y3:                        | CLOCKREGION_X1Y3:                        |
|   4 BUFRs available, 1 in use            |   2 BUFRs available, 0 in use            |
|   6 Regional Clock Spines, 1 in use      |   6 Regional Clock Spines, 0 in use      |
|   4 edge BUFIOs available, 0 in use      |   0 edge BUFIOs available, 0 in use      |
|   4 center BUFIOs available, 0 in use    |   4 center BUFIOs available, 0 in use    |
|                                          |                                          |
|------------------------------------------|------------------------------------------|
| CLOCKREGION_X0Y2:                        | CLOCKREGION_X1Y2:                        |
|   4 BUFRs available, 0 in use            |   2 BUFRs available, 0 in use            |
|   6 Regional Clock Spines, 1 in use      |   6 Regional Clock Spines, 0 in use      |
|   4 edge BUFIOs available, 0 in use      |   0 edge BUFIOs available, 0 in use      |
|   4 center BUFIOs available, 0 in use    |   4 center BUFIOs available, 0 in use    |
|                                          |                                          |
|------------------------------------------|------------------------------------------|
| CLOCKREGION_X0Y1:                        | CLOCKREGION_X1Y1:                        |
|   4 BUFRs available, 0 in use            |   2 BUFRs available, 0 in use            |
|   6 Regional Clock Spines, 0 in use      |   6 Regional Clock Spines, 0 in use      |
|   4 edge BUFIOs available, 0 in use      |   0 edge BUFIOs available, 0 in use      |
|   4 center BUFIOs available, 0 in use    |   4 center BUFIOs available, 0 in use    |
|                                          |                                          |
|------------------------------------------|------------------------------------------|
| CLOCKREGION_X0Y0:                        | CLOCKREGION_X1Y0:                        |
|   4 BUFRs available, 0 in use            |   2 BUFRs available, 0 in use            |
|   6 Regional Clock Spines, 0 in use      |   6 Regional Clock Spines, 0 in use      |
|   4 edge BUFIOs available, 0 in use      |   0 edge BUFIOs available, 0 in use      |
|   4 center BUFIOs available, 0 in use    |   4 center BUFIOs available, 0 in use    |
|                                          |                                          |
|------------------------------------------|------------------------------------------|


Clock-Region: <CLOCKREGION_X0Y3>
  key resource utilizations (used/available): edge-bufios - 0/4; center-bufios - 0/4; bufrs - 1/4; regional-clock-spines - 1/6
|-----------------------------------------------------------------------------------------------------------------------------------------------------------
|       |    clock    | BRAM |     |    |        |        |       |       |       |      |      |     |      |
|       |    region   | FIFO | DCM | GT | ILOGIC | OLOGIC |   FF  |  LUTM |  LUTL | MULT | EMAC | PPC | PCIe | <- (Types of Resources in Clock Region)
|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------
|       | Upper Region|  96  |  0  |  0 |   80   |   80   | 26880 |  9600 | 17280 |  64  |   0  |  0  |   0  | <- Available resources in the upper region
|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------
|       |CurrentRegion|  96  |  0  |  0 |   80   |   80   | 23040 |  9600 | 13440 |  64  |   0  |  0  |   0  | <- Available resources in the current region
|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------
|       | Lower Region|  96  |  0  |  0 |   80   |   80   | 23040 |  9600 | 13440 |  64  |   0  |  0  |   0  | <- Available resources in the lower region
|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------
| clock |    region   |                                                                                      -----------------------------------------------
|  type |  expansion  |                                                                                      | <IO/Regional clock Net Name>
|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------
|  BUFR | Upper/Lower |   0  |  0  |  0 |   14   |    0   |    28 |     0 |     0 |   0  |   0  |  0  |   0  | "cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/adc_str"
|-------|-------------|------|-----|----|--------|--------|-------|-------|-------|------|------|-----|------|----------------------------------------------




######################################################################################
# REGIONAL CLOCKING RESOURCE DISTRIBUTION UCF REPORT:
#
# Number of Regional Clocking Regions in the device: 12  (6 clock spines in each)
# Number of Regional Clock Networks used in this design: 1 (each network can be
# composed of up to 3 clock spines and cover up to 3 regional clock regions)
# 
######################################################################################

# Regional-Clock "cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/adc_str" driven by "BUFR_X0Y6"
INST "cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_adc_if/gen_adc_clk.cmp_adc_str/cmp_bufr" LOC = "BUFR_X0Y6" ;
NET "cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/adc_str" TNM_NET =
"TN_cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/adc_str" ;
TIMEGRP "TN_cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/adc_str" AREA_GROUP =
"CLKAG_cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/adc_str" ;
AREA_GROUP "CLKAG_cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/adc_str" RANGE = CLOCKREGION_X0Y3, CLOCKREGION_X0Y4,
CLOCKREGION_X0Y2;


Phase 5.2  Initial Placement for Architecture Specific Features (Checksum:4b412ef8) REAL time: 1 mins 37 secs 

Phase 6.36  Local Placement Optimization
Phase 6.36  Local Placement Optimization (Checksum:4b412ef8) REAL time: 1 mins 37 secs 

Phase 7.30  Global Clock Region Assignment
Phase 7.30  Global Clock Region Assignment (Checksum:4b412ef8) REAL time: 1 mins 37 secs 

Phase 8.3  Local Placement Optimization
Phase 8.3  Local Placement Optimization (Checksum:4b412ef8) REAL time: 1 mins 37 secs 

Phase 9.5  Local Placement Optimization
Phase 9.5  Local Placement Optimization (Checksum:4b412ef8) REAL time: 1 mins 37 secs 

Phase 10.8  Global Placement
............................................................................................................................................
.........................................................................................................................................................................................
.......................
....................................
Phase 10.8  Global Placement (Checksum:7339deaa) REAL time: 2 mins 2 secs 

Phase 11.5  Local Placement Optimization
Phase 11.5  Local Placement Optimization (Checksum:7339deaa) REAL time: 2 mins 2 secs 

Phase 12.18  Placement Optimization
Phase 12.18  Placement Optimization (Checksum:ed97b792) REAL time: 2 mins 20 secs 

Phase 13.5  Local Placement Optimization
Phase 13.5  Local Placement Optimization (Checksum:ed97b792) REAL time: 2 mins 20 secs 

Phase 14.34  Placement Validation
Phase 14.34  Placement Validation (Checksum:f785ef2f) REAL time: 2 mins 21 secs 

Total REAL time to Placer completion: 2 mins 21 secs 
Total CPU  time to Placer completion: 2 mins 27 secs 
Running post-placement packing...
Writing output files...

Design Summary:
Number of errors:      0
Number of warnings:   17
Slice Logic Utilization:
  Number of Slice Registers:                 4,454 out of 301,440    1%
    Number used as Flip Flops:               4,449
    Number used as Latches:                      4
    Number used as Latch-thrus:                  0
    Number used as AND/OR logics:                1
  Number of Slice LUTs:                      5,190 out of 150,720    3%
    Number used as logic:                    4,494 out of 150,720    2%
      Number using O6 output only:           3,522
      Number using O5 output only:             154
      Number using O5 and O6:                  818
      Number used as ROM:                        0
    Number used as Memory:                     400 out of  58,400    1%
      Number used as Dual Port RAM:             24
        Number using O6 output only:             4
        Number using O5 output only:             0
        Number using O5 and O6:                 20
      Number used as Single Port RAM:            0
      Number used as Shift Register:           376
        Number using O6 output only:           262
        Number using O5 output only:             0
        Number using O5 and O6:                114
    Number used exclusively as route-thrus:    296
      Number with same-slice register load:    281
      Number with same-slice carry load:        15
      Number with other load:                    0

Slice Logic Distribution:
  Number of occupied Slices:                 2,245 out of  37,680    5%
  Number of LUT Flip Flop pairs used:        6,580
    Number with an unused Flip Flop:         2,836 out of   6,580   43%
    Number with an unused LUT:               1,390 out of   6,580   21%
    Number of fully used LUT-FF pairs:       2,354 out of   6,580   35%
    Number of unique control sets:             209
    Number of slice register sites lost
      to control set restrictions:             701 out of 301,440    1%

  A LUT Flip Flop pair for this architecture represents one LUT paired with
  one Flip Flop within a slice.  A control set is a unique combination of
  clock, reset, set, and enable signals for a registered element.
  The Slice Logic Distribution report is not meaningful if the design is
  over-mapped for a non-slice resource or if Placement fails.
  OVERMAPPING of BRAM resources should be ignored if the design is
  over-mapped for a non-BRAM resource or if placement fails.

IO Utilization:
  Number of bonded IOBs:                        90 out of     600   15%
    Number of LOCed IOBs:                       90 out of      90  100%
    IOB Flip Flops:                             14
    IOB Master Pads:                            10
    IOB Slave Pads:                             10

Specific Feature Utilization:
  Number of RAMB36E1/FIFO36E1s:                 51 out of     416   12%
    Number using RAMB36E1 only:                 51
    Number using FIFO36E1 only:                  0
  Number of RAMB18E1/FIFO18E1s:                 11 out of     832    1%
    Number using RAMB18E1 only:                 11
    Number using FIFO18E1 only:                  0
  Number of BUFG/BUFGCTRLs:                     10 out of      32   31%
    Number used as BUFGs:                       10
    Number used as BUFGCTRLs:                    0
  Number of ILOGICE1/ISERDESE1s:                14 out of     720    1%
    Number used as ILOGICE1s:                   14
    Number used as ISERDESE1s:                   0
  Number of OLOGICE1/OSERDESE1s:                14 out of     720    1%
    Number used as OLOGICE1s:                    4
    Number used as OSERDESE1s:                  10
  Number of BSCANs:                              1 out of       4   25%
  Number of BUFHCEs:                             0 out of     144    0%
  Number of BUFIODQSs:                           0 out of      72    0%
  Number of BUFRs:                               1 out of      36    2%
  Number of CAPTUREs:                            0 out of       1    0%
  Number of DSP48E1s:                            3 out of     768    1%
  Number of EFUSE_USRs:                          0 out of       1    0%
  Number of FRAME_ECCs:                          0 out of       1    0%
  Number of GTXE1s:                              0 out of      20    0%
  Number of IBUFDS_GTXE1s:                       0 out of      12    0%
  Number of ICAPs:                               0 out of       2    0%
  Number of IDELAYCTRLs:                         1 out of      18    5%
  Number of IODELAYE1s:                         15 out of     720    2%
  Number of MMCM_ADVs:                           2 out of      12   16%
  Number of PCIE_2_0s:                           0 out of       2    0%
  Number of STARTUPs:                            1 out of       1  100%
  Number of SYSMONs:                             0 out of       1    0%
  Number of TEMAC_SINGLEs:                       0 out of       4    0%

  Number of RPM macros:           24
Average Fanout of Non-Clock Nets:                3.63

Peak Memory Usage:  1291 MB
Total REAL time to MAP completion:  2 mins 31 secs 
Total CPU time to MAP completion (all processors):   2 mins 37 secs 

Mapping completed.
See MAP report file "dbe_bpm_simple_top_map.mrp" for details.

Process "Map" completed successfully

Started : "Place & Route".
Running par...
Command Line: par -w -intstyle ise -ol high -mt off dbe_bpm_simple_top_map.ncd dbe_bpm_simple_top.ncd dbe_bpm_simple_top.pcf



Constraints file: dbe_bpm_simple_top.pcf.
Loading device for application Rf_Device from file '6vlx240t.nph' in environment /opt/Xilinx/13.4/ISE_DS/ISE/.
   "dbe_bpm_simple_top" is an NCD, version 3.2, device xc6vlx240t, package ff1156, speed -1
vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv
INFO:Security:56 - Part 'xc6vlx240t' is not a WebPack part.
WARNING:Security:9b - No 'ISE' feature version 2012.01 was available for part 'xc6vlx240t'.
WARNING:Security:42 - Your software subscription period has lapsed. Your current version of Xilinx tools will continue
to function, but you no longer qualify for Xilinx software updates or new releases.
WARNING:Security:42 - Your software subscription period has lapsed. Your current version of Xilinx tools will continue
to function, but you no longer qualify for Xilinx software updates or new releases.

----------------------------------------------------------------------

Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
Initializing voltage to 0.950 Volts. (default - Range: 0.950 to 1.050 Volts)


Device speed data version:  "PRODUCTION 1.17 2012-01-07".



Device Utilization Summary:

Slice Logic Utilization:
  Number of Slice Registers:                 4,454 out of 301,440    1%
    Number used as Flip Flops:               4,449
    Number used as Latches:                      4
    Number used as Latch-thrus:                  0
    Number used as AND/OR logics:                1
  Number of Slice LUTs:                      5,190 out of 150,720    3%
    Number used as logic:                    4,494 out of 150,720    2%
      Number using O6 output only:           3,522
      Number using O5 output only:             154
      Number using O5 and O6:                  818
      Number used as ROM:                        0
    Number used as Memory:                     400 out of  58,400    1%
      Number used as Dual Port RAM:             24
        Number using O6 output only:             4
        Number using O5 output only:             0
        Number using O5 and O6:                 20
      Number used as Single Port RAM:            0
      Number used as Shift Register:           376
        Number using O6 output only:           262
        Number using O5 output only:             0
        Number using O5 and O6:                114
    Number used exclusively as route-thrus:    296
      Number with same-slice register load:    281
      Number with same-slice carry load:        15
      Number with other load:                    0

Slice Logic Distribution:
  Number of occupied Slices:                 2,245 out of  37,680    5%
  Number of LUT Flip Flop pairs used:        6,580
    Number with an unused Flip Flop:         2,836 out of   6,580   43%
    Number with an unused LUT:               1,390 out of   6,580   21%
    Number of fully used LUT-FF pairs:       2,354 out of   6,580   35%
    Number of slice register sites lost
      to control set restrictions:               0 out of 301,440    0%

  A LUT Flip Flop pair for this architecture represents one LUT paired with
  one Flip Flop within a slice.  A control set is a unique combination of
  clock, reset, set, and enable signals for a registered element.
  The Slice Logic Distribution report is not meaningful if the design is
  over-mapped for a non-slice resource or if Placement fails.
  OVERMAPPING of BRAM resources should be ignored if the design is
  over-mapped for a non-BRAM resource or if placement fails.

IO Utilization:
  Number of bonded IOBs:                        90 out of     600   15%
    Number of LOCed IOBs:                       90 out of      90  100%
    IOB Flip Flops:                             14
    IOB Master Pads:                            10
    IOB Slave Pads:                             10

Specific Feature Utilization:
  Number of RAMB36E1/FIFO36E1s:                 51 out of     416   12%
    Number using RAMB36E1 only:                 51
    Number using FIFO36E1 only:                  0
  Number of RAMB18E1/FIFO18E1s:                 11 out of     832    1%
    Number using RAMB18E1 only:                 11
    Number using FIFO18E1 only:                  0
  Number of BUFG/BUFGCTRLs:                     10 out of      32   31%
    Number used as BUFGs:                       10
    Number used as BUFGCTRLs:                    0
  Number of ILOGICE1/ISERDESE1s:                14 out of     720    1%
    Number used as ILOGICE1s:                   14
    Number used as ISERDESE1s:                   0
  Number of OLOGICE1/OSERDESE1s:                14 out of     720    1%
    Number used as OLOGICE1s:                    4
    Number used as OSERDESE1s:                  10
  Number of BSCANs:                              1 out of       4   25%
  Number of BUFHCEs:                             0 out of     144    0%
  Number of BUFIODQSs:                           0 out of      72    0%
  Number of BUFRs:                               1 out of      36    2%
  Number of CAPTUREs:                            0 out of       1    0%
  Number of DSP48E1s:                            3 out of     768    1%
  Number of EFUSE_USRs:                          0 out of       1    0%
  Number of FRAME_ECCs:                          0 out of       1    0%
  Number of GTXE1s:                              0 out of      20    0%
  Number of IBUFDS_GTXE1s:                       0 out of      12    0%
  Number of ICAPs:                               0 out of       2    0%
  Number of IDELAYCTRLs:                         1 out of      18    5%
  Number of IODELAYE1s:                         15 out of     720    2%
  Number of MMCM_ADVs:                           2 out of      12   16%
  Number of PCIE_2_0s:                           0 out of       2    0%
  Number of STARTUPs:                            1 out of       1  100%
  Number of SYSMONs:                             0 out of       1    0%
  Number of TEMAC_SINGLEs:                       0 out of       4    0%


Overall effort level (-ol):   High 
Router effort level (-rl):    High 

INFO:Timing:3386 - Intersecting Constraints found and resolved.  For more information, see the TSI report.  Please consult the Xilinx
   Command Line Tools User Guide for information on generating a TSI report.
Starting initial Timing Analysis.  REAL time: 25 secs 
Finished initial Timing Analysis.  REAL time: 25 secs 

WARNING:Par:288 - The signal cmp_dma/Mram_ring4_RAMD_D1_O has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_dma/Mram_ring3_RAMD_D1_O has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_dma/Mram_ring5_RAMD_D1_O has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_dma/Mram_ring2_RAMD_D1_O has no load.  PAR will not attempt to route this signal.
WARNING:Par:288 - The signal cmp_dma/Mram_ring1_RAMD_D1_O has no load.  PAR will not attempt to route this signal.
Starting Router


Phase  1  : 48177 unrouted;      REAL time: 31 secs 

Phase  2  : 37657 unrouted;      REAL time: 36 secs 

Phase  3  : 12446 unrouted;      REAL time: 1 mins 25 secs 

Phase  4  : 12446 unrouted; (Setup:0, Hold:15229, Component Switching Limit:0)     REAL time: 1 mins 36 secs 

Updating file: dbe_bpm_simple_top.ncd with current fully routed design.

Phase  5  : 0 unrouted; (Setup:0, Hold:15049, Component Switching Limit:0)     REAL time: 1 mins 47 secs 

Phase  6  : 0 unrouted; (Setup:0, Hold:15049, Component Switching Limit:0)     REAL time: 1 mins 47 secs 

Phase  7  : 0 unrouted; (Setup:0, Hold:15049, Component Switching Limit:0)     REAL time: 1 mins 47 secs 

Phase  8  : 0 unrouted; (Setup:0, Hold:15049, Component Switching Limit:0)     REAL time: 1 mins 47 secs 

Phase  9  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 1 mins 48 secs 

Phase 10  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 1 mins 48 secs 
Total REAL time to Router completion: 1 mins 48 secs 
Total CPU time to Router completion: 1 mins 49 secs 

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

Generating "PAR" statistics.

**************************
Generating Clock Report
**************************

+---------------------+--------------+------+------+------------+-------------+
|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|             clk_sys | BUFGCTRL_X0Y4| No   | 1215 |  0.313     |  1.893      |
+---------------------+--------------+------+------+------------+-------------+
|cmp_xwb_fmc150/cmp_w |              |      |      |            |             |
|b_fmc150/cmp_fmc150_ |              |      |      |            |             |
|testbench/cmp_fmc150 |              |      |      |            |             |
|_ctrl/cdce72010_ctrl |              |      |      |            |             |
|_inst/serial_clk_BUF |              |      |      |            |             |
|                   G |BUFGCTRL_X0Y29| No   |  105 |  0.186     |  1.780      |
+---------------------+--------------+------+------+------------+-------------+
|             clk_adc | BUFGCTRL_X0Y2| No   |  206 |  0.356     |  2.020      |
+---------------------+--------------+------+------+------------+-------------+
|         CONTROL0<0> |BUFGCTRL_X0Y28| No   |  166 |  0.435     |  2.019      |
+---------------------+--------------+------+------+------------+-------------+
|cmp_xwb_fmc150/cmp_w |              |      |      |            |             |
|b_fmc150/cmp_fmc150_ |              |      |      |            |             |
|testbench/cmp_fmc150 |              |      |      |            |             |
|_ctrl/cdce72010_ctrl |              |      |      |            |             |
|_inst/gen_serial_clk |              |      |      |            |             |
|     .clk_div_3_BUFG |BUFGCTRL_X0Y30| No   |   27 |  0.261     |  1.860      |
+---------------------+--------------+------+------+------------+-------------+
|cmp_xwb_fmc150/cmp_w |              |      |      |            |             |
|b_fmc150/cmp_fmc150_ |              |      |      |            |             |
|   testbench/adc_str |  Regional Clk| No   |   36 |  0.043     |  0.951      |
+---------------------+--------------+------+------+------------+-------------+
|         sys_clk_gen |BUFGCTRL_X0Y31| No   |    5 |  0.004     |  1.822      |
+---------------------+--------------+------+------+------------+-------------+
|cmp_xwb_fmc150/cmp_w |              |      |      |            |             |
|b_fmc150/cmp_fmc150_ |              |      |      |            |             |
|testbench/clk_adc_2x |              |      |      |            |             |
|                     | BUFGCTRL_X0Y0| No   |   10 |  0.021     |  1.736      |
+---------------------+--------------+------+------+------------+-------------+
|          clk_200mhz | BUFGCTRL_X0Y5| No   |    1 |  0.000     |  1.681      |
+---------------------+--------------+------+------+------------+-------------+
|        CONTROL1<13> |         Local|      |    4 |  0.000     |  0.591      |
+---------------------+--------------+------+------+------------+-------------+
|MMCM_PHASE_CALIBRATI |              |      |      |            |             |
|ON_ML_LUT2_76_ML_NEW |              |      |      |            |             |
|                _CLK |         Local|      |    2 |  0.000     |  0.504      |
+---------------------+--------------+------+------+------------+-------------+
|MMCM_PHASE_CALIBRATI |              |      |      |            |             |
|ON_ML_LUT2_68_ML_NEW |              |      |      |            |             |
|                _CLK |         Local|      |    3 |  0.121     |  0.462      |
+---------------------+--------------+------+------+------------+-------------+
|cmp_xwb_fmc150/cmp_w |              |      |      |            |             |
|b_fmc150/cmp_fmc150_ |              |      |      |            |             |
|testbench/gen_clk.cm |              |      |      |            |             |
|p_mmcm_adc_ML_NEW_OU |              |      |      |            |             |
|                   T |         Local|      |    2 |  0.000     |  0.355      |
+---------------------+--------------+------+------+------------+-------------+
|cmp_sys_pll_inst/cmp |              |      |      |            |             |
|    _mmcm_ML_NEW_OUT |         Local|      |    2 |  0.000     |  0.562      |
+---------------------+--------------+------+------+------------+-------------+
|        CONTROL0<13> |         Local|      |    5 |  0.000     |  0.519      |
+---------------------+--------------+------+------+------------+-------------+
|cmp_xwb_fmc150/cmp_w |              |      |      |            |             |
|b_fmc150/cmp_fmc150_ |              |      |      |            |             |
|testbench/gen_clk.cm |              |      |      |            |             |
|p_mmcm_adc_ML_NEW_I1 |              |      |      |            |             |
|                     |         Local|      |    3 |  0.000     |  1.074      |
+---------------------+--------------+------+------+------------+-------------+
|cmp_sys_pll_inst/cmp |              |      |      |            |             |
|     _mmcm_ML_NEW_I1 |         Local|      |    3 |  0.000     |  1.424      |
+---------------------+--------------+------+------+------------+-------------+
|cmp_chipscope_icon_0 |              |      |      |            |             |
|     /U0/iUPDATE_OUT |         Local|      |    1 |  0.000     |  0.992      |
+---------------------+--------------+------+------+------------+-------------+

* Net Skew is the difference between the minimum and maximum routing
only delays for the net. Note this is different from Clock Skew which
is reported in TRCE timing report. Clock Skew is the difference between
the minimum and maximum path delays which includes logic delays.

* The fanout is the number of component pins not the individual BEL loads,
for example SLICE loads not FF loads.

Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0)

Number of Timing Constraints that were not applied: 4

Asterisk (*) preceding a constraint indicates it was not met.
   This may be due to a setup or hold violation.

----------------------------------------------------------------------------------------------------------
  Constraint                                |    Check    | Worst Case |  Best Case | Timing |   Timing   
                                            |             |    Slack   | Achievable | Errors |    Score   
----------------------------------------------------------------------------------------------------------
  TS_cmp_xwb_fmc150_cmp_wb_fmc150_cmp_fmc15 | MINPERIOD   |     6.709ns|     1.429ns|       0|           0
  0_testbench_adc_str_2x_out_0 = PERIOD     |             |            |            |        |            
       TIMEGRP         "cmp_xwb_fmc150_cmp_ |             |            |            |        |            
  wb_fmc150_cmp_fmc150_testbench_adc_str_2x |             |            |            |        |            
  _out_0"         TS_adc_clk_ab_n_i / 2 HIG |             |            |            |        |            
  H 50%                                     |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_cmp_xwb_fmc150_cmp_wb_fmc150_cmp_fmc15 | MINPERIOD   |     6.709ns|     1.429ns|       0|           0
  0_testbench_adc_str_2x_out_1 = PERIOD     |             |            |            |        |            
       TIMEGRP         "cmp_xwb_fmc150_cmp_ |             |            |            |        |            
  wb_fmc150_cmp_fmc150_testbench_adc_str_2x |             |            |            |        |            
  _out_1"         TS_adc_clk_ab_p_i / 2 HIG |             |            |            |        |            
  H 50%                                     |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_adc_clk_ab_n_i = PERIOD TIMEGRP "adc_c | MINLOWPULSE |    10.276ns|     6.000ns|       0|           0
  lk_ab_n_i" 16.276 ns HIGH 50%             |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_adc_clk_ab_p_i = PERIOD TIMEGRP "adc_c | SETUP       |    14.354ns|     1.922ns|       0|           0
  lk_ab_p_i" 16.276 ns HIGH 50%             | HOLD        |     0.300ns|            |       0|           0
                                            | MINLOWPULSE |    10.276ns|     6.000ns|       0|           0
----------------------------------------------------------------------------------------------------------
  TIMEGRP "TMN_fmc150_adc_chb_n" OFFSET = I | SETUP       |     7.855ns|     0.283ns|       0|           0
  N 8.138 ns VALID 16.276 ns BEFORE         | HOLD        |     6.300ns|            |       0|           0
   COMP "adc_clk_ab_n_i" "RISING"           |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TIMEGRP "TMN_fmc150_adc_chb_p" OFFSET = I | SETUP       |     7.855ns|     0.283ns|       0|           0
  N 8.138 ns VALID 16.276 ns BEFORE         | HOLD        |     6.300ns|            |       0|           0
   COMP "adc_clk_ab_p_i" "RISING"           |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TIMEGRP "TMN_fmc150_adc_cha_n" OFFSET = I | SETUP       |     7.873ns|     0.265ns|       0|           0
  N 8.138 ns VALID 16.276 ns BEFORE         | HOLD        |     6.318ns|            |       0|           0
   COMP "adc_clk_ab_n_i" "RISING"           |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TIMEGRP "TMN_fmc150_adc_cha_p" OFFSET = I | SETUP       |     7.873ns|     0.265ns|       0|           0
  N 8.138 ns VALID 16.276 ns BEFORE         | HOLD        |     6.318ns|            |       0|           0
   COMP "adc_clk_ab_p_i" "RISING"           |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_cmp_xwb_fmc150_cmp_wb_fmc150_cmp_fmc15 | SETUP       |    10.362ns|     5.914ns|       0|           0
  0_testbench_adc_str_out_1 = PERIOD        | HOLD        |     0.019ns|            |       0|           0
    TIMEGRP         "cmp_xwb_fmc150_cmp_wb_ |             |            |            |        |            
  fmc150_cmp_fmc150_testbench_adc_str_out_1 |             |            |            |        |            
  "         TS_adc_clk_ab_p_i HIGH 50%      |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_cmp_xwb_fmc150_cmp_wb_fmc150_cmp_fmc15 | MINPERIOD   |    14.054ns|     2.222ns|       0|           0
  0_testbench_adc_str_out_0 = PERIOD        |             |            |            |        |            
    TIMEGRP         "cmp_xwb_fmc150_cmp_wb_ |             |            |            |        |            
  fmc150_cmp_fmc150_testbench_adc_str_out_0 |             |            |            |        |            
  "         TS_adc_clk_ab_n_i HIGH 50%      |             |            |            |        |            
----------------------------------------------------------------------------------------------------------


Derived Constraint Report
Review Timing Report for more details on the following derived constraints.
To create a Timing Report, run "trce -v 12 -fastpaths -o design_timing_report design.ncd design.pcf"
or "Run Timing Analysis" from Timing Analyzer (timingan).
Derived Constraints for TS_adc_clk_ab_n_i
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|                               |   Period    |       Actual Period       |      Timing Errors        |      Paths Analyzed       |
|           Constraint          | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
|                               |             |   Direct    | Derivative  |   Direct    | Derivative  |   Direct    | Derivative  |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_adc_clk_ab_n_i              |     16.276ns|      6.000ns|      2.858ns|            0|            0|            0|            0|
| TS_cmp_xwb_fmc150_cmp_wb_fmc15|      8.138ns|      1.429ns|          N/A|            0|            0|            0|            0|
| 0_cmp_fmc150_testbench_adc_str|             |             |             |             |             |             |             |
| _2x_out_0                     |             |             |             |             |             |             |             |
| TS_cmp_xwb_fmc150_cmp_wb_fmc15|     16.276ns|      2.222ns|          N/A|            0|            0|            0|            0|
| 0_cmp_fmc150_testbench_adc_str|             |             |             |             |             |             |             |
| _out_0                        |             |             |             |             |             |             |             |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+

Derived Constraints for TS_adc_clk_ab_p_i
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|                               |   Period    |       Actual Period       |      Timing Errors        |      Paths Analyzed       |
|           Constraint          | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
|                               |             |   Direct    | Derivative  |   Direct    | Derivative  |   Direct    | Derivative  |
+-------------------------------+-------------+-------------+----------WARNING:ProjectMgmt - File
   /home/lerwys/Repos/bpm-sw/hdl/syn/dbe_bpm_simple/_xmsgs/bitgen.xmsgs is
   missing.
---+-------------+-------------+-------------+-------------+
|TS_adc_clk_ab_p_i              |     16.276ns|      6.000ns|      5.914ns|            0|            0|           28|         5775|
| TS_cmp_xwb_fmc150_cmp_wb_fmc15|      8.138ns|      1.429ns|          N/A|            0|            0|            0|            0|
| 0_cmp_fmc150_testbench_adc_str|             |             |             |             |             |             |             |
| _2x_out_1                     |             |             |             |             |             |             |             |
| TS_cmp_xwb_fmc150_cmp_wb_fmc15|     16.276ns|      5.914ns|          N/A|            0|            0|         5775|            0|
| 0_cmp_fmc150_testbench_adc_str|             |             |             |             |             |             |             |
| _out_1                        |             |             |             |             |             |             |             |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+

All constraints were met.


Generating Pad Report.

All signals are completely routed.

WARNING:Par:283 - There are 5 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.

Total REAL time to PAR completion: 1 mins 57 secs 
Total CPU time to PAR completion: 1 mins 57 secs 

Peak Memory Usage:  1166 MB

Placer: Placement generated during map.
Routing: Completed - No errors found.
Timing: Completed - No errors found.

Number of error messages: 0
Number of warning messages: 7
Number of info messages: 1

Writing design to file dbe_bpm_simple_top.ncd



PAR done!
WARNING:ProjectMgmt - File
   /home/lerwys/Repos/bpm-sw/hdl/syn/dbe_bpm_simple/_xmsgs/trce.xmsgs is
   missing.
WARNING:ProjectMgmt - File
   /home/lerwys/Repos/bpm-sw/hdl/syn/dbe_bpm_simple/dbe_bpm_simple_top.drc is
   missing.
WARNING:ProjectMgmt - File
   /home/lerwys/Repos/bpm-sw/hdl/syn/dbe_bpm_simple/dbe_bpm_simple_top.twr is
   missing.
WARNING:ProjectMgmt - File
   /home/lerwys/Repos/bpm-sw/hdl/syn/dbe_bpm_simple/dbe_bpm_simple_top.twx is
   missing.
WARNING:ProjectMgmt - File
   /home/lerwys/Repos/bpm-sw/hdl/syn/dbe_bpm_simple/dbe_bpm_simple_top.ut is
   missing.
WARNING:ProjectMgmt - File
   /home/lerwys/Repos/bpm-sw/hdl/syn/dbe_bpm_simple/webtalk.log is missing.

Process "Place & Route" completed successfully

Started : "Generate Post-Place & Route Static Timing".
Running trce...
Command Line: trce -intstyle ise -v 3 -s 1 -n 3 -fastpaths -xml dbe_bpm_simple_top.twx dbe_bpm_simple_top.ncd -o dbe_bpm_simple_top.twr dbe_bpm_simple_top.pcf
Loading device for application Rf_Device from file '6vlx240t.nph' in environment
/opt/Xilinx/13.4/ISE_DS/ISE/.
   "dbe_bpm_simple_top" is an NCD, version 3.2, device xc6vlx240t, package
ff1156, speed -1

Analysis completed Wed Oct 24 16:30:41 2012
--------------------------------------------------------------------------------

Generating Report ...

Number of warnings: 0
Total time: 26 secs 

Process "Generate Post-Place & Route Static Timing" completed successfully

Started : "Generate Programming File".
Running bitgen...
Command Line: bitgen -intstyle ise -f dbe_bpm_simple_top.ut dbe_bpm_simple_top.ncd
INFO:Bitgen:40 - Replacing "Auto" with "NoWait" for option "Match_cycle".  Most
   commonly, bitgen has determined and will use a specific value instead of the
   generic command-line value of "Auto".  Alternately, this message appears if
   the same option is specified multiple times on the command-line.  In this
   case, the option listed last will be used.
WARNING:PhysDesignRules:372 - Gated clock. Clock net CONTROL1<13> is sourced by
   a combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net CONTROL0<13> is sourced by
   a combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.
WARNING:PhysDesignRules:367 - The signal <cmp_dma/Mram_ring4_RAMD_D1_O> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <cmp_dma/Mram_ring3_RAMD_D1_O> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <cmp_dma/Mram_ring5_RAMD_D1_O> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <cmp_dma/Mram_ring2_RAMD_D1_O> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <cmp_dma/Mram_ring1_RAMD_D1_O> is
   incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:1362 - Unexpected programming for comp
   cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_dac_if/oserdes_clock
   with TRISTATE_WIDTH. DATA_RATE_TQ set DDR expects TRISTATE_WIDTH to be set 4.
    
WARNING:PhysDesignRules:1362 - Unexpected programming for comp
   cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_dac_if/oserdes_frame
   with TRISTATE_WIDTH. DATA_RATE_TQ set DDR expects TRISTATE_WIDTH to be set 4.
    
WARNING:PhysDesignRules:1362 - Unexpected programming for comp
   cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_dac_if/dac_data[4].oser
   des_data with TRISTATE_WIDTH. DATA_RATE_TQ set DDR expects TRISTATE_WIDTH to
   be set 4. 
WARNING:PhysDesignRules:1362 - Unexpected programming for comp
   cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_dac_if/dac_data[1].oser
   des_data with TRISTATE_WIDTH. DATA_RATE_TQ set DDR expects TRISTATE_WIDTH to
   be set 4. 
WARNING:PhysDesignRules:1362 - Unexpected programming for comp
   cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_dac_if/dac_data[6].oser
   des_data with TRISTATE_WIDTH. DATA_RATE_TQ set DDR expects TRISTATE_WIDTH to
   be set 4. 
WARNING:PhysDesignRules:1362 - Unexpected programming for comp
   cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_dac_if/dac_data[3].oser
   des_data with TRISTATE_WIDTH. DATA_RATE_TQ set DDR expects TRISTATE_WIDTH to
   be set 4. 
WARNING:PhysDesignRules:1362 - Unexpected programming for comp
   cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_dac_if/dac_data[0].oser
   des_data with TRISTATE_WIDTH. DATA_RATE_TQ set DDR expects TRISTATE_WIDTH to
   be set 4. 
WARNING:PhysDesignRules:1362 - Unexpected programming for cINFO:TclTasksC:1850 - process run : Generate Programming File is done.
omp
   cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_dac_if/dac_data[5].oser
   des_data with TRISTATE_WIDTH. DATA_RATE_TQ set DDR expects TRISTATE_WIDTH to
   be set 4. 
WARNING:PhysDesignRules:1362 - Unexpected programming for comp
   cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_dac_if/dac_data[2].oser
   des_data with TRISTATE_WIDTH. DATA_RATE_TQ set DDR expects TRISTATE_WIDTH to
   be set 4. 
WARNING:PhysDesignRules:1362 - Unexpected programming for comp
   cmp_xwb_fmc150/cmp_wb_fmc150/cmp_fmc150_testbench/cmp_dac_if/dac_data[7].oser
   des_data with TRISTATE_WIDTH. DATA_RATE_TQ set DDR expects TRISTATE_WIDTH to
   be set 4. 

Process "Generate Programming File" completed successfully
