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    <!-- This file contains project source information including a list of -->
    <!-- project source files, project and process properties.  This file, -->
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    <!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved. -->
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    <property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
    <property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Reduce Control Sets" xil_pn:value="Auto" xil_pn:valueState="default"/>
    <property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
    <property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
    <property xil_pn:name="Register Duplication Map" xil_pn:value="On" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Register Ordering virtex6" xil_pn:value="4" xil_pn:valueState="default"/>
    <property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
    <property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
    <property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
    <property xil_pn:name="Rename Top Level Entity to" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
    <property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
    <property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
    <property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
    <property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
    <property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
    <property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
    <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
    <property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Shift Register Minimum Size virtex6" xil_pn:value="2" xil_pn:valueState="default"/>
    <property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Simulation Model Target" xil_pn:value="Verilog" xil_pn:valueState="default"/>
    <property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
    <property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
    <property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
    <property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
    <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
    <property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
    <property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/>
    <property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
    <property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
    <property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
    <property xil_pn:name="Speed Grade" xil_pn:value="-1" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Starting Address for Fallback Configuration virtex6" xil_pn:value="None" xil_pn:valueState="default"/>
    <property xil_pn:name="Starting Placer Cost Table (1-100)" xil_pn:value="1" xil_pn:valueState="default"/>
    <property xil_pn:name="Synthesis Constraints File" xil_pn:value="../../../top/ml_605/dbe_bpm_dsp_fmc130m_4ch/dbe_bpm_dsp.xcf" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
    <property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
    <property xil_pn:name="Timing Mode Map" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
    <property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
    <property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
    <property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
    <property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
    <property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/>
    <property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Use DSP Block" xil_pn:value="Auto" xil_pn:valueState="default"/>
    <property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
    <property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
    <property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
    <property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="User Access Register Value" xil_pn:value="None" xil_pn:valueState="default"/>
    <property xil_pn:name="User Browsed Strategy Files" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
    <property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
    <property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Wait for DCI Match (Output Events) virtex5" xil_pn:value="Auto" xil_pn:valueState="default"/>
    <property xil_pn:name="Wait for PLL Lock (Output Events) virtex6" xil_pn:value="No Wait" xil_pn:valueState="default"/>
    <property xil_pn:name="Watchdog Timer Mode virtex5" xil_pn:value="Off" xil_pn:valueState="default"/>
    <property xil_pn:name="Watchdog Timer Value virtex5" xil_pn:value="0x000000" xil_pn:valueState="default"/>
    <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
    <property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
    <!--                                                                                  -->
    <!-- The following properties are for internal use only. These should not be modified.-->
    <!--                                                                                  -->
    <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="PROP_DesignName" xil_pn:value="dbe_bpm_dsp" xil_pn:valueState="non-default"/>
    <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="virtex6" xil_pn:valueState="default"/>
    <property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
    <property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
    <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2014-01-20T17:13:31" xil_pn:valueState="non-default"/>
    <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="18486A44AE81BE14C1E547BE458444B8" xil_pn:valueState="non-default"/>
    <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
    <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
  </properties>

  <libraries>
    <library xil_pn:name="blk_mem_gen_v4_1"/>
    <library xil_pn:name="fifo_generator_v6_1"/>
  </libraries>

  <files>
    <file xil_pn:name="../../../ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/dv_gn_v4_0_e1825854b6ed410d.ngc" xil_pn:type="FILE_NGC">
      <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
    </file>
    <file xil_pn:name="../../../platform/virtex6/chipscope/ila/chipscope_ila_4096.ngc" xil_pn:type="FILE_NGC">
      <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
    </file>
    <file xil_pn:name="../../../platform/virtex6/chipscope/ila/chipscope_ila.ngc" xil_pn:type="FILE_NGC">
      <association xil_pn:name="Implementation" xil_pn:seqID="3"/>
    </file>
    <file xil_pn:name="../../../ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/crdc_v5_0_19fb63dead3076ad.ngc" xil_pn:type="FILE_NGC">
      <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
    </file>
    <file xil_pn:name="../../../modules/dbe_wishbone/wb_fmc150/netlist/amc7823_init_mem.ngc" xil_pn:type="FILE_NGC">
      <association xil_pn:name="Implementation" xil_pn:seqID="5"/>
    </file>
    <file xil_pn:name="../../../ip_cores/pcie/ml605/mbuf_128x72.ngc" xil_pn:type="FILE_NGC">
      <association xil_pn:name="Implementation" xil_pn:seqID="6"/>
    </file>
    <file xil_pn:name="../../../platform/virtex6/chipscope/icon_13_port/chipscope_icon_13_port.ngc" xil_pn:type="FILE_NGC">
      <association xil_pn:name="Implementation" xil_pn:seqID="7"/>
    </file>
    <file xil_pn:name="../../../ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/fr_cmplr_v6_3_c7662ab7880aa65a.ngc" xil_pn:type="FILE_NGC">
      <association xil_pn:name="Implementation" xil_pn:seqID="8"/>
    </file>
    <file xil_pn:name="../../../platform/virtex6/ip_cores/dds_adc_input.ngc" xil_pn:type="FILE_NGC">
      <association xil_pn:name="Implementation" xil_pn:seqID="9"/>
    </file>
    <file xil_pn:name="../../../platform/virtex6/chipscope/icon_1_port/chipscope_icon_1_port.ngc" xil_pn:type="FILE_NGC">
      <association xil_pn:name="Implementation" xil_pn:seqID="10"/>
    </file>
    <file xil_pn:name="../../../platform/virtex6/chipscope/ila/chipscope_ila_1024_5_port.ngc" xil_pn:type="FILE_NGC">
      <association xil_pn:name="Implementation" xil_pn:seqID="11"/>
    </file>
    <file xil_pn:name="../../../ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/dv_gn_v4_0_f359164f94f65852.ngc" xil_pn:type="FILE_NGC">
      <association xil_pn:name="Implementation" xil_pn:seqID="12"/>
    </file>
    <file xil_pn:name="../../../platform/virtex6/chipscope/icon_7_port/chipscope_icon_7_port.ngc" xil_pn:type="FILE_NGC">
      <association xil_pn:name="Implementation" xil_pn:seqID="13"/>
    </file>
    <file xil_pn:name="../../../ip_cores/dsp-cores/hdl/platform/virtex6/multiplier_u16x16_DSP.ngc" xil_pn:type="FILE_NGC">
      <association xil_pn:name="Implementation" xil_pn:seqID="14"/>
    </file>
    <file xil_pn:name="../../../platform/virtex6/chipscope/icon_2_port/chipscope_icon_2_port.ngc" xil_pn:type="FILE_NGC">
      <association xil_pn:name="Implementation" xil_pn:seqID="15"/>
    </file>
    <file xil_pn:name="../../../platform/virtex6/chipscope/ila/chipscope_ila_65536.ngc" xil_pn:type="FILE_NGC">
      <association xil_pn:name="Implementation" xil_pn:seqID="16"/>
    </file>
    <file xil_pn:name="../../../ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/cc_cmplr_v3_0_72b7a24319d65c58.ngc" xil_pn:type="FILE_NGC">
      <association xil_pn:name="Implementation" xil_pn:seqID="17"/>
    </file>
    <file xil_pn:name="../../../ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/addsb_11_0_239e4f614ba09ab1.ngc" xil_pn:type="FILE_NGC">
      <association xil_pn:name="Implementation" xil_pn:seqID="18"/>
    </file>
    <file xil_pn:name="../../../ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/cntr_11_0_3166d4cc5b09c744.ngc" xil_pn:type="FILE_NGC">
      <association xil_pn:name="Implementation" xil_pn:seqID="19"/>
    </file>
    <file xil_pn:name="../../../platform/virtex6/chipscope/ila/chipscope_ila_1024.ngc" xil_pn:type="FILE_NGC">
      <association xil_pn:name="Implementation" xil_pn:seqID="20"/>
    </file>
    <file xil_pn:name="../../../platform/virtex6/chipscope/icon_8_port/chipscope_icon_8_port.ngc" xil_pn:type="FILE_NGC">
      <association xil_pn:name="Implementation" xil_pn:seqID="21"/>
    </file>
    <file xil_pn:name="../../../ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/xlpersistentdff.ngc" xil_pn:type="FILE_NGC">
      <association xil_pn:name="Implementation" xil_pn:seqID="22"/>
    </file>
    <file xil_pn:name="../../../ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/cc_cmplr_v3_0_7a1c77196b2a4f1a.ngc" xil_pn:type="FILE_NGC">
      <association xil_pn:name="Implementation" xil_pn:seqID="23"/>
    </file>
    <file xil_pn:name="../../../modules/dbe_wishbone/wb_fmc150/netlist/ads62p49_init_mem.ngc" xil_pn:type="FILE_NGC">
      <association xil_pn:name="Implementation" xil_pn:seqID="24"/>
    </file>
    <file xil_pn:name="../../../ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/fr_cmplr_v6_3_13cdfed42912891b.ngc" xil_pn:type="FILE_NGC">
      <association xil_pn:name="Implementation" xil_pn:seqID="25"/>
    </file>
    <file xil_pn:name="../../../ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/addsb_11_0_26986301a9f671cd.ngc" xil_pn:type="FILE_NGC">
      <association xil_pn:name="Implementation" xil_pn:seqID="26"/>
    </file>
    <file xil_pn:name="../../../platform/virtex6/chipscope/ila/chipscope_ila_32768.ngc" xil_pn:type="FILE_NGC">
      <association xil_pn:name="Implementation" xil_pn:seqID="27"/>
    </file>
    <file xil_pn:name="../../../platform/virtex6/chipscope/ila/chipscope_ila_8192.ngc" xil_pn:type="FILE_NGC">
      <association xil_pn:name="Implementation" xil_pn:seqID="28"/>
    </file>
    <file xil_pn:name="../../../platform/virtex6/chipscope/ila/chipscope_ila_131072.ngc" xil_pn:type="FILE_NGC">
      <association xil_pn:name="Implementation" xil_pn:seqID="29"/>
    </file>
    <file xil_pn:name="../../../ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/fr_cmplr_v6_3_51c8a9a7f4af2b84.ngc" xil_pn:type="FILE_NGC">
      <association xil_pn:name="Implementation" xil_pn:seqID="30"/>
    </file>
    <file xil_pn:name="../../../modules/dbe_wishbone/wb_fmc150/netlist/cdce72010_init_mem_ext.ngc" xil_pn:type="FILE_NGC">
      <association xil_pn:name="Implementation" xil_pn:seqID="31"/>
    </file>
    <file xil_pn:name="../../../top/ml_605/dbe_bpm_dsp_fmc130m_4ch/position_calc_core.ucf" xil_pn:type="FILE_UCF">
      <association xil_pn:name="Implementation" xil_pn:seqID="32"/>
    </file>
    <file xil_pn:name="../../../ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/cmpy_v5_0_fc1d91881e8e8ae6.ngc" xil_pn:type="FILE_NGC">
      <association xil_pn:name="Implementation" xil_pn:seqID="33"/>
    </file>
    <file xil_pn:name="../../../ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/mult_11_2_6d8e463c710483da.ngc" xil_pn:type="FILE_NGC">
      <association xil_pn:name="Implementation" xil_pn:seqID="34"/>
    </file>
    <file xil_pn:name="../../../ip_cores/pcie/ml605/sfifo_15x128.ngc" xil_pn:type="FILE_NGC">
      <association xil_pn:name="Implementation" xil_pn:seqID="35"/>
    </file>
    <file xil_pn:name="../../../ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/fifo_generator_virtex6_8_4_5960d79e895706a2.ngc" xil_pn:type="FILE_NGC">
      <association xil_pn:name="Implementation" xil_pn:seqID="36"/>
    </file>
    <file xil_pn:name="../../../ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/fr_cmplr_v6_3_151f7e91d56bb0e7.ngc" xil_pn:type="FILE_NGC">
      <association xil_pn:name="Implementation" xil_pn:seqID="37"/>
    </file>
    <file xil_pn:name="../../../platform/virtex6/chipscope/vio/chipscope_vio_256.ngc" xil_pn:type="FILE_NGC">
      <association xil_pn:name="Implementation" xil_pn:seqID="38"/>
    </file>
    <file xil_pn:name="../../../ip_cores/dsp-cores/hdl/modules/position_calc/generated/virtex6/addsb_11_0_8b0747970e52f130.ngc" xil_pn:type="FILE_NGC">
      <association xil_pn:name="Implementation" xil_pn:seqID="39"/>
    </file>
    <file xil_pn:name="../../../ip_cores/pcie/ml605/bram_x64.ngc" xil_pn:type="FILE_NGC">
      <association xil_pn:name="Implementation" xil_pn:seqID="40"/>
    </file>
    <file xil_pn:name="../../../platform/virtex6/chipscope/icon_4_port/chipscope_icon_4_port.ngc" xil_pn:type="FILE_NGC">
      <association xil_pn:name="Implementation" xil_pn:seqID="41"/>
    </file>
    <file xil_pn:name="../../../ip_cores/dsp-cores/hdl/platform/virtex6/multiplier_16x10_DSP.ngc" xil_pn:type="FILE_NGC">
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</project>
