wb_dma_ctl_iface
Wishbone DMA Streaming Control Interface
Simple Wishbone DMA interface for controlling the DMA Streaming peripheral
Contents:
1. Memory map summary
2. HDL symbol
3. Register description
3.1. Control/Status register
3.2. Transaction Counter
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→
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rst_n_i
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Control/Status register:
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→
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clk_sys_i
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dma_ctl_iface_ctl_start_o
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→
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→
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wb_adr_i
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dma_ctl_iface_ctl_done_i
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←
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⇒
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wb_dat_i[31:0]
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dma_ctl_iface_ctl_ovf_i
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←
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⇐
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wb_dat_o[31:0]
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→
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wb_cyc_i
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Transaction Counter:
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⇒
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wb_sel_i[3:0]
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dma_ctl_iface_tr_cntr_o[31:0]
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⇒
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→
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wb_stb_i
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→
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wb_we_i
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←
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wb_ack_o
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←
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wb_stall_o
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HW prefix:
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dma_ctl_iface_ctl
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HW address:
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0x0
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C prefix:
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CTL
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C offset:
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0x0
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A register defining the Control and Status of the core.
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31
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30
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29
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28
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27
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26
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25
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24
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-
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-
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-
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-
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-
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-
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-
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-
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23
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22
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21
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20
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19
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18
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17
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16
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-
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-
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-
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-
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-
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-
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-
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-
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15
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14
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13
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12
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11
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10
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9
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8
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-
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-
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-
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-
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-
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-
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-
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-
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7
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6
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5
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4
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3
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2
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1
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0
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-
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-
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-
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-
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-
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OVF
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DONE
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START
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-
START
[read/write]: Start Transaction
write 1: starts the DMA transaction.
write 0: no effect
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DONE
[read-only]: DMA complete
read 1: the DMA has completed the transaction
read 0: DMA transaction still in progress
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OVF
[read-only]: DMA overflow
read 1: the DMA overflow detected
read 0: No overflow detected
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HW prefix:
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dma_ctl_iface_tr_cntr
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HW address:
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0x1
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C prefix:
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TR_CNTR
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C offset:
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0x4
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Register holding the word count to be transfered to DMA
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31
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30
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29
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28
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27
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26
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25
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24
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TR_CNTR[31:24]
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23
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22
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21
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20
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19
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18
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17
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16
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TR_CNTR[23:16]
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|
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15
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14
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13
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12
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11
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10
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9
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8
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TR_CNTR[15:8]
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7
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6
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5
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4
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3
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2
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1
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0
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TR_CNTR[7:0]
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-
TR_CNTR
[read/write]: Transactions Counter
Stores the words to be transfered to DMA