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-- Title          : Wishbone slave core for FMC ADC 250MS/s core registers
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-- File           : wb_fmc516_regs.vhd
-- Author         : auto-generated by wbgen2 from wb_fmc516_regs.wb
-- Created        : Thu Dec  6 16:10:54 2012
-- Standard       : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wb_fmc516_regs.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

use work.fmc516_wbgen2_pkg.all;


entity wb_fmc516_regs is
  port (
    rst_n_i                                  : in     std_logic;
    clk_sys_i                                : in     std_logic;
    wb_adr_i                                 : in     std_logic_vector(3 downto 0);
    wb_dat_i                                 : in     std_logic_vector(31 downto 0);
    wb_dat_o                                 : out    std_logic_vector(31 downto 0);
    wb_cyc_i                                 : in     std_logic;
    wb_sel_i                                 : in     std_logic_vector(3 downto 0);
    wb_stb_i                                 : in     std_logic;
    wb_we_i                                  : in     std_logic;
    wb_ack_o                                 : out    std_logic;
    wb_stall_o                               : out    std_logic;
    fs_clk_i                                 : in     std_logic;
    wb_clk_i                                 : in     std_logic;
    regs_i                                   : in     t_fmc516_in_registers;
    regs_o                                   : out    t_fmc516_out_registers
  );
end wb_fmc516_regs;

architecture syn of wb_fmc516_regs is

signal fmc516_fmc_ctl_test_data_en_int          : std_logic      ;
signal fmc516_fmc_ctl_led_0_int                 : std_logic      ;
signal fmc516_fmc_ctl_led_1_int                 : std_logic      ;
signal fmc516_fmc_ctl_clk_sel_int               : std_logic      ;
signal fmc516_fmc_ctl_vcxo_out_en_int           : std_logic      ;
signal fmc516_fmc_ctl_reserved_int              : std_logic_vector(26 downto 0);
signal fmc516_trig_cfg_hw_trig_pol_int          : std_logic      ;
signal fmc516_trig_cfg_hw_trig_pol_sync0        : std_logic      ;
signal fmc516_trig_cfg_hw_trig_pol_sync1        : std_logic      ;
signal fmc516_trig_cfg_hw_trig_en_int           : std_logic      ;
signal fmc516_trig_cfg_hw_trig_en_sync0         : std_logic      ;
signal fmc516_trig_cfg_hw_trig_en_sync1         : std_logic      ;
signal fmc516_trig_cfg_reserved_int             : std_logic_vector(29 downto 0);
signal fmc516_adc_ctl_update_dly_dly0           : std_logic      ;
signal fmc516_adc_ctl_update_dly_int            : std_logic      ;
signal fmc516_adc_ctl_rst_adcs_dly0             : std_logic      ;
signal fmc516_adc_ctl_rst_adcs_int              : std_logic      ;
signal fmc516_adc_ctl_rst_div_adcs_dly0         : std_logic      ;
signal fmc516_adc_ctl_rst_div_adcs_int          : std_logic      ;
signal fmc516_ch0_sta_val_int                   : std_logic_vector(15 downto 0);
signal fmc516_ch0_sta_val_lwb                   : std_logic      ;
signal fmc516_ch0_sta_val_lwb_delay             : std_logic      ;
signal fmc516_ch0_sta_val_lwb_in_progress       : std_logic      ;
signal fmc516_ch0_sta_val_lwb_s0                : std_logic      ;
signal fmc516_ch0_sta_val_lwb_s1                : std_logic      ;
signal fmc516_ch0_sta_val_lwb_s2                : std_logic      ;
signal fmc516_ch0_ctl_inc_chain_dly_dly0        : std_logic      ;
signal fmc516_ch0_ctl_inc_chain_dly_int         : std_logic      ;
signal fmc516_ch0_ctl_dec_chain_dly_dly0        : std_logic      ;
signal fmc516_ch0_ctl_dec_chain_dly_int         : std_logic      ;
signal fmc516_ch0_ctl_reserved_int              : std_logic_vector(13 downto 0);
signal fmc516_ch1_sta_val_int                   : std_logic_vector(15 downto 0);
signal fmc516_ch1_sta_val_lwb                   : std_logic      ;
signal fmc516_ch1_sta_val_lwb_delay             : std_logic      ;
signal fmc516_ch1_sta_val_lwb_in_progress       : std_logic      ;
signal fmc516_ch1_sta_val_lwb_s0                : std_logic      ;
signal fmc516_ch1_sta_val_lwb_s1                : std_logic      ;
signal fmc516_ch1_sta_val_lwb_s2                : std_logic      ;
signal fmc516_ch1_ctl_inc_chain_dly_dly0        : std_logic      ;
signal fmc516_ch1_ctl_inc_chain_dly_int         : std_logic      ;
signal fmc516_ch1_ctl_dec_chain_dly_dly0        : std_logic      ;
signal fmc516_ch1_ctl_dec_chain_dly_int         : std_logic      ;
signal fmc516_ch1_ctl_reserved_int              : std_logic_vector(13 downto 0);
signal fmc516_ch2_sta_val_int                   : std_logic_vector(15 downto 0);
signal fmc516_ch2_sta_val_lwb                   : std_logic      ;
signal fmc516_ch2_sta_val_lwb_delay             : std_logic      ;
signal fmc516_ch2_sta_val_lwb_in_progress       : std_logic      ;
signal fmc516_ch2_sta_val_lwb_s0                : std_logic      ;
signal fmc516_ch2_sta_val_lwb_s1                : std_logic      ;
signal fmc516_ch2_sta_val_lwb_s2                : std_logic      ;
signal fmc516_ch2_ctl_inc_chain_dly_dly0        : std_logic      ;
signal fmc516_ch2_ctl_inc_chain_dly_int         : std_logic      ;
signal fmc516_ch2_ctl_dec_chain_dly_dly0        : std_logic      ;
signal fmc516_ch2_ctl_dec_chain_dly_int         : std_logic      ;
signal fmc516_ch2_ctl_reserved_int              : std_logic_vector(13 downto 0);
signal fmc516_ch3_sta_val_int                   : std_logic_vector(15 downto 0);
signal fmc516_ch3_sta_val_lwb                   : std_logic      ;
signal fmc516_ch3_sta_val_lwb_delay             : std_logic      ;
signal fmc516_ch3_sta_val_lwb_in_progress       : std_logic      ;
signal fmc516_ch3_sta_val_lwb_s0                : std_logic      ;
signal fmc516_ch3_sta_val_lwb_s1                : std_logic      ;
signal fmc516_ch3_sta_val_lwb_s2                : std_logic      ;
signal fmc516_ch3_ctl_inc_chain_dly_dly0        : std_logic      ;
signal fmc516_ch3_ctl_inc_chain_dly_int         : std_logic      ;
signal fmc516_ch3_ctl_dec_chain_dly_dly0        : std_logic      ;
signal fmc516_ch3_ctl_dec_chain_dly_int         : std_logic      ;
signal fmc516_ch3_ctl_reserved_int              : std_logic_vector(13 downto 0);
signal ack_sreg                                 : std_logic_vector(9 downto 0);
signal rddata_reg                               : std_logic_vector(31 downto 0);
signal wrdata_reg                               : std_logic_vector(31 downto 0);
signal bwsel_reg                                : std_logic_vector(3 downto 0);
signal rwaddr_reg                               : std_logic_vector(3 downto 0);
signal ack_in_progress                          : std_logic      ;
signal wr_int                                   : std_logic      ;
signal rd_int                                   : std_logic      ;
signal allones                                  : std_logic_vector(31 downto 0);
signal allzeros                                 : std_logic_vector(31 downto 0);

begin
-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
  wrdata_reg <= wb_dat_i;
  bwsel_reg <= wb_sel_i;
  rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
  wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
  allones <= (others => '1');
  allzeros <= (others => '0');
-- 
-- Main register bank access process.
  process (clk_sys_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      ack_sreg <= "0000000000";
      ack_in_progress <= '0';
      rddata_reg <= "00000000000000000000000000000000";
      fmc516_fmc_ctl_test_data_en_int <= '0';
      fmc516_fmc_ctl_led_0_int <= '0';
      fmc516_fmc_ctl_led_1_int <= '0';
      fmc516_fmc_ctl_clk_sel_int <= '0';
      fmc516_fmc_ctl_vcxo_out_en_int <= '0';
      fmc516_fmc_ctl_reserved_int <= "000000000000000000000000000";
      fmc516_trig_cfg_hw_trig_pol_int <= '0';
      fmc516_trig_cfg_hw_trig_en_int <= '0';
      fmc516_trig_cfg_reserved_int <= "000000000000000000000000000000";
      fmc516_adc_ctl_update_dly_int <= '0';
      fmc516_adc_ctl_rst_adcs_int <= '0';
      fmc516_adc_ctl_rst_div_adcs_int <= '0';
      fmc516_ch0_sta_val_lwb <= '0';
      fmc516_ch0_sta_val_lwb_delay <= '0';
      fmc516_ch0_sta_val_lwb_in_progress <= '0';
      regs_o.ch0_ctl_clk_chain_dly_load_o <= '0';
      regs_o.ch0_ctl_data_chain_dly_load_o <= '0';
      fmc516_ch0_ctl_inc_chain_dly_int <= '0';
      fmc516_ch0_ctl_dec_chain_dly_int <= '0';
      fmc516_ch0_ctl_reserved_int <= "00000000000000";
      fmc516_ch1_sta_val_lwb <= '0';
      fmc516_ch1_sta_val_lwb_delay <= '0';
      fmc516_ch1_sta_val_lwb_in_progress <= '0';
      regs_o.ch1_ctl_clk_chain_dly_load_o <= '0';
      regs_o.ch1_ctl_data_chain_dly_load_o <= '0';
      fmc516_ch1_ctl_inc_chain_dly_int <= '0';
      fmc516_ch1_ctl_dec_chain_dly_int <= '0';
      fmc516_ch1_ctl_reserved_int <= "00000000000000";
      fmc516_ch2_sta_val_lwb <= '0';
      fmc516_ch2_sta_val_lwb_delay <= '0';
      fmc516_ch2_sta_val_lwb_in_progress <= '0';
      regs_o.ch2_ctl_clk_chain_dly_load_o <= '0';
      regs_o.ch2_ctl_data_chain_dly_load_o <= '0';
      fmc516_ch2_ctl_inc_chain_dly_int <= '0';
      fmc516_ch2_ctl_dec_chain_dly_int <= '0';
      fmc516_ch2_ctl_reserved_int <= "00000000000000";
      fmc516_ch3_sta_val_lwb <= '0';
      fmc516_ch3_sta_val_lwb_delay <= '0';
      fmc516_ch3_sta_val_lwb_in_progress <= '0';
      regs_o.ch3_ctl_clk_chain_dly_load_o <= '0';
      regs_o.ch3_ctl_data_chain_dly_load_o <= '0';
      fmc516_ch3_ctl_inc_chain_dly_int <= '0';
      fmc516_ch3_ctl_dec_chain_dly_int <= '0';
      fmc516_ch3_ctl_reserved_int <= "00000000000000";
    elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
      ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
      ack_sreg(9) <= '0';
      if (ack_in_progress = '1') then
        if (ack_sreg(0) = '1') then
          fmc516_adc_ctl_update_dly_int <= '0';
          fmc516_adc_ctl_rst_adcs_int <= '0';
          fmc516_adc_ctl_rst_div_adcs_int <= '0';
          regs_o.ch0_ctl_clk_chain_dly_load_o <= '0';
          regs_o.ch0_ctl_data_chain_dly_load_o <= '0';
          fmc516_ch0_ctl_inc_chain_dly_int <= '0';
          fmc516_ch0_ctl_dec_chain_dly_int <= '0';
          regs_o.ch1_ctl_clk_chain_dly_load_o <= '0';
          regs_o.ch1_ctl_data_chain_dly_load_o <= '0';
          fmc516_ch1_ctl_inc_chain_dly_int <= '0';
          fmc516_ch1_ctl_dec_chain_dly_int <= '0';
          regs_o.ch2_ctl_clk_chain_dly_load_o <= '0';
          regs_o.ch2_ctl_data_chain_dly_load_o <= '0';
          fmc516_ch2_ctl_inc_chain_dly_int <= '0';
          fmc516_ch2_ctl_dec_chain_dly_int <= '0';
          regs_o.ch3_ctl_clk_chain_dly_load_o <= '0';
          regs_o.ch3_ctl_data_chain_dly_load_o <= '0';
          fmc516_ch3_ctl_inc_chain_dly_int <= '0';
          fmc516_ch3_ctl_dec_chain_dly_int <= '0';
          ack_in_progress <= '0';
        else
          fmc516_ch0_sta_val_lwb <= fmc516_ch0_sta_val_lwb_delay;
          fmc516_ch0_sta_val_lwb_delay <= '0';
          if ((ack_sreg(1) = '1') and (fmc516_ch0_sta_val_lwb_in_progress = '1')) then
            rddata_reg(15 downto 0) <= fmc516_ch0_sta_val_int;
            fmc516_ch0_sta_val_lwb_in_progress <= '0';
          end if;
          regs_o.ch0_ctl_clk_chain_dly_load_o <= '0';
          regs_o.ch0_ctl_data_chain_dly_load_o <= '0';
          fmc516_ch1_sta_val_lwb <= fmc516_ch1_sta_val_lwb_delay;
          fmc516_ch1_sta_val_lwb_delay <= '0';
          if ((ack_sreg(1) = '1') and (fmc516_ch1_sta_val_lwb_in_progress = '1')) then
            rddata_reg(15 downto 0) <= fmc516_ch1_sta_val_int;
            fmc516_ch1_sta_val_lwb_in_progress <= '0';
          end if;
          regs_o.ch1_ctl_clk_chain_dly_load_o <= '0';
          regs_o.ch1_ctl_data_chain_dly_load_o <= '0';
          fmc516_ch2_sta_val_lwb <= fmc516_ch2_sta_val_lwb_delay;
          fmc516_ch2_sta_val_lwb_delay <= '0';
          if ((ack_sreg(1) = '1') and (fmc516_ch2_sta_val_lwb_in_progress = '1')) then
            rddata_reg(15 downto 0) <= fmc516_ch2_sta_val_int;
            fmc516_ch2_sta_val_lwb_in_progress <= '0';
          end if;
          regs_o.ch2_ctl_clk_chain_dly_load_o <= '0';
          regs_o.ch2_ctl_data_chain_dly_load_o <= '0';
          fmc516_ch3_sta_val_lwb <= fmc516_ch3_sta_val_lwb_delay;
          fmc516_ch3_sta_val_lwb_delay <= '0';
          if ((ack_sreg(1) = '1') and (fmc516_ch3_sta_val_lwb_in_progress = '1')) then
            rddata_reg(15 downto 0) <= fmc516_ch3_sta_val_int;
            fmc516_ch3_sta_val_lwb_in_progress <= '0';
          end if;
          regs_o.ch3_ctl_clk_chain_dly_load_o <= '0';
          regs_o.ch3_ctl_data_chain_dly_load_o <= '0';
        end if;
      else
        if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
          case rwaddr_reg(3 downto 0) is
          when "0000" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(0) <= regs_i.fmc_sta_lmk_locked_i;
            rddata_reg(1) <= regs_i.fmc_sta_mmcm_locked_i;
            rddata_reg(2) <= regs_i.fmc_sta_pwr_good_i;
            rddata_reg(3) <= regs_i.fmc_sta_prst_i;
            rddata_reg(31 downto 4) <= regs_i.fmc_sta_reserved_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "0001" => 
            if (wb_we_i = '1') then
              fmc516_fmc_ctl_test_data_en_int <= wrdata_reg(0);
              fmc516_fmc_ctl_led_0_int <= wrdata_reg(1);
              fmc516_fmc_ctl_led_1_int <= wrdata_reg(2);
              fmc516_fmc_ctl_clk_sel_int <= wrdata_reg(3);
              fmc516_fmc_ctl_vcxo_out_en_int <= wrdata_reg(4);
              fmc516_fmc_ctl_reserved_int <= wrdata_reg(31 downto 5);
            end if;
            rddata_reg(0) <= fmc516_fmc_ctl_test_data_en_int;
            rddata_reg(1) <= fmc516_fmc_ctl_led_0_int;
            rddata_reg(2) <= fmc516_fmc_ctl_led_1_int;
            rddata_reg(3) <= fmc516_fmc_ctl_clk_sel_int;
            rddata_reg(4) <= fmc516_fmc_ctl_vcxo_out_en_int;
            rddata_reg(31 downto 5) <= fmc516_fmc_ctl_reserved_int;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "0010" => 
            if (wb_we_i = '1') then
              fmc516_trig_cfg_hw_trig_pol_int <= wrdata_reg(0);
              fmc516_trig_cfg_hw_trig_en_int <= wrdata_reg(1);
              fmc516_trig_cfg_reserved_int <= wrdata_reg(31 downto 2);
            end if;
            rddata_reg(0) <= fmc516_trig_cfg_hw_trig_pol_int;
            rddata_reg(1) <= fmc516_trig_cfg_hw_trig_en_int;
            rddata_reg(31 downto 2) <= fmc516_trig_cfg_reserved_int;
            ack_sreg(3) <= '1';
            ack_in_progress <= '1';
          when "0011" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(3 downto 0) <= regs_i.adc_sta_clk_chains_i;
            rddata_reg(7 downto 4) <= regs_i.adc_sta_reserved_clk_chains_i;
            rddata_reg(11 downto 8) <= regs_i.adc_sta_data_chains_i;
            rddata_reg(15 downto 12) <= regs_i.adc_sta_reserved_data_chains_i;
            rddata_reg(31 downto 16) <= regs_i.adc_sta_adc_pkt_size_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "0100" => 
            if (wb_we_i = '1') then
              fmc516_adc_ctl_update_dly_int <= wrdata_reg(0);
              fmc516_adc_ctl_rst_adcs_int <= wrdata_reg(1);
              fmc516_adc_ctl_rst_div_adcs_int <= wrdata_reg(2);
            end if;
            rddata_reg(0) <= 'X';
            rddata_reg(1) <= 'X';
            rddata_reg(2) <= 'X';
            rddata_reg(31 downto 3) <= regs_i.adc_ctl_reserved_i;
            ack_sreg(2) <= '1';
            ack_in_progress <= '1';
          when "0101" => 
            if (wb_we_i = '1') then
            end if;
            if (wb_we_i = '0') then
              fmc516_ch0_sta_val_lwb <= '1';
              fmc516_ch0_sta_val_lwb_delay <= '1';
              fmc516_ch0_sta_val_lwb_in_progress <= '1';
            end if;
            rddata_reg(31 downto 16) <= regs_i.ch0_sta_reserved_i;
            ack_sreg(5) <= '1';
            ack_in_progress <= '1';
          when "0110" => 
            if (wb_we_i = '1') then
              regs_o.ch0_ctl_clk_chain_dly_load_o <= '1';
              regs_o.ch0_ctl_data_chain_dly_load_o <= '1';
              fmc516_ch0_ctl_inc_chain_dly_int <= wrdata_reg(16);
              fmc516_ch0_ctl_dec_chain_dly_int <= wrdata_reg(17);
              fmc516_ch0_ctl_reserved_int <= wrdata_reg(31 downto 18);
            end if;
            rddata_reg(4 downto 0) <= regs_i.ch0_ctl_clk_chain_dly_i;
            rddata_reg(7 downto 5) <= regs_i.ch0_ctl_reserved_clk_chain_dly_i;
            rddata_reg(12 downto 8) <= regs_i.ch0_ctl_data_chain_dly_i;
            rddata_reg(15 downto 13) <= regs_i.ch0_ctl_reserved_data_chain_dly_i;
            rddata_reg(16) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(31 downto 18) <= fmc516_ch0_ctl_reserved_int;
            ack_sreg(2) <= '1';
            ack_in_progress <= '1';
          when "0111" => 
            if (wb_we_i = '1') then
            end if;
            if (wb_we_i = '0') then
              fmc516_ch1_sta_val_lwb <= '1';
              fmc516_ch1_sta_val_lwb_delay <= '1';
              fmc516_ch1_sta_val_lwb_in_progress <= '1';
            end if;
            rddata_reg(31 downto 16) <= regs_i.ch1_sta_reserved_i;
            ack_sreg(5) <= '1';
            ack_in_progress <= '1';
          when "1000" => 
            if (wb_we_i = '1') then
              regs_o.ch1_ctl_clk_chain_dly_load_o <= '1';
              regs_o.ch1_ctl_data_chain_dly_load_o <= '1';
              fmc516_ch1_ctl_inc_chain_dly_int <= wrdata_reg(16);
              fmc516_ch1_ctl_dec_chain_dly_int <= wrdata_reg(17);
              fmc516_ch1_ctl_reserved_int <= wrdata_reg(31 downto 18);
            end if;
            rddata_reg(4 downto 0) <= regs_i.ch1_ctl_clk_chain_dly_i;
            rddata_reg(7 downto 5) <= regs_i.ch1_ctl_reserved_clk_chain_dly_i;
            rddata_reg(12 downto 8) <= regs_i.ch1_ctl_data_chain_dly_i;
            rddata_reg(15 downto 13) <= regs_i.ch1_ctl_reserved_data_chain_dly_i;
            rddata_reg(16) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(31 downto 18) <= fmc516_ch1_ctl_reserved_int;
            ack_sreg(2) <= '1';
            ack_in_progress <= '1';
          when "1001" => 
            if (wb_we_i = '1') then
            end if;
            if (wb_we_i = '0') then
              fmc516_ch2_sta_val_lwb <= '1';
              fmc516_ch2_sta_val_lwb_delay <= '1';
              fmc516_ch2_sta_val_lwb_in_progress <= '1';
            end if;
            rddata_reg(31 downto 16) <= regs_i.ch2_sta_reserved_i;
            ack_sreg(5) <= '1';
            ack_in_progress <= '1';
          when "1010" => 
            if (wb_we_i = '1') then
              regs_o.ch2_ctl_clk_chain_dly_load_o <= '1';
              regs_o.ch2_ctl_data_chain_dly_load_o <= '1';
              fmc516_ch2_ctl_inc_chain_dly_int <= wrdata_reg(16);
              fmc516_ch2_ctl_dec_chain_dly_int <= wrdata_reg(17);
              fmc516_ch2_ctl_reserved_int <= wrdata_reg(31 downto 18);
            end if;
            rddata_reg(4 downto 0) <= regs_i.ch2_ctl_clk_chain_dly_i;
            rddata_reg(7 downto 5) <= regs_i.ch2_ctl_reserved_clk_chain_dly_i;
            rddata_reg(12 downto 8) <= regs_i.ch2_ctl_data_chain_dly_i;
            rddata_reg(15 downto 13) <= regs_i.ch2_ctl_reserved_data_chain_dly_i;
            rddata_reg(16) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(31 downto 18) <= fmc516_ch2_ctl_reserved_int;
            ack_sreg(2) <= '1';
            ack_in_progress <= '1';
          when "1011" => 
            if (wb_we_i = '1') then
            end if;
            if (wb_we_i = '0') then
              fmc516_ch3_sta_val_lwb <= '1';
              fmc516_ch3_sta_val_lwb_delay <= '1';
              fmc516_ch3_sta_val_lwb_in_progress <= '1';
            end if;
            rddata_reg(31 downto 16) <= regs_i.ch3_sta_reserved_i;
            ack_sreg(5) <= '1';
            ack_in_progress <= '1';
          when "1100" => 
            if (wb_we_i = '1') then
              regs_o.ch3_ctl_clk_chain_dly_load_o <= '1';
              regs_o.ch3_ctl_data_chain_dly_load_o <= '1';
              fmc516_ch3_ctl_inc_chain_dly_int <= wrdata_reg(16);
              fmc516_ch3_ctl_dec_chain_dly_int <= wrdata_reg(17);
              fmc516_ch3_ctl_reserved_int <= wrdata_reg(31 downto 18);
            end if;
            rddata_reg(4 downto 0) <= regs_i.ch3_ctl_clk_chain_dly_i;
            rddata_reg(7 downto 5) <= regs_i.ch3_ctl_reserved_clk_chain_dly_i;
            rddata_reg(12 downto 8) <= regs_i.ch3_ctl_data_chain_dly_i;
            rddata_reg(15 downto 13) <= regs_i.ch3_ctl_reserved_data_chain_dly_i;
            rddata_reg(16) <= 'X';
            rddata_reg(17) <= 'X';
            rddata_reg(31 downto 18) <= fmc516_ch3_ctl_reserved_int;
            ack_sreg(2) <= '1';
            ack_in_progress <= '1';
          when others =>
-- prevent the slave from hanging the bus on invalid address
            ack_in_progress <= '1';
            ack_sreg(0) <= '1';
          end case;
        end if;
      end if;
    end if;
  end process;
  
  
-- Drive the data output bus
  wb_dat_o <= rddata_reg;
-- LMK (Clock Distribution CI) locked status
-- MMCM locked status
-- FMC power good status
-- FMC board present status
-- Reserved
-- Enable test data
  regs_o.fmc_ctl_test_data_en_o <= fmc516_fmc_ctl_test_data_en_int;
-- Manual LED 0
  regs_o.fmc_ctl_led_0_o <= fmc516_fmc_ctl_led_0_int;
-- Manual LED 1
  regs_o.fmc_ctl_led_1_o <= fmc516_fmc_ctl_led_1_int;
-- Internal/External clock distribution selection
  regs_o.fmc_ctl_clk_sel_o <= fmc516_fmc_ctl_clk_sel_int;
-- VCXO Ouput enable selection
  regs_o.fmc_ctl_vcxo_out_en_o <= fmc516_fmc_ctl_vcxo_out_en_int;
-- Reserved
  regs_o.fmc_ctl_reserved_o <= fmc516_fmc_ctl_reserved_int;
-- Hardware trigger polarity
-- synchronizer chain for field : Hardware trigger polarity (type RW/RO, clk_sys_i <-> fs_clk_i)
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      regs_o.trig_cfg_hw_trig_pol_o <= '0';
      fmc516_trig_cfg_hw_trig_pol_sync0 <= '0';
      fmc516_trig_cfg_hw_trig_pol_sync1 <= '0';
    elsif rising_edge(fs_clk_i) then
      fmc516_trig_cfg_hw_trig_pol_sync0 <= fmc516_trig_cfg_hw_trig_pol_int;
      fmc516_trig_cfg_hw_trig_pol_sync1 <= fmc516_trig_cfg_hw_trig_pol_sync0;
      regs_o.trig_cfg_hw_trig_pol_o <= fmc516_trig_cfg_hw_trig_pol_sync1;
    end if;
  end process;
  
  
-- Hardware trigger enable
-- synchronizer chain for field : Hardware trigger enable (type RW/RO, clk_sys_i <-> fs_clk_i)
  process (fs_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      regs_o.trig_cfg_hw_trig_en_o <= '0';
      fmc516_trig_cfg_hw_trig_en_sync0 <= '0';
      fmc516_trig_cfg_hw_trig_en_sync1 <= '0';
    elsif rising_edge(fs_clk_i) then
      fmc516_trig_cfg_hw_trig_en_sync0 <= fmc516_trig_cfg_hw_trig_en_int;
      fmc516_trig_cfg_hw_trig_en_sync1 <= fmc516_trig_cfg_hw_trig_en_sync0;
      regs_o.trig_cfg_hw_trig_en_o <= fmc516_trig_cfg_hw_trig_en_sync1;
    end if;
  end process;
  
  
-- Reserved
  regs_o.trig_cfg_reserved_o <= fmc516_trig_cfg_reserved_int;
-- FMC ADC clock chains
-- Reserved
-- FMC ADC Data chains
-- Reserved
-- FMC ADC packet size
-- Reset/Update ADC clock/data chains delay
  process (clk_sys_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      fmc516_adc_ctl_update_dly_dly0 <= '0';
      regs_o.adc_ctl_update_dly_o <= '0';
    elsif rising_edge(clk_sys_i) then
      fmc516_adc_ctl_update_dly_dly0 <= fmc516_adc_ctl_update_dly_int;
      regs_o.adc_ctl_update_dly_o <= fmc516_adc_ctl_update_dly_int and (not fmc516_adc_ctl_update_dly_dly0);
    end if;
  end process;
  
  
-- Reset ADCs
  process (clk_sys_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      fmc516_adc_ctl_rst_adcs_dly0 <= '0';
      regs_o.adc_ctl_rst_adcs_o <= '0';
    elsif rising_edge(clk_sys_i) then
      fmc516_adc_ctl_rst_adcs_dly0 <= fmc516_adc_ctl_rst_adcs_int;
      regs_o.adc_ctl_rst_adcs_o <= fmc516_adc_ctl_rst_adcs_int and (not fmc516_adc_ctl_rst_adcs_dly0);
    end if;
  end process;
  
  
-- Reset Div ADCs
  process (clk_sys_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      fmc516_adc_ctl_rst_div_adcs_dly0 <= '0';
      regs_o.adc_ctl_rst_div_adcs_o <= '0';
    elsif rising_edge(clk_sys_i) then
      fmc516_adc_ctl_rst_div_adcs_dly0 <= fmc516_adc_ctl_rst_div_adcs_int;
      regs_o.adc_ctl_rst_div_adcs_o <= fmc516_adc_ctl_rst_div_adcs_int and (not fmc516_adc_ctl_rst_div_adcs_dly0);
    end if;
  end process;
  
  
-- Reserved
-- Channel 0 current ADC value
-- asynchronous std_logic_vector register : Channel 0 current ADC value (type RO/WO, wb_clk_i <-> clk_sys_i)
  process (wb_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      fmc516_ch0_sta_val_lwb_s0 <= '0';
      fmc516_ch0_sta_val_lwb_s1 <= '0';
      fmc516_ch0_sta_val_lwb_s2 <= '0';
      fmc516_ch0_sta_val_int <= "0000000000000000";
    elsif rising_edge(wb_clk_i) then
      fmc516_ch0_sta_val_lwb_s0 <= fmc516_ch0_sta_val_lwb;
      fmc516_ch0_sta_val_lwb_s1 <= fmc516_ch0_sta_val_lwb_s0;
      fmc516_ch0_sta_val_lwb_s2 <= fmc516_ch0_sta_val_lwb_s1;
      if ((fmc516_ch0_sta_val_lwb_s1 = '1') and (fmc516_ch0_sta_val_lwb_s2 = '0')) then
        fmc516_ch0_sta_val_int <= regs_i.ch0_sta_val_i;
      end if;
    end if;
  end process;
  
  
-- Reserved
-- ADC clock chain delay
  regs_o.ch0_ctl_clk_chain_dly_o <= wrdata_reg(4 downto 0);
-- Reserved
-- ADC data chain delay
  regs_o.ch0_ctl_data_chain_dly_o <= wrdata_reg(12 downto 8);
-- Reserved
-- Increment ADC clock chains delay
  process (clk_sys_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      fmc516_ch0_ctl_inc_chain_dly_dly0 <= '0';
      regs_o.ch0_ctl_inc_chain_dly_o <= '0';
    elsif rising_edge(clk_sys_i) then
      fmc516_ch0_ctl_inc_chain_dly_dly0 <= fmc516_ch0_ctl_inc_chain_dly_int;
      regs_o.ch0_ctl_inc_chain_dly_o <= fmc516_ch0_ctl_inc_chain_dly_int and (not fmc516_ch0_ctl_inc_chain_dly_dly0);
    end if;
  end process;
  
  
-- Decrement ADC clock chains delay
  process (clk_sys_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      fmc516_ch0_ctl_dec_chain_dly_dly0 <= '0';
      regs_o.ch0_ctl_dec_chain_dly_o <= '0';
    elsif rising_edge(clk_sys_i) then
      fmc516_ch0_ctl_dec_chain_dly_dly0 <= fmc516_ch0_ctl_dec_chain_dly_int;
      regs_o.ch0_ctl_dec_chain_dly_o <= fmc516_ch0_ctl_dec_chain_dly_int and (not fmc516_ch0_ctl_dec_chain_dly_dly0);
    end if;
  end process;
  
  
-- Reserved
  regs_o.ch0_ctl_reserved_o <= fmc516_ch0_ctl_reserved_int;
-- Channel 1 current ADC value
-- asynchronous std_logic_vector register : Channel 1 current ADC value (type RO/WO, wb_clk_i <-> clk_sys_i)
  process (wb_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      fmc516_ch1_sta_val_lwb_s0 <= '0';
      fmc516_ch1_sta_val_lwb_s1 <= '0';
      fmc516_ch1_sta_val_lwb_s2 <= '0';
      fmc516_ch1_sta_val_int <= "0000000000000000";
    elsif rising_edge(wb_clk_i) then
      fmc516_ch1_sta_val_lwb_s0 <= fmc516_ch1_sta_val_lwb;
      fmc516_ch1_sta_val_lwb_s1 <= fmc516_ch1_sta_val_lwb_s0;
      fmc516_ch1_sta_val_lwb_s2 <= fmc516_ch1_sta_val_lwb_s1;
      if ((fmc516_ch1_sta_val_lwb_s1 = '1') and (fmc516_ch1_sta_val_lwb_s2 = '0')) then
        fmc516_ch1_sta_val_int <= regs_i.ch1_sta_val_i;
      end if;
    end if;
  end process;
  
  
-- Reserved
-- ADC clock chain delay
  regs_o.ch1_ctl_clk_chain_dly_o <= wrdata_reg(4 downto 0);
-- Reserved
-- ADC data chain delay
  regs_o.ch1_ctl_data_chain_dly_o <= wrdata_reg(12 downto 8);
-- Reserved
-- Increment ADC clock chains delay
  process (clk_sys_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      fmc516_ch1_ctl_inc_chain_dly_dly0 <= '0';
      regs_o.ch1_ctl_inc_chain_dly_o <= '0';
    elsif rising_edge(clk_sys_i) then
      fmc516_ch1_ctl_inc_chain_dly_dly0 <= fmc516_ch1_ctl_inc_chain_dly_int;
      regs_o.ch1_ctl_inc_chain_dly_o <= fmc516_ch1_ctl_inc_chain_dly_int and (not fmc516_ch1_ctl_inc_chain_dly_dly0);
    end if;
  end process;
  
  
-- Decrement ADC clock chains delay
  process (clk_sys_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      fmc516_ch1_ctl_dec_chain_dly_dly0 <= '0';
      regs_o.ch1_ctl_dec_chain_dly_o <= '0';
    elsif rising_edge(clk_sys_i) then
      fmc516_ch1_ctl_dec_chain_dly_dly0 <= fmc516_ch1_ctl_dec_chain_dly_int;
      regs_o.ch1_ctl_dec_chain_dly_o <= fmc516_ch1_ctl_dec_chain_dly_int and (not fmc516_ch1_ctl_dec_chain_dly_dly0);
    end if;
  end process;
  
  
-- Reserved
  regs_o.ch1_ctl_reserved_o <= fmc516_ch1_ctl_reserved_int;
-- Channel 2 current ADC value
-- asynchronous std_logic_vector register : Channel 2 current ADC value (type RO/WO, wb_clk_i <-> clk_sys_i)
  process (wb_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      fmc516_ch2_sta_val_lwb_s0 <= '0';
      fmc516_ch2_sta_val_lwb_s1 <= '0';
      fmc516_ch2_sta_val_lwb_s2 <= '0';
      fmc516_ch2_sta_val_int <= "0000000000000000";
    elsif rising_edge(wb_clk_i) then
      fmc516_ch2_sta_val_lwb_s0 <= fmc516_ch2_sta_val_lwb;
      fmc516_ch2_sta_val_lwb_s1 <= fmc516_ch2_sta_val_lwb_s0;
      fmc516_ch2_sta_val_lwb_s2 <= fmc516_ch2_sta_val_lwb_s1;
      if ((fmc516_ch2_sta_val_lwb_s1 = '1') and (fmc516_ch2_sta_val_lwb_s2 = '0')) then
        fmc516_ch2_sta_val_int <= regs_i.ch2_sta_val_i;
      end if;
    end if;
  end process;
  
  
-- Reserved
-- ADC clock chain delay
  regs_o.ch2_ctl_clk_chain_dly_o <= wrdata_reg(4 downto 0);
-- Reserved
-- ADC data chain delay
  regs_o.ch2_ctl_data_chain_dly_o <= wrdata_reg(12 downto 8);
-- Reserved
-- Increment ADC clock chains delay
  process (clk_sys_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      fmc516_ch2_ctl_inc_chain_dly_dly0 <= '0';
      regs_o.ch2_ctl_inc_chain_dly_o <= '0';
    elsif rising_edge(clk_sys_i) then
      fmc516_ch2_ctl_inc_chain_dly_dly0 <= fmc516_ch2_ctl_inc_chain_dly_int;
      regs_o.ch2_ctl_inc_chain_dly_o <= fmc516_ch2_ctl_inc_chain_dly_int and (not fmc516_ch2_ctl_inc_chain_dly_dly0);
    end if;
  end process;
  
  
-- Decrement ADC clock chains delay
  process (clk_sys_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      fmc516_ch2_ctl_dec_chain_dly_dly0 <= '0';
      regs_o.ch2_ctl_dec_chain_dly_o <= '0';
    elsif rising_edge(clk_sys_i) then
      fmc516_ch2_ctl_dec_chain_dly_dly0 <= fmc516_ch2_ctl_dec_chain_dly_int;
      regs_o.ch2_ctl_dec_chain_dly_o <= fmc516_ch2_ctl_dec_chain_dly_int and (not fmc516_ch2_ctl_dec_chain_dly_dly0);
    end if;
  end process;
  
  
-- Reserved
  regs_o.ch2_ctl_reserved_o <= fmc516_ch2_ctl_reserved_int;
-- Channel 3 current ADC value
-- asynchronous std_logic_vector register : Channel 3 current ADC value (type RO/WO, wb_clk_i <-> clk_sys_i)
  process (wb_clk_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      fmc516_ch3_sta_val_lwb_s0 <= '0';
      fmc516_ch3_sta_val_lwb_s1 <= '0';
      fmc516_ch3_sta_val_lwb_s2 <= '0';
      fmc516_ch3_sta_val_int <= "0000000000000000";
    elsif rising_edge(wb_clk_i) then
      fmc516_ch3_sta_val_lwb_s0 <= fmc516_ch3_sta_val_lwb;
      fmc516_ch3_sta_val_lwb_s1 <= fmc516_ch3_sta_val_lwb_s0;
      fmc516_ch3_sta_val_lwb_s2 <= fmc516_ch3_sta_val_lwb_s1;
      if ((fmc516_ch3_sta_val_lwb_s1 = '1') and (fmc516_ch3_sta_val_lwb_s2 = '0')) then
        fmc516_ch3_sta_val_int <= regs_i.ch3_sta_val_i;
      end if;
    end if;
  end process;
  
  
-- Reserved
-- ADC clock chain delay
  regs_o.ch3_ctl_clk_chain_dly_o <= wrdata_reg(4 downto 0);
-- Reserved
-- ADC data chain delay
  regs_o.ch3_ctl_data_chain_dly_o <= wrdata_reg(12 downto 8);
-- Reserved
-- Increment ADC clock chains delay
  process (clk_sys_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      fmc516_ch3_ctl_inc_chain_dly_dly0 <= '0';
      regs_o.ch3_ctl_inc_chain_dly_o <= '0';
    elsif rising_edge(clk_sys_i) then
      fmc516_ch3_ctl_inc_chain_dly_dly0 <= fmc516_ch3_ctl_inc_chain_dly_int;
      regs_o.ch3_ctl_inc_chain_dly_o <= fmc516_ch3_ctl_inc_chain_dly_int and (not fmc516_ch3_ctl_inc_chain_dly_dly0);
    end if;
  end process;
  
  
-- Decrement ADC clock chains delay
  process (clk_sys_i, rst_n_i)
  begin
    if (rst_n_i = '0') then 
      fmc516_ch3_ctl_dec_chain_dly_dly0 <= '0';
      regs_o.ch3_ctl_dec_chain_dly_o <= '0';
    elsif rising_edge(clk_sys_i) then
      fmc516_ch3_ctl_dec_chain_dly_dly0 <= fmc516_ch3_ctl_dec_chain_dly_int;
      regs_o.ch3_ctl_dec_chain_dly_o <= fmc516_ch3_ctl_dec_chain_dly_int and (not fmc516_ch3_ctl_dec_chain_dly_dly0);
    end if;
  end process;
  
  
-- Reserved
  regs_o.ch3_ctl_reserved_o <= fmc516_ch3_ctl_reserved_int;
  rwaddr_reg <= wb_adr_i;
  wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
-- ACK signal generation. Just pass the LSB of ACK counter.
  wb_ack_o <= ack_sreg(0);
end syn;
