# wb_fmc516_regs

### FMC ADC 250MS/s core registers

Wishbone slave for FMC ADC 250MS/s core

### Contents:

1. Memory map summary
2. HDL symbol
3. Register description
3.1. Status register
3.2. Control register
3.3. Trigger configuration
3.4. Global ADC Status register
3.5. Global ADC Control register
3.6. Channel 0 status register
3.7. Channel 0 control register
3.8. Channel 1 status register
3.9. Channel 1 control register
3.10. Channel 2 status register
3.11. Channel 2 control register
3.12. Channel 3 status register
3.13. Channel 3 control register

### 1. Memory map summary

H/W Address | Type | Name | VHDL/Verilog prefix | C prefix
--- | --- | --- | --- | ---
0x0 | REG | Status register | fmc516_fmc_sta | FMC_STA
0x1 | REG | Control register | fmc516_fmc_ctl | FMC_CTL
0x2 | REG | Trigger configuration | fmc516_trig_cfg | TRIG_CFG
0x3 | REG | Global ADC Status register | fmc516_adc_sta | ADC_STA
0x4 | REG | Global ADC Control register | fmc516_adc_ctl | ADC_CTL
0x5 | REG | Channel 0 status register | fmc516_ch0_sta | CH0_STA
0x6 | REG | Channel 0 control register | fmc516_ch0_ctl | CH0_CTL
0x7 | REG | Channel 1 status register | fmc516_ch1_sta | CH1_STA
0x8 | REG | Channel 1 control register | fmc516_ch1_ctl | CH1_CTL
0x9 | REG | Channel 2 status register | fmc516_ch2_sta | CH2_STA
0xa | REG | Channel 2 control register | fmc516_ch2_ctl | CH2_CTL
0xb | REG | Channel 3 status register | fmc516_ch3_sta | CH3_STA
0xc | REG | Channel 3 control register | fmc516_ch3_ctl | CH3_CTL

### 2. HDL symbol

→ | rst_n_i |  | Status register: |
→ | clk_sys_i |  | fmc516_fmc_sta_lmk_locked_i | ←
⇒ | wb_adr_i[3:0] |  | fmc516_fmc_sta_mmcm_locked_i | ←
⇒ | wb_dat_i[31:0] |  | fmc516_fmc_sta_pwr_good_i | ←
⇐ | wb_dat_o[31:0] |  | fmc516_fmc_sta_prst_i | ←
→ | wb_cyc_i |  | fmc516_fmc_sta_reserved_i[27:0] | ⇐
⇒ | wb_sel_i[3:0] |  |  |
→ | wb_stb_i |  | Control register: |
→ | wb_we_i |  | fmc516_fmc_ctl_test_data_en_o | →
← | wb_ack_o |  | fmc516_fmc_ctl_led_0_o | →
← | wb_stall_o |  | fmc516_fmc_ctl_led_1_o | →
|  |  | fmc516_fmc_ctl_clk_sel_o | →
|  |  | fmc516_fmc_ctl_vcxo_out_en_o | →
|  |  | fmc516_fmc_ctl_reserved_o[26:0] | ⇒
|  |  | Trigger configuration: |
|  |  | fmc516_trig_cfg_hw_trig_pol_o | →
|  |  | fmc516_trig_cfg_hw_trig_en_o | →
|  |  | fmc516_trig_cfg_reserved_o[29:0] | ⇒
|  |  | Global ADC Status register: |
|  |  | fmc516_adc_sta_clk_chains_i[3:0] | ⇐
|  |  | fmc516_adc_sta_reserved_clk_chains_i[3:0] | ⇐
|  |  | fmc516_adc_sta_data_chains_i[3:0] | ⇐
|  |  | fmc516_adc_sta_reserved_data_chains_i[3:0] | ⇐
|  |  | fmc516_adc_sta_adc_pkt_size_i[15:0] | ⇐
|  |  | Global ADC Control register: |
|  |  | fmc516_adc_ctl_update_dly_o | →
|  |  | fmc516_adc_ctl_rst_adcs_o | →
|  |  | fmc516_adc_ctl_rst_div_adcs_o | →
|  |  | fmc516_adc_ctl_reserved_i[28:0] | ⇐
|  |  | Channel 0 status register: |
|  |  | fmc516_ch0_sta_val_i[15:0] | ⇐
|  |  | fmc516_ch0_sta_reserved_i[15:0] | ⇐
|  |  | Channel 0 control register: |
|  |  | fmc516_ch0_ctl_clk_chain_dly_o[4:0] | ⇒
|  |  | fmc516_ch0_ctl_clk_chain_dly_i[4:0] | ⇐
|  |  | fmc516_ch0_ctl_clk_chain_dly_load_o | →
|  |  | fmc516_ch0_ctl_reserved_clk_chain_dly_i[2:0] | ⇐
|  |  | fmc516_ch0_ctl_data_chain_dly_o[4:0] | ⇒
|  |  | fmc516_ch0_ctl_data_chain_dly_i[4:0] | ⇐
|  |  | fmc516_ch0_ctl_data_chain_dly_load_o | →
|  |  | fmc516_ch0_ctl_reserved_data_chain_dly_i[2:0] | ⇐
|  |  | fmc516_ch0_ctl_inc_chain_dly_o | →
|  |  | fmc516_ch0_ctl_dec_chain_dly_o | →
|  |  | fmc516_ch0_ctl_reserved_o[13:0] | ⇒
|  |  | Channel 1 status register: |
|  |  | fmc516_ch1_sta_val_i[15:0] | ⇐
|  |  | fmc516_ch1_sta_reserved_i[15:0] | ⇐
|  |  | Channel 1 control register: |
|  |  | fmc516_ch1_ctl_clk_chain_dly_o[4:0] | ⇒
|  |  | fmc516_ch1_ctl_clk_chain_dly_i[4:0] | ⇐
|  |  | fmc516_ch1_ctl_clk_chain_dly_load_o | →
|  |  | fmc516_ch1_ctl_reserved_clk_chain_dly_i[2:0] | ⇐
|  |  | fmc516_ch1_ctl_data_chain_dly_o[4:0] | ⇒
|  |  | fmc516_ch1_ctl_data_chain_dly_i[4:0] | ⇐
|  |  | fmc516_ch1_ctl_data_chain_dly_load_o | →
|  |  | fmc516_ch1_ctl_reserved_data_chain_dly_i[2:0] | ⇐
|  |  | fmc516_ch1_ctl_inc_chain_dly_o | →
|  |  | fmc516_ch1_ctl_dec_chain_dly_o | →
|  |  | fmc516_ch1_ctl_reserved_o[13:0] | ⇒
|  |  | Channel 2 status register: |
|  |  | fmc516_ch2_sta_val_i[15:0] | ⇐
|  |  | fmc516_ch2_sta_reserved_i[15:0] | ⇐
|  |  | Channel 2 control register: |
|  |  | fmc516_ch2_ctl_clk_chain_dly_o[4:0] | ⇒
|  |  | fmc516_ch2_ctl_clk_chain_dly_i[4:0] | ⇐
|  |  | fmc516_ch2_ctl_clk_chain_dly_load_o | →
|  |  | fmc516_ch2_ctl_reserved_clk_chain_dly_i[2:0] | ⇐
|  |  | fmc516_ch2_ctl_data_chain_dly_o[4:0] | ⇒
|  |  | fmc516_ch2_ctl_data_chain_dly_i[4:0] | ⇐
|  |  | fmc516_ch2_ctl_data_chain_dly_load_o | →
|  |  | fmc516_ch2_ctl_reserved_data_chain_dly_i[2:0] | ⇐
|  |  | fmc516_ch2_ctl_inc_chain_dly_o | →
|  |  | fmc516_ch2_ctl_dec_chain_dly_o | →
|  |  | fmc516_ch2_ctl_reserved_o[13:0] | ⇒
|  |  | Channel 3 status register: |
|  |  | fmc516_ch3_sta_val_i[15:0] | ⇐
|  |  | fmc516_ch3_sta_reserved_i[15:0] | ⇐
|  |  | Channel 3 control register: |
|  |  | fmc516_ch3_ctl_clk_chain_dly_o[4:0] | ⇒
|  |  | fmc516_ch3_ctl_clk_chain_dly_i[4:0] | ⇐
|  |  | fmc516_ch3_ctl_clk_chain_dly_load_o | →
|  |  | fmc516_ch3_ctl_reserved_clk_chain_dly_i[2:0] | ⇐
|  |  | fmc516_ch3_ctl_data_chain_dly_o[4:0] | ⇒
|  |  | fmc516_ch3_ctl_data_chain_dly_i[4:0] | ⇐
|  |  | fmc516_ch3_ctl_data_chain_dly_load_o | →
|  |  | fmc516_ch3_ctl_reserved_data_chain_dly_i[2:0] | ⇐
|  |  | fmc516_ch3_ctl_inc_chain_dly_o | →
|  |  | fmc516_ch3_ctl_dec_chain_dly_o | →
|  |  | fmc516_ch3_ctl_reserved_o[13:0] | ⇒

### 3. Register description

### 3.1. Status register

HW prefix: | fmc516_fmc_sta
HW address: | 0x0
C prefix: | FMC_STA
C offset: | 0x0

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
RESERVED[27:20] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
RESERVED[19:12] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
RESERVED[11:4] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
RESERVED[3:0] | PRST | PWR_GOOD | MMCM_LOCKED | LMK_LOCKED |  |  |

- LMK_LOCKED [read-only]: LMK (Clock Distribution CI) locked status
  LMK locked status.
  read 0: not locked
  read 1: locked
- MMCM_LOCKED [read-only]: MMCM locked status
  ADC Clock Chain MMCM locked status.
  read 0: not locked
  read 1: locked
- PWR_GOOD [read-only]: FMC power good status
  FMC power good status.
  read 0: power not good
  read 1: power good
- PRST [read-only]: FMC board present status
  FMC board present status.
  0: not present
  1: present
- RESERVED [read-only]: Reserved
  Ignore on write, read as 0's

### 3.2. Control register

HW prefix: | fmc516_fmc_ctl
HW address: | 0x1
C prefix: | FMC_CTL
C offset: | 0x4

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
RESERVED[26:19] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
RESERVED[18:11] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
RESERVED[10:3] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
RESERVED[2:0] | VCXO_OUT_EN | CLK_SEL | LED_1 | LED_0 | TEST_DATA_EN |  |

- TEST_DATA_EN [read/write]: Enable test data
  Write the address counter value instead of ADC data to Wishbone Streaming Interface
- LED_0 [read/write]: Manual LED 0
  Manual control of the front panel LED 0
- LED_1 [read/write]: Manual LED 1
  Manual control of the front panel LED 1
- CLK_SEL [read/write]: Internal/External clock distribution selection
  Select between internal VCXO or external reference clock
  write 0: internal reference
  write 1: external reference
- VCXO_OUT_EN [read/write]: VCXO Ouput enable selection
  Enable VCXO output
  write 0: disable VCXO output
  write 1: enable VCXO output
- RESERVED [read/write]: Reserved
  Ignore on write, read as 0's

### 3.3. Trigger configuration

HW prefix: | fmc516_trig_cfg
HW address: | 0x2
C prefix: | TRIG_CFG
C offset: | 0x8

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
RESERVED[29:22] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
RESERVED[21:14] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
RESERVED[13:6] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
RESERVED[5:0] | HW_TRIG_EN | HW_TRIG_POL |  |  |  |  |

- HW_TRIG_POL [read/write]: Hardware trigger polarity
  write 0: positive edge/slope
  write 1: negative edge/slope
- HW_TRIG_EN [read/write]: Hardware trigger enable
  write 0: disable
  write 1: enable
- RESERVED [read/write]: Reserved
  Ignore on write, read as 0's

### 3.4. Global ADC Status register

HW prefix: | fmc516_adc_sta
HW address: | 0x3
C prefix: | ADC_STA
C offset: | 0xc

Global ADC status register.

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
ADC_PKT_SIZE[15:8] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
ADC_PKT_SIZE[7:0] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
RESERVED_DATA_CHAINS[3:0] | DATA_CHAINS[3:0] |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
RESERVED_CLK_CHAINS[3:0] | CLK_CHAINS[3:0] |  |  |  |  |  |

- CLK_CHAINS [read-only]: FMC ADC clock chains
  FMC ADC used clock chains.
  read 1: clock chain is used
  read 0: clock chain is not used
- RESERVED_CLK_CHAINS [read-only]: Reserved
  Ignore on write, read as 0's
- DATA_CHAINS [read-only]: FMC ADC Data chains
  FMC ADC used clock chains.
  read 1: data chain is used
  read 0: data chain is not used
- RESERVED_DATA_CHAINS [read-only]: Reserved
  Ignore on write, read as 0's
- ADC_PKT_SIZE [read-only]: FMC ADC packet size
  Size of the packet sent to the Wishbone Streaming Interface.
  This will appear as cycles of <packet_size> clock cycles on
  the wishbone interface

### 3.5. Global ADC Control register

HW prefix: | fmc516_adc_ctl
HW address: | 0x4
C prefix: | ADC_CTL
C offset: | 0x10

Global ADC control register.

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
RESERVED[28:21] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
RESERVED[20:13] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
RESERVED[12:5] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
RESERVED[4:0] | RST_DIV_ADCS | RST_ADCS | UPDATE_DLY |  |  |  |

- UPDATE_DLY [read/write]: Reset/Update ADC clock/data chains delay
  write 1: reset/update clock/data chains to its default
  values or from the values in the delay registers.
  write 0: no effect
- RST_ADCS [read/write]: Reset ADCs
  Reset and recalibrate ADCs
  write 0: no reset
  write 1: enable ADC reset
- RST_DIV_ADCS [read/write]: Reset Div ADCs
  Reset for synchronization between multiple ADCs
  write 0: no reset
  write 1: enable ADC div reset
- RESERVED [read-only]: Reserved
  Ignore on write, read as 0's

### 3.6. Channel 0 status register

HW prefix: | fmc516_ch0_sta
HW address: | 0x5
C prefix: | CH0_STA
C offset: | 0x14

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
RESERVED[15:8] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
RESERVED[7:0] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
VAL[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
VAL[7:0] |  |  |  |  |  |  |

- VAL [read-only]: Channel 0 current ADC value
  Current ADC raw value. The format is binary two's complement.
- RESERVED [read-only]: Reserved
  Ignore on write, read as 0's

### 3.7. Channel 0 control register

HW prefix: | fmc516_ch0_ctl
HW address: | 0x6
C prefix: | CH0_CTL
C offset: | 0x18

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
RESERVED[13:6] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
RESERVED[5:0] | DEC_CHAIN_DLY | INC_CHAIN_DLY |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
RESERVED_DATA_CHAIN_DLY[2:0] | DATA_CHAIN_DLY[4:0] |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
RESERVED_CLK_CHAIN_DLY[2:0] | CLK_CHAIN_DLY[4:0] |  |  |  |  |  |

- CLK_CHAIN_DLY [read/write]: ADC clock chain delay
  ADC clock chain delay
- RESERVED_CLK_CHAIN_DLY [read-only]: Reserved
  Ignore on write, read as 0's
- DATA_CHAIN_DLY [read/write]: ADC data chain delay
  ADC data chain delay
- RESERVED_DATA_CHAIN_DLY [read-only]: Reserved
  Ignore on write, read as 0's
- INC_CHAIN_DLY [read/write]: Increment ADC clock chains delay
  write 1: increment clock chains delay.
  write 0: no effect
- DEC_CHAIN_DLY [read/write]: Decrement ADC clock chains delay
  write 1: decrement clock chains delay.
  write 0: no effect
- RESERVED [read/write]: Reserved
  Ignore on write, read as 0's

### 3.8. Channel 1 status register

HW prefix: | fmc516_ch1_sta
HW address: | 0x7
C prefix: | CH1_STA
C offset: | 0x1c

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
RESERVED[15:8] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
RESERVED[7:0] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
VAL[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
VAL[7:0] |  |  |  |  |  |  |

- VAL [read-only]: Channel 1 current ADC value
  Current ADC raw value. The format is binary two's complement.
- RESERVED [read-only]: Reserved
  Ignore on write, read as 0's

### 3.9. Channel 1 control register

HW prefix: | fmc516_ch1_ctl
HW address: | 0x8
C prefix: | CH1_CTL
C offset: | 0x20

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
RESERVED[13:6] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
RESERVED[5:0] | DEC_CHAIN_DLY | INC_CHAIN_DLY |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
RESERVED_DATA_CHAIN_DLY[2:0] | DATA_CHAIN_DLY[4:0] |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
RESERVED_CLK_CHAIN_DLY[2:0] | CLK_CHAIN_DLY[4:0] |  |  |  |  |  |

- CLK_CHAIN_DLY [read/write]: ADC clock chain delay
  ADC clock chain delay
- RESERVED_CLK_CHAIN_DLY [read-only]: Reserved
  Ignore on write, read as 0's
- DATA_CHAIN_DLY [read/write]: ADC data chain delay
  ADC data chain delay
- RESERVED_DATA_CHAIN_DLY [read-only]: Reserved
  Ignore on write, read as 0's
- INC_CHAIN_DLY [read/write]: Increment ADC clock chains delay
  write 1: increment clock chains delay.
  write 0: no effect
- DEC_CHAIN_DLY [read/write]: Decrement ADC clock chains delay
  write 1: decrement clock chains delay.
  write 0: no effect
- RESERVED [read/write]: Reserved
  Ignore on write, read as 0's

### 3.10. Channel 2 status register

HW prefix: | fmc516_ch2_sta
HW address: | 0x9
C prefix: | CH2_STA
C offset: | 0x24

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
RESERVED[15:8] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
RESERVED[7:0] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
VAL[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
VAL[7:0] |  |  |  |  |  |  |

- VAL [read-only]: Channel 2 current ADC value
  Current ADC raw value. The format is binary two's complement.
- RESERVED [read-only]: Reserved
  Ignore on write, read as 0's

### 3.11. Channel 2 control register

HW prefix: | fmc516_ch2_ctl
HW address: | 0xa
C prefix: | CH2_CTL
C offset: | 0x28

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
RESERVED[13:6] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
RESERVED[5:0] | DEC_CHAIN_DLY | INC_CHAIN_DLY |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
RESERVED_DATA_CHAIN_DLY[2:0] | DATA_CHAIN_DLY[4:0] |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
RESERVED_CLK_CHAIN_DLY[2:0] | CLK_CHAIN_DLY[4:0] |  |  |  |  |  |

- CLK_CHAIN_DLY [read/write]: ADC clock chain delay
  ADC clock chain delay
- RESERVED_CLK_CHAIN_DLY [read-only]: Reserved
  Ignore on write, read as 0's
- DATA_CHAIN_DLY [read/write]: ADC data chain delay
  ADC data chain delay
- RESERVED_DATA_CHAIN_DLY [read-only]: Reserved
  Ignore on write, read as 0's
- INC_CHAIN_DLY [read/write]: Increment ADC clock chains delay
  write 1: increment clock chains delay.
  write 0: no effect
- DEC_CHAIN_DLY [read/write]: Decrement ADC clock chains delay
  write 1: decrement clock chains delay.
  write 0: no effect
- RESERVED [read/write]: Reserved
  Ignore on write, read as 0's

### 3.12. Channel 3 status register

HW prefix: | fmc516_ch3_sta
HW address: | 0xb
C prefix: | CH3_STA
C offset: | 0x2c

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
RESERVED[15:8] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
RESERVED[7:0] |  |  |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
VAL[15:8] |  |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
VAL[7:0] |  |  |  |  |  |  |

- VAL [read-only]: Channel 3 current ADC value
  Current ADC raw value. The format is binary two's complement.
- RESERVED [read-only]: Reserved
  Ignore on write, read as 0's

### 3.13. Channel 3 control register

HW prefix: | fmc516_ch3_ctl
HW address: | 0xc
C prefix: | CH3_CTL
C offset: | 0x30

31 | 30 | 29 | 28 | 27 | 26 | 25 | 24
RESERVED[13:6] |  |  |  |  |  |  |

23 | 22 | 21 | 20 | 19 | 18 | 17 | 16
RESERVED[5:0] | DEC_CHAIN_DLY | INC_CHAIN_DLY |  |  |  |  |

15 | 14 | 13 | 12 | 11 | 10 | 9 | 8
RESERVED_DATA_CHAIN_DLY[2:0] | DATA_CHAIN_DLY[4:0] |  |  |  |  |  |

7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
RESERVED_CLK_CHAIN_DLY[2:0] | CLK_CHAIN_DLY[4:0] |  |  |  |  |  |

- CLK_CHAIN_DLY [read/write]: ADC clock chain delay
  ADC clock chain delay
- RESERVED_CLK_CHAIN_DLY [read-only]: Reserved
  Ignore on write, read as 0's
- DATA_CHAIN_DLY [read/write]: ADC data chain delay
  ADC data chain delay
- RESERVED_DATA_CHAIN_DLY [read-only]: Reserved
  Ignore on write, read as 0's
- INC_CHAIN_DLY [read/write]: Increment ADC clock chains delay
  write 1: increment clock chains delay.
  write 0: no effect
- DEC_CHAIN_DLY [read/write]: Decrement ADC clock chains delay
  write 1: decrement clock chains delay.
  write 0: no effect
- RESERVED [read/write]: Reserved
  Ignore on write, read as 0's