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# Sirius Beam Position Monitor FPGA firmware
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## Project Folder Organization
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```
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*
|
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|-- hdl:
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|    |   HDL (Verilog/VHDL) cores related to the BPM.
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|    |
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|    |-- ip_cores:
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|    |    |   Third party reusable modules, primarily Open hardware
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|    |    |     modules (http://www.ohwr.org).
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|    |    |
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|    |    |-- etherbone-core:
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|    |    |       Connects two Wishbone buses, either a true hardware bus
|    |    |         or emulated software bus, through Ethernet.
|    |    |-- general-cores (fork from original project):
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|    |            General reusable modules.
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|    |
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|    |-- modules:
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|    |    |   Modules specific to BPM hardware.
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|    |    |
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|    |    |-- custom_common:
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|    |    |       Common (reusable) modules to BPM hardware and possibly
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|    |    |         to other designs.
|    |    |-- custom_wishbone:
|    |            Wishbone modules to BPM hardware.
|    |
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|    |-- platform:
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|    |        Platform-specific code, such as Xilinx Chipscope wrappers.
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|    |
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|    |-- sim:
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|    |        Generic simulation files, reusable Bus Functional Modules (BFMs),
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|    |          constants definitions.
|    |
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|    |-- syn:
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|    |        Synthesis specific files (user constraints files and top design
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|    |          specification).
|    |
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|    |-- testbench:
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|    |        Testbenches for modules and top level designs. May use modules
|    |          defined elsewhere (specific within the 'sim" directory).
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|    |
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|    |-- top:
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|             Top design modules.
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```
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## Cloning Instructions
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This repository makes use of git submodules, located at 'hdl/ip_cores' folder:
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  hdl/ip_cores/general-cores
  hdl/ip_cores/etherbone-core
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  hdl/ip_cores/dsp-cores
  hdl/ip_cores/infra-cores
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To clone the whole repository use the following command:

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    git clone --recursive git://github.com/lnls-dig/bpm-gw.git (read only)
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  or

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    git clone --recursive git@github.com:lnls-dig/bpm-gw.git (read+write)
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For older versions of Git (<1.6.5), use the following:
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    git clone git://github.com/lnls-dig/bpm-gw.git
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or
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    git clone git@github.com:lnls-dig/bpm-gw.git
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    git submodule init
    git submodule update
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To update each submodule within this project use:
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    git submodule foreach git rebase origin master
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## Simulation Instructions
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Go to a testbench directory. It must have a top manifest file:
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    cd hdl/testbench/path_to_testbench
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Run the following commands. You must have hdlmake command available
in your PATH environment variable.
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Create the simualation makefile
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    hdlmake
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Compile the project
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    make
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Execute the simulation with GUI and aditional commands
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    vsim -do run.do &
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## Synthesis Instructions
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Go to a syn directory. It must have a synthesis manifest file:
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    cd hdl/syn/path_to_syn_design
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Run the following commands. You must have hdlmake command available
in your PATH environment variable.
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    ./build_bitstream_local.sh
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## Known Issues
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wb_fmc150/sim/: This folder containts behavioral simulation models
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  for memories (ROMs). However, the xilinx initialization file (.mif)
  paths are absolute to a specific machine! You either have to change
  the path to match your machine or figure a way to specifies a relative
  path (specifiying only the name of the mif file does not work as the
  simulator is not called within this folder). Try a relative path based
  on the simulation folder.