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Beam Positoning Monitor - Gateware
Commit 083a57d9 authored by Lucas Russo's avatar Lucas Russo
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Merge branch 'devel'

parents 2bcc5263 a56170bd
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.gitmodules
View file @ 083a57d9
[submodule "hdl/ip_cores/general-cores"]
path = hdl/ip_cores/general-cores
url = git://github.com/lerwys/general-cores.git
url = https://github.com/lerwys/general-cores.git
[submodule "hdl/ip_cores/etherbone-core"]
path = hdl/ip_cores/etherbone-core
url = git://ohwr.org/hdl-core-lib/etherbone-core.git
......
hdl/Manifest.py
View file @ 083a57d9
......@@ -3,9 +3,10 @@
modules = { "local": [
"modules/dbe_wishbone",
"modules/dbe_common",
"modules/rffe_top",
# "modules/rffe_top",
"modules/fabric",
"modules/fmc_adc_common",
"modules/pcie",
"ip_cores/general-cores",
"ip_cores/etherbone-core",
"ip_cores/dsp-cores",
......
dsp-cores @ a4359eef
Subproject commit acfc59d620619a0e6ce3b333236d44e4096dbb25
Subproject commit a4359eefce5a3e152a13a9b2a660766026e849fa
etherbone-core @ b29565ac
Subproject commit 541e5b834123ad6a86325edf607c885069706f3f
Subproject commit b29565ac63ca92987cd9a9a754b6add857fc5351
general-cores @ 9596442d
Subproject commit 093d4d355065d81e16306fd3bf4463d6a7272695
Subproject commit 9596442d462afa1e89c05b2280f1e26f5507bdd2
hdl/modules/dbe_common/Manifest.py
View file @ 083a57d9
modules = { "local" : ["reset_synch"] };
modules = { "local" : ["reset_synch",
"pulse2level"] };
files = [ "dbe_common_pkg.vhd" ];
hdl/modules/dbe_common/dbe_common_pkg.vhd
View file @ 083a57d9
......@@ -3,17 +3,38 @@ use ieee.std_logic_1164.all;
package dbe_common_pkg is
--------------------------------------------------------------------
-- Components
--------------------------------------------------------------------
--------------------------------------------------------------------
-- Components
--------------------------------------------------------------------
component reset_synch
port
(
clk_i : in std_logic;
arst_n_i : in std_logic;
rst_n_o : out std_logic
);
end component;
component reset_synch
generic
(
-- Select 1 for no pipeline, and greater than 1 to insert
-- pipeline stages
g_pipeline : natural := 4
);
port
(
clk_i : in std_logic;
arst_n_i : in std_logic;
rst_n_o : out std_logic
);
end component;
component pulse2level
port
(
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Pulse input
pulse_i : in std_logic;
-- Clear level
clr_i : in std_logic;
-- Level output
level_o : out std_logic
);
end component;
end dbe_common_pkg;
hdl/modules/dbe_common/pulse2level/pulse2level.vhd 0 → 100755
View file @ 083a57d9
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity pulse2level is
port
(
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Pulse input
pulse_i : in std_logic;
-- Clear level
clr_i : in std_logic;
-- Level output
level_o : out std_logic
);
end pulse2level;
architecture rtl of pulse2level is
signal level : std_logic := '0';
begin
-- Convert from pulse to level signal
p_pulse_to_level : process (clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
level <= '0';
else
if clr_i = '1'then
level <= '0';
elsif pulse_i = '1' then
level <= '1';
end if;
end if;
end if;
end process;
level_o <= level;
end rtl;
hdl/modules/dbe_common/reset_synch/reset_synch.vhd
View file @ 083a57d9
......@@ -3,25 +3,54 @@ use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity reset_synch is
port
(
clk_i : in std_logic;
arst_n_i : in std_logic;
rst_n_o : out std_logic
);
generic
(
-- Select 1 for no pipeline, and greater than 1 to insert
-- pipeline stages
g_pipeline : natural := 4
);
port
(
clk_i : in std_logic;
arst_n_i : in std_logic;
rst_n_o : out std_logic
);
end reset_synch;
architecture rtl of reset_synch is
signal s_ff : std_logic;
signal s_ff : std_logic_vector(g_pipeline-1 downto 0) := (others => '0');
-- Try to reduce fanout of reset signal
attribute MAX_FANOUT : string;
attribute MAX_FANOUT of s_ff : signal is "REDUCE";
begin
process(clk_i, arst_n_i)
assert (g_pipeline >= 1)
report "[reset_synch] g_pipeline must be at least 1!"
severity failure;
p_rst_sync : process(clk_i, arst_n_i)
begin
if arst_n_i = '0' then
s_ff <= '0';
rst_n_o <= '0';
s_ff(0) <= '0';
elsif rising_edge(clk_i) then
s_ff <= '1';
rst_n_o <= s_ff;
s_ff(0) <= '1';
end if;
end process;
gen_pipe : if g_pipeline > 1 generate
-- Shift reg
p_rst_pipe : process (clk_i)
begin
if rising_edge(clk_i) then
for i in 0 to g_pipeline-2 loop
s_ff(i+1) <= s_ff(i);
end loop;
end if;
end process;
end generate;
rst_n_o <= s_ff(s_ff'left);
end rtl;
hdl/modules/dbe_wishbone/Manifest.py
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......@@ -8,5 +8,7 @@ modules = { "local" : [
"wb_ethmac_adapter",
"wb_ethmac",
"wb_dbe_periph",
"wb_rs232_syscon"
"wb_rs232_syscon",
"wb_acq_core",
"wb_pcie"
] };
hdl/modules/dbe_wishbone/wb_acq_core/Manifest.py 0 → 100644
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files = ["wb_acq_core.vhd",
"xwb_acq_core.vhd",
"wb_acq_core_plain.vhd",
"acq_fsm.vhd",
"acq_core_pkg.vhd",
"acq_multishot_dpram.vhd",
"acq_fc_fifo.vhd",
"acq_fwft_fifo.vhd",
"fc_source.vhd",
"acq_ddr3_iface.vhd",
"acq_ddr3_read.vhd",
"acq_cnt.vhd",
"acq_sel_chan.vhd",
"data_checker.vhd",
"wbgen/acq_core_regs_pkg.vhd",
"wbgen/acq_core_regs.vhd"
];
hdl/modules/dbe_wishbone/wb_acq_core/acq_cnt.vhd 0 → 100644
View file @ 083a57d9
------------------------------------------------------------------------------
-- Title : BPM Acquisition Counter
------------------------------------------------------------------------------
-- Author : Lucas Maziero Russo
-- Company : CNPEM LNLS-DIG
-- Created : 2013-06-11
-- Platform : FPGA-generic
-------------------------------------------------------------------------------
-- Description: Simple counter of transactions and shots
-------------------------------------------------------------------------------
-- Copyright (c) 2013 CNPEM
-- Licensed under GNU Lesser General Public License (LGPL) v3.0
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2013-06-11 1.0 lucas.russo Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- Main Wishbone Definitions
use work.wishbone_pkg.all;
-- Genrams cores
use work.genram_pkg.all;
-- Genrams cores
use work.gencores_pkg.all;
-- Acquisition cores
use work.acq_core_pkg.all;
entity acq_cnt is
port
(
-- DDR3 external clock
clk_i : in std_logic;
rst_n_i : in std_logic;
cnt_all_pkts_ct_done_p_o : out std_logic; -- all current transaction packets done
cnt_all_trans_done_p_o : out std_logic; -- all transactions done
cnt_en_i : in std_logic;
-- Size of the transaction in g_fifo_size bytes
lmt_pkt_size_i : in unsigned(c_pkt_size_width-1 downto 0);
-- Number of shots in this acquisition
lmt_shots_nb_i : in unsigned(c_shots_size_width-1 downto 0);
-- Acquisition limits valid signal. Qualifies lmt_pkt_size_i and lmt_shots_nb_i
lmt_valid_i : in std_logic;
dbg_pkt_ct_cnt_o : out std_logic_vector(c_pkt_size_width-1 downto 0);
dbg_shots_cnt_o : out std_logic_vector(c_shots_size_width-1 downto 0)
);
end acq_cnt;
architecture rtl of acq_cnt is
signal pkt_ct_cnt : unsigned(c_pkt_size_width-1 downto 0);
signal pkt_cnt_en : std_logic;
signal pkt_ct_cnt_all : std_logic;
signal shots_cnt : unsigned(c_shots_size_width-1 downto 0);
signal shots_cnt_all : std_logic;
--signal shots_cnt_all_p : std_logic;
signal lmt_pkt_size : unsigned(c_pkt_size_width-1 downto 0);
signal lmt_shots_nb : unsigned(c_shots_size_width-1 downto 0);
begin
-----------------------------------------------------------------------------
-- Register input
-----------------------------------------------------------------------------
p_in_reg : process (clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
--Avoid detection of *_done pulses by setting them to 1
lmt_pkt_size <= to_unsigned(1, lmt_pkt_size'length);
lmt_shots_nb <= to_unsigned(1, lmt_shots_nb'length);
else
if lmt_valid_i = '1' then
lmt_pkt_size <= lmt_pkt_size_i;
lmt_shots_nb <= lmt_shots_nb_i;
end if;
end if;
end if;
end process;
-----------------------------------------------------------------------------
-- Number of packets
-----------------------------------------------------------------------------
p_pkt_ct_cnt : process (clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
pkt_ct_cnt <= to_unsigned(0, pkt_ct_cnt'length);
else
if pkt_ct_cnt_all = '1' then -- counter wrap-around
if pkt_cnt_en = '1' then -- simultaneously wrap-around and increment by one
pkt_ct_cnt <= to_unsigned(1, pkt_ct_cnt'length);
else
pkt_ct_cnt <= to_unsigned(0, pkt_ct_cnt'length);
end if;
elsif pkt_cnt_en = '1' then
pkt_ct_cnt <= pkt_ct_cnt + 1;
end if;
end if;
end if;
end process;
pkt_cnt_en <= cnt_en_i;
-- Debug outputs
dbg_pkt_ct_cnt_o <= std_logic_vector(pkt_ct_cnt);
p_pkt_ct_cnt_reg : process (clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
pkt_ct_cnt_all <= '0';
else
if pkt_ct_cnt = lmt_pkt_size-1 and pkt_cnt_en = '1' then
pkt_ct_cnt_all <= '1';
else
pkt_ct_cnt_all <= '0';
end if;
end if;
end if;
end process;
cnt_all_pkts_ct_done_p_o <= pkt_ct_cnt_all; -- this is necessarilly a pulse
-----------------------------------------------------------------------------
-- Number of shots
-----------------------------------------------------------------------------
p_shots_cnt : process (clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
shots_cnt <= to_unsigned(0, shots_cnt'length);
else
if shots_cnt_all = '1' then
if pkt_ct_cnt_all = '1' then -- This case won't happen. Should we keep it?
shots_cnt <= to_unsigned(1, shots_cnt'length);
else
shots_cnt <= to_unsigned(0, shots_cnt'length);
end if;
elsif pkt_ct_cnt_all = '1' then
shots_cnt <= shots_cnt + 1;
end if;
end if;
end if;
end process;
-- Debug outputs
dbg_shots_cnt_o <= std_logic_vector(shots_cnt);
p_shots_cnt_reg : process (clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
shots_cnt_all <= '0';
else
if shots_cnt = lmt_shots_nb-1 and pkt_ct_cnt_all = '1' then
shots_cnt_all <= '1';
else
shots_cnt_all <= '0';
end if;
end if;
end if;
end process;
cnt_all_trans_done_p_o <= shots_cnt_all;
end rtl;
hdl/modules/dbe_wishbone/wb_acq_core/acq_core_pkg.vhd 0 → 100644
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hdl/modules/dbe_wishbone/wb_acq_core/acq_ddr3_iface.vhd 0 → 100644
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hdl/modules/dbe_wishbone/wb_acq_core/acq_ddr3_read.vhd 0 → 100644
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hdl/modules/dbe_wishbone/wb_acq_core/acq_fc_fifo.vhd 0 → 100644
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hdl/modules/dbe_wishbone/wb_acq_core/acq_fsm.vhd 0 → 100644
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hdl/modules/dbe_wishbone/wb_acq_core/acq_fwft_fifo.vhd 0 → 100644
View file @ 083a57d9
------------------------------------------------------------------------------
-- Title : BPM FWFT FIFO conversion
------------------------------------------------------------------------------
-- Author : Lucas Maziero Russo
-- Company : CNPEM LNLS-DIG
-- Created : 2013-22-10
-- Platform : FPGA-generic
-------------------------------------------------------------------------------
-- Description: Module for converting a standard FIFO into a FWFT (First word
-- fall through) FIFO
-------------------------------------------------------------------------------
-- Copyright (c) 2013 CNPEM
-- Licensed under GNU Lesser General Public License (LGPL) v3.0
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2014-12-09 1.0 lucas.russo Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- Genrams cores
use work.genram_pkg.all;
-- General cores
use work.gencores_pkg.all;
-- Acquisition cores
use work.acq_core_pkg.all;
entity acq_fwft_fifo is
generic
(
g_data_width : natural := 64;
g_size : natural := 64;
g_with_wr_count : boolean := false;
g_with_rd_count : boolean := false;
g_almost_full_threshold : integer;
g_almost_empty_threshold : integer
);
port
(
-- Write clock
wr_clk_i : in std_logic;
wr_rst_n_i : in std_logic;
wr_data_i : in std_logic_vector(g_data_width-1 downto 0);
wr_en_i : in std_logic;
wr_full_o : out std_logic;
wr_count_o : out std_logic_vector(f_log2_size(g_size)-1 downto 0);
-- Read clock
rd_clk_i : in std_logic;
rd_rst_n_i : in std_logic;
rd_data_o : out std_logic_vector(g_data_width-1 downto 0);
rd_valid_o : out std_logic;
rd_en_i : in std_logic;
rd_empty_o : out std_logic;
rd_count_o : out std_logic_vector(f_log2_size(g_size)-1 downto 0)
);
end acq_fwft_fifo;
architecture rtl of acq_fwft_fifo is
-- Signals
signal fwft_rd_en : std_logic;
signal fwft_rd_valid : std_logic;
signal fwft_rd_empty : std_logic;
begin
cmp_fwft_async_fifo : generic_async_fifo
generic map (
g_data_width => g_data_width,
g_size => g_size,
g_almost_empty_threshold => g_almost_empty_threshold,
g_almost_full_threshold => g_almost_full_threshold,
g_with_wr_count => g_with_wr_count,
g_with_rd_count => g_with_rd_count
)
port map(
rst_n_i => wr_rst_n_i,
clk_wr_i => wr_clk_i,
d_i => wr_data_i,
we_i => wr_en_i,
wr_count_o => wr_count_o,
clk_rd_i => rd_clk_i,
q_o => rd_data_o,
rd_i => fwft_rd_en,
rd_count_o => rd_count_o,
rd_empty_o => fwft_rd_empty,
wr_full_o => wr_full_o
);
-- First Word Fall Through (FWFT) implementation
fwft_rd_en <= not(fwft_rd_empty) and (not(fwft_rd_valid) or rd_en_i);
p_fwft_rd_valid : process (rd_clk_i) is
begin
if rising_edge(rd_clk_i) then
if rd_rst_n_i = '0' then
fwft_rd_valid <= '0';
else
if fwft_rd_en = '1' then
fwft_rd_valid <= '1';
elsif rd_en_i = '1' then
fwft_rd_valid <= '0';
end if;
end if;
end if;
end process;
-- This is the actual valid flag for this FIFO
rd_valid_o <= fwft_rd_valid;
end rtl;
hdl/modules/dbe_wishbone/wb_acq_core/acq_multishot_dpram.vhd 0 → 100644
View file @ 083a57d9
------------------------------------------------------------------------------
-- Title : BPM Multishot DPRAM
------------------------------------------------------------------------------
-- Author : Lucas Maziero Russo
-- Company : CNPEM LNLS-DIG
-- Created : 2013-22-10
-- Platform : FPGA-generic
-------------------------------------------------------------------------------
-- Description: Module for the buffering samples in multishot acquisition
-------------------------------------------------------------------------------
-- Copyright (c) 2013 CNPEM
-- Licensed under GNU Lesser General Public License (LGPL) v3.0
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2013-22-10 1.0 lucas.russo Created
-------------------------------------------------------------------------------
-- Based on FMC-ADC-100M (http://www.ohwr.org/projects/fmc-adc-100m14b4cha/repository)
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- Main Wishbone Definitions
use work.wishbone_pkg.all;
-- General common cores
use work.gencores_pkg.all;
-- Genrams cores
use work.genram_pkg.all;
-- Acquisition cores
use work.acq_core_pkg.all;
entity acq_multishot_dpram is
generic
(
g_data_width : natural := 64;
g_multishot_ram_size : natural := 2048
);
port
(
fs_clk_i : in std_logic;
fs_ce_i : in std_logic;
fs_rst_n_i : in std_logic;
data_i : in std_logic_vector(g_data_width-1 downto 0);
dvalid_i : in std_logic;
wr_en_i : in std_logic;
addr_rst_i : in std_logic;
buffer_sel_i : in std_logic;
acq_trig_i : in std_logic;
pre_trig_samples_i : in unsigned(c_acq_samples_size-1 downto 0);
post_trig_samples_i : in unsigned(c_acq_samples_size-1 downto 0);
acq_pre_trig_done_i : in std_logic;
acq_wait_trig_skip_done_i : in std_logic;
acq_post_trig_done_i : in std_logic;
dpram_dout_o : out std_logic_vector(g_data_width-1 downto 0);
dpram_valid_o : out std_logic
);
end acq_multishot_dpram;
architecture rtl of acq_multishot_dpram is
constant c_dpram_depth : integer := f_log2_size(g_multishot_ram_size);
signal dpram_addra_cnt : unsigned(c_dpram_depth-1 downto 0);
signal dpram_addra_trig : unsigned(c_dpram_depth-1 downto 0);
signal dpram_addra_post_done : unsigned(c_dpram_depth-1 downto 0);
signal dpram_addrb_cnt : unsigned(c_dpram_depth-1 downto 0);
signal dpram_valid : std_logic;
signal dpram_valid_t : std_logic;
signal dpram0_dina : std_logic_vector(g_data_width-1 downto 0);
signal dpram0_addra : std_logic_vector(c_dpram_depth-1 downto 0);
signal dpram0_wea : std_logic;
signal dpram0_addrb : std_logic_vector(c_dpram_depth-1 downto 0);
signal dpram0_doutb : std_logic_vector(g_data_width-1 downto 0);
signal dpram1_dina : std_logic_vector(g_data_width-1 downto 0);
signal dpram1_addra : std_logic_vector(c_dpram_depth-1 downto 0);
signal dpram1_wea : std_logic;
signal dpram1_addrb : std_logic_vector(c_dpram_depth-1 downto 0);
signal dpram1_doutb : std_logic_vector(g_data_width-1 downto 0);
begin
-- DPRAM input address counter
p_dpram_addra_cnt : process (fs_clk_i)
begin
if rising_edge(fs_clk_i) then
if fs_rst_n_i = '0' then
dpram_addra_cnt <= (others => '0');
dpram_addra_trig <= (others => '0');
dpram_addra_post_done <= (others => '0');
else
if addr_rst_i = '1' then
dpram_addra_cnt <= to_unsigned(0, dpram_addra_cnt'length);
elsif (wr_en_i = '1' and dvalid_i = '1') then
dpram_addra_cnt <= dpram_addra_cnt + 1;
end if;
-- Mark the point in RAM where a trigger occured or just the
-- pre-trigger number of samples if we are in acquire now mode
if acq_trig_i = '1' or acq_wait_trig_skip_done_i = '1' then
dpram_addra_trig <= dpram_addra_cnt;
end if;
if acq_post_trig_done_i = '1' then
if post_trig_samples_i = to_unsigned(0, post_trig_samples_i'length) then
dpram_addra_post_done <= dpram_addra_cnt - 1;
else
dpram_addra_post_done <= dpram_addra_cnt;
end if;
end if;
end if;
end if;
end process;
-- DPRAM inputs
dpram0_addra <= std_logic_vector(dpram_addra_cnt);
dpram1_addra <= std_logic_vector(dpram_addra_cnt);
dpram0_dina <= data_i;
dpram1_dina <= data_i;
dpram0_wea <= (wr_en_i and dvalid_i) when buffer_sel_i = '0' else '0';
dpram1_wea <= (wr_en_i and dvalid_i) when buffer_sel_i = '1' else '0';
-- DPRAMs
cmp_multishot_dpram0 : generic_dpram
generic map
(
g_data_width => g_data_width,
g_size => g_multishot_ram_size,
g_with_byte_enable => false,
g_addr_conflict_resolution => "read_first",
g_dual_clock => false
)
port map
(
rst_n_i => fs_rst_n_i,
-- Write through port A
clka_i => fs_clk_i,
bwea_i => open,
wea_i => dpram0_wea,
aa_i => dpram0_addra,
da_i => dpram0_dina,
qa_o => open,
-- Read through port B
clkb_i => fs_clk_i,
bweb_i => open,
ab_i => dpram0_addrb,
qb_o => dpram0_doutb
);
cmp_multishot_dpram1 : generic_dpram
generic map
(
g_data_width => g_data_width,
g_size => g_multishot_ram_size,
g_with_byte_enable => false,
g_addr_conflict_resolution => "read_first",
g_dual_clock => false
)
port map
(
rst_n_i => fs_rst_n_i,
clka_i => fs_clk_i,
bwea_i => open,
wea_i => dpram1_wea,
aa_i => dpram1_addra,
da_i => dpram1_dina,
qa_o => open,
clkb_i => fs_clk_i,
bweb_i => open,
ab_i => dpram1_addrb,
qb_o => dpram1_doutb
);
-- DPRAM output address counter
p_dpram_addrb_cnt : process (fs_clk_i)
begin
if rising_edge(fs_clk_i) then
if fs_rst_n_i = '0' then
dpram_addrb_cnt <= (others => '0');
dpram_valid_t <= '0';
dpram_valid <= '0';
else
if acq_post_trig_done_i = '1' then
dpram_addrb_cnt <= dpram_addra_trig - pre_trig_samples_i(c_dpram_depth-1 downto 0);
dpram_valid_t <= '1';
elsif (dpram_addrb_cnt = dpram_addra_post_done) then
dpram_valid_t <= '0';
else
dpram_addrb_cnt <= dpram_addrb_cnt + 1;
end if;
-- Account for DPRAM 1 cycle latency
dpram_valid <= dpram_valid_t;
end if;
end if;
end process p_dpram_addrb_cnt;
dpram0_addrb <= std_logic_vector(dpram_addrb_cnt);
dpram1_addrb <= std_logic_vector(dpram_addrb_cnt);
-- DPRAM output mux. When writing to DPRAM 0, reads from DPRAM 1 and vice-versa
dpram_dout_o <= dpram0_doutb when buffer_sel_i = '1' else dpram1_doutb;
dpram_valid_o <= dpram_valid;
end rtl;
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------------------------------------------------------------------------------
-- Title : Acquisition Select Channel
------------------------------------------------------------------------------
-- Author : Lucas Maziero Russo
-- Company : CNPEM LNLS-DIG
-- Created : 2013-06-11
-- Platform : FPGA-generic
-------------------------------------------------------------------------------
-- Description: Simple MUX for selecting an acquisition channel. Basically a
-- 1 clock cycle latency MUX
-------------------------------------------------------------------------------
-- Copyright (c) 2013 CNPEM
-- Licensed under GNU Lesser General Public License (LGPL) v3.0
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2014-21-07 1.0 lucas.russo Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.acq_core_pkg.all;
entity acq_sel_chan is
generic
(
g_acq_num_channels : natural := 1
);
port
(
clk_i : in std_logic;
rst_n_i : in std_logic;
-----------------------------
-- Acquisiton Interface
-----------------------------
acq_val_low_i : in t_acq_val_half_array(g_acq_num_channels-1 downto 0);
acq_val_high_i : in t_acq_val_half_array(g_acq_num_channels-1 downto 0);
acq_dvalid_i : in std_logic_vector(g_acq_num_channels-1 downto 0);
acq_trig_i : in std_logic_vector(g_acq_num_channels-1 downto 0);
acq_curr_chan_id_i : in unsigned(c_chan_id_width-1 downto 0);
-----------------------------
-- Output Interface.
-----------------------------
acq_data_o : out std_logic_vector(c_acq_chan_max_w-1 downto 0);
acq_dvalid_o : out std_logic;
acq_trig_o : out std_logic
);
end acq_sel_chan;
architecture rtl of acq_sel_chan is
signal acq_data_marsh_demux : std_logic_vector(c_acq_chan_max_w-1 downto 0);
signal acq_trig_demux : std_logic;
signal acq_dvalid_demux : std_logic;
signal acq_data_marsh_demux_reg : std_logic_vector(c_acq_chan_max_w-1 downto 0);
signal acq_trig_demux_reg : std_logic;
signal acq_dvalid_demux_reg : std_logic;
begin
acq_data_marsh_demux <=
f_acq_chan_conv_val(f_acq_chan_marshall_val(acq_val_high_i(to_integer(acq_curr_chan_id_i)),
acq_val_low_i(to_integer(acq_curr_chan_id_i))));
acq_trig_demux <= acq_trig_i(to_integer(acq_curr_chan_id_i));
acq_dvalid_demux <= acq_dvalid_i(to_integer(acq_curr_chan_id_i));
p_reg_demux : process (clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
acq_data_marsh_demux_reg <= (others => '0');
acq_dvalid_demux_reg <= '0';
acq_trig_demux_reg <= '0';
else
acq_data_marsh_demux_reg <= acq_data_marsh_demux;
acq_dvalid_demux_reg <= acq_dvalid_demux;
acq_trig_demux_reg <= acq_trig_demux;
end if;
end if;
end process;
acq_data_o <= acq_data_marsh_demux_reg;
acq_dvalid_o <= acq_dvalid_demux_reg;
acq_trig_o <= acq_trig_demux_reg;
end rtl;
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---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for BPM FSM Acquisition registers
---------------------------------------------------------------------------------------
-- File : acq_core_regs_pkg.vhd
-- Author : auto-generated by wbgen2 from acq_core.wb
-- Created : Sat Dec 7 04:09:07 2013
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE acq_core.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package acq_core_wbgen2_pkg is
-- Input registers (user design -> WB slave)
type t_acq_core_in_registers is record
sta_fsm_state_i : std_logic_vector(2 downto 0);
sta_fsm_acq_done_i : std_logic;
sta_reserved1_i : std_logic_vector(3 downto 0);
sta_fc_trans_done_i : std_logic;
sta_fc_full_i : std_logic;
sta_reserved2_i : std_logic_vector(5 downto 0);
sta_ddr3_trans_done_i : std_logic;
sta_reserved3_i : std_logic_vector(14 downto 0);
trig_pos_i : std_logic_vector(31 downto 0);
samples_cnt_i : std_logic_vector(31 downto 0);
end record;
constant c_acq_core_in_registers_init_value: t_acq_core_in_registers := (
sta_fsm_state_i => (others => '0'),
sta_fsm_acq_done_i => '0',
sta_reserved1_i => (others => '0'),
sta_fc_trans_done_i => '0',
sta_fc_full_i => '0',
sta_reserved2_i => (others => '0'),
sta_ddr3_trans_done_i => '0',
sta_reserved3_i => (others => '0'),
trig_pos_i => (others => '0'),
samples_cnt_i => (others => '0')
);
-- Output registers (WB slave -> user design)
type t_acq_core_out_registers is record
ctl_fsm_start_acq_o : std_logic;
ctl_fsm_stop_acq_o : std_logic;
ctl_reserved1_o : std_logic_vector(13 downto 0);
ctl_fsm_acq_now_o : std_logic;
ctl_reserved2_o : std_logic_vector(14 downto 0);
trig_cfg_hw_trig_sel_o : std_logic;
trig_cfg_hw_trig_pol_o : std_logic;
trig_cfg_hw_trig_en_o : std_logic;
trig_cfg_sw_trig_en_o : std_logic;
trig_cfg_int_trig_sel_o : std_logic_vector(1 downto 0);
trig_cfg_reserved_o : std_logic_vector(9 downto 0);
trig_cfg_int_trig_thres_o : std_logic_vector(15 downto 0);
trig_dly_o : std_logic_vector(31 downto 0);
sw_trig_o : std_logic_vector(31 downto 0);
sw_trig_wr_o : std_logic;
shots_nb_o : std_logic_vector(15 downto 0);
shots_reserved_o : std_logic_vector(15 downto 0);
pre_samples_o : std_logic_vector(31 downto 0);
post_samples_o : std_logic_vector(31 downto 0);
ddr3_start_addr_o : std_logic_vector(31 downto 0);
acq_chan_ctl_which_o : std_logic_vector(4 downto 0);
end record;
constant c_acq_core_out_registers_init_value: t_acq_core_out_registers := (
ctl_fsm_start_acq_o => '0',
ctl_fsm_stop_acq_o => '0',
ctl_reserved1_o => (others => '0'),
ctl_fsm_acq_now_o => '0',
ctl_reserved2_o => (others => '0'),
trig_cfg_hw_trig_sel_o => '0',
trig_cfg_hw_trig_pol_o => '0',
trig_cfg_hw_trig_en_o => '0',
trig_cfg_sw_trig_en_o => '0',
trig_cfg_int_trig_sel_o => (others => '0'),
trig_cfg_reserved_o => (others => '0'),
trig_cfg_int_trig_thres_o => (others => '0'),
trig_dly_o => (others => '0'),
sw_trig_o => (others => '0'),
sw_trig_wr_o => '0',
shots_nb_o => (others => '0'),
shots_reserved_o => (others => '0'),
pre_samples_o => (others => '0'),
post_samples_o => (others => '0'),
ddr3_start_addr_o => (others => '0'),
acq_chan_ctl_which_o => (others => '0')
);
function "or" (left, right: t_acq_core_in_registers) return t_acq_core_in_registers;
function f_x_to_zero (x:std_logic) return std_logic;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector;
end package;
package body acq_core_wbgen2_pkg is
function f_x_to_zero (x:std_logic) return std_logic is
begin
if(x = 'X' or x = 'U') then
return '0';
else
return x;
end if;
end function;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector is
variable tmp: std_logic_vector(x'length-1 downto 0);
begin
for i in 0 to x'length-1 loop
if(x(i) = 'X' or x(i) = 'U') then
tmp(i):= '0';
else
tmp(i):=x(i);
end if;
end loop;
return tmp;
end function;
function "or" (left, right: t_acq_core_in_registers) return t_acq_core_in_registers is
variable tmp: t_acq_core_in_registers;
begin
tmp.sta_fsm_state_i := f_x_to_zero(left.sta_fsm_state_i) or f_x_to_zero(right.sta_fsm_state_i);
tmp.sta_fsm_acq_done_i := f_x_to_zero(left.sta_fsm_acq_done_i) or f_x_to_zero(right.sta_fsm_acq_done_i);
tmp.sta_reserved1_i := f_x_to_zero(left.sta_reserved1_i) or f_x_to_zero(right.sta_reserved1_i);
tmp.sta_fc_trans_done_i := f_x_to_zero(left.sta_fc_trans_done_i) or f_x_to_zero(right.sta_fc_trans_done_i);
tmp.sta_fc_full_i := f_x_to_zero(left.sta_fc_full_i) or f_x_to_zero(right.sta_fc_full_i);
tmp.sta_reserved2_i := f_x_to_zero(left.sta_reserved2_i) or f_x_to_zero(right.sta_reserved2_i);
tmp.sta_ddr3_trans_done_i := f_x_to_zero(left.sta_ddr3_trans_done_i) or f_x_to_zero(right.sta_ddr3_trans_done_i);
tmp.sta_reserved3_i := f_x_to_zero(left.sta_reserved3_i) or f_x_to_zero(right.sta_reserved3_i);
tmp.trig_pos_i := f_x_to_zero(left.trig_pos_i) or f_x_to_zero(right.trig_pos_i);
tmp.samples_cnt_i := f_x_to_zero(left.samples_cnt_i) or f_x_to_zero(right.samples_cnt_i);
return tmp;
end function;
end package body;
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