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Beam Positoning Monitor - Gateware
Commit 15fdf54b authored by Lucas Russo's avatar Lucas Russo
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module/fmc_adc_common: propagate mmcm_rst signal up to fmc_adc_iface module

parent 41b30686
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Showing with 19 additions and 1 deletion
hdl/modules/fmc_adc_common/fmc_adc_clk.vhd
View file @ 15fdf54b
...@@ -50,6 +50,9 @@ port ...@@ -50,6 +50,9 @@ port
sys_clk_200Mhz_i : in std_logic; sys_clk_200Mhz_i : in std_logic;
sys_rst_i : in std_logic; sys_rst_i : in std_logic;
-- MMCM reset port
mmcm_rst_i : in std_logic := '0';
----------------------------- -----------------------------
-- External ports -- External ports
----------------------------- -----------------------------
...@@ -115,6 +118,7 @@ architecture rtl of fmc_adc_clk is ...@@ -115,6 +118,7 @@ architecture rtl of fmc_adc_clk is
signal adc_clk2x_mmcm_out : std_logic; signal adc_clk2x_mmcm_out : std_logic;
signal mmcm_adc_locked_int : std_logic; signal mmcm_adc_locked_int : std_logic;
signal mmcm_adc_locked_sync : std_logic; signal mmcm_adc_locked_sync : std_logic;
signal mmcm_rst_int : std_logic;
-- Clock delay signals -- Clock delay signals
signal iodelay_update : std_logic; signal iodelay_update : std_logic;
...@@ -437,9 +441,11 @@ begin ...@@ -437,9 +441,11 @@ begin
CLKINSTOPPED => open, CLKINSTOPPED => open,
CLKFBSTOPPED => open, CLKFBSTOPPED => open,
PWRDWN => '0', PWRDWN => '0',
RST => sys_rst_i RST => mmcm_rst_int
); );
mmcm_rst_int <= sys_rst_i or mmcm_rst_i;
-- Global clock buffer for MMCM feedback. Deskew MMCM configuration -- Global clock buffer for MMCM feedback. Deskew MMCM configuration
cmp_adc_clk_fb_bufg : BUFG cmp_adc_clk_fb_bufg : BUFG
port map( port map(
......
hdl/modules/fmc_adc_common/fmc_adc_iface.vhd
View file @ 15fdf54b
...@@ -74,6 +74,9 @@ port ...@@ -74,6 +74,9 @@ port
sys_rst_n_i : in std_logic; sys_rst_n_i : in std_logic;
sys_clk_200Mhz_i : in std_logic; sys_clk_200Mhz_i : in std_logic;
-- MMCM reset port
mmcm_rst_i : in std_logic := '0';
----------------------------- -----------------------------
-- External ports -- External ports
----------------------------- -----------------------------
...@@ -228,6 +231,9 @@ begin ...@@ -228,6 +231,9 @@ begin
sys_clk_200Mhz_i => sys_clk_200Mhz_i, sys_clk_200Mhz_i => sys_clk_200Mhz_i,
sys_rst_i => sys_rst, sys_rst_i => sys_rst,
-- MMCM reset port
mmcm_rst_i => mmcm_rst_i,
----------------------------- -----------------------------
-- External ports -- External ports
----------------------------- -----------------------------
......
hdl/modules/fmc_adc_common/fmc_adc_pkg.vhd
View file @ 15fdf54b
...@@ -361,6 +361,9 @@ package fmc_adc_pkg is ...@@ -361,6 +361,9 @@ package fmc_adc_pkg is
-- ADC clocks. One clock per ADC channel -- ADC clocks. One clock per ADC channel
adc_clk_i : in std_logic; adc_clk_i : in std_logic;
-- MMCM reset port
mmcm_rst_i : in std_logic := '0';
----------------------------- -----------------------------
-- ADC Delay signals. -- ADC Delay signals.
----------------------------- -----------------------------
...@@ -474,6 +477,9 @@ package fmc_adc_pkg is ...@@ -474,6 +477,9 @@ package fmc_adc_pkg is
sys_rst_n_i : in std_logic; sys_rst_n_i : in std_logic;
sys_clk_200Mhz_i : in std_logic; sys_clk_200Mhz_i : in std_logic;
-- MMCM reset port
mmcm_rst_i : in std_logic := '0';
----------------------------- -----------------------------
-- External ports -- External ports
----------------------------- -----------------------------
......
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