Commit 15fdf54b authored by Lucas Russo's avatar Lucas Russo

module/fmc_adc_common: propagate mmcm_rst signal up to fmc_adc_iface module

parent 41b30686
......@@ -50,6 +50,9 @@ port
sys_clk_200Mhz_i : in std_logic;
sys_rst_i : in std_logic;
-- MMCM reset port
mmcm_rst_i : in std_logic := '0';
-----------------------------
-- External ports
-----------------------------
......@@ -115,6 +118,7 @@ architecture rtl of fmc_adc_clk is
signal adc_clk2x_mmcm_out : std_logic;
signal mmcm_adc_locked_int : std_logic;
signal mmcm_adc_locked_sync : std_logic;
signal mmcm_rst_int : std_logic;
-- Clock delay signals
signal iodelay_update : std_logic;
......@@ -437,9 +441,11 @@ begin
CLKINSTOPPED => open,
CLKFBSTOPPED => open,
PWRDWN => '0',
RST => sys_rst_i
RST => mmcm_rst_int
);
mmcm_rst_int <= sys_rst_i or mmcm_rst_i;
-- Global clock buffer for MMCM feedback. Deskew MMCM configuration
cmp_adc_clk_fb_bufg : BUFG
port map(
......
......@@ -74,6 +74,9 @@ port
sys_rst_n_i : in std_logic;
sys_clk_200Mhz_i : in std_logic;
-- MMCM reset port
mmcm_rst_i : in std_logic := '0';
-----------------------------
-- External ports
-----------------------------
......@@ -228,6 +231,9 @@ begin
sys_clk_200Mhz_i => sys_clk_200Mhz_i,
sys_rst_i => sys_rst,
-- MMCM reset port
mmcm_rst_i => mmcm_rst_i,
-----------------------------
-- External ports
-----------------------------
......
......@@ -361,6 +361,9 @@ package fmc_adc_pkg is
-- ADC clocks. One clock per ADC channel
adc_clk_i : in std_logic;
-- MMCM reset port
mmcm_rst_i : in std_logic := '0';
-----------------------------
-- ADC Delay signals.
-----------------------------
......@@ -474,6 +477,9 @@ package fmc_adc_pkg is
sys_rst_n_i : in std_logic;
sys_clk_200Mhz_i : in std_logic;
-- MMCM reset port
mmcm_rst_i : in std_logic := '0';
-----------------------------
-- External ports
-----------------------------
......
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