Commit 19b4ba7d authored by Lucas Russo's avatar Lucas Russo

{modules,platform,sim,testbench}: remove files moved to infra-cores repo

All of this files are already present in infra-cores
repo. So, no need to keep them here.
parent f9db01ed
modules = { "local" : ["reset_synch",
"pulse2level",
"trigger_rcv",
"counter_simple",
"extend_pulse_dyn",
"heartbeat"] };
files = [ "dbe_common_pkg.vhd" ];
-------------------------------------------------------------------------------
-- Title : Simple counter
-- Project :
-------------------------------------------------------------------------------
-- File : counter.vhd
-- Author : aylons <aylons@LNLS190>
-- Company :
-- Created : 2015-11-11
-- Last update: 2015-12-11
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Simple counter for testing, with clock enable
-------------------------------------------------------------------------------
-- Copyright (c) 2015
-- This program is free software: you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public License
-- as published by the Free Software Foundation, either version 3 of
-- the License, or (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public
-- License along with this program. If not, see
-- <http://www.gnu.org/licenses/>.
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2015-11-11 1.0 aylons Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity counter_simple is
generic(
g_output_width : positive := 8
);
port(
clk_i : in std_logic;
rst_n_i : in std_logic;
ce_i : in std_logic;
up_i : in std_logic;
down_i : in std_logic;
count_o : out std_logic_vector(g_output_width-1 downto 0)
);
end counter_simple;
architecture behavioural of counter_simple is
signal count : unsigned(g_output_width-1 downto 0) := to_unsigned(0, g_output_width);
begin
counter_simple : process(clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
count <= to_unsigned(0, g_output_width);
else
if ce_i = '1' then
if up_i = '1' then
count <= count + 1;
elsif down_i = '1' then
count <= count - 1;
end if;
end if; --ce
end if; --rst
end if; -- clk
end process;
count_o <= std_logic_vector(count);
end architecture behavioural;
library ieee;
use ieee.std_logic_1164.all;
use ieee.NUMERIC_STD.all;
package dbe_common_pkg is
--------------------------------------------------------------------
-- Components
--------------------------------------------------------------------
component reset_synch
generic
(
-- Select 1 for no pipeline, and greater than 1 to insert
-- pipeline stages
g_pipeline : natural := 4
);
port
(
clk_i : in std_logic;
arst_n_i : in std_logic;
rst_n_o : out std_logic
);
end component;
component pulse2level
port
(
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Pulse input
pulse_i : in std_logic;
-- Clear level
clr_i : in std_logic;
-- Level output
level_o : out std_logic
);
end component;
component trigger_rcv is
generic (
g_glitch_len_width : positive;
g_sync_edge : string);
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
len_i : in std_logic_vector(g_glitch_len_width-1 downto 0);
data_i : in std_logic;
pulse_o : out std_logic);
end component trigger_rcv;
component extend_pulse_dyn is
generic (
g_width_bus_size : natural);
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
pulse_i : in std_logic;
pulse_width_i : in unsigned(g_width_bus_size-1 downto 0);
extended_o : out std_logic := '0');
end component extend_pulse_dyn;
component counter_simple is
generic (
g_output_width : positive);
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
ce_i : in std_logic;
up_i : in std_logic;
down_i : in std_logic;
count_o : out std_logic_vector(g_output_width-1 downto 0));
end component counter_simple;
component heartbeat
generic
(
-- number of system clock cycles to count before blinking
g_clk_counts : natural := 100000000
);
port
(
-- 100 MHz system clock
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Heartbeat pulse output
heartbeat_o : out std_logic
);
end component;
end dbe_common_pkg;
-------------------------------------------------------------------------------
-- Title : Dynamic pulse width extender
-- Project :
-------------------------------------------------------------------------------
-- File : extend_pulse_dyn.vhd
-- Author : Vitor Finotti Ferreira <vfinotti@finotti-Inspiron-7520>
-- Company : Brazilian Synchrotron Light Laboratory, LNLS/CNPEM
-- Created : 2016-01-22
-- Last update: 2016-01-27
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
-- Synchronous pulse extender. Generates a pulse of dynamically programmable width upon
-- detection of a rising edge in the input. The code is based on
-- gc_extend_pulse.vhd created by Tomasz Wlostowskyt, from General Cores library.
-------------------------------------------------------------------------------
-- Copyright (c) 2016 Brazilian Synchrotron Light Laboratory, LNLS/CNPEM
-- This program is free software: you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public License
-- as published by the Free Software Foundation, either version 3 of
-- the License, or (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public
-- License along with this program. If not, see
-- <http://www.gnu.org/licenses/>.
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2015-dec-17 0.9 vfinotti Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.NUMERIC_STD.all;
entity extend_pulse_dyn is
generic (
-- output pulse width in clk_i cycles
g_width_bus_size : natural := 32
);
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
pulse_i : in std_logic;
pulse_width_i : in unsigned(g_width_bus_size-1 downto 0);
-- extended output pulse
extended_o : out std_logic := '0');
end extend_pulse_dyn;
architecture rtl of extend_pulse_dyn is
signal cntr : unsigned(g_width_bus_size-1 downto 0);
signal extended_int : std_logic;
begin -- rtl
extend : process (clk_i, rst_n_i)
begin -- process extend
if rst_n_i = '0' then -- asynchronous reset (active low)
extended_int <= '0';
cntr <= (others => '0');
elsif clk_i'event and clk_i = '1' then -- rising clock edge
if(pulse_i = '1') then
extended_int <= '1';
cntr <= pulse_width_i - 2;
elsif cntr /= to_unsigned(0, cntr'length) then
cntr <= cntr - 1;
else
extended_int <= '0';
end if;
end if;
end process extend;
extended_o <= pulse_i or extended_int;
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- Common cores
use work.genram_pkg.all;
entity heartbeat is
generic
(
-- number of system clock cycles to count before blinking
g_clk_counts : natural := 100000000
);
port
(
-- 100 MHz system clock
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Heartbeat pulse output
heartbeat_o : out std_logic
);
end heartbeat;
architecture rtl of heartbeat is
constant c_pps_counter_width : natural := f_log2_size(g_clk_counts);
signal hb : std_logic := '0';
signal pps_counter : unsigned(c_pps_counter_width-1 downto 0) :=
(others => '0');
begin
p_heartbeat : process (clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
pps_counter <= to_unsigned(0, pps_counter'length);
hb <= '0';
else
if pps_counter = g_clk_counts-1 then
pps_counter <= to_unsigned(0, pps_counter'length);
hb <= not hb;
else
pps_counter <= pps_counter + 1;
end if;
end if;
end if;
end process;
heartbeat_o <= hb;
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity pulse2level is
port
(
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Pulse input
pulse_i : in std_logic;
-- Clear level
clr_i : in std_logic;
-- Level output
level_o : out std_logic
);
end pulse2level;
architecture rtl of pulse2level is
signal level : std_logic := '0';
begin
-- Convert from pulse to level signal
p_pulse_to_level : process (clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
level <= '0';
else
if clr_i = '1'then
level <= '0';
elsif pulse_i = '1' then
level <= '1';
end if;
end if;
end if;
end process;
level_o <= level;
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity reset_synch is
generic
(
-- Select 1 for no pipeline, and greater than 1 to insert
-- pipeline stages
g_pipeline : natural := 4
);
port
(
clk_i : in std_logic;
arst_n_i : in std_logic;
rst_n_o : out std_logic
);
end reset_synch;
architecture rtl of reset_synch is
signal s_ff : std_logic_vector(g_pipeline-1 downto 0) := (others => '0');
-- force tool to not remove pipeline registers
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of s_ff
: signal is "no";
-- force tool to not infer shift-register
attribute shreg_extract : string;
attribute shreg_extract of s_ff : signal is "no";
-- force tool to keep register
attribute keep : string;
attribute keep of s_ff : signal is "true";
-- try to reduce fanout of reset signal
attribute max_fanout : string;
attribute max_fanout of s_ff : signal is "reduce";
begin
assert (g_pipeline >= 1)
report "[reset_synch] g_pipeline must be at least 1!"
severity failure;
p_rst_sync : process(clk_i, arst_n_i)
begin
if arst_n_i = '0' then
s_ff(0) <= '0';
elsif rising_edge(clk_i) then
s_ff(0) <= '1';
end if;
end process;
gen_pipe : if g_pipeline > 1 generate
-- Shift reg
p_rst_pipe : process (clk_i, arst_n_i)
begin
if arst_n_i = '0' then
for i in 0 to g_pipeline-2 loop
s_ff(i+1) <= '0';
end loop;
elsif rising_edge(clk_i) then
for i in 0 to g_pipeline-2 loop
s_ff(i+1) <= s_ff(i);
end loop;
end if;
end process;
end generate;
rst_n_o <= s_ff(s_ff'left);
end rtl;
-------------------------------------------------------------------------------
-- Title : Trigger receiver
-- Project :
-------------------------------------------------------------------------------
-- File : trigger_rcv.vhd
-- Author : aylons <aylons@LNLS190>
-- Company :
-- Created : 2015-11-09
-- Last update: 2016-01-22
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Receives a signal from an FPGA port, debounces the signal and
-- outputs a pulse with a configurable clock width.
-------------------------------------------------------------------------------
-- Copyright (c) 2015
-- This program is free software: you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public License
-- as published by the Free Software Foundation, either version 3 of
-- the License, or (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public
-- License along with this program. If not, see
-- <http://www.gnu.org/licenses/>.
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2015-11-09 1.0 aylons Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.gencores_pkg.all;
entity trigger_rcv is
generic (
-- Number of glicth filter registers
g_glitch_len_width : positive := 8;
-- Width of the output pulse after edge detection
g_sync_edge : string := "positive"
);
port(
clk_i : in std_logic;
rst_n_i : in std_logic;
len_i : in std_logic_vector(g_glitch_len_width-1 downto 0);
data_i : in std_logic;
pulse_o : out std_logic
);
end entity trigger_rcv;
architecture structural of trigger_rcv is
signal deglitched : std_logic;
signal data_sync : std_logic := '0';
component gc_dyn_glitch_filt is
generic (
g_len_width : natural);
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
len_i : in std_logic_vector(g_len_width-1 downto 0);
dat_i : in std_logic;
dat_o : out std_logic);
end component gc_dyn_glitch_filt;
component gc_sync_ffs is
generic (
g_sync_edge : string);
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
data_i : in std_logic;
synced_o : out std_logic;
npulse_o : out std_logic;
ppulse_o : out std_logic);
end component gc_sync_ffs;
begin
-- Prevent matastability problems
cmp_input_sync : gc_sync_ffs
generic map(
g_sync_edge => "positive")
port map(
clk_i => clk_i,
rst_n_i => rst_n_i,
data_i => data_i,
synced_o => data_sync,
npulse_o => open,
ppulse_o => open);
cmp_deglitcher : gc_dyn_glitch_filt
generic map (
g_len_width => g_glitch_len_width)
port map (
clk_i => clk_i,
rst_n_i => rst_n_i,
len_i => len_i,
dat_i => data_sync,
dat_o => deglitched);
cmp_edge_detector : gc_sync_ffs
generic map(
g_sync_edge => g_sync_edge)
port map(
clk_i => clk_i,
rst_n_i => rst_n_i,
data_i => deglitched,
synced_o => open,
npulse_o => open,
ppulse_o => pulse_o);
end architecture structural;
files = [ "dbe_wishbone_pkg.vhd" ];
modules = { "local" : [
"wb_stream",
"wb_trigger_iface",
"wb_trigger_mux",
"wb_trigger",
"wb_afc_diag",
"wb_fmc150",
"wb_fmc516",
"wb_fmc130m_4ch",
"wb_fmc250m_4ch",
"wb_fmcpico1m_4ch",
"wb_ethmac_adapter",
"wb_ethmac",
"wb_dbe_periph",
"wb_rs232_syscon",
"wb_acq_core",
"wb_acq_core_mux",
"wb_facq_core",
"wb_facq_core_mux",
"wb_pcie",
"wb_fmc_adc_common",
"wb_fmc_active_clk"
] };
This source diff could not be displayed because it is too large. You can view the blob instead.
files = ["wb_acq_core.vhd",
"xwb_acq_core.vhd",
"wb_acq_core_plain.vhd",
"acq_fsm.vhd",
"acq_core_pkg.vhd",
"acq_multishot_dpram.vhd",
"acq_fc_fifo.vhd",
"acq_fwft_fifo.vhd",
"fc_source.vhd",
"acq_ddr3_ui_write.vhd",
"acq_ddr3_ui_read.vhd",
"acq_ddr3_axis_write.vhd",
"acq_ddr3_axis_read.vhd",
"acq_cnt.vhd",
"acq_sel_chan.vhd",
"acq_2_diff_cnt.vhd",
"data_checker.vhd",
"acq_pulse_level_sync.vhd",
"acq_trigger.vhd",
"wbgen/acq_core_regs_pkg.vhd",
"wbgen/acq_core_regs.vhd"
];
------------------------------------------------------------------------------
-- Title : BPM Acquisition Difference Counter
------------------------------------------------------------------------------
-- Author : Lucas Maziero Russo
-- Company : CNPEM LNLS-DIG
-- Created : 2014-10-29
-- Platform : FPGA-generic
-------------------------------------------------------------------------------
-- Description: Simple difference counter. It works computing the difference
-- between two counters. When a threshold is hit, a flag is
-- asserted and the counter who hit the threshold does not
-- incremente anymore. After the difference is reduced, the
-- counters resume counting normally
-------------------------------------------------------------------------------
-- Copyright (c) 2013 CNPEM
-- Licensed under GNU Lesser General Public License (LGPL) v3.0
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2014-10-29 1.0 lucas.russo Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.genram_pkg.all;
entity acq_2_diff_cnt is
generic
(
-- Threshold in which the counters can differ
g_threshold_max : natural := 2
);
port
(
clk_i : in std_logic;
rst_n_i : in std_logic;
cnt0_en_i : in std_logic;
cnt0_thres_hit_o : out std_logic;
cnt1_en_i : in std_logic;
cnt1_thres_hit_o : out std_logic
);
end acq_2_diff_cnt;
architecture rtl of acq_2_diff_cnt is
signal diff_cnt0 : unsigned(f_log2_size(g_threshold_max) downto 0);
signal diff_cnt0_max : std_logic;
signal diff_cnt0_zero : std_logic;
signal diff_cnt1 : unsigned(f_log2_size(g_threshold_max) downto 0);
signal diff_cnt1_max : std_logic;
signal diff_cnt1_zero : std_logic;
begin
-- counter 0 as reference, looking at counter 1
p_diff_cnt0 : process(clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
diff_cnt0 <= to_unsigned(0, diff_cnt0'length);
else
if cnt0_en_i = '1' then -- counter 0 increments
-- and counter 1 does not increment
if cnt1_en_i = '0' and diff_cnt0_max = '0' then
diff_cnt0 <= diff_cnt0 + 1; -- diff counter 0 effectively increments
--else --both pointers increment simultaneouslly. Do nothing in this case
end if;
-- counter 0 does not increment and counter 1 increments
elsif cnt1_en_i = '1' and diff_cnt0_zero = '0' then
diff_cnt0 <= diff_cnt0 - 1; -- diff counter 0 effectivelly decrements
--else -- both pointers does not increment. Do nothing in this case
end if;
end if;
end if;
end process;
-- diff counter overflow
diff_cnt0_max <= '1' when diff_cnt0 = g_threshold_max else '0';
-- diff counter zero
diff_cnt0_zero <= '1' when diff_cnt0 = to_unsigned(0, diff_cnt0'length) else '0';
cnt0_thres_hit_o <= diff_cnt0_max;
-- counter 1 as reference, looking at counter 1
p_diff_cnt1 : process(clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
diff_cnt1 <= to_unsigned(0, diff_cnt1'length);
else
if cnt1_en_i = '1' then -- counter 1 increments
-- and counter 1 does not increment
if cnt0_en_i = '0' and diff_cnt1_max = '0' then
diff_cnt1 <= diff_cnt1 + 1; -- diff counter 1 effectively increments
--else --both pointers increment simultaneouslly. Do nothing in this case
end if;
-- counter 1 does not increment and counter 1 increments
elsif cnt0_en_i = '1' and diff_cnt1_zero = '0' then
diff_cnt1 <= diff_cnt1 - 1; -- diff counter 1 effectivelly decrements
--else -- both pointers does not increment. Do nothing in this case
end if;
end if;
end if;
end process;
-- diff counter overflow
diff_cnt1_max <= '1' when diff_cnt1 = g_threshold_max else '0';
-- diff counter zero
diff_cnt1_zero <= '1' when diff_cnt1 = to_unsigned(0, diff_cnt1'length) else '0';
cnt1_thres_hit_o <= diff_cnt1_max;
end rtl;
------------------------------------------------------------------------------
-- Title : BPM Acquisition Counter
------------------------------------------------------------------------------
-- Author : Lucas Maziero Russo
-- Company : CNPEM LNLS-DIG
-- Created : 2013-06-11
-- Platform : FPGA-generic
-------------------------------------------------------------------------------
-- Description: Simple counter of transactions and shots
-------------------------------------------------------------------------------
-- Copyright (c) 2013 CNPEM
-- Licensed under GNU Lesser General Public License (LGPL) v3.0
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2013-06-11 1.0 lucas.russo Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- Main Wishbone Definitions
use work.wishbone_pkg.all;
-- Genrams cores
use work.genram_pkg.all;
-- Genrams cores
use work.gencores_pkg.all;
-- Acquisition cores
use work.acq_core_pkg.all;
entity acq_cnt is
port
(
-- DDR3 external clock
clk_i : in std_logic;
rst_n_i : in std_logic;
cnt_all_pkts_ct_done_p_o : out std_logic; -- all current transaction packets done
cnt_all_trans_done_p_o : out std_logic; -- all transactions done
cnt_en_i : in std_logic;
-- Size of the transaction in g_fifo_size bytes
lmt_pkt_size_i : in unsigned(c_pkt_size_width-1 downto 0);
-- Number of shots in this acquisition
lmt_shots_nb_i : in unsigned(c_shots_size_width-1 downto 0);
-- Acquisition limits valid signal. Qualifies lmt_pkt_size_i and lmt_shots_nb_i
lmt_valid_i : in std_logic;
dbg_pkt_ct_cnt_o : out std_logic_vector(c_pkt_size_width-1 downto 0);
dbg_shots_cnt_o : out std_logic_vector(c_shots_size_width-1 downto 0)
);
end acq_cnt;
architecture rtl of acq_cnt is
signal pkt_ct_cnt : unsigned(c_pkt_size_width-1 downto 0);
signal pkt_cnt_en : std_logic;
signal pkt_ct_cnt_all : std_logic;
signal pkt_ct_cnt_will_finish : std_logic;
signal shots_cnt : unsigned(c_shots_size_width-1 downto 0);
signal shots_cnt_all : std_logic;
signal lmt_pkt_size : unsigned(c_pkt_size_width-1 downto 0);
signal lmt_shots_nb : unsigned(c_shots_size_width-1 downto 0);
begin
-----------------------------------------------------------------------------
-- Register input
-----------------------------------------------------------------------------
p_in_reg : process (clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
--Avoid detection of *_done pulses by setting them to 1
lmt_pkt_size <= to_unsigned(1, lmt_pkt_size'length);
lmt_shots_nb <= to_unsigned(1, lmt_shots_nb'length);
else
if lmt_valid_i = '1' then
lmt_pkt_size <= lmt_pkt_size_i;
lmt_shots_nb <= lmt_shots_nb_i;
end if;
end if;
end if;
end process;
-----------------------------------------------------------------------------
-- Number of packets
-----------------------------------------------------------------------------
p_pkt_ct_cnt : process (clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
pkt_ct_cnt <= to_unsigned(0, pkt_ct_cnt'length);
else
if pkt_ct_cnt_all = '1' then -- counter wrap-around
if pkt_cnt_en = '1' then -- simultaneously wrap-around and increment by one
pkt_ct_cnt <= to_unsigned(1, pkt_ct_cnt'length);
else
pkt_ct_cnt <= to_unsigned(0, pkt_ct_cnt'length);
end if;
elsif pkt_cnt_en = '1' then
pkt_ct_cnt <= pkt_ct_cnt + 1;
end if;
end if;
end if;
end process;
pkt_cnt_en <= cnt_en_i;
-- Debug outputs
dbg_pkt_ct_cnt_o <= std_logic_vector(pkt_ct_cnt);
p_pkt_ct_cnt_reg : process (clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
pkt_ct_cnt_all <= '0';
else
if pkt_ct_cnt = lmt_pkt_size-1 and pkt_cnt_en = '1' then
pkt_ct_cnt_all <= '1';
else
pkt_ct_cnt_all <= '0';
end if;
end if;
end if;
end process;
pkt_ct_cnt_will_finish <= '1' when pkt_ct_cnt = lmt_pkt_size-1 and pkt_cnt_en = '1'
else '0';
cnt_all_pkts_ct_done_p_o <= pkt_ct_cnt_all; -- this is necessarilly a pulse
-----------------------------------------------------------------------------
-- Number of shots
-----------------------------------------------------------------------------
p_shots_cnt : process (clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
shots_cnt <= to_unsigned(0, shots_cnt'length);
else
if shots_cnt_all = '1' then
if pkt_ct_cnt_will_finish = '1' then -- This case won't happen. Should we keep it?
shots_cnt <= to_unsigned(1, shots_cnt'length);
else
shots_cnt <= to_unsigned(0, shots_cnt'length);
end if;
elsif pkt_ct_cnt_will_finish = '1' then
shots_cnt <= shots_cnt + 1;
end if;
end if;
end if;
end process;
-- Debug outputs
dbg_shots_cnt_o <= std_logic_vector(shots_cnt);
p_shots_cnt_reg : process (clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
shots_cnt_all <= '0';
else
if shots_cnt = lmt_shots_nb-1 and pkt_ct_cnt_will_finish = '1' then
shots_cnt_all <= '1';
else
shots_cnt_all <= '0';
end if;
end if;
end if;
end process;
cnt_all_trans_done_p_o <= shots_cnt_all;
end rtl;
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------------------------------------------------------------------------------
-- Title : BPM FWFT FIFO conversion
------------------------------------------------------------------------------
-- Author : Lucas Maziero Russo
-- Company : CNPEM LNLS-DIG
-- Created : 2013-22-10
-- Platform : FPGA-generic
-------------------------------------------------------------------------------
-- Description: Module for converting a standard FIFO into a FWFT (First word
-- fall through) FIFO
-------------------------------------------------------------------------------
-- Copyright (c) 2013 CNPEM
-- Licensed under GNU Lesser General Public License (LGPL) v3.0
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2014-12-09 1.0 lucas.russo Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- Genrams cores
use work.genram_pkg.all;
-- General cores
use work.gencores_pkg.all;
-- Acquisition cores
use work.acq_core_pkg.all;
entity acq_fwft_fifo is
generic
(
g_data_width : natural := 64;
g_size : natural := 64;
g_with_rd_empty : boolean := true;
g_with_rd_full : boolean := false;
g_with_rd_almost_empty : boolean := false;
g_with_rd_almost_full : boolean := false;
g_with_rd_count : boolean := false;
g_with_wr_empty : boolean := false;
g_with_wr_full : boolean := true;
g_with_wr_almost_empty : boolean := false;
g_with_wr_almost_full : boolean := false;
g_with_wr_count : boolean := false;
g_with_fifo_inferred : boolean := false;
g_almost_empty_threshold : integer;
g_almost_full_threshold : integer;
g_async : boolean := true
);
port
(
-- Write clock
wr_clk_i : in std_logic;
wr_rst_n_i : in std_logic;
wr_data_i : in std_logic_vector(g_data_width-1 downto 0);
wr_en_i : in std_logic;
wr_full_o : out std_logic;
wr_count_o : out std_logic_vector(f_log2_size(g_size)-1 downto 0);
wr_almost_empty_o : out std_logic;
wr_almost_full_o : out std_logic;
-- Read clock
rd_clk_i : in std_logic;
rd_rst_n_i : in std_logic;
rd_data_o : out std_logic_vector(g_data_width-1 downto 0);
rd_valid_o : out std_logic;
rd_en_i : in std_logic;
rd_empty_o : out std_logic;
rd_count_o : out std_logic_vector(f_log2_size(g_size)-1 downto 0);
rd_almost_empty_o : out std_logic;
rd_almost_full_o : out std_logic
);
end acq_fwft_fifo;
architecture rtl of acq_fwft_fifo is
-- Signals
signal fwft_rd_en : std_logic;
signal fwft_rd_valid : std_logic;
signal fwft_rd_empty : std_logic;
signal fifo_count_int : std_logic_vector(f_log2_size(g_size)-1 downto 0);
signal fifo_almost_empty_int : std_logic;
signal fifo_almost_full_int : std_logic;
begin
gen_async_fifo : if (g_async) generate
cmp_fwft_async_fifo : generic_async_fifo
generic map (
g_data_width => g_data_width,
g_size => g_size,
g_with_rd_empty => g_with_rd_empty,
g_with_rd_full => g_with_rd_full,
g_with_rd_almost_empty => g_with_rd_almost_empty,
g_with_rd_almost_full => g_with_rd_almost_full,
g_with_rd_count => g_with_rd_count,
g_with_wr_empty => g_with_wr_empty,
g_with_wr_full => g_with_wr_full,
g_with_wr_almost_empty => g_with_wr_almost_empty,
g_with_wr_almost_full => g_with_wr_almost_full,
g_with_wr_count => g_with_wr_count,
g_with_fifo_inferred => g_with_fifo_inferred,
g_almost_empty_threshold => g_almost_empty_threshold,
g_almost_full_threshold => g_almost_full_threshold
)
port map(
rst_n_i => wr_rst_n_i,
clk_wr_i => wr_clk_i,
d_i => wr_data_i,
we_i => wr_en_i,
wr_count_o => wr_count_o,
wr_almost_empty_o => wr_almost_empty_o,
wr_almost_full_o => wr_almost_full_o,
clk_rd_i => rd_clk_i,
q_o => rd_data_o,
rd_i => fwft_rd_en,
rd_count_o => rd_count_o,
rd_almost_empty_o => rd_almost_empty_o,
rd_almost_full_o => rd_almost_full_o,
rd_empty_o => fwft_rd_empty,
wr_full_o => wr_full_o
);
end generate;
gen_sync_fifo : if (not g_async) generate
cmp_fwft_sync_fifo : generic_sync_fifo
generic map (
g_data_width => g_data_width,
g_size => g_size,
g_with_empty => g_with_rd_empty or g_with_wr_empty,
g_with_full => g_with_rd_full or g_with_wr_full,
g_with_almost_empty => g_with_rd_almost_empty or g_with_wr_almost_empty,
g_with_almost_full => g_with_rd_almost_full or g_with_wr_almost_full,
g_with_count => g_with_rd_count or g_with_wr_count,
g_with_fifo_inferred => g_with_fifo_inferred,
g_almost_empty_threshold => g_almost_empty_threshold,
g_almost_full_threshold => g_almost_full_threshold
)
port map(
rst_n_i => wr_rst_n_i,
clk_i => wr_clk_i,
d_i => wr_data_i,
we_i => wr_en_i,
count_o => fifo_count_int,
q_o => rd_data_o,
rd_i => fwft_rd_en,
empty_o => fwft_rd_empty,
full_o => wr_full_o,
almost_empty_o => fifo_almost_empty_int,
almost_full_o => fifo_almost_full_int
);
wr_count_o <= fifo_count_int;
rd_count_o <= fifo_count_int;
wr_almost_empty_o <= fifo_almost_empty_int;
rd_almost_empty_o <= fifo_almost_empty_int;
wr_almost_full_o <= fifo_almost_full_int;
rd_almost_full_o <= fifo_almost_full_int;
end generate;
-- First Word Fall Through (FWFT) implementation
fwft_rd_en <= not(fwft_rd_empty) and (not(fwft_rd_valid) or rd_en_i);
p_fwft_rd_valid : process (rd_clk_i) is
begin
if rising_edge(rd_clk_i) then
if rd_rst_n_i = '0' then
fwft_rd_valid <= '0';
else
if fwft_rd_en = '1' then
fwft_rd_valid <= '1';
elsif rd_en_i = '1' then
fwft_rd_valid <= '0';
end if;
end if;
end if;
end process;
-- This is the actual valid flag for this FIFO
rd_valid_o <= fwft_rd_valid;
-- Output assignments
rd_empty_o <= fwft_rd_empty;
end rtl;
------------------------------------------------------------------------------
-- Title : BPM Pulse to Level and Synchronization
------------------------------------------------------------------------------
-- Author : Lucas Maziero Russo
-- Company : CNPEM LNLS-DIG
-- Created : 2015-08-18
-- Platform : FPGA-generic
-------------------------------------------------------------------------------
-- Description: Pulse to level and synchronizer circuits
-------------------------------------------------------------------------------
-- Copyright (c) 2015 CNPEM
-- Licensed under GNU Lesser General Public License (LGPL) v3.0
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2015-08-18 1.0 lucas.russo Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- General common cores
use work.gencores_pkg.all;
-- DBE Common cores
use work.dbe_common_pkg.all;
-- Acquisition cores
use work.acq_core_pkg.all;
entity acq_pulse_level_sync is
generic
(
g_num_inputs : natural := 1;
g_with_pulse_sync : t_acq_bool_array;
g_with_pulse2level : t_acq_bool_array
);
port
(
-- Input pulse clock
clk_in_i : in std_logic_vector(g_num_inputs-1 downto 0);
-- Input pulse reset
rst_in_n_i : in std_logic_vector(g_num_inputs-1 downto 0);
-- Synched pulse clock
clk_out_i : in std_logic_vector(g_num_inputs-1 downto 0);
-- Input pulse reset
rst_out_n_i : in std_logic_vector(g_num_inputs-1 downto 0);
-- Pulse input
pulse_i : in std_logic_vector(g_num_inputs-1 downto 0);
-- Clear level_o
clr_i : in std_logic_vector(g_num_inputs-1 downto 0);
-- clk_out_i synched pulse (using full feedback synchronizer)
pulse_synched_o : out std_logic_vector(g_num_inputs-1 downto 0);
-- level generated by pulse_i and synched with clk_out_i
level_synched_o : out std_logic_vector(g_num_inputs-1 downto 0)
);
end acq_pulse_level_sync;
architecture rtl of acq_pulse_level_sync is
signal pulse_synched : std_logic_vector(g_num_inputs-1 downto 0);
signal level_synched : std_logic_vector(g_num_inputs-1 downto 0);
begin
gen_pulse_synchronizer : for i in 0 to g_num_inputs-1 generate
gen_with_sync : if (g_with_pulse_sync(i)) generate
cmp_gc_pulse_synchronizer : gc_pulse_synchronizer
port map (
clk_in_i => clk_in_i(i),
rst_n_i => rst_in_n_i(i),
clk_out_i => clk_out_i(i),
d_ready_o => open,
d_p_i => pulse_i(i), -- pulse input
q_p_o => pulse_synched(i) -- pulse output
);
end generate;
gen_without_sync : if (not g_with_pulse_sync(i)) generate
pulse_synched(i) <= pulse_i(i);
end generate;
pulse_synched_o(i) <= pulse_synched(i);
gen_with_level : if (g_with_pulse2level(i)) generate
cmp_pulse_to_level : pulse2level
port map
(
clk_i => clk_out_i(i),
rst_n_i => rst_out_n_i(i),
pulse_i => pulse_synched(i),
clr_i => clr_i(i),
level_o => level_synched(i)
);
end generate;
gen_without_level : if (not g_with_pulse2level(i)) generate
level_synched(i) <= pulse_synched(i);
end generate;
level_synched_o(i) <= level_synched(i);
end generate;
end rtl;
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#!/bin/bash
wbgen2 -V acq_core_regs.vhd -H record -p acq_core_regs_pkg.vhd -K ../../../../sim/regs/wb_acq_core_regs.vh -s defines -C wb_acq_core_regs.h -f html -D doc/wb_acq_core.html acq_core.wb
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files = ["wb_acq_core_mux.vhd",
"wb_acq_core_mux_plain.vhd",
"xwb_acq_core_mux.vhd",
];
files = ["wb_afc_diag.vhd",
"xwb_afc_diag.vhd",
"dpram_init.coe",
"shift_reg.v",
"dpram_init.coe",
"shift_reg.v",
"spi2wb_dpram.ngc",
"spi2wb_dpram.v",
"spi2wb.v",
"spi_fifo.ngc",
"spi_fifo.v",
"spi_link_top.vhd",
"spi_link.vhd"
];
SET busformat = BusFormatAngleBracketNotRipped
SET designentry = VHDL
SET device = xc7a200t
SET devicefamily = artix7
SET flowvendor = Other
SET package = ffg1156
SET speedgrade = -2
SET verilogsim = false
SET vhdlsim = true
; Sample initialization file for a
; 32-bit wide by 16 deep RAM
memory_initialization_radix = 16;
memory_initialization_vector =
12345678, ABCDEF11, 22334455, AAA55ABA, A55ABCDE;
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files = [ "wb_dbe_periph.vhd", "xwb_dbe_periph.vhd"];
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