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Beam Positoning Monitor - Gateware
Commit 349c211e authored by Lucas Russo's avatar Lucas Russo
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Merge branch 'phase-sync-trig' into devel

parents ea193f70 9f10a102
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Showing with 15 additions and 2 deletions
dsp-cores @ f1bb430e
Subproject commit ff87c658c5a9858ea496fb208e231f71bbb2e9fe Subproject commit f1bb430e7f14dd6e5b823b8dbe218b6477c62f20
hdl/top/afc_v3/vivado/dbe_bpm_gen/dbe_bpm_gen.vhd
View file @ 349c211e
...@@ -706,8 +706,9 @@ architecture rtl of dbe_bpm_gen is ...@@ -706,8 +706,9 @@ architecture rtl of dbe_bpm_gen is
constant c_acq_monit_amp_id : natural := 16; constant c_acq_monit_amp_id : natural := 16;
constant c_acq_monit_pos_id : natural := 17; constant c_acq_monit_pos_id : natural := 17;
constant c_trigger_sw_clk_id : natural := 18; constant c_trigger_sw_clk_id : natural := 18;
constant c_phase_sync_trigger_id : natural := 19;
constant c_trig_num_channels : natural := 1; constant c_trig_num_channels : natural := 2;
-- Number of channels per acquisition core -- Number of channels per acquisition core
constant c_acq_num_channels : natural := 18; -- ADC + ADC SWAP + MIXER + TBT AMP + TBT POS + constant c_acq_num_channels : natural := 18; -- ADC + ADC SWAP + MIXER + TBT AMP + TBT POS +
-- FOFB AMP + FOFB POS + MONIT AMP + MONIT POS + MONIT1 AMP + -- FOFB AMP + FOFB POS + MONIT AMP + MONIT POS + MONIT1 AMP +
...@@ -2995,6 +2996,12 @@ begin ...@@ -2995,6 +2996,12 @@ begin
----------------------------- -----------------------------
rffe_swclk_o => dsp1_clk_rffe_swap, rffe_swclk_o => dsp1_clk_rffe_swap,
-----------------------------
-- Synchronization trigger for RFFE swap clock
-----------------------------
sync_trig_i => trig_pulse_rcv(c_trig_mux_0_id, c_phase_sync_trigger_id).pulse,
----------------------------- -----------------------------
-- Debug signals -- Debug signals
----------------------------- -----------------------------
...@@ -3213,6 +3220,12 @@ begin ...@@ -3213,6 +3220,12 @@ begin
----------------------------- -----------------------------
rffe_swclk_o => dsp2_clk_rffe_swap, rffe_swclk_o => dsp2_clk_rffe_swap,
-----------------------------
-- Synchronization trigger for RFFE swap clock
-----------------------------
sync_trig_i => trig_pulse_rcv(c_trig_mux_1_id, c_phase_sync_trigger_id).pulse,
----------------------------- -----------------------------
-- Debug signals -- Debug signals
----------------------------- -----------------------------
......
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