hdl/modules/*/fmc_adc_iface.vhd: remove useless module

The sync chains module was just a sync FIFO for synchronizing all data chanins to a single clock domain. however, this synchronization is already done, as all channels are clock-crossed to the same reference clock.

hdl/modules/*/fmc_adc_iface.vhd: remove useless module
The sync chains module was just a sync FIFO for synchronizing all data chanins to a single clock domain. however, this synchronization is already done, as all channels are clock-crossed to the same reference clock.
47275fe5 · Lucas Russo · 8bb854c7 · 47275fe5
Commit 47275fe5 authored Aug 27, 2014 by Lucas Russo
Hide whitespace changes
Inline Side-by-side

Showing with 1 addition and 27 deletions

fmc_adc_iface.vhd hdl/modules/fmc_adc_common/fmc_adc_iface.vhd +1 -27

No files found.
--- a/hdl/modules/fmc_adc_common/fmc_adc_iface.vhd
+++ b/hdl/modules/fmc_adc_common/fmc_adc_iface.vhd
@@ -338,32 +338,6 @@ begin
    end generate;
  end generate;

-  -- We have the possibility that some adc data chains are clocked with
-  -- different source-synchronous clocks. In this case, we need to synchronize
-  -- all data chains to a single clock domain. Need to evaluate its real
-  -- necessity
-
-  cmp_fmc_adc_sync_chains : fmc_adc_sync_chains
-  --generic map (
-  --)
-  port map (
-    sys_clk_i                               => sys_clk_i,
-    --sys_rst_n_i                             => sys_rst_n_i,
-    sys_rst_n_i                             => adc_in_t(c_ref_clk).adc_rst_n,
-
-    -----------------------------
-    -- ADC Data Input signals. Each data chain is synchronous to its
-    -- own clock.
-    -----------------------------
-    adc_out_i                              => adc_out_int,
-
-    -- Reference clock for synchronization with all data chains
-    adc_refclk_i                            => adc_clk_chain_glob_int,
-
-    -----------------------------
-    -- ADC output signals. Synchronous to a single clock
-    -----------------------------
-    adc_out_o                              => adc_out_o
-  );
+  adc_out_o <= adc_out_int;

 end rtl;