Commit 55b4a420 authored by Lucas Russo's avatar Lucas Russo

scripts/*/afc_scansta_cfg.svf: add SCANSTA configuration SVF

In order to program the FPGA via JTAG in the AFCs is necessary to
first configure the SCANSTA chip as a transparent bridge.
parent 47275fe5
// Created using Xilinx Cse Software [ISE - 14.6]
// Date: Thu Aug 21 17:38:25 2014
TRST OFF;
ENDIR IDLE;
ENDDR IDLE;
STATE RESET;
STATE IDLE;
FREQUENCY 1E6 HZ;
//Operation: bsdebug -start
TIR 0 ;
HIR 0 ;
TDR 0 ;
HDR 0 ;
//Operation: bsdebug -reset
TIR 0 ;
HIR 0 ;
TDR 0 ;
HDR 0 ;
//Operation: bsdebug -scanir 00000000
TIR 0 ;
HIR 0 ;
TDR 0 ;
HDR 0 ;
ENDIR IDLE;
SIR 8 TDI (00) SMASK (ff) TDO (ff) MASK (ff) ;
//Operation: bsdebug -scanir 10100000
TIR 0 ;
HIR 0 ;
TDR 0 ;
HDR 0 ;
ENDIR IDLE;
SIR 8 TDI (a0) TDO (01) ;
//Operation: bsdebug -scanir 10100101
TIR 0 ;
HIR 0 ;
TDR 0 ;
HDR 0 ;
ENDIR IDLE;
SIR 8 TDI (a5) TDO (51) ;
//Operation: bsdebug -scandr 01011010
TIR 0 ;
HIR 0 ;
TDR 0 ;
HDR 0 ;
ENDDR IDLE;
SDR 8 TDI (5a) SMASK (ff) TDO (b4) MASK (ff) ;
//Operation: bsdebug -scanir 11000011
TIR 0 ;
HIR 0 ;
TDR 0 ;
HDR 0 ;
ENDIR IDLE;
SIR 8 TDI (c3) TDO (d1) ;
//Operation: bsdebug -scandr 01011010
TIR 0 ;
HIR 0 ;
TDR 0 ;
HDR 0 ;
ENDDR IDLE;
SDR 8 TDI (5a) TDO (00) ;
//Operation: bsdebug -stop
TIR 0 ;
HIR 0 ;
TDR 0 ;
HDR 0 ;
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