Commit 5ec1cba3 authored by Lucas Russo's avatar Lucas Russo

Merge branch 'devel'

parents d520e6f1 db91a531
Subproject commit c544b987e77dde307103cb4114ce26f2d7dbc413
Subproject commit a136c03e7358a6099622d4c36e90a9f97d12dcfa
......@@ -309,6 +309,7 @@ architecture rtl of wb_fmc130m_4ch is
signal fs_rst2x_sync_n : std_logic_vector(c_num_adc_channels-1 downto 0);
signal adc_rst : std_logic; -- ADC reset from wishbone
signal mmcm_adc_locked : std_logic;
signal mmcm_rst_reg : std_logic;
-- ADC clock + data single ended inputs
signal adc_in : t_adc_sdr_in_array(c_num_adc_channels-1 downto 0);
......@@ -964,6 +965,7 @@ begin
fmc_led3_int <= regs_acommon_out.monitor_led3_o;
adc_test_data_en <= regs_acommon_out.monitor_test_data_en_o;
mmcm_rst_reg <= regs_acommon_out.monitor_mmcm_rst_o;
-----------------------------
-- Pins connections for ADC interface structures
......@@ -1096,6 +1098,9 @@ begin
-- ADC clock generation reset. Just a regular asynchronous reset.
sys_clk_200Mhz_i => sys_clk_200Mhz_i,
-- MMCM reset port
mmcm_rst_i => mmcm_rst_reg,
-----------------------------
-- External ports
-----------------------------
......
......@@ -322,6 +322,7 @@ architecture rtl of wb_fmc250m_4ch is
signal fs_rst2x_sync_n : std_logic_vector(c_num_adc_channels-1 downto 0);
signal adc_rst : std_logic; -- ADC reset from wishbone
signal mmcm_adc_locked : std_logic;
signal mmcm_rst_reg : std_logic;
-- ADC clock + data single ended inputs
signal adc_in : t_adc_in_array(c_num_adc_channels-1 downto 0);
......@@ -530,9 +531,9 @@ architecture rtl of wb_fmc250m_4ch is
end component;
begin
-- Reset signals and sychronization with positive edge of
-- respective clock
--sys_rst_n <= sys_rst_n_i and mmcm_adc_locked;
sys_rst_n <= sys_rst_n_i;
fs_rst_n <= sys_rst_n and mmcm_adc_locked;
......@@ -545,9 +546,6 @@ begin
rst_n_o => sys_rst_sync_n
);
--sys_rst_sync_n <= sys_rst_n;
-- Reset synchronization with FS clock domain (just clock 1
-- is used for now). Align the reset deassertion to the next
-- clock edge
......@@ -557,7 +555,6 @@ begin
port map(
clk_i => fs_clk(i),
arst_n_i => fs_rst_n,
--rst_n_o => fs_rst_sync_n
rst_n_o => fs_rst_sync_n(i)
);
......@@ -571,7 +568,6 @@ begin
-- Output adc sync'ed reset to downstream FPGA logic
adc_rst_n_o(i) <= fs_rst_sync_n(i);
adc_rst2x_n_o(i) <= fs_rst2x_sync_n(i);
--fs_rst_sync_n(i) <= fs_rst_n;
end generate;
end generate;
......@@ -979,6 +975,7 @@ begin
fmc_led3_int <= regs_acommon_out.monitor_led3_o;
adc_test_data_en <= regs_acommon_out.monitor_test_data_en_o;
mmcm_rst_reg <= regs_acommon_out.monitor_mmcm_rst_o;
-----------------------------
-- Pins connections for ADC interface structures
......@@ -1120,6 +1117,9 @@ begin
-- ADC clock generation reset. Just a regular asynchronous reset.
sys_clk_200Mhz_i => sys_clk_200Mhz_i,
-- MMCM reset port
mmcm_rst_i => mmcm_rst_reg,
-----------------------------
-- External ports
-----------------------------
......@@ -1245,7 +1245,7 @@ begin
)
port map (
sys_clk_i => sys_clk_i,
sys_rst_n_i => sys_rst_n_i,
sys_rst_n_i => sys_rst_sync_n,
-----------------------------
-- Wishbone Control Interface signals
......
......@@ -308,6 +308,7 @@ architecture rtl of wb_fmc516 is
signal fs_rst_n : std_logic;
signal fs_rst_sync_n : std_logic_vector(c_num_adc_channels-1 downto 0);
signal mmcm_adc_locked : std_logic;
signal mmcm_rst_reg : std_logic := '0';
-- ADC clock + data single ended inputs
signal adc_in : t_adc_in_array(c_num_adc_channels-1 downto 0);
......@@ -1033,6 +1034,9 @@ begin
-- ADC clock generation reset. Just a regular asynchronous reset.
sys_clk_200Mhz_i => sys_clk_200Mhz_i,
-- MMCM reset port
mmcm_rst_i => mmcm_rst_reg,
-----------------------------
-- External ports
-----------------------------
......
......@@ -411,7 +411,24 @@ wb_fmc_adc_common_csr_monitor_led3_o
</td>
<td class="td_pblock_right">
wb_fmc_adc_common_csr_monitor_reserved_i[27:0]
wb_fmc_adc_common_csr_monitor_mmcm_rst_o
</td>
<td class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
wb_fmc_adc_common_csr_monitor_reserved_i[26:0]
</td>
<td class="td_arrow_right">
&lArr;
......@@ -1025,7 +1042,7 @@ MONITOR
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[27:20]
RESERVED[26:19]
</td>
<td >
......@@ -1079,7 +1096,7 @@ RESERVED[27:20]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[19:12]
RESERVED[18:11]
</td>
<td >
......@@ -1133,7 +1150,7 @@ RESERVED[19:12]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
RESERVED[11:4]
RESERVED[10:3]
</td>
<td >
......@@ -1186,8 +1203,11 @@ RESERVED[11:4]
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=4 class="td_field">
RESERVED[3:0]
<td style="border: solid 1px black;" colspan=3 class="td_field">
RESERVED[2:0]
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
MMCM_RST
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
LED3
......@@ -1206,9 +1226,6 @@ TEST_DATA_EN
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
......@@ -1230,6 +1247,10 @@ LED3
</b>[<i>read/write</i>]: Led 3
<br>FMC LED3 (green) - trigger status indicator<br>0 - LED off - LED on
<li><b>
MMCM_RST
</b>[<i>read/write</i>]: MMCM reset
<br>write 1: reset MMCM.<br> write 0: no effect
<li><b>
RESERVED
</b>[<i>read-only</i>]: Reserved
<br>Ignore on read, write with 0's.
......
......@@ -3,7 +3,7 @@
* File : wb_fmc_adc_common_regs.h
* Author : auto-generated by wbgen2 from wb_fmc_adc_common_regs.wb
* Created : Mon Apr 18 09:02:33 2016
* Created : Fri Jul 21 13:54:07 2017
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wb_fmc_adc_common_regs.wb
......@@ -79,11 +79,14 @@
/* definitions for field: Led 3 in reg: Monitor and FMC status control register */
#define WB_FMC_ADC_COMMON_CSR_MONITOR_LED3 WBGEN2_GEN_MASK(3, 1)
/* definitions for field: MMCM reset in reg: Monitor and FMC status control register */
#define WB_FMC_ADC_COMMON_CSR_MONITOR_MMCM_RST WBGEN2_GEN_MASK(4, 1)
/* definitions for field: Reserved in reg: Monitor and FMC status control register */
#define WB_FMC_ADC_COMMON_CSR_MONITOR_RESERVED_MASK WBGEN2_GEN_MASK(4, 28)
#define WB_FMC_ADC_COMMON_CSR_MONITOR_RESERVED_SHIFT 4
#define WB_FMC_ADC_COMMON_CSR_MONITOR_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 4, 28)
#define WB_FMC_ADC_COMMON_CSR_MONITOR_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 4, 28)
#define WB_FMC_ADC_COMMON_CSR_MONITOR_RESERVED_MASK WBGEN2_GEN_MASK(5, 27)
#define WB_FMC_ADC_COMMON_CSR_MONITOR_RESERVED_SHIFT 5
#define WB_FMC_ADC_COMMON_CSR_MONITOR_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 5, 27)
#define WB_FMC_ADC_COMMON_CSR_MONITOR_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 5, 27)
/* [0x0]: REG Status register */
#define WB_FMC_ADC_COMMON_CSR_REG_FMC_STATUS 0x00000000
/* [0x4]: REG Trigger control */
......
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : wb_fmc_adc_common_regs.vhd
-- Author : auto-generated by wbgen2 from wb_fmc_adc_common_regs.wb
-- Created : Mon Apr 18 09:02:33 2016
-- Created : Fri Jul 21 13:54:07 2017
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wb_fmc_adc_common_regs.wb
......@@ -44,6 +44,7 @@ signal wb_fmc_adc_common_csr_monitor_test_data_en_int : std_logic ;
signal wb_fmc_adc_common_csr_monitor_led1_int : std_logic ;
signal wb_fmc_adc_common_csr_monitor_led2_int : std_logic ;
signal wb_fmc_adc_common_csr_monitor_led3_int : std_logic ;
signal wb_fmc_adc_common_csr_monitor_mmcm_rst_int : std_logic ;
signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
......@@ -78,6 +79,7 @@ begin
wb_fmc_adc_common_csr_monitor_led1_int <= '0';
wb_fmc_adc_common_csr_monitor_led2_int <= '0';
wb_fmc_adc_common_csr_monitor_led3_int <= '0';
wb_fmc_adc_common_csr_monitor_mmcm_rst_int <= '0';
elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
......@@ -118,12 +120,14 @@ begin
wb_fmc_adc_common_csr_monitor_led1_int <= wrdata_reg(1);
wb_fmc_adc_common_csr_monitor_led2_int <= wrdata_reg(2);
wb_fmc_adc_common_csr_monitor_led3_int <= wrdata_reg(3);
wb_fmc_adc_common_csr_monitor_mmcm_rst_int <= wrdata_reg(4);
end if;
rddata_reg(0) <= wb_fmc_adc_common_csr_monitor_test_data_en_int;
rddata_reg(1) <= wb_fmc_adc_common_csr_monitor_led1_int;
rddata_reg(2) <= wb_fmc_adc_common_csr_monitor_led2_int;
rddata_reg(3) <= wb_fmc_adc_common_csr_monitor_led3_int;
rddata_reg(31 downto 4) <= regs_i.monitor_reserved_i;
rddata_reg(4) <= wb_fmc_adc_common_csr_monitor_mmcm_rst_int;
rddata_reg(31 downto 5) <= regs_i.monitor_reserved_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when others =>
......@@ -158,6 +162,8 @@ begin
regs_o.monitor_led2_o <= wb_fmc_adc_common_csr_monitor_led2_int;
-- Led 3
regs_o.monitor_led3_o <= wb_fmc_adc_common_csr_monitor_led3_int;
-- MMCM reset
regs_o.monitor_mmcm_rst_o <= wb_fmc_adc_common_csr_monitor_mmcm_rst_int;
-- Reserved
rwaddr_reg <= wb_adr_i;
wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
......
......@@ -139,12 +139,23 @@ peripheral {
access_dev = READ_ONLY;
};
field {
name = "MMCM reset";
description = "write 1: reset MMCM.\
write 0: no effect";
prefix = "mmcm_rst";
-- Pulse to start
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Reserved";
description = "Ignore on read, write with 0's.";
prefix = "reserved";
type = SLV;
size = 28;
size = 27;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
......
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : wb_fmc_adc_common_regs_pkg.vhd
-- Author : auto-generated by wbgen2 from wb_fmc_adc_common_regs.wb
-- Created : Mon Apr 18 09:02:33 2016
-- Created : Fri Jul 21 13:54:07 2017
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wb_fmc_adc_common_regs.wb
......@@ -25,7 +25,7 @@ package wb_fmc_adc_common_csr_wbgen2_pkg is
fmc_status_prst_i : std_logic;
fmc_status_reserved_i : std_logic_vector(27 downto 0);
trigger_reserved_i : std_logic_vector(28 downto 0);
monitor_reserved_i : std_logic_vector(27 downto 0);
monitor_reserved_i : std_logic_vector(26 downto 0);
end record;
constant c_wb_fmc_adc_common_csr_in_registers_init_value: t_wb_fmc_adc_common_csr_in_registers := (
......@@ -47,6 +47,7 @@ package wb_fmc_adc_common_csr_wbgen2_pkg is
monitor_led1_o : std_logic;
monitor_led2_o : std_logic;
monitor_led3_o : std_logic;
monitor_mmcm_rst_o : std_logic;
end record;
constant c_wb_fmc_adc_common_csr_out_registers_init_value: t_wb_fmc_adc_common_csr_out_registers := (
......@@ -56,7 +57,8 @@ package wb_fmc_adc_common_csr_wbgen2_pkg is
monitor_test_data_en_o => '0',
monitor_led1_o => '0',
monitor_led2_o => '0',
monitor_led3_o => '0'
monitor_led3_o => '0',
monitor_mmcm_rst_o => '0'
);
function "or" (left, right: t_wb_fmc_adc_common_csr_in_registers) return t_wb_fmc_adc_common_csr_in_registers;
function f_x_to_zero (x:std_logic) return std_logic;
......
......@@ -26,6 +26,7 @@ use unisim.vcomponents.all;
library work;
use work.fmc_adc_pkg.all;
use work.gencores_pkg.all;
entity fmc_adc_clk is
generic
......@@ -49,6 +50,9 @@ port
sys_clk_200Mhz_i : in std_logic;
sys_rst_i : in std_logic;
-- MMCM reset port
mmcm_rst_i : in std_logic := '0';
-----------------------------
-- External ports
-----------------------------
......@@ -79,8 +83,16 @@ end fmc_adc_clk;
architecture rtl of fmc_adc_clk is
constant c_num_tlvl_clks : natural := 3; -- CLK_SYS, FS_CLK, FS_CLK2x
constant c_clk_sys_id : natural := 0;
constant c_clk_adc_id : natural := 1;
constant c_clk_adc2x_id : natural := 2;
alias c_mmcm_param is g_mmcm_param;
signal reset_clks : std_logic_vector(c_num_tlvl_clks-1 downto 0);
signal reset_rstn : std_logic_vector(c_num_tlvl_clks-1 downto 0);
-- Clock and reset signals
signal adc_clk_ibufgds : std_logic;
signal adc_clk_ibufgds_dly : std_logic;
......@@ -105,6 +117,8 @@ architecture rtl of fmc_adc_clk is
signal adc_clk_mmcm_out : std_logic;
signal adc_clk2x_mmcm_out : std_logic;
signal mmcm_adc_locked_int : std_logic;
signal mmcm_adc_locked_sync : std_logic;
signal mmcm_rst_int : std_logic;
-- Clock delay signals
signal iodelay_update : std_logic;
......@@ -427,9 +441,11 @@ begin
CLKINSTOPPED => open,
CLKFBSTOPPED => open,
PWRDWN => '0',
RST => sys_rst_i
RST => mmcm_rst_int
);
mmcm_rst_int <= sys_rst_i or mmcm_rst_i;
-- Global clock buffer for MMCM feedback. Deskew MMCM configuration
cmp_adc_clk_fb_bufg : BUFG
port map(
......@@ -452,6 +468,25 @@ begin
end generate;
-- Generate a well-behaved MMCM locked, to be used as a reset signal
cmp_reset : gc_reset
generic map(
g_clocks => c_num_tlvl_clks
)
port map(
free_clk_i => sys_clk_i,
locked_i => mmcm_adc_locked_int,
clks_i => reset_clks,
rstn_o => reset_rstn
);
reset_clks(c_clk_sys_id) <= sys_clk_i;
reset_clks(c_clk_adc_id) <= adc_clk_bufg;
reset_clks(c_clk_adc2x_id) <= adc_clk2x_bufg;
-- Use the slower clock to sync
mmcm_adc_locked_sync <= reset_rstn(c_clk_adc_id);
-- Only instantiate BUFG if BUFIO and BUFR not selected and not a reference clock
gen_without_ref_clk : if (not g_with_ref_clk) generate
......@@ -518,7 +553,7 @@ begin
end generate;
gen_true_mmcm_lock_ref_clk : if (g_with_ref_clk) generate
adc_clk_chain_glob_o.mmcm_adc_locked <= mmcm_adc_locked_int;
adc_clk_chain_glob_o.mmcm_adc_locked <= mmcm_adc_locked_sync;
end generate;
gen_false_mmcm_lock_ref_clk : if (not g_with_ref_clk) generate
......
......@@ -74,6 +74,9 @@ port
sys_rst_n_i : in std_logic;
sys_clk_200Mhz_i : in std_logic;
-- MMCM reset port
mmcm_rst_i : in std_logic := '0';
-----------------------------
-- External ports
-----------------------------
......@@ -228,6 +231,9 @@ begin
sys_clk_200Mhz_i => sys_clk_200Mhz_i,
sys_rst_i => sys_rst,
-- MMCM reset port
mmcm_rst_i => mmcm_rst_i,
-----------------------------
-- External ports
-----------------------------
......
......@@ -361,6 +361,9 @@ package fmc_adc_pkg is
-- ADC clocks. One clock per ADC channel
adc_clk_i : in std_logic;
-- MMCM reset port
mmcm_rst_i : in std_logic := '0';
-----------------------------
-- ADC Delay signals.
-----------------------------
......@@ -474,6 +477,9 @@ package fmc_adc_pkg is
sys_rst_n_i : in std_logic;
sys_clk_200Mhz_i : in std_logic;
-- MMCM reset port
mmcm_rst_i : in std_logic := '0';
-----------------------------
-- External ports
-----------------------------
......
......@@ -25,5 +25,7 @@
`define WB_FMC_ADC_COMMON_CSR_MONITOR_LED2 32'h00000004
`define WB_FMC_ADC_COMMON_CSR_MONITOR_LED3_OFFSET 3
`define WB_FMC_ADC_COMMON_CSR_MONITOR_LED3 32'h00000008
`define WB_FMC_ADC_COMMON_CSR_MONITOR_RESERVED_OFFSET 4
`define WB_FMC_ADC_COMMON_CSR_MONITOR_RESERVED 32'hfffffff0
`define WB_FMC_ADC_COMMON_CSR_MONITOR_MMCM_RST_OFFSET 4
`define WB_FMC_ADC_COMMON_CSR_MONITOR_MMCM_RST 32'h00000010
`define WB_FMC_ADC_COMMON_CSR_MONITOR_RESERVED_OFFSET 5
`define WB_FMC_ADC_COMMON_CSR_MONITOR_RESERVED 32'hffffffe0
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