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Beam Positoning Monitor - Gateware
Commit b985100a authored by Lucas Russo's avatar Lucas Russo
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update initial design

parent c9217ac1
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hdl/modules/custom_wishbone/Manifest.py
View file @ b985100a
files = [ "custom_wishbone_pkg.vhd" ];
modules = { "local" : [
# "wb_irq_mngr",
# "wb_dma_interface" ,
"wb_stream",
"wb_fmc150"
] };
files = [ "custom_wishbone_pkg.vhd" ];
] };
hdl/modules/custom_wishbone/wb_fmc150/Makefile 0 → 100644
View file @ b985100a
########################################
# This file was generated by hdlmake #
# http://ohwr.org/projects/hdl-make/ #
########################################
## variables #############################
PWD := $(shell pwd)
TOP_MODULE :=
FUSE_OUTPUT ?= isim_proj
XILINX_INI_PATH := /opt/Xilinx/13.4/ISE_DS/ISE/vhdl/hdp/lin64
VHPCOMP_FLAGS := -intstyle default -incremental -initfile xilinxsim.ini
ISIM_FLAGS :=
VLOGCOMP_FLAGS := -intstyle default -incremental -initfile xilinxsim.ini
VERILOG_SRC :=
VERILOG_OBJ :=
VHDL_SRC := wb_fmc150.vhd \
xwb_fmc150.vhd \
xfmc150_regs_pkg.vhd \
wb_fmc150_port.vhd \
adc/adc_channel_lvds_ddr.vhd \
adc/adc_pkg.vhd \
adc/strobe_lvds.vhd \
fmc150/ads62p49_ctrl.vhd \
fmc150/amc7823_ctrl.vhd \
fmc150/cdce72010_ctrl.vhd \
fmc150/dac3283_ctrl.vhd \
fmc150/fmc150_adc_if.vhd \
fmc150/fmc150_dac_if.vhd \
fmc150/fmc150_pkg.vhd \
fmc150/fmc150_spi_ctrl.vhd \
fmc150/fmc150_stellar_cmd.vhd \
fmc150/fmc150_testbench.vhd \
fmc150/pulse2pulse.vhd \
VHDL_OBJ := work/wb_fmc150/.wb_fmc150_vhd \
work/xwb_fmc150/.xwb_fmc150_vhd \
work/xfmc150_regs_pkg/.xfmc150_regs_pkg_vhd \
work/wb_fmc150_port/.wb_fmc150_port_vhd \
work/adc_channel_lvds_ddr/.adc_channel_lvds_ddr_vhd \
work/adc_pkg/.adc_pkg_vhd \
work/strobe_lvds/.strobe_lvds_vhd \
work/ads62p49_ctrl/.ads62p49_ctrl_vhd \
work/amc7823_ctrl/.amc7823_ctrl_vhd \
work/cdce72010_ctrl/.cdce72010_ctrl_vhd \
work/dac3283_ctrl/.dac3283_ctrl_vhd \
work/fmc150_adc_if/.fmc150_adc_if_vhd \
work/fmc150_dac_if/.fmc150_dac_if_vhd \
work/fmc150_pkg/.fmc150_pkg_vhd \
work/fmc150_spi_ctrl/.fmc150_spi_ctrl_vhd \
work/fmc150_stellar_cmd/.fmc150_stellar_cmd_vhd \
work/fmc150_testbench/.fmc150_testbench_vhd \
work/pulse2pulse/.pulse2pulse_vhd \
LIBS := work
LIB_IND := work/.work
## rules #################################
sim: xilinxsim.ini $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ)
$(VERILOG_OBJ): $(VHDL_OBJ)
$(VHDL_OBJ): $(LIB_IND) xilinxsim.ini
xilinxsim.ini: $(XILINX_INI_PATH)/xilinxsim.ini
cp $< .
fuse: ;
ifeq ($(TOP_MODULE),)
@echo "Environment variable TOP_MODULE not set!"
else
fuse work.$(TOP_MODULE) -intstyle ise -incremental -o $(FUSE_OUTPUT)
endif
clean:
rm -rf ./xilinxsim.ini $(LIBS) fuse.xmsgs fuse.log fuseRelaunch.cmd isim isim.log isim.wdb
.PHONY: clean
work/.work:
(mkdir work && touch work/.work && echo "work=work" >> xilinxsim.ini) || rm -rf work
work/wb_fmc150/.wb_fmc150_vhd: wb_fmc150.vhd work/wb_fmc150/.wb_fmc150
vhpcomp $(VHPCOMP_FLAGS) -work work=./work $<
@mkdir -p $(dir $@) && touch $@
work/wb_fmc150/.wb_fmc150:
work/xwb_fmc150/.xwb_fmc150_vhd: xwb_fmc150.vhd work/xwb_fmc150/.xwb_fmc150
vhpcomp $(VHPCOMP_FLAGS) -work work=./work $<
@mkdir -p $(dir $@) && touch $@
work/xwb_fmc150/.xwb_fmc150:
work/xfmc150_regs_pkg/.xfmc150_regs_pkg_vhd: xfmc150_regs_pkg.vhd work/xfmc150_regs_pkg/.xfmc150_regs_pkg
vhpcomp $(VHPCOMP_FLAGS) -work work=./work $<
@mkdir -p $(dir $@) && touch $@
work/xfmc150_regs_pkg/.xfmc150_regs_pkg:
work/wb_fmc150_port/.wb_fmc150_port_vhd: wb_fmc150_port.vhd work/wb_fmc150_port/.wb_fmc150_port
vhpcomp $(VHPCOMP_FLAGS) -work work=./work $<
@mkdir -p $(dir $@) && touch $@
work/wb_fmc150_port/.wb_fmc150_port: \
work/xfmc150_regs_pkg/.xfmc150_regs_pkg_vhd
work/adc_channel_lvds_ddr/.adc_channel_lvds_ddr_vhd: adc/adc_channel_lvds_ddr.vhd work/adc_channel_lvds_ddr/.adc_channel_lvds_ddr
vhpcomp $(VHPCOMP_FLAGS) -work work=./work $<
@mkdir -p $(dir $@) && touch $@
work/adc_channel_lvds_ddr/.adc_channel_lvds_ddr:
work/adc_pkg/.adc_pkg_vhd: adc/adc_pkg.vhd work/adc_pkg/.adc_pkg
vhpcomp $(VHPCOMP_FLAGS) -work work=./work $<
@mkdir -p $(dir $@) && touch $@
work/adc_pkg/.adc_pkg:
work/strobe_lvds/.strobe_lvds_vhd: adc/strobe_lvds.vhd work/strobe_lvds/.strobe_lvds
vhpcomp $(VHPCOMP_FLAGS) -work work=./work $<
@mkdir -p $(dir $@) && touch $@
work/strobe_lvds/.strobe_lvds:
work/ads62p49_ctrl/.ads62p49_ctrl_vhd: fmc150/ads62p49_ctrl.vhd work/ads62p49_ctrl/.ads62p49_ctrl
vhpcomp $(VHPCOMP_FLAGS) -work work=./work $<
@mkdir -p $(dir $@) && touch $@
work/ads62p49_ctrl/.ads62p49_ctrl:
work/amc7823_ctrl/.amc7823_ctrl_vhd: fmc150/amc7823_ctrl.vhd work/amc7823_ctrl/.amc7823_ctrl
vhpcomp $(VHPCOMP_FLAGS) -work work=./work $<
@mkdir -p $(dir $@) && touch $@
work/amc7823_ctrl/.amc7823_ctrl:
work/cdce72010_ctrl/.cdce72010_ctrl_vhd: fmc150/cdce72010_ctrl.vhd work/cdce72010_ctrl/.cdce72010_ctrl
vhpcomp $(VHPCOMP_FLAGS) -work work=./work $<
@mkdir -p $(dir $@) && touch $@
work/cdce72010_ctrl/.cdce72010_ctrl:
work/dac3283_ctrl/.dac3283_ctrl_vhd: fmc150/dac3283_ctrl.vhd work/dac3283_ctrl/.dac3283_ctrl
vhpcomp $(VHPCOMP_FLAGS) -work work=./work $<
@mkdir -p $(dir $@) && touch $@
work/dac3283_ctrl/.dac3283_ctrl:
work/fmc150_adc_if/.fmc150_adc_if_vhd: fmc150/fmc150_adc_if.vhd work/fmc150_adc_if/.fmc150_adc_if
vhpcomp $(VHPCOMP_FLAGS) -work work=./work $<
@mkdir -p $(dir $@) && touch $@
work/fmc150_adc_if/.fmc150_adc_if: \
work/adc_pkg/.adc_pkg_vhd
work/fmc150_dac_if/.fmc150_dac_if_vhd: fmc150/fmc150_dac_if.vhd work/fmc150_dac_if/.fmc150_dac_if
vhpcomp $(VHPCOMP_FLAGS) -work work=./work $<
@mkdir -p $(dir $@) && touch $@
work/fmc150_dac_if/.fmc150_dac_if:
work/fmc150_pkg/.fmc150_pkg_vhd: fmc150/fmc150_pkg.vhd work/fmc150_pkg/.fmc150_pkg
vhpcomp $(VHPCOMP_FLAGS) -work work=./work $<
@mkdir -p $(dir $@) && touch $@
work/fmc150_pkg/.fmc150_pkg:
work/fmc150_spi_ctrl/.fmc150_spi_ctrl_vhd: fmc150/fmc150_spi_ctrl.vhd work/fmc150_spi_ctrl/.fmc150_spi_ctrl
vhpcomp $(VHPCOMP_FLAGS) -work work=./work $<
@mkdir -p $(dir $@) && touch $@
work/fmc150_spi_ctrl/.fmc150_spi_ctrl:
work/fmc150_stellar_cmd/.fmc150_stellar_cmd_vhd: fmc150/fmc150_stellar_cmd.vhd work/fmc150_stellar_cmd/.fmc150_stellar_cmd
vhpcomp $(VHPCOMP_FLAGS) -work work=./work $<
@mkdir -p $(dir $@) && touch $@
work/fmc150_stellar_cmd/.fmc150_stellar_cmd:
work/fmc150_testbench/.fmc150_testbench_vhd: fmc150/fmc150_testbench.vhd work/fmc150_testbench/.fmc150_testbench
vhpcomp $(VHPCOMP_FLAGS) -work work=./work $<
@mkdir -p $(dir $@) && touch $@
work/fmc150_testbench/.fmc150_testbench: \
work/fmc150_pkg/.fmc150_pkg_vhd
work/pulse2pulse/.pulse2pulse_vhd: fmc150/pulse2pulse.vhd work/pulse2pulse/.pulse2pulse
vhpcomp $(VHPCOMP_FLAGS) -work work=./work $<
@mkdir -p $(dir $@) && touch $@
work/pulse2pulse/.pulse2pulse:
hdl/modules/custom_wishbone/wb_fmc150/output 0 → 100644
View file @ b985100a
This diff is collapsed.
hdl/modules/custom_wishbone/wb_fmc150/wb_fmc150.vhd
View file @ b985100a
......@@ -3,12 +3,14 @@ use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.wb_fmc150_pkg.all;
--use work.wb_fmc150_pkg.all;
use work.wb_stream_pkg.all;
entity wb_fmc150 is
generic
(
g_interface_mode : t_wishbone_interface_mode := PIPELINED;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_packet_size : natural := 32
);
port
......@@ -112,15 +114,15 @@ architecture rtl of wb_fmc150 is
-----------------------------------------------------------------------------------------------
-- IP / user logic interface signals
-----------------------------------------------------------------------------------------------
--signal s_adc_dout : std_logic_vector(31 downto 0);
--signal s_clk_adc : std_logic;
-- wb_fmc150 reg structure
signal regs_in : t_fmc150_out_registers;
signal regs_out : t_fmc150_in_registers;
-- Stream nterface structure
signal wbs_stream_out : t_wbs_source_out;
signal wbs_stream_in : t_wbs_source_in;
-- FMC 150 testbench
-- FMC 150 testbench signals
signal cdce_pll_status : std_logic;
signal s_mmcm_adc_locked : std_logic;
......@@ -138,35 +140,16 @@ architecture rtl of wb_fmc150 is
signal s_bytesel : std_logic_vector((c_wbs_data_width/8)-1 downto 0);
signal s_dreq : std_logic;
begin
-- Glue logic
--adc_dout_o <= s_adc_dout;
--clk_adc_o <= s_clk_adc;
-- Wishbone adapter structures
signal wb_out : t_wishbone_slave_out;
signal wb_in : t_wishbone_slave_in;
signal resized_addr : std_logic_vector(c_wishbone_address_width-1 downto 0);
begin
-----------------------------------------------------------------------------------------------
-- BUS / IP interface
-----------------------------------------------------------------------------------------------
--s_clk_out_pulse_sync(0) <= clk_100Mhz;
--gen_pulse_register_sync : for i in 0 to (C_SLV_DWIDTH/2)-1 generate
--
-- cmp_adc_delay_update : pulse2pulse
-- port map
-- (
-- in_clk => Bus2IP_Clk,
-- out_clk => s_clk_out_pulse_sync(i),
-- rst => not Bus2IP_Resetn,
-- pulsein => s_registers(FLAGS_PULSE_0)(i),
-- inbusy => open,
-- pulseout => s_pulse_register_sync(i)
-- );
--
--end generate;
--
--s_adc_delay_update <= s_pulse_register_sync(0);
cmp_fmc150_testbench: fmc150_testbench
port map
......@@ -236,19 +219,50 @@ begin
regs_out.flgs_out_pll_status_i <= cdce_pll_status;
regs_out.flgs_out_adc_clk_locked_i <= s_mmcm_adc_locked;
-- Pipelined <--> Classic cycles / Word <--> Byte address granularity
-- conversion
cmp_adapter : wb_slave_adapter
generic map (
g_master_use_struct => true,
g_master_mode => PIPELINED,
g_master_granularity => WORD,
g_slave_use_struct => false,
g_slave_mode => g_interface_mode,
g_slave_granularity => g_address_granularity)
port map (
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
master_i => wb_out,
master_o => wb_in,
sl_adr_i => resized_addr,
sl_dat_i => wb_dat_i,
sl_sel_i => wb_sel_i,
sl_cyc_i => wb_cyc_i,
sl_stb_i => wb_stb_i,
sl_we_i => wb_we_i,
sl_dat_o => wb_dat_o,
sl_ack_o => wb_ack_o,
sl_stall_o => wb_stall_o
);
resized_addr(2 downto 0) <= wb_adr_i(2 downto 0);
resized_addr(c_wishbone_address_width-1 downto 3)
<= (others => '0');
-- Register Bank / Wishbone Interface
cmp_wb_fmc150_port : wb_fmc150_port
port map (
rst_n_i => rst_n_i,
clk_sys_i => clk_sys_i,
wb_adr_i => wb_adr_i,
wb_dat_i => wb_dat_i,
wb_dat_o => wb_dat_o,
wb_cyc_i => wb_cyc_i,
wb_sel_i => wb_sel_i,
wb_stb_i => wb_stb_i,
wb_we_i => wb_we_i,
wb_ack_o => wb_ack_o,
wb_stall_o => wb_stall_o,
wb_adr_i => wb_in.adr(2 downto 0),
wb_dat_i => wb_in.dat,
wb_dat_o => wb_out.dat,
wb_cyc_i => wb_in.cyc,
wb_sel_i => wb_in.sel,
wb_stb_i => wb_in.stb,
wb_we_i => wb_in.we,
wb_ack_o => wb_out.ack,
wb_stall_o => wb_out.stall,
clk_100Mhz => clk_100_i,
regs_i => regs_out,
regs_o => regs_in
......@@ -278,7 +292,6 @@ begin
s_data <= s_adc_dout;
s_dvalid <= cdce_pll_status and s_mmcm_adc_locked;
p_gen_sof_eof : process(s_clk_adc, rst_n_i)
begin
if rst_n_i = '0' then
......
hdl/modules/custom_wishbone/wb_fmc150/wb_fmc150_port.vhd
View file @ b985100a
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : wb_fmc150_port.vhd
-- Author : auto-generated by wbgen2 from xfmc150.wb
-- Created : Mon Oct 1 15:20:18 2012
-- Created : Tue Oct 2 09:38:47 2012
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE xfmc150.wb
......
hdl/modules/custom_wishbone/wb_fmc150/xfmc150_regs_pkg.vhd
View file @ b985100a
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : xfmc150_regs_pkg.vhd
-- Author : auto-generated by wbgen2 from xfmc150.wb
-- Created : Mon Oct 1 15:20:18 2012
-- Created : Tue Oct 2 09:38:47 2012
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE xfmc150.wb
......
hdl/modules/custom_wishbone/wb_fmc150/xfmc150_regs_regs.h
View file @ b985100a
......@@ -3,7 +3,7 @@
* File : xfmc150_regs_regs.h
* Author : auto-generated by wbgen2 from xfmc150.wb
* Created : Mon Oct 1 15:20:18 2012
* Created : Tue Oct 2 09:38:47 2012
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE xfmc150.wb
......
hdl/modules/custom_wishbone/wb_stream/Manifest.py
View file @ b985100a
files = ["wb_stream_pkg.vhd", "xwb_stream_sink.vhd", "xwb_stream_source.vhd"]
files = ["wb_stream_pkg.vhd", "xwb_stream_sink.vhd", "xwb_stream_source.vhd"];
hdl/modules/custom_wishbone/wb_stream/wb_stream_pkg.vhd
View file @ b985100a
......@@ -3,6 +3,7 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package wb_stream_pkg is
-- Must be at least 2 bits wide
......@@ -17,15 +18,15 @@ package wb_stream_pkg is
subtype t_wbs_byte_select is
std_logic_vector((c_wbs_data_width/8)-1 downto 0);
constant c_WRF_DATA : unsigned(c_wbs_address_width-1 downto 0) := 0;
constant c_WRF_OOB : unsigned(c_wbs_address_width-1 downto 0) := 1;
constant c_WRF_STATUS : unsigned(c_wbs_address_width-1 downto 0) := 2;
constant c_WRF_USER : unsigned(c_wbs_address_width-1 downto 0) := 3;
constant c_WRF_DATA : unsigned(c_wbs_address_width-1 downto 0) := to_unsigned(0, c_wbs_address_width);
constant c_WRF_OOB : unsigned(c_wbs_address_width-1 downto 0) := to_unsigned(1, c_wbs_address_width);
constant c_WRF_STATUS : unsigned(c_wbs_address_width-1 downto 0) := to_unsigned(2, c_wbs_address_width);
constant c_WRF_USER : unsigned(c_wbs_address_width-1 downto 0) := to_unsigned(3, c_wbs_address_width);
--constant c_WRF_OOB_TYPE_RX : std_logic_vector(3 downto 0) := "0000";
--constant c_WRF_OOB_TYPE_TX : std_logic_vector(3 downto 0) := "0001";
type t_wb_stream_status_reg is record
type t_wbs_status_reg is record
is_hp : std_logic;
has_smac : std_logic;
has_crc : std_logic;
......@@ -36,7 +37,7 @@ package wb_stream_pkg is
type t_wbs_source_out is record
adr : t_wbs_address;
dat : c_wbs_data_width;
dat : t_wbs_data;
cyc : std_logic;
stb : std_logic;
we : std_logic;
......@@ -68,7 +69,7 @@ package wb_stream_pkg is
subtype t_wbs_sink_in_array is t_wbs_source_out_array;
subtype t_wbs_sink_out_array is t_wbs_source_in_array;
function f_marshall_wbs_status (stat : t_wrf_status_reg) return std_logic_vector;
function f_marshall_wbs_status (stat : t_wbs_status_reg) return std_logic_vector;
function f_unmarshall_wbs_status(stat : std_logic_vector) return t_wbs_status_reg;
constant cc_dummy_wbs_addr : std_logic_vector(c_wbs_address_width-1 downto 0):=
......@@ -82,13 +83,59 @@ package wb_stream_pkg is
('0', '0', '0', '0');
constant c_dummy_snk_in : t_wbs_sink_in :=
(cc_dummy_wbs_addr, cc_dummy_wbs_dat, '0', '0', '0', cc_dummy_wbs_sel);
-- Components
component xwb_stream_source
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Wishbone Fabric Interface I/O
src_i : in t_wbs_source_in;
src_o : out t_wbs_source_out;
-- Decoded & buffered logic
addr_i : in std_logic_vector(c_wbs_address_width-1 downto 0);
data_i : in std_logic_vector(c_wbs_data_width-1 downto 0);
dvalid_i : in std_logic;
sof_i : in std_logic;
eof_i : in std_logic;
error_i : in std_logic;
bytesel_i : in std_logic;
dreq_o : out std_logic
);
end component;
component xwb_stream_sink
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Wishbone Fabric Interface I/O
snk_i : in t_wbs_sink_in;
snk_o : out t_wbs_sink_out;
-- Decoded & buffered fabric
addr_o : out std_logic_vector(c_wbs_address_width-1 downto 0);
data_o : out std_logic_vector(c_wbs_data_width-1 downto 0);
dvalid_o : out std_logic;
sof_o : out std_logic;
eof_o : out std_logic;
error_o : out std_logic;
bytesel_o : out std_logic;
dreq_i : in std_logic
);
end component;
end wb_stream_pkg;
package body wb_stream_pkg is
package body wb_stream_pkg is
function f_marshall_wbs_status(stat : t_wbs_status_reg)
return std_logic_vector is
return std_logic_vector
is
-- Wishbone bus data_width is at least 16 bits
variable tmp : std_logic_vector(c_wbs_data_width-1 downto 0);
begin
......@@ -98,9 +145,11 @@ package body wb_stream_pkg is
tmp(3) := stat.has_crc;
tmp(15 downto 8) := stat.match_class;
return tmp;
end function;
end;
function f_unmarshall_wbs_status(stat : std_logic_vector) return t_wbs_status_reg is
function f_unmarshall_wbs_status(stat : std_logic_vector)
return t_wbs_status_reg
is
variable tmp : t_wbs_status_reg;
begin
tmp.is_hp := stat(0);
......@@ -109,7 +158,6 @@ package body wb_stream_pkg is
tmp.has_crc := stat(3);
tmp.match_class := stat(15 downto 8);
return tmp;
end function;
end;
end wb_stream_pkg;
hdl/sim/regs/xctl_iface_regs.vh deleted 100644 → 0
View file @ c9217ac1
`define ADDR_CTL_IFACE_CTL 3'h0
`define CTL_IFACE_CTL_START_OFFSET 0
`define CTL_IFACE_CTL_START 32'h00000001
`define CTL_IFACE_CTL_DONE_OFFSET 1
`define CTL_IFACE_CTL_DONE 32'h00000002
`define CTL_IFACE_CTL_OVF_OFFSET 2
`define CTL_IFACE_CTL_OVF 32'h00000004
`define ADDR_CTL_IFACE_TR_CNTR 3'h4
hdl/sim/regs/xdata_sink_regs.vh deleted 100644 → 0
View file @ c9217ac1
`define ADDR_DATA_SINK_FIFO_C2B_R0 4'h0
`define DATA_SINK_FIFO_C2B_R0_DATA_OFFSET 0
`define DATA_SINK_FIFO_C2B_R0_DATA 32'hffffffff
`define ADDR_DATA_SINK_FIFO_C2B_R1 4'h4
`define DATA_SINK_FIFO_C2B_R1_LAST_OFFSET 0
`define DATA_SINK_FIFO_C2B_R1_LAST 32'h00000001
`define ADDR_DATA_SINK_FIFO_C2B_CSR 4'h8
`define DATA_SINK_FIFO_C2B_CSR_FULL_OFFSET 16
`define DATA_SINK_FIFO_C2B_CSR_FULL 32'h00010000
`define DATA_SINK_FIFO_C2B_CSR_EMPTY_OFFSET 17
`define DATA_SINK_FIFO_C2B_CSR_EMPTY 32'h00020000
`define DATA_SINK_FIFO_C2B_CSR_USEDW_OFFSET 0
`define DATA_SINK_FIFO_C2B_CSR_USEDW 32'h000000ff
hdl/sim/regs/xdata_src_regs.vh deleted 100644 → 0
View file @ c9217ac1
`define ADDR_DATA_SRC_B2C_R0 3'h0
`define DATA_SRC_B2C_R0_DATA_OFFSET 0
`define DATA_SRC_B2C_R0_DATA 32'hffffffff
`define ADDR_DATA_SRC_B2C_CSR 3'h4
`define DATA_SRC_B2C_CSR_FULL_OFFSET 16
`define DATA_SRC_B2C_CSR_FULL 32'h00010000
`define DATA_SRC_B2C_CSR_EMPTY_OFFSET 17
`define DATA_SRC_B2C_CSR_EMPTY 32'h00020000
`define DATA_SRC_B2C_CSR_USEDW_OFFSET 0
`define DATA_SRC_B2C_CSR_USEDW 32'h000000ff
hdl/sim/wishbone_test_master/wishbone_test_master.v → hdl/sim/wishbone_test_master.v
View file @ b985100a
......@@ -71,7 +71,6 @@ module WB_TEST_MASTER;
begin
wb_monitor_bus = onoff;
end
endtask // monitor_bus
task rw_generic;
......@@ -189,4 +188,4 @@ module WB_TEST_MASTER;
endmodule
\ No newline at end of file
endmodule
hdl/testbench/wishbone/wb_fmc150_test/Makefile 0 → 100644
View file @ b985100a
This diff is collapsed.
hdl/testbench/wishbone/wb_fmc150_test/Manifest.py 0 → 100644
View file @ b985100a
action = "simulation"
target = "xilinx"
modules = {"local" : [ "../../.." ] };
files = ["wb_fmc150_tb.vhd"]
#vlog_opt = -i ../../../sim/regs -i ../../../sim
hdl/testbench/wishbone/wb_fmc150_test/fuse.xmsgs 0 → 100644
View file @ b985100a
<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="error" file="HDLCompiler" num="69" delta="unknown" >"../../../modules/custom_wishbone/custom_wishbone_pkg.vhd" Line 198: &lt;<arg fmt="%s" index="1">c_wbs_address_width</arg>&gt; is not declared.
</msg>
<msg type="error" file="HDLCompiler" num="69" delta="unknown" >"../../../modules/custom_wishbone/custom_wishbone_pkg.vhd" Line 199: &lt;<arg fmt="%s" index="1">c_wbs_data_width</arg>&gt; is not declared.
</msg>
<msg type="error" file="HDLCompiler" num="69" delta="unknown" >"../../../modules/custom_wishbone/custom_wishbone_pkg.vhd" Line 203: &lt;<arg fmt="%s" index="1">c_wbs_data_width</arg>&gt; is not declared.
</msg>
<msg type="error" file="HDLCompiler" num="806" delta="unknown" >"../../../modules/custom_wishbone/custom_wishbone_pkg.vhd" Line 212: Syntax error near &quot;<arg fmt="%s" index="1">entity</arg>&quot;.
</msg>
<msg type="error" file="HDLCompiler" num="854" delta="unknown" >"../../../modules/custom_wishbone/custom_wishbone_pkg.vhd" Line 7: Unit &lt;<arg fmt="%s" index="1">custom_wishbone_pkg</arg>&gt; ignored due to previous errors.
</msg>
</messages>
hdl/testbench/wishbone/wb_fmc150_test/output 0 → 100644
View file @ b985100a
This diff is collapsed.
hdl/testbench/wishbone/wb_fmc150_test/run.do 0 → 100644
View file @ b985100a
make
vsim -L XilinxCoreLib -L secureip -L unisim work.main -voptargs="+acc"
radix -hexadecimal
do wave.do
set StdArithNoWarnings 1
set NumericStdNoWarnings 1
run 100us
wave zoomfull
\ No newline at end of file
hdl/testbench/wishbone/wb_fmc150_test/wave.do 0 → 100644
View file @ b985100a
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate /main/clk_sys
add wave -noupdate /main/DUT/U_CPU/dwb_o
add wave -noupdate /main/DUT/U_CPU/dwb_i
add wave -noupdate /main/DUT/U_Intercon/granted
add wave -noupdate /main/DUT/U_CPU/gen_profile_medium/U_Wrapped_LM32/D_STB_O
add wave -noupdate /main/DUT/U_CPU/gen_profile_medium/U_Wrapped_LM32/D_ACK_I
add wave -noupdate /main/DUT/U_CPU/data_was_busy
add wave -noupdate /main/DUT/U_CPU/data_addr_reg
add wave -noupdate /main/DUT/U_CPU/data_remaining
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {2672526 ps} 0}
configure wave -namecolwidth 350
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 1
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {2262366 ps} {3082686 ps}
hdl/testbench/wishbone/wb_fmc150_test/wb_fmc150_tb.vhd 0 → 100644
View file @ b985100a
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.wishbone_pkg.all;
use work.custom_wishbone_pkg.all;
use work.wb_stream_pkg.all;
entity wb_fmc150_tb is
end wb_fmc150_tb;
architecture sim of wb_fmc150_tb is
-- Constants
-- 100.00 MHz clock
constant c_100mhz_clk_period : time := 10.00 ns;
-- 200.00 MHz clock
constant c_200mhz_clk_period : time := 5.00 ns;
constant c_sim_time : time := 10000.00 ns;
signal g_end_simulation : boolean := false; -- Set to true to halt the simulation
-- Clock signals
signal clk_100mhz : std_logic := '0';
signal clk_200mhz : std_logic := '0';
signal clk_sys : std_logic := '0';
signal rst_n_i : std_logic := '0';
-- Wishbone signals
signal wb_slv_in : t_wishbone_slave_in := cc_dummy_slave_in;
signal wb_slv_out : t_wishbone_slave_out;
signal wbs_src_in : t_wbs_source_in := c_dummy_src_in;
signal wbs_src_out : t_wbs_source_out;
-- Dummy signals
constant cc_dummy_bit : std_logic := '0';
constant cc_dummy_slv : std_logic_vector := '0';
-- Generate dummy (0) values
function f_zeros(size : integer)
return std_logic_vector is
begin
return std_logic_vector(to_unsigned(0, size));
end f_zeros;
begin -- sim
p_100mhz_clk_gen : process
begin
while g_end_simulation = false loop
wait for c_100mhz_clk_period/2;
clk_100mhz <= not clk_100mhz;
wait for c_100mhz_clk_period/2;
clk_100mhz <= not clk_100mhz;
end loop;
wait; -- simulation stops here
end process;
p_200mhz_clk_gen : process
begin
while g_end_simulation = false loop
wait for c_200mhz_clk_period/2;
clk_200mhz <= not clk_200mhz;
wait for c_200mhz_clk_period/2;
clk_200mhz <= not clk_200mhz;
end loop;
wait; -- simulation stops here
end process;
p_main_simulation : process
begin
-- Generate reset signal
rst_n_i <= '0';
wait for 3*c_100mhz_clk_period;
rst_n_i <= '1';
wait for c_sim_time;
g_end_simulation <= true;
wait;
end process;
cmp_dut : xwb_fmc150
--generic map
--(
--g_interface_mode => PIPELINED,
--g_address_granularity => WORD,
--g_packet_size => 32
--);
port map
(
rst_n_i => rst_n_i,
clk_sys_i => clk_sys,
clk_100Mhz_i => clk_100Mhz,
clk_200Mhz_i => clk_200Mhz,
-----------------------------
-- Wishbone signals
-----------------------------
wb_slv_i => wb_slv_in,
wb_slv_o => wb_slv_out,
-----------------------------
-- External ports
-----------------------------
--Clock/Data connection to ADC on FMC150 (ADS62P49)
adc_clk_ab_p_i => '0',
adc_clk_ab_n_i => '0',
adc_cha_p_i => f_zeros(7),
adc_cha_n_i => f_zeros(7),
adc_chb_p_i => f_zeros(7),
adc_chb_n_i => f_zeros(7),
--Clock/Data connection to DAC on FMC150 (DAC3283)
dac_dclk_p_o => open,
dac_dclk_n_o => open,
dac_data_p_o => open,
dac_data_n_o => open,
dac_frame_p_o => open,
dac_frame_n_o => open,
txenable_o => open,
--Clock/Trigger connection to FMC150
clk_to_fpga_p_i => '0',
clk_to_fpga_n_i => '0',
ext_trigger_p_i => '0',
ext_trigger_n_i => '0',
-- Control signals from/to FMC150
--Serial Peripheral Interface (SPI)
spi_sclk_o => open, -- Shared SPI clock line
spi_sdata_o => open, -- Shared SPI data line
-- ADC specific signals
adc_n_en_o => open, -- SPI chip select
adc_sdo_i => '0', -- SPI data out
adc_reset_o => open, -- SPI reset
-- CDCE specific signals
cdce_n_en_o => open, -- SPI chip select
cdce_sdo_i =>'0', -- SPI data out
cdce_n_reset_o => open,
cdce_n_pd_o => open,
cdce_ref_en_o => open,
cdce_pll_status_i => '0',
-- DAC specific signals
dac_n_en_o => open, -- SPI chip select
dac_sdo_i => '0', -- SPI data out
-- Monitoring specific signals
mon_n_en_o => open, -- SPI chip select
mon_sdo_i => '0', -- SPI data out
mon_n_reset_o => open,
mon_n_int_i => '0',
--FMC Present status
prsnt_m2c_l_i => '0',
-- Wishbone Streaming Interface Source
wbs_source_i => wbs_src_in,
wbs_source_o => wbs_src_out
);
clk_sys <= clk_100Mhz;
end sim;
hdl/testbench/wishbone/wb_fmc150_test/xilinxsim.ini 0 → 100644
View file @ b985100a
-- Default lib mapping for Simulator
std=$XILINX/vhdl/hdp/lin64/std
ieee=$XILINX/vhdl/hdp/lin64/ieee
ieee_proposed=$XILINX/vhdl/hdp/lin64/ieee_proposed
vl=$XILINX/vhdl/hdp/lin64/vl
synopsys=$XILINX/vhdl/hdp/lin64/synopsys
simprim=$XILINX/vhdl/hdp/lin64/simprim
unisim=$XILINX/vhdl/hdp/lin64/unisim
unimacro=$XILINX/vhdl/hdp/lin64/unimacro
aim=$XILINX/vhdl/hdp/lin64/aim
cpld=$XILINX/vhdl/hdp/lin64/cpld
pls=$XILINX/vhdl/hdp/lin64/pls
xilinxcorelib=$XILINX/vhdl/hdp/lin64/xilinxcorelib
aim_ver=$XILINX/verilog/hdp/lin64/aim_ver
cpld_ver=$XILINX/verilog/hdp/lin64/cpld_ver
simprims_ver=$XILINX/verilog/hdp/lin64/simprims_ver
unisims_ver=$XILINX/verilog/hdp/lin64/unisims_ver
uni9000_ver=$XILINX/verilog/hdp/lin64/uni9000_ver
unimacro_ver=$XILINX/verilog/hdp/lin64/unimacro_ver
xilinxcorelib_ver=$XILINX/verilog/hdp/lin64/xilinxcorelib_ver
secureip=$XILINX/verilog/hdp/lin64/xip/secureip
work=work
fifo_generator_v6_1=fifo_generator_v6_1
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