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Beam Positoning Monitor - Gateware
Commit c9217ac1 authored by Lucas Russo's avatar Lucas Russo
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.gitignore 0 → 100644
View file @ c9217ac1
*~
*.swp
*.orig
.gitmodules 0 → 100644
View file @ c9217ac1
[submodule "hdl/ip_cores/general-cores"]
path = hdl/ip_cores/general-cores
url = git://ohwr.org/hdl-core-lib/general-cores.git
README 0 → 100644
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Repository containing the Beam Position Monitor FPGA firmware and
software.
==========================================================
hdl/Manifest.py 0 → 100644
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modules = { "local": [
"modules/custom_wishbone",
"modules/custom_common",
"ip_cores/general-cores",
"platform/virtex6/chipscope"] };
hdl/README 0 → 100644
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Folder containing all the BPM FPGA firmware and related tests
==========================================================
general-cores @ 065d6958
Subproject commit 065d69583659890a1180a024e937bc66f7340d72
hdl/modules/custom_common/Manifest.py 0 → 100644
View file @ c9217ac1
modules = { "local" : ["reset_synch"] };
files = [ "custom_common_pkg.vhd" ];
hdl/modules/custom_common/custom_common_pkg.vhd 0 → 100755
View file @ c9217ac1
library ieee;
use ieee.std_logic_1164.all;
package custom_common_pkg is
--------------------------------------------------------------------
-- Components
--------------------------------------------------------------------
component reset_synch
port
(
clk_i : in std_logic;
arst_n_i : in std_logic;
rst_n_o : out std_logic
);
end component;
end custom_common_pkg;
hdl/modules/custom_common/reset_synch/reset_synch.vhd 0 → 100755
View file @ c9217ac1
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity reset_synch is
port
(
clk_i : in std_logic;
arst_n_i : in std_logic;
rst_n_o : out std_logic
);
end reset_synch;
architecture rtl of reset_synch is
signal s_ff : std_logic;
begin
process(clk_i, arst_n_i)
begin
if arst_n_i = '0' then
s_ff <= '0';
rst_n_o <= '0';
elsif rising_edge(clk_i) then
s_ff <= '1';
rst_n_o <= s_ff;
end if;
end process;
end rtl;
hdl/modules/custom_wishbone/Manifest.py 0 → 100644
View file @ c9217ac1
modules = { "local" : [
# "wb_irq_mngr",
# "wb_dma_interface" ,
"wb_stream",
"wb_fmc150"
] };
files = [ "custom_wishbone_pkg.vhd" ];
hdl/modules/custom_wishbone/custom_wishbone_pkg.vhd 0 → 100755
View file @ c9217ac1
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.wishbone_pkg.all;
package custom_wishbone_pkg is
--------------------------------------------------------------------
-- Records
--------------------------------------------------------------------
type t_wishbone_dflow_master_out is record
cyc : std_logic;
stb : std_logic;
adr : t_wishbone_address;
sel : t_wishbone_byte_select;
cti : t_wishbone_cycle_type;
bte : t_wishbone_burst_type;
we : std_logic;
dat : t_wishbone_data;
end record t_wishbone_dflow_master_out;
subtype t_wishbone_dflow_slave_in is t_wishbone_dflow_master_out;
type t_wishbone_dflow_slave_out is record
ack : std_logic;
err : std_logic;
rty : std_logic;
stall : std_logic;
int : std_logic;
dat : t_wishbone_data;
end record t_wishbone_dflow_slave_out;
subtype t_wishbone_dflow_master_in is t_wishbone_dflow_slave_out;
--------------------------------------------------------------------
-- Components
--------------------------------------------------------------------
component wb_dma_interface
generic(
g_ovf_counter_width : natural := 10
);
port(
-- Asynchronous Reset signal
arst_n_i : in std_logic;
-- Write Domain Clock
dma_clk_i : in std_logic;
--dma_valid_o : out std_logic;
--dma_data_o : out std_logic_vector(C_NBITS_DATA_INPUT-1 downto 0);
--dma_be_o : out std_logic_vector(C_NBITS_DATA_INPUT/8 - 1 downto 0);
--dma_last_o : out std_logic;
--dma_ready_i : in std_logic;
-- Slave Data Flow port
--dma_dflow_slave_i : in t_wishbone_dflow_slave_in;
--dma_dflow_slave_o : out t_wishbone_dflow_slave_out;
wb_sel_i : in std_logic_vector(c_wishbone_data_width/8-1 downto 0);
wb_cyc_i : in std_logic;
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_adr_i : in std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
-- Slave Data Input Port
--data_slave_i : in t_wishbone_slave_in;
--data_slave_o : out t_wishbone_slave_out;
data_clk_i : in std_logic;
data_i : in std_logic_vector(c_wishbone_data_width-1 downto 0);
data_valid_i : in std_logic;
data_ready_o : out std_logic;
-- Slave control port. use wbgen2 tool or not if it is simple.
--control_slave_i : in t_wishbone_slave_in;
--control_slave_o : out t_wishbone_slave_out;
capture_ctl_i : in std_logic_vector(c_wishbone_data_width-1 downto 0);
dma_complete_o : out std_logic;
dma_ovf_o : out std_logic
-- Debug Signals
--dma_debug_clk_o : out std_logic;
--dma_debug_data_o : out std_logic_vector(255 downto 0);
--dma_debug_trigger_o : out std_logic_vector(15 downto 0)
);
end component;
component xwb_dma_interface
generic(
-- Three 32-bit data input. LSB bits are valid.
--C_NBITS_VALID_INPUT : natural := 128;
--C_NBITS_DATA_INPUT : natural := 128;
--C_OVF_COUNTER_SIZE : natural := 10
g_ovf_counter_width : natural := 10
);
port(
-- Asynchronous Reset signal
arst_n_i : in std_logic;
-- Write Domain Clock
dma_clk_i : in std_logic;
--dma_valid_o : out std_logic;
--dma_data_o : out std_logic_vector(C_NBITS_DATA_INPUT-1 downto 0);
--dma_be_o : out std_logic_vector(C_NBITS_DATA_INPUT/8 - 1 downto 0);
--dma_last_o : out std_logic;
--dma_ready_i : in std_logic;
-- Slave Data Flow port
dma_slave_i : in t_wishbone_slave_in;
dma_slave_o : out t_wishbone_slave_out;
-- Slave Data Input Port
--data_slave_i : in t_wishbone_slave_in;
--data_slave_o : out t_wishbone_slave_out;
data_clk_i : in std_logic;
data_i : in std_logic_vector(c_wishbone_data_width-1 downto 0);
data_valid_i : in std_logic;
data_ready_o : out std_logic;
-- Slave control port. use wbgen2 tool or not if it is simple.
--control_slave_i : in t_wishbone_slave_in;
--control_slave_o : out t_wishbone_slave_out;
capture_ctl_i : in std_logic_vector(c_wishbone_data_width-1 downto 0);
dma_complete_o : out std_logic;
dma_ovf_o : out std_logic
-- Debug Signals
--dma_debug_clk_o : out std_logic;
--dma_debug_data_o : out std_logic_vector(255 downto 0);
--dma_debug_trigger_o : out std_logic_vector(15 downto 0)
);
end component;
component dma_status_reg_synch
generic
(
C_NUM_REG : integer := 10;
C_SLV_DWIDTH : integer := 32;
C_STATUS_REG_IDX : natural := 1
);
port
(
bus_clk_i : in std_logic;
bus_rst_n_i : in std_logic;
bus_reg_read_sel_i : in std_logic_vector(C_NUM_REG-1 downto 0);
bus_reg_write_sel_i : in std_logic_vector(C_NUM_REG-1 downto 0);
bus_2_ip_data_i : in std_logic_vector(C_SLV_DWIDTH-1 downto 0);
dma_complete_i : in std_logic;
dma_ovf_i : in std_logic;
dma_complete_synch_o : out std_logic;
dma_ovf_synch_o : out std_logic
);
end component;
end custom_wishbone_pkg;
hdl/modules/custom_wishbone/wb_dma_interface_FIX/Manifest.py 0 → 100644
View file @ c9217ac1
files = [ "wb_dma_interface.vhd",
"xwb_dma_interface.vhd",
# "wb_dma_iface_ctl/xdma_ctl_regs_pkg.vhd",
# "wb_dma_iface_ctl/xdma_ctl_iface.vhd"
];
hdl/modules/custom_wishbone/wb_dma_interface_FIX/dma_status_reg_synch.vhd 0 → 100755
View file @ c9217ac1
------------------------------------------------------------------------------
-- dma_status_reg_synch.vhd - entity/architecture pair
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.dma_pkg.all;
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
entity dma_status_reg_synch is
generic
(
C_NUM_REG : integer := 10;
C_SLV_DWIDTH : integer := 32;
C_STATUS_REG_IDX : natural := 1
);
port
(
bus_clk_i : in std_logic;
bus_rst_n_i : in std_logic;
bus_reg_read_sel_i : in std_logic_vector(C_NUM_REG-1 downto 0);
bus_reg_write_sel_i : in std_logic_vector(C_NUM_REG-1 downto 0);
bus_2_ip_data_i : in std_logic_vector(C_SLV_DWIDTH-1 downto 0);
dma_complete_i : in std_logic;
dma_ovf_i : in std_logic;
dma_complete_synch_o : out std_logic;
dma_ovf_synch_o : out std_logic
);
end entity dma_status_reg_synch;
architecture IMP of dma_status_reg_synch is
-- DMA status synch regs
signal s_dma_complete_d1 : std_logic;
signal s_dma_complete_d2 : std_logic;
signal s_dma_complete_d3 : std_logic;
signal s_dma_complete_status : std_logic;
signal s_dma_ovf_d1 : std_logic;
signal s_dma_ovf_d2 : std_logic;
signal s_dma_ovf_status : std_logic;
-- Glue logic
signal dma_complete_synch_glue : std_logic;
signal dma_ovf_synch_glue : std_logic;
begin
-- Glue logic
dma_complete_synch_o <= dma_complete_synch_glue;
dma_ovf_synch_o <= dma_ovf_synch_glue;
p_dma_status_synch : process(bus_clk_i) is
begin
if rising_edge(bus_clk_i) then
if bus_rst_n_i = '0' then
s_dma_complete_d1 <= '0';
s_dma_complete_d2 <= '0';
s_dma_complete_d3 <= '0';
s_dma_complete_status <= '0';
s_dma_ovf_d1 <= '0';
s_dma_ovf_d2 <= '0';
s_dma_ovf_status <= '0';
else
s_dma_complete_d1 <= dma_complete_i;
s_dma_complete_d2 <= s_dma_complete_d1;
s_dma_complete_d3 <= s_dma_complete_d2;
-- Every dma_complete toggle is recognized as a dma_complete
s_dma_complete_status <= s_dma_complete_d3 xor s_dma_complete_d2;
s_dma_ovf_d1 <= dma_ovf_i;
s_dma_ovf_d2 <= s_dma_ovf_d1;
s_dma_ovf_status <= s_dma_ovf_d2;
end if;
end if;
end process p_dma_status_synch;
-- DMA Status set and clear software accessible regs
-- If a condition is detected, set the bit accordingly.
-- Otherwise, wait for "user" to clear the bit.
-- This is done in order to ensure that the user can detected
-- the condition.
p_dma_status_reg : process(bus_clk_i) is
begin
if rising_edge(bus_clk_i) then
if bus_rst_n_i = '0' then
dma_complete_synch_glue <= '0';
dma_ovf_synch_glue <= '0';
else
if s_dma_complete_status = '1' then
dma_complete_synch_glue <= '1';
elsif bus_reg_write_sel_i = std_logic_vector(to_unsigned(2**(C_NUM_REG-1-C_STATUS_REG_IDX), C_NUM_REG)) and dma_complete_synch_glue = '1' then
dma_complete_synch_glue <= bus_2_ip_data_i(0);
end if;
if s_dma_ovf_status = '1' then
dma_ovf_synch_glue <= '1';
elsif bus_reg_write_sel_i = std_logic_vector(to_unsigned(2**(C_NUM_REG-1-C_STATUS_REG_IDX), C_NUM_REG)) and dma_ovf_synch_glue = '1' then
dma_ovf_synch_glue <= bus_2_ip_data_i(1);
end if;
end if;
end if;
end process p_dma_status_reg;
end IMP;
\ No newline at end of file
hdl/modules/custom_wishbone/wb_dma_interface_FIX/old/xdma_interface_registers_pkg.vhd 0 → 100644
View file @ c9217ac1
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for Wishbone DMA Streaming Interface
---------------------------------------------------------------------------------------
-- File : xdma_interface_registers_pkg.vhd
-- Author : auto-generated by wbgen2 from xdma_interface_wb.wb
-- Created : Thu Sep 27 15:39:56 2012
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE xdma_interface_wb.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wbgen2_pkg.all;
package dma_iface_wbgen2_pkg is
-- Input registers (user design -> WB slave)
type t_dma_iface_in_registers is record
ctl_done_i : std_logic;
ctl_ovf_i : std_logic;
fifo_c2b_wr_req_i : std_logic;
fifo_c2b_data_i : std_logic_vector(31 downto 0);
fifo_c2b_last_i : std_logic;
fifo_b2c_rd_req_i : std_logic;
end record;
constant c_dma_iface_in_registers_init_value: t_dma_iface_in_registers := (
ctl_done_i => '0',
ctl_ovf_i => '0',
fifo_c2b_wr_req_i => '0',
fifo_c2b_data_i => (others => '0'),
fifo_c2b_last_i => '0',
fifo_b2c_rd_req_i => '0'
);
-- Output registers (WB slave -> user design)
type t_dma_iface_out_registers is record
ctl_start_o : std_logic;
tr_cntr_o : std_logic_vector(31 downto 0);
fifo_c2b_wr_full_o : std_logic;
fifo_c2b_wr_empty_o : std_logic;
fifo_c2b_wr_usedw_o : std_logic_vector(7 downto 0);
fifo_b2c_rd_full_o : std_logic;
fifo_b2c_rd_empty_o : std_logic;
fifo_b2c_rd_usedw_o : std_logic_vector(7 downto 0);
fifo_b2c_data_o : std_logic_vector(31 downto 0);
end record;
constant c_dma_iface_out_registers_init_value: t_dma_iface_out_registers := (
ctl_start_o => '0',
tr_cntr_o => (others => '0'),
fifo_c2b_wr_full_o => '0',
fifo_c2b_wr_empty_o => '0',
fifo_c2b_wr_usedw_o => (others => '0'),
fifo_b2c_rd_full_o => '0',
fifo_b2c_rd_empty_o => '0',
fifo_b2c_rd_usedw_o => (others => '0'),
fifo_b2c_data_o => (others => '0')
);
function "or" (left, right: t_dma_iface_in_registers) return t_dma_iface_in_registers;
function f_x_to_zero (x:std_logic) return std_logic;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector;
end package;
package body dma_iface_wbgen2_pkg is
function f_x_to_zero (x:std_logic) return std_logic is
begin
if(x = 'X' or x = 'U') then
return '0';
else
return x;
end if;
end function;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector is
variable tmp: std_logic_vector(x'length-1 downto 0);
begin
for i in 0 to x'length-1 loop
if(x(i) = 'X' or x(i) = 'U') then
tmp(i):= '0';
else
tmp(i):=x(i);
end if;
end loop;
return tmp;
end function;
function "or" (left, right: t_dma_iface_in_registers) return t_dma_iface_in_registers is
variable tmp: t_dma_iface_in_registers;
begin
tmp.ctl_done_i := f_x_to_zero(left.ctl_done_i) or f_x_to_zero(right.ctl_done_i);
tmp.ctl_ovf_i := f_x_to_zero(left.ctl_ovf_i) or f_x_to_zero(right.ctl_ovf_i);
tmp.fifo_c2b_wr_req_i := f_x_to_zero(left.fifo_c2b_wr_req_i) or f_x_to_zero(right.fifo_c2b_wr_req_i);
tmp.fifo_c2b_data_i := f_x_to_zero(left.fifo_c2b_data_i) or f_x_to_zero(right.fifo_c2b_data_i);
tmp.fifo_c2b_last_i := f_x_to_zero(left.fifo_c2b_last_i) or f_x_to_zero(right.fifo_c2b_last_i);
tmp.fifo_b2c_rd_req_i := f_x_to_zero(left.fifo_b2c_rd_req_i) or f_x_to_zero(right.fifo_b2c_rd_req_i);
return tmp;
end function;
end package body;
hdl/modules/custom_wishbone/wb_dma_interface_FIX/old/xdma_interface_regs.h 0 → 100644
View file @ c9217ac1
/*
Register definitions for slave core: Wishbone DMA Streaming Interface
* File : xdma_interface_regs.h
* Author : auto-generated by wbgen2 from xdma_interface_wb.wb
* Created : Thu Sep 27 15:39:56 2012
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE xdma_interface_wb.wb
DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
*/
#ifndef __WBGEN2_REGDEFS_XDMA_INTERFACE_WB_WB
#define __WBGEN2_REGDEFS_XDMA_INTERFACE_WB_WB
#include <inttypes.h>
#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
#else
#error "Unsupported compiler?"
#endif
#ifndef __WBGEN2_MACROS_DEFINED__
#define __WBGEN2_MACROS_DEFINED__
#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
#endif
/* definitions for register: Control/Status register */
/* definitions for field: Start Transaction in reg: Control/Status register */
#define DMA_IFACE_CTL_START WBGEN2_GEN_MASK(0, 1)
/* definitions for field: DMA complete in reg: Control/Status register */
#define DMA_IFACE_CTL_DONE WBGEN2_GEN_MASK(1, 1)
/* definitions for field: DMA overflow in reg: Control/Status register */
#define DMA_IFACE_CTL_OVF WBGEN2_GEN_MASK(2, 1)
/* definitions for register: Transaction Counter */
/* definitions for register: FIFO 'FIFO C2B (Core -> DMA) synchronization' data output register 0 */
/* definitions for field: Output FIFO data value in reg: FIFO 'FIFO C2B (Core -> DMA) synchronization' data output register 0 */
#define DMA_IFACE_FIFO_C2B_R0_DATA_MASK WBGEN2_GEN_MASK(0, 32)
#define DMA_IFACE_FIFO_C2B_R0_DATA_SHIFT 0
#define DMA_IFACE_FIFO_C2B_R0_DATA_W(value) WBGEN2_GEN_WRITE(value, 0, 32)
#define DMA_IFACE_FIFO_C2B_R0_DATA_R(reg) WBGEN2_GEN_READ(reg, 0, 32)
/* definitions for register: FIFO 'FIFO C2B (Core -> DMA) synchronization' data output register 1 */
/* definitions for field: Transaction Last Data in reg: FIFO 'FIFO C2B (Core -> DMA) synchronization' data output register 1 */
#define DMA_IFACE_FIFO_C2B_R1_LAST WBGEN2_GEN_MASK(0, 1)
/* definitions for register: FIFO 'FIFO C2B (Core -> DMA) synchronization' control/status register */
/* definitions for field: FIFO full flag in reg: FIFO 'FIFO C2B (Core -> DMA) synchronization' control/status register */
#define DMA_IFACE_FIFO_C2B_CSR_FULL WBGEN2_GEN_MASK(16, 1)
/* definitions for field: FIFO empty flag in reg: FIFO 'FIFO C2B (Core -> DMA) synchronization' control/status register */
#define DMA_IFACE_FIFO_C2B_CSR_EMPTY WBGEN2_GEN_MASK(17, 1)
/* definitions for field: FIFO counter in reg: FIFO 'FIFO C2B (Core -> DMA) synchronization' control/status register */
#define DMA_IFACE_FIFO_C2B_CSR_USEDW_MASK WBGEN2_GEN_MASK(0, 8)
#define DMA_IFACE_FIFO_C2B_CSR_USEDW_SHIFT 0
#define DMA_IFACE_FIFO_C2B_CSR_USEDW_W(value) WBGEN2_GEN_WRITE(value, 0, 8)
#define DMA_IFACE_FIFO_C2B_CSR_USEDW_R(reg) WBGEN2_GEN_READ(reg, 0, 8)
/* definitions for register: FIFO 'FIFO B2C (Bus -> Core) synchronization' data input register 0 */
/* definitions for field: Input FIFO data value in reg: FIFO 'FIFO B2C (Bus -> Core) synchronization' data input register 0 */
#define DMA_IFACE_FIFO_B2C_R0_DATA_MASK WBGEN2_GEN_MASK(0, 32)
#define DMA_IFACE_FIFO_B2C_R0_DATA_SHIFT 0
#define DMA_IFACE_FIFO_B2C_R0_DATA_W(value) WBGEN2_GEN_WRITE(value, 0, 32)
#define DMA_IFACE_FIFO_B2C_R0_DATA_R(reg) WBGEN2_GEN_READ(reg, 0, 32)
/* definitions for register: FIFO 'FIFO B2C (Bus -> Core) synchronization' control/status register */
/* definitions for field: FIFO full flag in reg: FIFO 'FIFO B2C (Bus -> Core) synchronization' control/status register */
#define DMA_IFACE_FIFO_B2C_CSR_FULL WBGEN2_GEN_MASK(16, 1)
/* definitions for field: FIFO empty flag in reg: FIFO 'FIFO B2C (Bus -> Core) synchronization' control/status register */
#define DMA_IFACE_FIFO_B2C_CSR_EMPTY WBGEN2_GEN_MASK(17, 1)
/* definitions for field: FIFO counter in reg: FIFO 'FIFO B2C (Bus -> Core) synchronization' control/status register */
#define DMA_IFACE_FIFO_B2C_CSR_USEDW_MASK WBGEN2_GEN_MASK(0, 8)
#define DMA_IFACE_FIFO_B2C_CSR_USEDW_SHIFT 0
#define DMA_IFACE_FIFO_B2C_CSR_USEDW_W(value) WBGEN2_GEN_WRITE(value, 0, 8)
#define DMA_IFACE_FIFO_B2C_CSR_USEDW_R(reg) WBGEN2_GEN_READ(reg, 0, 8)
PACKED struct DMA_IFACE_WB {
/* [0x0]: REG Control/Status register */
uint32_t CTL;
/* [0x4]: REG Transaction Counter */
uint32_t TR_CNTR;
/* [0x8]: REG FIFO 'FIFO C2B (Core -> DMA) synchronization' data output register 0 */
uint32_t FIFO_C2B_R0;
/* [0xc]: REG FIFO 'FIFO C2B (Core -> DMA) synchronization' data output register 1 */
uint32_t FIFO_C2B_R1;
/* [0x10]: REG FIFO 'FIFO C2B (Core -> DMA) synchronization' control/status register */
uint32_t FIFO_C2B_CSR;
/* [0x14]: REG FIFO 'FIFO B2C (Bus -> Core) synchronization' data input register 0 */
uint32_t FIFO_B2C_R0;
/* [0x18]: REG FIFO 'FIFO B2C (Bus -> Core) synchronization' control/status register */
uint32_t FIFO_B2C_CSR;
};
#endif
hdl/modules/custom_wishbone/wb_dma_interface_FIX/old/xdma_interface_wb.wb 0 → 100644
View file @ c9217ac1
-- Description of the wishbone interface for the wb_dma_interface core
peripheral {
name = "Wishbone DMA Streaming Interface";
description = "Simple Wishbone DMA interface for peripherals which want to stream data to a DMA";
-- Prefix for all generated ports
prefix = "dma_iface";
-- Name of the vhdl entity to be generated
hdl_entity = "wb_dma_interface_port";
mode = PIPELINED;
-- Control Register
reg {
name = "Control/Status register";
description = "A register defining the Control and Status of the core.";
prefix = "ctl";
field {
name = "Start Transaction";
description = "write 1: starts the DMA transaction.\
write 0: no effect";
prefix = "start";
-- Pulse to start
type = MONOSTABLE;
clock = "data_clk_i";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "DMA complete";
description = "read 1: the DMA has completed the transaction\
read 0: DMA transaction still in progress";
prefix = "done";
type = BIT;
clock = "dma_clk_i";
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "DMA overflow";
description = "read 1: the DMA overflow detected\
read 0: No overflow detected";
prefix = "ovf";
type = BIT;
clock = "dma_clk_i";
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
-- Transaction Counter Register
reg {
name = "Transaction Counter";
description = "Register holding the word count to be transfered to DMA";
prefix = "tr_cntr";
field {
name = "Transactions Counter";
description = "Stores the words to be transfered to DMA";
--prefix = "";
type = SLV;
size = 32;
clock = "data_clk_i";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
-- Bus = Read, Core = Write (Core -> Bus)
fifo_reg {
size = 256;
direction = CORE_TO_BUS;
prefix = "fifo_c2b";
name = "FIFO C2B (Core -> DMA) synchronization";
description = "Data to to be written to DMA";
flags_bus = {FIFO_FULL, FIFO_EMPTY, FIFO_COUNT};
flags_dev = {FIFO_FULL, FIFO_EMPTY, FIFO_COUNT};
clock = "dma_clk_i";
--mode = PIPELINED;
field {
name = "Output FIFO data value";
description = "Value of data word synchronized to the core clock";
prefix = "data";
type = SLV;
size = 32;
};
field {
name = "Transaction Last Data";
description = "0: Current entry is not the last transaction data\
1: Current entry is the last transaction data";
prefix = "last";
type = BIT;
};
};
-- Bus = Write, Core = Read (Bus -> Core)
fifo_reg {
size = 256;
direction = BUS_TO_CORE;
prefix = "fifo_b2c";
name = "FIFO B2C (Bus -> Core) synchronization";
flags_bus = {FIFO_FULL, FIFO_EMPTY, FIFO_COUNT};
flags_dev = {FIFO_FULL, FIFO_EMPTY, FIFO_COUNT};
clock = "data_clk_i";
--mode = PIPELINED;
field {
name = "Input FIFO data value";
description = "Value of data word synchronized to the core clock";
prefix = "data";
type = SLV;
size = 32;
};
};
};
hdl/modules/custom_wishbone/wb_dma_interface_FIX/xdma_interface.wb 0 → 100644
View file @ c9217ac1
-- Description of the wishbone interface for the wb_dma_interface core
peripheral {
name = "Wishbone DMA Streaming Interface";
description = "Simple Wishbone DMA interface for peripherals which want to stream data to a DMA";
-- Prefix for all generated ports
prefix = "dma_iface";
-- Name of the vhdl entity to be generated
hdl_entity = "wb_dma_interface_port";
-- Control Register
reg {
name = "Control/Status register";
prefix = "ctl";
field {
name = "Start Transaction";
description = "write 1: starts the DMA transaction.\
write 0: no effect";
prefix = "start";
-- Pulse to start
type = MONOSTABLE;
clock = "data_clk_i";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "DMA complete";
description = "read 1: the DMA has completed the transaction\
read 0: DMA transaction still in progress";
prefix = "done";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "DMA overflow";
description = "read 1: the DMA overflow detected\
read 0: No overflow detected";
prefix = "done";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
-- Data Count Register
reg {
name = "Transaction Counter";
prefix = "tr_cntr";
field {
--name = "";
description = "Stores the the words to be transfered to DMA";
--prefix = "";
type = SLV;
size = 32;
clock = "data_clk_i";
access_bus = WRITE_ONLY;
access_dev = READ_ONLY;
};
};
-- Bus = Read, Core = Write (Core -> Bus)
fifo_reg {
size = 256;
direction = CORE_TO_BUS;
prefix = "fifo_out";
name = "FIFO DMA synchronization";
description = "Data to to be written to DMA";
flags_bus = {FIFO_FULL, FIFO_EMPTY, FIFO_COUNT};
flags_dev = {FIFO_FULL, FIFO_EMPTY, FIFO_COUNT};
mode = PIPELINE;
field {
name = "Output FIFO data value";
description = "Value of data word synchronized to the core clock";
--prefix = "";
type = SLV;
size = 32;
clock = "dma_clk_i";
};
field {
name = "Transaction Last Data";
description = "0: Current entry is not the last transaction data\
1: Current entry is the last transaction data";
prefix = "last";
type = BIT;
clock = "dma_clk_i";
};
};
-- Bus = Write, Core = Read (Bus -> Core)
fifo_reg {
size = 256;
direction = BUS_TO_CORE;
prefix = "fifo_in";
name = "FIFO input synchronization";
flags_bus = {FIFO_FULL, FIFO_EMPTY, FIFO_COUNT};
flags_dev = {FIFO_FULL, FIFO_EMPTY, FIFO_COUNT};
mode = PIPELINE;
field {
name = "Input FIFO data value";
description = "Value of data word synchronized to the core clock";
--prefix = "";
type = SLV;
size = 32;
clock = "data_clk_i";
};
};
};
hdl/modules/custom_wishbone/wb_dma_interface_FIX/xwb_dma_interface.old.vhd 0 → 100755
View file @ c9217ac1
------------------------------------------------------------------------------
-- dma_if.vhd - entity/architecture pair
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.wishbone_pkg.all;
use work.custom_wishbone_pkg.all;
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
entity xwb_dma_interface is
generic(
-- Three 32-bit data input. LSB bits are valid.
--C_NBITS_VALID_INPUT : natural := 128;
--C_NBITS_DATA_INPUT : natural := 128;
--C_OVF_COUNTER_SIZE : natural := 10
g_ovf_counter_width : natural := 10
);
port(
-- Asynchronous Reset signal
arst_n_i : in std_logic;
-- Write Domain Clock
dma_clk_i : in std_logic;
--dma_valid_o : out std_logic;
--dma_data_o : out std_logic_vector(C_NBITS_DATA_INPUT-1 downto 0);
--dma_be_o : out std_logic_vector(C_NBITS_DATA_INPUT/8 - 1 downto 0);
--dma_last_o : out std_logic;
--dma_ready_i : in std_logic;
-- Slave Data Flow port
--dma_dflow_slave_i : in t_wishbone_dflow_slave_in;
--dma_dflow_slave_o : out t_wishbone_dflow_slave_out;
dma_slave_i : in t_wishbone_slave_in;
dma_slave_o : out t_wishbone_slave_out;
-- Slave Data Input Port
--data_slave_i : in t_wishbone_slave_in;
--data_slave_o : out t_wishbone_slave_out;
data_clk_i : in std_logic;
data_i : in std_logic_vector(c_wishbone_data_width-1 downto 0);
data_valid_i : in std_logic;
data_ready_o : out std_logic;
-- Slave control port. use wbgen2 tool or not if it is simple.
--control_slave_i : in t_wishbone_slave_in;
--control_slave_o : out t_wishbone_slave_out;
capture_ctl_i : in std_logic_vector(c_wishbone_data_width-1 downto 0);
dma_complete_o : out std_logic;
dma_ovf_o : out std_logic
-- Debug Signals
--dma_debug_clk_o : out std_logic;
--dma_debug_data_o : out std_logic_vector(255 downto 0);
--dma_debug_trigger_o : out std_logic_vector(15 downto 0)
);
end xwb_dma_interface;
architecture rtl of xwb_dma_interface is
begin
cmp_wb_dma_interface : wb_dma_interface
port map(
-- Asynchronous Reset signal
arst_n_i => arst_n_i,
-- Write Domain Clock
dma_clk_i => dma_clk_i,
--dma_valid_o : out std_logic;
--dma_data_o : out std_logic_vector(C_NBITS_DATA_INPUT-1 downto 0);
--dma_be_o : out std_logic_vector(C_NBITS_DATA_INPUT/8 - 1 downto 0);
--dma_last_o : out std_logic;
--dma_ready_i : in std_logic;
-- Slave Data Flow port
--dma_dflow_slave_i : in t_wishbone_dflow_slave_in;
--dma_dflow_slave_o : out t_wishbone_dflow_slave_out;
wb_sel_i => dma_slave_i.sel,
wb_cyc_i => dma_slave_i.cyc,
wb_stb_i => dma_slave_i.stb,
wb_we_i => dma_slave_i.we,
wb_adr_i => dma_slave_i.adr,
wb_dat_i => dma_slave_i.dat,
--wb_cti_i => dma_dflow_slave_i.cti,
--wb_bte_i => dma_dflow_slave_i.bte,
wb_dat_o => dma_slave_o.dat,
wb_ack_o => dma_slave_o.ack,
wb_stall_o => dma_slave_o.stall,
-- Slave Data Input Port
--data_slave_i : in t_wishbone_slave_in;
--data_slave_o : out t_wishbone_slave_out;
data_clk_i => data_clk_i,
data_i => data_i,
data_valid_i => data_valid_i,
data_ready_o => data_ready_o,
-- Slave control port. use wbgen2 tool or not if it is simple.
--control_slave_i : in t_wishbone_slave_in;
--control_slave_o : out t_wishbone_slave_out;
capture_ctl_i => capture_ctl_i,
dma_complete_o => dma_complete_o,
dma_ovf_o => dma_ovf_o
-- Debug Signals
--dma_debug_clk_o : out std_logic;
--dma_debug_data_o : out std_logic_vector(255 downto 0);
--dma_debug_trigger_o : out std_logic_vector(15 downto 0)
);
dma_slave_o.rty <= '0';
dma_slave_o.err <= '0';
dma_slave_o.int <= '0';
end rtl;
hdl/modules/custom_wishbone/wb_dma_interface_FIX/xwb_dma_interface.vhd 0 → 100755
View file @ c9217ac1
------------------------------------------------------------------------------
-- dma_if.vhd - entity/architecture pair
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.wishbone_pkg.all;
use work.custom_wishbone_pkg.all;
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
entity xwb_dma_interface is
port(
-- Asynchronous Reset signal
arst_n_i : in std_logic;
-- Write Domain Clock
dma_clk_i : in std_logic;
--dma_valid_o : out std_logic;
--dma_data_o : out std_logic_vector(C_NBITS_DATA_INPUT-1 downto 0);
--dma_be_o : out std_logic_vector(C_NBITS_DATA_INPUT/8 - 1 downto 0);
--dma_last_o : out std_logic;
--dma_ready_i : in std_logic;
-- Slave Data Flow port
--dma_dflow_slave_i : in t_wishbone_dflow_slave_in;
--dma_dflow_slave_o : out t_wishbone_dflow_slave_out;
dma_slave_i : in t_wishbone_slave_in;
dma_slave_o : out t_wishbone_slave_out;
-- Slave Data Input Port
--data_slave_i : in t_wishbone_slave_in;
--data_slave_o : out t_wishbone_slave_out;
data_clk_i : in std_logic;
data_i : in std_logic_vector(c_wishbone_data_width-1 downto 0);
data_valid_i : in std_logic;
data_ready_o : out std_logic;
-- Slave control port. use wbgen2 tool or not if it is simple.
--control_slave_i : in t_wishbone_slave_in;
--control_slave_o : out t_wishbone_slave_out;
capture_ctl_i : in std_logic_vector(c_wishbone_data_width-1 downto 0);
dma_complete_o : out std_logic;
dma_ovf_o : out std_logic
-- Debug Signals
--dma_debug_clk_o : out std_logic;
--dma_debug_data_o : out std_logic_vector(255 downto 0);
--dma_debug_trigger_o : out std_logic_vector(15 downto 0)
);
end xwb_dma_interface;
architecture rtl of xwb_dma_interface is
begin
cmp_wb_dma_interface : wb_dma_interface
port map(
-- Asynchronous Reset signal
arst_n_i => arst_n_i,
-- Write Domain Clock
dma_clk_i => dma_clk_i,
--dma_valid_o : out std_logic;
--dma_data_o : out std_logic_vector(C_NBITS_DATA_INPUT-1 downto 0);
--dma_be_o : out std_logic_vector(C_NBITS_DATA_INPUT/8 - 1 downto 0);
--dma_last_o : out std_logic;
--dma_ready_i : in std_logic;
-- Slave Data Flow port
--dma_dflow_slave_i : in t_wishbone_dflow_slave_in;
--dma_dflow_slave_o : out t_wishbone_dflow_slave_out;
wb_sel_i => dma_slave_i.sel,
wb_cyc_i => dma_slave_i.cyc,
wb_stb_i => dma_slave_i.stb,
wb_we_i => dma_slave_i.we,
wb_adr_i => dma_slave_i.adr,
wb_dat_i => dma_slave_i.dat,
--wb_cti_i => dma_dflow_slave_i.cti,
--wb_bte_i => dma_dflow_slave_i.bte,
wb_dat_o => dma_slave_o.dat,
wb_ack_o => dma_slave_o.ack,
wb_stall_o => dma_slave_o.stall,
-- Slave Data Input Port
--data_slave_i : in t_wishbone_slave_in;
--data_slave_o : out t_wishbone_slave_out;
data_clk_i => data_clk_i,
data_i => data_i,
data_valid_i => data_valid_i,
data_ready_o => data_ready_o,
-- Slave control port. use wbgen2 tool or not if it is simple.
--control_slave_i : in t_wishbone_slave_in;
--control_slave_o : out t_wishbone_slave_out;
capture_ctl_i => capture_ctl_i,
dma_complete_o => dma_complete_o,
dma_ovf_o => dma_ovf_o
-- Debug Signals
--dma_debug_clk_o : out std_logic;
--dma_debug_data_o : out std_logic_vector(255 downto 0);
--dma_debug_trigger_o : out std_logic_vector(15 downto 0)
);
dma_slave_o.rty <= '0';
dma_slave_o.err <= '0';
dma_slave_o.int <= '0';
end rtl;
hdl/modules/custom_wishbone/wb_fmc150/Manifest.py 0 → 100644
View file @ c9217ac1
modules = { "local" : [
"adc",
"fmc150",
"netlist" ] };
files = ["wb_fmc150.vhd", "xwb_fmc150.vhd", "xfmc150_regs_pkg.vhd", "wb_fmc150_port.vhd",
"xwb_fmc150.vhd" ];
hdl/modules/custom_wishbone/wb_fmc150/adc/Manifest.py 0 → 100644
View file @ c9217ac1
files = ["adc_channel_lvds_ddr.vhd", "adc_pkg.vhd", "strobe_lvds.vhd" ];
hdl/modules/custom_wishbone/wb_fmc150/adc/adc_channel_lvds_ddr.vhd 0 → 100755
View file @ c9217ac1
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity adc_channel_lvds_ddr is
generic
(
C_NBITS : natural := 16;
C_DEFAULT_DELAY : natural := 0
);
port
(
clk_adc_i : in std_logic;
clk_ctrl_i : in std_logic;
adc_p_i : in std_logic_vector(C_NBITS/2 - 1 downto 0);
adc_n_i : in std_logic_vector(C_NBITS/2 - 1 downto 0);
adc_data_o : out std_logic_vector(C_NBITS - 1 downto 0);
ctrl_delay_update_i : in std_logic;
ctrl_delay_value_i : in std_logic_vector(4 downto 0)
);
end adc_channel_lvds_ddr;
architecture rtl of adc_channel_lvds_ddr is
signal s_adc_raw : std_logic_vector(C_NBITS/2 - 1 downto 0);
signal s_adc_ddr : std_logic_vector(C_NBITS/2 - 1 downto 0);
signal s_adc_ddr_dly : std_logic_vector(C_NBITS/2 - 1 downto 0);
begin
gen_adc_lvds_ddr : for i in 0 to (C_NBITS/2)-1 generate
-- Differential input buffer with termination (LVDS)
cmp_ibufds : ibufds
generic map
(
IOSTANDARD => "LVDS_25",
DIFF_TERM => TRUE
)
port map
(
i => adc_p_i(i),
ib => adc_n_i(i),
o => s_adc_ddr(i)
);
-- Input delay
cmp_iodelay : iodelaye1
generic map
(
IDELAY_TYPE => "VAR_LOADABLE",
IDELAY_VALUE => C_DEFAULT_DELAY,
SIGNAL_PATTERN => "DATA",
DELAY_SRC => "I"
)
port map
(
idatain => s_adc_ddr(i),
dataout => s_adc_ddr_dly(i),
c => clk_ctrl_i,
ce => '0',
inc => '0',
datain => '0',
odatain => '0',
clkin => '0',
rst => ctrl_delay_update_i,
cntvaluein => ctrl_delay_value_i,
cntvalueout => open,
cinvctrl => '0',
t => '1'
);
-- DDR to SDR
cmp_iddr : iddr
generic map
(
DDR_CLK_EDGE => "SAME_EDGE_PIPELINED"
)
port map
(
q1 => adc_data_o(2*i),
q2 => adc_data_o(2*i+1),
c => clk_adc_i,
ce => '1',
d => s_adc_ddr_dly(i),
r => '0',
s => '0'
);
end generate;
end rtl;
\ No newline at end of file
hdl/modules/custom_wishbone/wb_fmc150/adc/adc_pkg.vhd 0 → 100755
View file @ c9217ac1
library ieee;
use ieee.std_logic_1164.all;
package adc_pkg is
--------------------------------------------------------------------
-- Components
--------------------------------------------------------------------
component strobe_lvds is
generic
(
C_DEFAULT_DELAY : natural := 0
);
port
(
clk_ctrl_i : in std_logic;
strobe_p_i : in std_logic;
strobe_n_i : in std_logic;
strobe_o : out std_logic;
ctrl_delay_update_i : in std_logic;
ctrl_delay_value_i : in std_logic_vector(4 downto 0);
ctrl_delay_value_o : out std_logic_vector(4 downto 0)
);
end component;
component adc_channel_lvds_ddr is
generic
(
C_NBITS : natural := 16;
C_DEFAULT_DELAY : natural := 0
);
port
(
clk_adc_i : in std_logic;
clk_ctrl_i : in std_logic;
adc_p_i : in std_logic_vector(C_NBITS/2 - 1 downto 0);
adc_n_i : in std_logic_vector(C_NBITS/2 - 1 downto 0);
adc_data_o : out std_logic_vector(C_NBITS - 1 downto 0);
ctrl_delay_update_i : in std_logic;
ctrl_delay_value_i : in std_logic_vector(4 downto 0)
);
end component;
end adc_pkg;
\ No newline at end of file
hdl/modules/custom_wishbone/wb_fmc150/adc/strobe_lvds.vhd 0 → 100755
View file @ c9217ac1
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hdl/modules/custom_wishbone/wb_fmc150/build_wb.sh 0 → 100755
View file @ c9217ac1
#!/bin/bash
wbgen2 -V wb_fmc150_port.vhd -H record -p xfmc150_regs_pkg.vhd -K ../../../sim/regs/xfmc150_regs_regs.vh -s struct -C xfmc150_regs_regs.h -D doc/xfmc150_regs_wb.html xfmc150.wb
hdl/modules/custom_wishbone/wb_fmc150/doc/xfmc150_regs_wb.html 0 → 100644
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hdl/modules/custom_wishbone/wb_fmc150/fmc150/Manifest.py 0 → 100644
View file @ c9217ac1
files = ["ads62p49_ctrl.vhd", "amc7823_ctrl.vhd", "cdce72010_ctrl.vhd", "dac3283_ctrl.vhd",
"fmc150_adc_if.vhd", "fmc150_dac_if.vhd", "fmc150_pkg.vhd", "fmc150_spi_ctrl.vhd",
"fmc150_stellar_cmd.vhd", "fmc150_testbench.vhd", "pulse2pulse.vhd"];
hdl/modules/custom_wishbone/wb_fmc150/fmc150/ads62p49_ctrl.vhd 0 → 100755
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hdl/modules/custom_wishbone/wb_fmc150/fmc150/amc7823_ctrl.vhd 0 → 100755
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hdl/modules/custom_wishbone/wb_fmc150/fmc150/dac3283_ctrl.vhd 0 → 100755
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hdl/modules/custom_wishbone/wb_fmc150/fmc150/fmc150_adc_if.vhd 0 → 100755
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hdl/modules/custom_wishbone/wb_fmc150/fmc150/fmc150_dac_if.vhd 0 → 100755
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hdl/modules/custom_wishbone/wb_fmc150/fmc150/fmc150_pkg.vhd 0 → 100755
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hdl/modules/custom_wishbone/wb_fmc150/fmc150/pulse2pulse.vhd 0 → 100755
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hdl/modules/custom_wishbone/wb_fmc150/netlist/Manifest.py 0 → 100644
View file @ c9217ac1
files = ["ads62p49_init_mem.ngc", "amc7823_init_mem.ngc", "cdce72010_init_mem_ext.ngc",
"cdce72010_init_mem_int.ngc", "dac3283_init_mem.ngc"];
hdl/modules/custom_wishbone/wb_fmc150/wb_fmc150.vhd 0 → 100755
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hdl/modules/custom_wishbone/wb_fmc150/wb_fmc150_port.vhd 0 → 100644
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hdl/modules/custom_wishbone/wb_fmc150/xfmc150.wb 0 → 100644
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hdl/modules/custom_wishbone/wb_fmc150/xfmc150_regs_pkg.vhd 0 → 100644
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hdl/modules/custom_wishbone/wb_fmc150/xfmc150_regs_regs.h 0 → 100644
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hdl/modules/custom_wishbone/wb_fmc150/xwb_fmc150.vhd 0 → 100755
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hdl/modules/custom_wishbone/wb_irq_mngr/Manifest.py 0 → 100644
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hdl/modules/custom_wishbone/wb_irq_mngr/wb_irq_mngr.vhd 0 → 100755
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hdl/modules/custom_wishbone/wb_irq_mngr/xwb_irq_mngr.vhd 0 → 100755
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hdl/modules/custom_wishbone/wb_stream/Manifest.py 0 → 100644
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hdl/modules/custom_wishbone/wb_stream/wb_stream_pkg.vhd 0 → 100644
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