Commit d4341f4c authored by Lucas Russo's avatar Lucas Russo

Merge branch 'devel'

parents 5ec1cba3 a9645c2f
......@@ -7,3 +7,6 @@
[submodule "hdl/ip_cores/dsp-cores"]
path = hdl/ip_cores/dsp-cores
url = https://github.com/lnls-dig/dsp-cores.git
[submodule "hdl/ip_cores/infra-cores"]
path = hdl/ip_cores/infra-cores
url = https://github.com/lnls-dig/infra-cores
#fetchto = "ip_cores"
modules = { "local": [
"modules/dbe_wishbone",
"modules/dbe_common",
# "modules/dbe_wishbone",
# "modules/dbe_common",
# "modules/rffe_top",
"modules/fabric",
"modules/fmc_adc_common",
"modules/utils",
"modules/pcie",
# "modules/fabric",
# "modules/fmc_adc_common",
# "modules/utils",
# "modules/pcie",
"ip_cores/general-cores",
"ip_cores/etherbone-core",
"ip_cores/dsp-cores",
"platform"]
"ip_cores/infra-cores",
# "platform"
]
};
Subproject commit a136c03e7358a6099622d4c36e90a9f97d12dcfa
Subproject commit a521ad22095096174203c669bc8c82fe07307ea3
Subproject commit 24100ec49972e4acb7b71fba97e0108c7e1690ff
modules = { "local" : ["reset_synch",
"pulse2level",
"trigger_rcv",
"counter_simple",
"extend_pulse_dyn",
"heartbeat"] };
files = [ "dbe_common_pkg.vhd" ];
-------------------------------------------------------------------------------
-- Title : Simple counter
-- Project :
-------------------------------------------------------------------------------
-- File : counter.vhd
-- Author : aylons <aylons@LNLS190>
-- Company :
-- Created : 2015-11-11
-- Last update: 2015-12-11
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Simple counter for testing, with clock enable
-------------------------------------------------------------------------------
-- Copyright (c) 2015
-- This program is free software: you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public License
-- as published by the Free Software Foundation, either version 3 of
-- the License, or (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public
-- License along with this program. If not, see
-- <http://www.gnu.org/licenses/>.
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2015-11-11 1.0 aylons Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity counter_simple is
generic(
g_output_width : positive := 8
);
port(
clk_i : in std_logic;
rst_n_i : in std_logic;
ce_i : in std_logic;
up_i : in std_logic;
down_i : in std_logic;
count_o : out std_logic_vector(g_output_width-1 downto 0)
);
end counter_simple;
architecture behavioural of counter_simple is
signal count : unsigned(g_output_width-1 downto 0) := to_unsigned(0, g_output_width);
begin
counter_simple : process(clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
count <= to_unsigned(0, g_output_width);
else
if ce_i = '1' then
if up_i = '1' then
count <= count + 1;
elsif down_i = '1' then
count <= count - 1;
end if;
end if; --ce
end if; --rst
end if; -- clk
end process;
count_o <= std_logic_vector(count);
end architecture behavioural;
library ieee;
use ieee.std_logic_1164.all;
use ieee.NUMERIC_STD.all;
package dbe_common_pkg is
--------------------------------------------------------------------
-- Components
--------------------------------------------------------------------
component reset_synch
generic
(
-- Select 1 for no pipeline, and greater than 1 to insert
-- pipeline stages
g_pipeline : natural := 4
);
port
(
clk_i : in std_logic;
arst_n_i : in std_logic;
rst_n_o : out std_logic
);
end component;
component pulse2level
port
(
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Pulse input
pulse_i : in std_logic;
-- Clear level
clr_i : in std_logic;
-- Level output
level_o : out std_logic
);
end component;
component trigger_rcv is
generic (
g_glitch_len_width : positive;
g_sync_edge : string);
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
len_i : in std_logic_vector(g_glitch_len_width-1 downto 0);
data_i : in std_logic;
pulse_o : out std_logic);
end component trigger_rcv;
component extend_pulse_dyn is
generic (
g_width_bus_size : natural);
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
pulse_i : in std_logic;
pulse_width_i : in unsigned(g_width_bus_size-1 downto 0);
extended_o : out std_logic := '0');
end component extend_pulse_dyn;
component counter_simple is
generic (
g_output_width : positive);
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
ce_i : in std_logic;
up_i : in std_logic;
down_i : in std_logic;
count_o : out std_logic_vector(g_output_width-1 downto 0));
end component counter_simple;
component heartbeat
generic
(
-- number of system clock cycles to count before blinking
g_clk_counts : natural := 100000000
);
port
(
-- 100 MHz system clock
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Heartbeat pulse output
heartbeat_o : out std_logic
);
end component;
end dbe_common_pkg;
-------------------------------------------------------------------------------
-- Title : Dynamic pulse width extender
-- Project :
-------------------------------------------------------------------------------
-- File : extend_pulse_dyn.vhd
-- Author : Vitor Finotti Ferreira <vfinotti@finotti-Inspiron-7520>
-- Company : Brazilian Synchrotron Light Laboratory, LNLS/CNPEM
-- Created : 2016-01-22
-- Last update: 2016-01-27
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
-- Synchronous pulse extender. Generates a pulse of dynamically programmable width upon
-- detection of a rising edge in the input. The code is based on
-- gc_extend_pulse.vhd created by Tomasz Wlostowskyt, from General Cores library.
-------------------------------------------------------------------------------
-- Copyright (c) 2016 Brazilian Synchrotron Light Laboratory, LNLS/CNPEM
-- This program is free software: you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public License
-- as published by the Free Software Foundation, either version 3 of
-- the License, or (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public
-- License along with this program. If not, see
-- <http://www.gnu.org/licenses/>.
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2015-dec-17 0.9 vfinotti Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.NUMERIC_STD.all;
entity extend_pulse_dyn is
generic (
-- output pulse width in clk_i cycles
g_width_bus_size : natural := 32
);
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
pulse_i : in std_logic;
pulse_width_i : in unsigned(g_width_bus_size-1 downto 0);
-- extended output pulse
extended_o : out std_logic := '0');
end extend_pulse_dyn;
architecture rtl of extend_pulse_dyn is
signal cntr : unsigned(g_width_bus_size-1 downto 0);
signal extended_int : std_logic;
begin -- rtl
extend : process (clk_i, rst_n_i)
begin -- process extend
if rst_n_i = '0' then -- asynchronous reset (active low)
extended_int <= '0';
cntr <= (others => '0');
elsif clk_i'event and clk_i = '1' then -- rising clock edge
if(pulse_i = '1') then
extended_int <= '1';
cntr <= pulse_width_i - 2;
elsif cntr /= to_unsigned(0, cntr'length) then
cntr <= cntr - 1;
else
extended_int <= '0';
end if;
end if;
end process extend;
extended_o <= pulse_i or extended_int;
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- Common cores
use work.genram_pkg.all;
entity heartbeat is
generic
(
-- number of system clock cycles to count before blinking
g_clk_counts : natural := 100000000
);
port
(
-- 100 MHz system clock
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Heartbeat pulse output
heartbeat_o : out std_logic
);
end heartbeat;
architecture rtl of heartbeat is
constant c_pps_counter_width : natural := f_log2_size(g_clk_counts);
signal hb : std_logic := '0';
signal pps_counter : unsigned(c_pps_counter_width-1 downto 0) :=
(others => '0');
begin
p_heartbeat : process (clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
pps_counter <= to_unsigned(0, pps_counter'length);
hb <= '0';
else
if pps_counter = g_clk_counts-1 then
pps_counter <= to_unsigned(0, pps_counter'length);
hb <= not hb;
else
pps_counter <= pps_counter + 1;
end if;
end if;
end if;
end process;
heartbeat_o <= hb;
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity pulse2level is
port
(
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Pulse input
pulse_i : in std_logic;
-- Clear level
clr_i : in std_logic;
-- Level output
level_o : out std_logic
);
end pulse2level;
architecture rtl of pulse2level is
signal level : std_logic := '0';
begin