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Beam Positoning Monitor - Gateware
Commits
d520e6f1
Commit
d520e6f1
authored
Jul 12, 2017
by
Lucas Russo
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Merge branch 'devel'
parents
2fe9e3a8
d56c1195
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2 changed files
with
33 additions
and
33 deletions
+33
-33
dsp-cores
hdl/ip_cores/dsp-cores
+1
-1
dbe_bpm_gen.vhd
hdl/top/afc_v3/vivado/dbe_bpm_gen/dbe_bpm_gen.vhd
+32
-32
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dsp-cores
@
c544b987
Subproject commit
d8ddce38be9fa14fe486f8273985782ecd9b7427
Subproject commit
c544b987e77dde307103cb4114ce26f2d7dbc413
hdl/top/afc_v3/vivado/dbe_bpm_gen/dbe_bpm_gen.vhd
View file @
d520e6f1
...
...
@@ -3312,10 +3312,10 @@ begin
--------------------
-- TBT PHASE 1 data
--------------------
acq_chan_array
(
c_acq_core_0_id
,
c_acq_tbt_phase_id
)
.
val
<=
std_logic_vector
(
resize
(
to_signed
(
0
,
c_dsp_ref_num_bits_ns
),
32
))
&
std_logic_vector
(
resize
(
to_signed
(
0
,
c_dsp_ref_num_bits_ns
),
32
))
&
std_logic_vector
(
resize
(
to_signed
(
0
,
c_dsp_ref_num_bits_ns
),
32
))
&
std_logic_vector
(
resize
(
to_signed
(
0
,
c_dsp_ref_num_bits_ns
),
32
));
acq_chan_array
(
c_acq_core_0_id
,
c_acq_tbt_phase_id
)
.
val
<=
std_logic_vector
(
resize
(
signed
(
dsp1_tbt_pha_ch3
),
32
))
&
std_logic_vector
(
resize
(
signed
(
dsp1_tbt_pha_ch2
),
32
))
&
std_logic_vector
(
resize
(
signed
(
dsp1_tbt_pha_ch1
),
32
))
&
std_logic_vector
(
resize
(
signed
(
dsp1_tbt_pha_ch0
),
32
));
acq_chan_array
(
c_acq_core_0_id
,
c_acq_tbt_phase_id
)
.
dvalid
<=
dsp1_tbt_pha_valid
;
acq_chan_array
(
c_acq_core_0_id
,
c_acq_tbt_phase_id
)
.
trig
<=
trig_pulse_rcv
(
c_trig_mux_0_id
,
c_acq_tbt_phase_id
)
.
pulse
;
...
...
@@ -3363,10 +3363,10 @@ begin
--------------------
-- FOFB PHASE 1 data
--------------------
acq_chan_array
(
c_acq_core_0_id
,
c_acq_fofb_phase_id
)
.
val
<=
std_logic_vector
(
resize
(
to_signed
(
0
,
c_dsp_ref_num_bits_ns
),
32
))
&
std_logic_vector
(
resize
(
to_signed
(
0
,
c_dsp_ref_num_bits_ns
),
32
))
&
std_logic_vector
(
resize
(
to_signed
(
0
,
c_dsp_ref_num_bits_ns
),
32
))
&
std_logic_vector
(
resize
(
to_signed
(
0
,
c_dsp_ref_num_bits_ns
),
32
));
acq_chan_array
(
c_acq_core_0_id
,
c_acq_fofb_phase_id
)
.
val
<=
std_logic_vector
(
resize
(
signed
(
dsp1_fofb_pha_ch3
),
32
))
&
std_logic_vector
(
resize
(
signed
(
dsp1_fofb_pha_ch2
),
32
))
&
std_logic_vector
(
resize
(
signed
(
dsp1_fofb_pha_ch1
),
32
))
&
std_logic_vector
(
resize
(
signed
(
dsp1_fofb_pha_ch0
),
32
));
acq_chan_array
(
c_acq_core_0_id
,
c_acq_fofb_phase_id
)
.
dvalid
<=
dsp1_fofb_pha_valid
;
acq_chan_array
(
c_acq_core_0_id
,
c_acq_fofb_phase_id
)
.
trig
<=
trig_pulse_rcv
(
c_trig_mux_0_id
,
c_acq_fofb_phase_id
)
.
pulse
;
...
...
@@ -3482,10 +3482,10 @@ begin
--------------------
-- TBT PHASE 2 data
--------------------
acq_chan_array
(
c_acq_core_1_id
,
c_acq_tbt_phase_id
)
.
val
<=
std_logic_vector
(
resize
(
to_signed
(
0
,
c_dsp_ref_num_bits_ns
),
32
))
&
std_logic_vector
(
resize
(
to_signed
(
0
,
c_dsp_ref_num_bits_ns
),
32
))
&
std_logic_vector
(
resize
(
to_signed
(
0
,
c_dsp_ref_num_bits_ns
),
32
))
&
std_logic_vector
(
resize
(
to_signed
(
0
,
c_dsp_ref_num_bits_ns
),
32
));
acq_chan_array
(
c_acq_core_1_id
,
c_acq_tbt_phase_id
)
.
val
<=
std_logic_vector
(
resize
(
signed
(
dsp2_tbt_pha_ch3
),
32
))
&
std_logic_vector
(
resize
(
signed
(
dsp2_tbt_pha_ch2
),
32
))
&
std_logic_vector
(
resize
(
signed
(
dsp2_tbt_pha_ch1
),
32
))
&
std_logic_vector
(
resize
(
signed
(
dsp2_tbt_pha_ch0
),
32
));
acq_chan_array
(
c_acq_core_1_id
,
c_acq_tbt_phase_id
)
.
dvalid
<=
dsp2_tbt_pha_valid
;
acq_chan_array
(
c_acq_core_1_id
,
c_acq_tbt_phase_id
)
.
trig
<=
trig_pulse_rcv
(
c_trig_mux_1_id
,
c_acq_tbt_phase_id
)
.
pulse
;
...
...
@@ -3533,10 +3533,10 @@ begin
--------------------
-- FOFB PHASE 2 data
--------------------
acq_chan_array
(
c_acq_core_1_id
,
c_acq_fofb_phase_id
)
.
val
<=
std_logic_vector
(
resize
(
to_signed
(
0
,
c_dsp_ref_num_bits_ns
),
32
))
&
std_logic_vector
(
resize
(
to_signed
(
0
,
c_dsp_ref_num_bits_ns
),
32
))
&
std_logic_vector
(
resize
(
to_signed
(
0
,
c_dsp_ref_num_bits_ns
),
32
))
&
std_logic_vector
(
resize
(
to_signed
(
0
,
c_dsp_ref_num_bits_ns
),
32
));
acq_chan_array
(
c_acq_core_1_id
,
c_acq_fofb_phase_id
)
.
val
<=
std_logic_vector
(
resize
(
signed
(
dsp2_fofb_pha_ch3
),
32
))
&
std_logic_vector
(
resize
(
signed
(
dsp2_fofb_pha_ch2
),
32
))
&
std_logic_vector
(
resize
(
signed
(
dsp2_fofb_pha_ch1
),
32
))
&
std_logic_vector
(
resize
(
signed
(
dsp2_fofb_pha_ch0
),
32
));
acq_chan_array
(
c_acq_core_1_id
,
c_acq_fofb_phase_id
)
.
dvalid
<=
dsp2_fofb_pha_valid
;
acq_chan_array
(
c_acq_core_1_id
,
c_acq_fofb_phase_id
)
.
trig
<=
trig_pulse_rcv
(
c_trig_mux_1_id
,
c_acq_fofb_phase_id
)
.
pulse
;
...
...
@@ -3652,10 +3652,10 @@ begin
--------------------
-- TBT PHASE 3 data
--------------------
acq_chan_array
(
c_acq_core_2_id
,
c_acq_tbt_phase_id
)
.
val
<=
std_logic_vector
(
resize
(
to_signed
(
0
,
c_dsp_ref_num_bits_ns
),
32
))
&
std_logic_vector
(
resize
(
to_signed
(
0
,
c_dsp_ref_num_bits_ns
),
32
))
&
std_logic_vector
(
resize
(
to_signed
(
0
,
c_dsp_ref_num_bits_ns
),
32
))
&
std_logic_vector
(
resize
(
to_signed
(
0
,
c_dsp_ref_num_bits_ns
),
32
));
acq_chan_array
(
c_acq_core_2_id
,
c_acq_tbt_phase_id
)
.
val
<=
std_logic_vector
(
resize
(
signed
(
dsp1_tbt_pha_ch3
),
32
))
&
std_logic_vector
(
resize
(
signed
(
dsp1_tbt_pha_ch2
),
32
))
&
std_logic_vector
(
resize
(
signed
(
dsp1_tbt_pha_ch1
),
32
))
&
std_logic_vector
(
resize
(
signed
(
dsp1_tbt_pha_ch0
),
32
));
acq_chan_array
(
c_acq_core_2_id
,
c_acq_tbt_phase_id
)
.
dvalid
<=
dsp1_tbt_pha_valid
;
acq_chan_array
(
c_acq_core_2_id
,
c_acq_tbt_phase_id
)
.
trig
<=
trig_pulse_rcv
(
c_trig_mux_2_id
,
c_acq_tbt_phase_id
)
.
pulse
;
...
...
@@ -3703,10 +3703,10 @@ begin
--------------------
-- FOFB PHASE 3 data
--------------------
acq_chan_array
(
c_acq_core_2_id
,
c_acq_fofb_phase_id
)
.
val
<=
std_logic_vector
(
resize
(
to_signed
(
0
,
c_dsp_ref_num_bits_ns
),
32
))
&
std_logic_vector
(
resize
(
to_signed
(
0
,
c_dsp_ref_num_bits_ns
),
32
))
&
std_logic_vector
(
resize
(
to_signed
(
0
,
c_dsp_ref_num_bits_ns
),
32
))
&
std_logic_vector
(
resize
(
to_signed
(
0
,
c_dsp_ref_num_bits_ns
),
32
));
acq_chan_array
(
c_acq_core_2_id
,
c_acq_fofb_phase_id
)
.
val
<=
std_logic_vector
(
resize
(
signed
(
dsp1_fofb_pha_ch3
),
32
))
&
std_logic_vector
(
resize
(
signed
(
dsp1_fofb_pha_ch2
),
32
))
&
std_logic_vector
(
resize
(
signed
(
dsp1_fofb_pha_ch1
),
32
))
&
std_logic_vector
(
resize
(
signed
(
dsp1_fofb_pha_ch0
),
32
));
acq_chan_array
(
c_acq_core_2_id
,
c_acq_fofb_phase_id
)
.
dvalid
<=
dsp1_fofb_pha_valid
;
acq_chan_array
(
c_acq_core_2_id
,
c_acq_fofb_phase_id
)
.
trig
<=
trig_pulse_rcv
(
c_trig_mux_2_id
,
c_acq_fofb_phase_id
)
.
pulse
;
...
...
@@ -3822,10 +3822,10 @@ begin
--------------------
-- TBT PHASE 4 data
--------------------
acq_chan_array
(
c_acq_core_3_id
,
c_acq_tbt_phase_id
)
.
val
<=
std_logic_vector
(
resize
(
to_signed
(
0
,
c_dsp_ref_num_bits_ns
),
32
))
&
std_logic_vector
(
resize
(
to_signed
(
0
,
c_dsp_ref_num_bits_ns
),
32
))
&
std_logic_vector
(
resize
(
to_signed
(
0
,
c_dsp_ref_num_bits_ns
),
32
))
&
std_logic_vector
(
resize
(
to_signed
(
0
,
c_dsp_ref_num_bits_ns
),
32
));
acq_chan_array
(
c_acq_core_3_id
,
c_acq_tbt_phase_id
)
.
val
<=
std_logic_vector
(
resize
(
signed
(
dsp2_tbt_pha_ch3
),
32
))
&
std_logic_vector
(
resize
(
signed
(
dsp2_tbt_pha_ch2
),
32
))
&
std_logic_vector
(
resize
(
signed
(
dsp2_tbt_pha_ch1
),
32
))
&
std_logic_vector
(
resize
(
signed
(
dsp2_tbt_pha_ch0
),
32
));
acq_chan_array
(
c_acq_core_3_id
,
c_acq_tbt_phase_id
)
.
dvalid
<=
dsp2_tbt_pha_valid
;
acq_chan_array
(
c_acq_core_3_id
,
c_acq_tbt_phase_id
)
.
trig
<=
trig_pulse_rcv
(
c_trig_mux_3_id
,
c_acq_tbt_phase_id
)
.
pulse
;
...
...
@@ -3873,10 +3873,10 @@ begin
--------------------
-- FOFB PHASE 4 data
--------------------
acq_chan_array
(
c_acq_core_3_id
,
c_acq_fofb_phase_id
)
.
val
<=
std_logic_vector
(
resize
(
to_signed
(
0
,
c_dsp_ref_num_bits_ns
),
32
))
&
std_logic_vector
(
resize
(
to_signed
(
0
,
c_dsp_ref_num_bits_ns
),
32
))
&
std_logic_vector
(
resize
(
to_signed
(
0
,
c_dsp_ref_num_bits_ns
),
32
))
&
std_logic_vector
(
resize
(
to_signed
(
0
,
c_dsp_ref_num_bits_ns
),
32
));
acq_chan_array
(
c_acq_core_3_id
,
c_acq_fofb_phase_id
)
.
val
<=
std_logic_vector
(
resize
(
signed
(
dsp2_fofb_pha_ch3
),
32
))
&
std_logic_vector
(
resize
(
signed
(
dsp2_fofb_pha_ch2
),
32
))
&
std_logic_vector
(
resize
(
signed
(
dsp2_fofb_pha_ch1
),
32
))
&
std_logic_vector
(
resize
(
signed
(
dsp2_fofb_pha_ch0
),
32
));
acq_chan_array
(
c_acq_core_3_id
,
c_acq_fofb_phase_id
)
.
dvalid
<=
dsp2_fofb_pha_valid
;
acq_chan_array
(
c_acq_core_3_id
,
c_acq_fofb_phase_id
)
.
trig
<=
trig_pulse_rcv
(
c_trig_mux_3_id
,
c_acq_fofb_phase_id
)
.
pulse
;
...
...
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