Skip to content
Projects
Groups
Snippets
Help
Loading...
Sign in
Toggle navigation
B
Beam Positoning Monitor - Gateware
Project
Project
Details
Activity
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Issues
0
Issues
0
List
Board
Labels
Milestones
Merge Requests
0
Merge Requests
0
Wiki
Wiki
image/svg+xml
Discourse
Discourse
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Create a new issue
Commits
Issue Boards
Open sidebar
Projects
Beam Positoning Monitor - Gateware
Commits
d801cdff
Commit
d801cdff
authored
Jul 21, 2017
by
Lucas Russo
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
modules/*/wb_fmc*: connect mmcm_rst register to mmcm_rst signal
In this way, we can reset MMCM by software
parent
15fdf54b
Hide whitespace changes
Inline
Side-by-side
Showing
3 changed files
with
14 additions
and
0 deletions
+14
-0
wb_fmc130m_4ch.vhd
hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd
+5
-0
wb_fmc250m_4ch.vhd
hdl/modules/dbe_wishbone/wb_fmc250m_4ch/wb_fmc250m_4ch.vhd
+5
-0
wb_fmc516.vhd
hdl/modules/dbe_wishbone/wb_fmc516/wb_fmc516.vhd
+4
-0
No files found.
hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd
View file @
d801cdff
...
...
@@ -309,6 +309,7 @@ architecture rtl of wb_fmc130m_4ch is
signal
fs_rst2x_sync_n
:
std_logic_vector
(
c_num_adc_channels
-1
downto
0
);
signal
adc_rst
:
std_logic
;
-- ADC reset from wishbone
signal
mmcm_adc_locked
:
std_logic
;
signal
mmcm_rst_reg
:
std_logic
;
-- ADC clock + data single ended inputs
signal
adc_in
:
t_adc_sdr_in_array
(
c_num_adc_channels
-1
downto
0
);
...
...
@@ -964,6 +965,7 @@ begin
fmc_led3_int
<=
regs_acommon_out
.
monitor_led3_o
;
adc_test_data_en
<=
regs_acommon_out
.
monitor_test_data_en_o
;
mmcm_rst_reg
<=
regs_acommon_out
.
monitor_mmcm_rst_o
;
-----------------------------
-- Pins connections for ADC interface structures
...
...
@@ -1096,6 +1098,9 @@ begin
-- ADC clock generation reset. Just a regular asynchronous reset.
sys_clk_200Mhz_i
=>
sys_clk_200Mhz_i
,
-- MMCM reset port
mmcm_rst_i
=>
mmcm_rst_reg
,
-----------------------------
-- External ports
-----------------------------
...
...
hdl/modules/dbe_wishbone/wb_fmc250m_4ch/wb_fmc250m_4ch.vhd
View file @
d801cdff
...
...
@@ -322,6 +322,7 @@ architecture rtl of wb_fmc250m_4ch is
signal
fs_rst2x_sync_n
:
std_logic_vector
(
c_num_adc_channels
-1
downto
0
);
signal
adc_rst
:
std_logic
;
-- ADC reset from wishbone
signal
mmcm_adc_locked
:
std_logic
;
signal
mmcm_rst_reg
:
std_logic
;
-- ADC clock + data single ended inputs
signal
adc_in
:
t_adc_in_array
(
c_num_adc_channels
-1
downto
0
);
...
...
@@ -974,6 +975,7 @@ begin
fmc_led3_int
<=
regs_acommon_out
.
monitor_led3_o
;
adc_test_data_en
<=
regs_acommon_out
.
monitor_test_data_en_o
;
mmcm_rst_reg
<=
regs_acommon_out
.
monitor_mmcm_rst_o
;
-----------------------------
-- Pins connections for ADC interface structures
...
...
@@ -1115,6 +1117,9 @@ begin
-- ADC clock generation reset. Just a regular asynchronous reset.
sys_clk_200Mhz_i
=>
sys_clk_200Mhz_i
,
-- MMCM reset port
mmcm_rst_i
=>
mmcm_rst_reg
,
-----------------------------
-- External ports
-----------------------------
...
...
hdl/modules/dbe_wishbone/wb_fmc516/wb_fmc516.vhd
View file @
d801cdff
...
...
@@ -308,6 +308,7 @@ architecture rtl of wb_fmc516 is
signal
fs_rst_n
:
std_logic
;
signal
fs_rst_sync_n
:
std_logic_vector
(
c_num_adc_channels
-1
downto
0
);
signal
mmcm_adc_locked
:
std_logic
;
signal
mmcm_rst_reg
:
std_logic
:
=
'0'
;
-- ADC clock + data single ended inputs
signal
adc_in
:
t_adc_in_array
(
c_num_adc_channels
-1
downto
0
);
...
...
@@ -1033,6 +1034,9 @@ begin
-- ADC clock generation reset. Just a regular asynchronous reset.
sys_clk_200Mhz_i
=>
sys_clk_200Mhz_i
,
-- MMCM reset port
mmcm_rst_i
=>
mmcm_rst_reg
,
-----------------------------
-- External ports
-----------------------------
...
...
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment