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Beam Positoning Monitor - Gateware
Commit d801cdff authored by Lucas Russo's avatar Lucas Russo
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modules/*/wb_fmc*: connect mmcm_rst register to mmcm_rst signal 

In this way, we can reset MMCM by software
parent 15fdf54b
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hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd
View file @ d801cdff
...@@ -309,6 +309,7 @@ architecture rtl of wb_fmc130m_4ch is ...@@ -309,6 +309,7 @@ architecture rtl of wb_fmc130m_4ch is
signal fs_rst2x_sync_n : std_logic_vector(c_num_adc_channels-1 downto 0); signal fs_rst2x_sync_n : std_logic_vector(c_num_adc_channels-1 downto 0);
signal adc_rst : std_logic; -- ADC reset from wishbone signal adc_rst : std_logic; -- ADC reset from wishbone
signal mmcm_adc_locked : std_logic; signal mmcm_adc_locked : std_logic;
signal mmcm_rst_reg : std_logic;
-- ADC clock + data single ended inputs -- ADC clock + data single ended inputs
signal adc_in : t_adc_sdr_in_array(c_num_adc_channels-1 downto 0); signal adc_in : t_adc_sdr_in_array(c_num_adc_channels-1 downto 0);
...@@ -964,6 +965,7 @@ begin ...@@ -964,6 +965,7 @@ begin
fmc_led3_int <= regs_acommon_out.monitor_led3_o; fmc_led3_int <= regs_acommon_out.monitor_led3_o;
adc_test_data_en <= regs_acommon_out.monitor_test_data_en_o; adc_test_data_en <= regs_acommon_out.monitor_test_data_en_o;
mmcm_rst_reg <= regs_acommon_out.monitor_mmcm_rst_o;
----------------------------- -----------------------------
-- Pins connections for ADC interface structures -- Pins connections for ADC interface structures
...@@ -1096,6 +1098,9 @@ begin ...@@ -1096,6 +1098,9 @@ begin
-- ADC clock generation reset. Just a regular asynchronous reset. -- ADC clock generation reset. Just a regular asynchronous reset.
sys_clk_200Mhz_i => sys_clk_200Mhz_i, sys_clk_200Mhz_i => sys_clk_200Mhz_i,
-- MMCM reset port
mmcm_rst_i => mmcm_rst_reg,
----------------------------- -----------------------------
-- External ports -- External ports
----------------------------- -----------------------------
......
hdl/modules/dbe_wishbone/wb_fmc250m_4ch/wb_fmc250m_4ch.vhd
View file @ d801cdff
...@@ -322,6 +322,7 @@ architecture rtl of wb_fmc250m_4ch is ...@@ -322,6 +322,7 @@ architecture rtl of wb_fmc250m_4ch is
signal fs_rst2x_sync_n : std_logic_vector(c_num_adc_channels-1 downto 0); signal fs_rst2x_sync_n : std_logic_vector(c_num_adc_channels-1 downto 0);
signal adc_rst : std_logic; -- ADC reset from wishbone signal adc_rst : std_logic; -- ADC reset from wishbone
signal mmcm_adc_locked : std_logic; signal mmcm_adc_locked : std_logic;
signal mmcm_rst_reg : std_logic;
-- ADC clock + data single ended inputs -- ADC clock + data single ended inputs
signal adc_in : t_adc_in_array(c_num_adc_channels-1 downto 0); signal adc_in : t_adc_in_array(c_num_adc_channels-1 downto 0);
...@@ -974,6 +975,7 @@ begin ...@@ -974,6 +975,7 @@ begin
fmc_led3_int <= regs_acommon_out.monitor_led3_o; fmc_led3_int <= regs_acommon_out.monitor_led3_o;
adc_test_data_en <= regs_acommon_out.monitor_test_data_en_o; adc_test_data_en <= regs_acommon_out.monitor_test_data_en_o;
mmcm_rst_reg <= regs_acommon_out.monitor_mmcm_rst_o;
----------------------------- -----------------------------
-- Pins connections for ADC interface structures -- Pins connections for ADC interface structures
...@@ -1115,6 +1117,9 @@ begin ...@@ -1115,6 +1117,9 @@ begin
-- ADC clock generation reset. Just a regular asynchronous reset. -- ADC clock generation reset. Just a regular asynchronous reset.
sys_clk_200Mhz_i => sys_clk_200Mhz_i, sys_clk_200Mhz_i => sys_clk_200Mhz_i,
-- MMCM reset port
mmcm_rst_i => mmcm_rst_reg,
----------------------------- -----------------------------
-- External ports -- External ports
----------------------------- -----------------------------
......
hdl/modules/dbe_wishbone/wb_fmc516/wb_fmc516.vhd
View file @ d801cdff
...@@ -308,6 +308,7 @@ architecture rtl of wb_fmc516 is ...@@ -308,6 +308,7 @@ architecture rtl of wb_fmc516 is
signal fs_rst_n : std_logic; signal fs_rst_n : std_logic;
signal fs_rst_sync_n : std_logic_vector(c_num_adc_channels-1 downto 0); signal fs_rst_sync_n : std_logic_vector(c_num_adc_channels-1 downto 0);
signal mmcm_adc_locked : std_logic; signal mmcm_adc_locked : std_logic;
signal mmcm_rst_reg : std_logic := '0';
-- ADC clock + data single ended inputs -- ADC clock + data single ended inputs
signal adc_in : t_adc_in_array(c_num_adc_channels-1 downto 0); signal adc_in : t_adc_in_array(c_num_adc_channels-1 downto 0);
...@@ -1033,6 +1034,9 @@ begin ...@@ -1033,6 +1034,9 @@ begin
-- ADC clock generation reset. Just a regular asynchronous reset. -- ADC clock generation reset. Just a regular asynchronous reset.
sys_clk_200Mhz_i => sys_clk_200Mhz_i, sys_clk_200Mhz_i => sys_clk_200Mhz_i,
-- MMCM reset port
mmcm_rst_i => mmcm_rst_reg,
----------------------------- -----------------------------
-- External ports -- External ports
----------------------------- -----------------------------
......
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