Merge branch 'devel'

d8bd780e · Lucas Russo · 083a57d9 · 4a13e92e · d8bd780e · d8bd780e
Commit d8bd780e authored Jun 15, 2015 by Lucas Russo
215 changed files
--- a/.gitmodules
+++ b/.gitmodules
 [submodule "hdl/ip_cores/general-cores"]
 	path = hdl/ip_cores/general-cores
-	url = https://github.com/lerwys/general-cores.git
+	url = https://github.com/lnls-dig/general-cores.git
 [submodule "hdl/ip_cores/etherbone-core"]
 	path = hdl/ip_cores/etherbone-core
 	url = git://ohwr.org/hdl-core-lib/etherbone-core.git
 [submodule "hdl/ip_cores/dsp-cores"]
 	path = hdl/ip_cores/dsp-cores
-	url = https://github.com/lerwys/dsp-cores.git
+	url = https://github.com/lnls-dig/dsp-cores.git
--- a/hdl/Manifest.py
+++ b/hdl/Manifest.py
@@ -10,8 +10,5 @@ modules = { "local": [
                "ip_cores/general-cores",
                "ip_cores/etherbone-core",
                "ip_cores/dsp-cores",
-                "platform/virtex6/chipscope",
-				"platform/virtex6/ip_cores"]
-#     "git" : [
-#     ]
+				"platform"]
    };
--- a/dsp-cores @ dbd00a07
+++ b/dsp-cores @ dbd00a07
-Subproject commit a4359eefce5a3e152a13a9b2a660766026e849fa
+Subproject commit dbd00a073c94d2a484712e9ffa3be9299c08cd78
--- a/general-cores @ cc53ef7f
+++ b/general-cores @ cc53ef7f
-Subproject commit 9596442d462afa1e89c05b2280f1e26f5507bdd2
+Subproject commit cc53ef7f6c381ca1ce56355b2fd992462e832ec4
--- a/hdl/ip_cores/pcie/7a200ffg1156/Manifest.py
+++ b/hdl/ip_cores/pcie/7a200ffg1156/Manifest.py
@@ -15,4 +15,5 @@ else:
             "sfifo_15x128.vhd"]

 modules = {"local" : ["pcie_core/source",
-                      "ddr_core/user_design"]}
+                      "ddr_core_2_3/user_design"]}
+                      #"ddr_core/user_design"]}
--- a/hdl/ip_cores/pcie/7a200ffg1156/ddr_core_2_3.xci
+++ b/hdl/ip_cores/pcie/7a200ffg1156/ddr_core_2_3.xci
--- a/hdl/ip_cores/pcie/7a200ffg1156/ddr_core_2_3/mig.prj
+++ b/hdl/ip_cores/pcie/7a200ffg1156/ddr_core_2_3/mig.prj
--- a/hdl/ip_cores/pcie/7a200ffg1156/ddr_core_2_3/user_design/Manifest.py
+++ b/hdl/ip_cores/pcie/7a200ffg1156/ddr_core_2_3/user_design/Manifest.py
+files = ["rtl/ddr_core.vhd",
+         "rtl/ddr_core_mig.vhd",
+         "rtl/clocking/",
+         "rtl/controller/",
+         "rtl/ecc/",
+         "rtl/ip_top/",
+         "rtl/phy/",
+         "rtl/ui/",
+         "constraints/ddr_core.xdc"]
+
--- a/hdl/ip_cores/pcie/7a200ffg1156/ddr_core_2_3/user_design/constraints/ddr_core.xdc
+++ b/hdl/ip_cores/pcie/7a200ffg1156/ddr_core_2_3/user_design/constraints/ddr_core.xdc
--- a/hdl/ip_cores/pcie/7a200ffg1156/ddr_core_2_3/user_design/constraints/ddr_core_ooc.xdc
+++ b/hdl/ip_cores/pcie/7a200ffg1156/ddr_core_2_3/user_design/constraints/ddr_core_ooc.xdc
+###################################################################################################
+## This constraints file contains default clock frequencies to be used during creation of a 
+## Synthesis Design Checkpoint (DCP). For best results the frequencies should be modified 
+## to match the target frequencies. 
+## This constraints file is not used in top-down/global synthesis (not the default flow of Vivado).
+###################################################################################################
+
+
+##################################################################################################
+## 
+##  Xilinx, Inc. 2010            www.xilinx.com 
+##  sáb fev 21 11:40:05 2015
+##  Generated by MIG Version 2.3
+##  
+##################################################################################################
+##  File name :       ddr_core.xdc
+##  Details :     Constraints file
+##                    FPGA Family:       ARTIX7
+##                    FPGA Part:         XC7A200T-FFG1156
+##                    Speedgrade:        -1
+##                    Design Entry:      VHDL
+##                    Frequency:         0 MHz
+##                    Time Period:       2500 ps
+##################################################################################################
+
+##################################################################################################
+## Controller 0
+## Memory Device: DDR3_SDRAM->Components->MT41J512M8XX-125
+## Data Width: 32
+## Time Period: 2500
+## Data Mask: 1
+##################################################################################################
+
+create_clock -period -2.14748e+06 [get_ports sys_clk_i]
+set_propagated_clock sys_clk_i
+          
\ No newline at end of file
--- a/hdl/ip_cores/pcie/7a200ffg1156/ddr_core_2_3/user_design/rtl/clocking/mig_7series_v2_3_clk_ibuf.v
+++ b/hdl/ip_cores/pcie/7a200ffg1156/ddr_core_2_3/user_design/rtl/clocking/mig_7series_v2_3_clk_ibuf.v
+//*****************************************************************************
+// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//
+//*****************************************************************************
+//   ____  ____
+//  /   /\/   /
+// /___/  \  /    Vendor: Xilinx
+// \   \   \/     Version:%version
+//  \   \         Application: MIG
+//  /   /         Filename: clk_ibuf.v
+// /___/   /\     Date Last Modified: $Date: 2011/06/02 08:34:56 $
+// \   \  /  \    Date Created:Mon Aug 3 2009
+//  \___\/\___\
+//
+//Device: Virtex-6
+//Design Name: DDR3 SDRAM
+//Purpose:
+//   Clock generation/distribution and reset synchronization
+//Reference:
+//Revision History:
+//*****************************************************************************
+`timescale 1ns/1ps
+
+module mig_7series_v2_3_clk_ibuf #
+  (
+   parameter SYSCLK_TYPE      = "DIFFERENTIAL",
+                                // input clock type
+   parameter DIFF_TERM_SYSCLK = "TRUE"
+                                // Differential Termination
+   )
+  (
+   // Clock inputs
+   input  sys_clk_p,          // System clock diff input
+   input  sys_clk_n,
+   input  sys_clk_i,
+   output mmcm_clk
+   );
+
+   (* KEEP = "TRUE" *) wire sys_clk_ibufg /* synthesis syn_keep = 1 */;
+
+  generate
+    if (SYSCLK_TYPE == "DIFFERENTIAL") begin: diff_input_clk
+
+      //***********************************************************************
+      // Differential input clock input buffers
+      //***********************************************************************
+
+      IBUFGDS #
+        (
+         .DIFF_TERM    (DIFF_TERM_SYSCLK),
+         .IBUF_LOW_PWR ("FALSE")
+         )
+        u_ibufg_sys_clk
+          (
+           .I  (sys_clk_p),
+           .IB (sys_clk_n),
+           .O  (sys_clk_ibufg)
+           );
+
+    end else if (SYSCLK_TYPE == "SINGLE_ENDED") begin: se_input_clk
+
+      //***********************************************************************
+      // SINGLE_ENDED input clock input buffers
+      //***********************************************************************
+
+      IBUFG #
+        (
+         .IBUF_LOW_PWR ("FALSE")
+         )
+        u_ibufg_sys_clk
+          (
+           .I  (sys_clk_i),
+           .O  (sys_clk_ibufg)
+           );
+    end else if (SYSCLK_TYPE == "NO_BUFFER") begin: internal_clk
+
+      //***********************************************************************
+      // System clock is driven from FPGA internal clock (clock from fabric)
+      //***********************************************************************
+      assign sys_clk_ibufg = sys_clk_i;
+   end
+  endgenerate
+
+  assign mmcm_clk = sys_clk_ibufg;
+
+endmodule
--- a/hdl/ip_cores/pcie/7a200ffg1156/ddr_core_2_3/user_design/rtl/clocking/mig_7series_v2_3_infrastructure.v
+++ b/hdl/ip_cores/pcie/7a200ffg1156/ddr_core_2_3/user_design/rtl/clocking/mig_7series_v2_3_infrastructure.v
--- a/hdl/ip_cores/pcie/7a200ffg1156/ddr_core_2_3/user_design/rtl/clocking/mig_7series_v2_3_iodelay_ctrl.v
+++ b/hdl/ip_cores/pcie/7a200ffg1156/ddr_core_2_3/user_design/rtl/clocking/mig_7series_v2_3_iodelay_ctrl.v
--- a/hdl/ip_cores/pcie/7a200ffg1156/ddr_core_2_3/user_design/rtl/clocking/mig_7series_v2_3_tempmon.v
+++ b/hdl/ip_cores/pcie/7a200ffg1156/ddr_core_2_3/user_design/rtl/clocking/mig_7series_v2_3_tempmon.v
--- a/hdl/ip_cores/pcie/7a200ffg1156/ddr_core_2_3/user_design/rtl/controller/mig_7series_v2_3_arb_mux.v
+++ b/hdl/ip_cores/pcie/7a200ffg1156/ddr_core_2_3/user_design/rtl/controller/mig_7series_v2_3_arb_mux.v
--- a/hdl/ip_cores/pcie/7a200ffg1156/ddr_core_2_3/user_design/rtl/controller/mig_7series_v2_3_arb_row_col.v
+++ b/hdl/ip_cores/pcie/7a200ffg1156/ddr_core_2_3/user_design/rtl/controller/mig_7series_v2_3_arb_row_col.v
--- a/hdl/ip_cores/pcie/7a200ffg1156/ddr_core_2_3/user_design/rtl/controller/mig_7series_v2_3_arb_select.v
+++ b/hdl/ip_cores/pcie/7a200ffg1156/ddr_core_2_3/user_design/rtl/controller/mig_7series_v2_3_arb_select.v
--- a/hdl/ip_cores/pcie/7a200ffg1156/ddr_core_2_3/user_design/rtl/controller/mig_7series_v2_3_bank_cntrl.v
+++ b/hdl/ip_cores/pcie/7a200ffg1156/ddr_core_2_3/user_design/rtl/controller/mig_7series_v2_3_bank_cntrl.v
--- a/hdl/ip_cores/pcie/7a200ffg1156/ddr_core_2_3/user_design/rtl/controller/mig_7series_v2_3_bank_common.v
+++ b/hdl/ip_cores/pcie/7a200ffg1156/ddr_core_2_3/user_design/rtl/controller/mig_7series_v2_3_bank_common.v
--- a/hdl/ip_cores/pcie/7a200ffg1156/ddr_core_2_3/user_design/rtl/controller/mig_7series_v2_3_bank_compare.v
+++ b/hdl/ip_cores/pcie/7a200ffg1156/ddr_core_2_3/user_design/rtl/controller/mig_7series_v2_3_bank_compare.v
--- a/hdl/ip_cores/pcie/7a200ffg1156/ddr_core_2_3/user_design/rtl/controller/mig_7series_v2_3_bank_mach.v
+++ b/hdl/ip_cores/pcie/7a200ffg1156/ddr_core_2_3/user_design/rtl/controller/mig_7series_v2_3_bank_mach.v
--- a/hdl/ip_cores/pcie/7a200ffg1156/ddr_core_2_3/user_design/rtl/controller/mig_7series_v2_3_bank_queue.v
+++ b/hdl/ip_cores/pcie/7a200ffg1156/ddr_core_2_3/user_design/rtl/controller/mig_7series_v2_3_bank_queue.v
--- a/hdl/ip_cores/pcie/7a200ffg1156/ddr_core_2_3/user_design/rtl/controller/mig_7series_v2_3_bank_state.v
+++ b/hdl/ip_cores/pcie/7a200ffg1156/ddr_core_2_3/user_design/rtl/controller/mig_7series_v2_3_bank_state.v
--- a/hdl/ip_cores/pcie/7a200ffg1156/ddr_core_2_3/user_design/rtl/controller/mig_7series_v2_3_col_mach.v
+++ b/hdl/ip_cores/pcie/7a200ffg1156/ddr_core_2_3/user_design/rtl/controller/mig_7series_v2_3_col_mach.v
--- a/hdl/ip_cores/pcie/7a200ffg1156/ddr_core_2_3/user_design/rtl/controller/mig_7series_v2_3_mc.v
+++ b/hdl/ip_cores/pcie/7a200ffg1156/ddr_core_2_3/user_design/rtl/controller/mig_7series_v2_3_mc.v
--- a/hdl/ip_cores/pcie/7a200ffg1156/ddr_core_2_3/user_design/rtl/controller/mig_7series_v2_3_rank_cntrl.v
+++ b/hdl/ip_cores/pcie/7a200ffg1156/ddr_core_2_3/user_design/rtl/controller/mig_7series_v2_3_rank_cntrl.v
--- a/hdl/ip_cores/pcie/7a200ffg1156/ddr_core_2_3/user_design/rtl/controller/mig_7series_v2_3_rank_common.v
+++ b/hdl/ip_cores/pcie/7a200ffg1156/ddr_core_2_3/user_design/rtl/controller/mig_7series_v2_3_rank_common.v
--- a/hdl/ip_cores/pcie/7a200ffg1156/ddr_core_2_3/user_design/rtl/controller/mig_7series_v2_3_rank_mach.v
+++ b/hdl/ip_cores/pcie/7a200ffg1156/ddr_core_2_3/user_design/rtl/controller/mig_7series_v2_3_rank_mach.v
--- a/hdl/ip_cores/pcie/7a200ffg1156/ddr_core_2_3/user_design/rtl/controller/mig_7series_v2_3_round_robin_arb.v
+++ b/hdl/ip_cores/pcie/7a200ffg1156/ddr_core_2_3/user_design/rtl/controller/mig_7series_v2_3_round_robin_arb.v
--- a/hdl/ip_cores/pcie/7a200ffg1156/ddr_core_2_3/user_design/rtl/ddr_core.vhd
+++ b/hdl/ip_cores/pcie/7a200ffg1156/ddr_core_2_3/user_design/rtl/ddr_core.vhd
--- a/hdl/ip_cores/pcie/7a200ffg1156/ddr_core_2_3/user_design/rtl/ddr_core_mig.vhd
+++ b/hdl/ip_cores/pcie/7a200ffg1156/ddr_core_2_3/user_design/rtl/ddr_core_mig.vhd
--- a/hdl/ip_cores/pcie/7a200ffg1156/ddr_core_2_3/user_design/rtl/ddr_core_mig_sim.vhd
+++ b/hdl/ip_cores/pcie/7a200ffg1156/ddr_core_2_3/user_design/rtl/ddr_core_mig_sim.vhd
--- a/hdl/ip_cores/pcie/7a200ffg1156/ddr_core_2_3/user_design/rtl/ecc/mig_7series_v2_3_ecc_buf.v
+++ b/hdl/ip_cores/pcie/7a200ffg1156/ddr_core_2_3/user_design/rtl/ecc/mig_7series_v2_3_ecc_buf.v
--- a/hdl/ip_cores/pcie/7a200ffg1156/ddr_core_2_3/user_design/rtl/ecc/mig_7series_v2_3_ecc_dec_fix.v
+++ b/hdl/ip_cores/pcie/7a200ffg1156/ddr_core_2_3/user_design/rtl/ecc/mig_7series_v2_3_ecc_dec_fix.v
--- a/hdl/ip_cores/pcie/7a200ffg1156/ddr_core_2_3/user_design/rtl/ecc/mig_7series_v2_3_ecc_gen.v
+++ b/hdl/ip_cores/pcie/7a200ffg1156/ddr_core_2_3/user_design/rtl/ecc/mig_7series_v2_3_ecc_gen.v
--- a/hdl/ip_cores/pcie/7a200ffg1156/ddr_core_2_3/user_design/rtl/ecc/mig_7series_v2_3_ecc_merge_enc.v
+++ b/hdl/ip_cores/pcie/7a200ffg1156/ddr_core_2_3/user_design/rtl/ecc/mig_7series_v2_3_ecc_merge_enc.v
+//*****************************************************************************
+// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//
+//*****************************************************************************
+//   ____  ____
+//  /   /\/   /
+// /___/  \  /    Vendor                : Xilinx
+// \   \   \/     Version               : %version
+//  \   \         Application           : MIG
+//  /   /         Filename              : ecc_merge_enc.v
+// /___/   /\     Date Last Modified    : $date$
+// \   \  /  \    Date Created          : Tue Jun 30 2009
+//  \___\/\___\
+//
+//Device            : 7-Series
+//Design Name       : DDR3 SDRAM
+//Purpose           :
+//Reference         :
+//Revision History  :
+//*****************************************************************************
+
+`timescale 1ps/1ps
+
+module mig_7series_v2_3_ecc_merge_enc
+  #(
+    parameter TCQ = 100,
+    parameter PAYLOAD_WIDTH         = 64,
+    parameter CODE_WIDTH            = 72,
+    parameter DATA_BUF_ADDR_WIDTH   = 4,
+    parameter DATA_BUF_OFFSET_WIDTH = 1,
+    parameter DATA_WIDTH            = 64,
+    parameter DQ_WIDTH              = 72,
+    parameter ECC_WIDTH             = 8,
+    parameter nCK_PER_CLK           = 4
+   )
+   (
+    /*AUTOARG*/
+  // Outputs
+  mc_wrdata, mc_wrdata_mask,
+  // Inputs
+  clk, rst, wr_data, wr_data_mask, rd_merge_data, h_rows, raw_not_ecc
+  );
+
+  input clk;
+  input rst;
+
+  input [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] wr_data;
+  input [2*nCK_PER_CLK*DATA_WIDTH/8-1:0] wr_data_mask;
+  input [2*nCK_PER_CLK*DATA_WIDTH-1:0] rd_merge_data;
+  
+  reg [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] wr_data_r;
+  reg [2*nCK_PER_CLK*DATA_WIDTH/8-1:0] wr_data_mask_r;
+  reg [2*nCK_PER_CLK*DATA_WIDTH-1:0] rd_merge_data_r;
+
+  always @(posedge clk) wr_data_r <= #TCQ wr_data;
+  always @(posedge clk) wr_data_mask_r <= #TCQ wr_data_mask;
+  always @(posedge clk) rd_merge_data_r <= #TCQ rd_merge_data;
+  
+  // Merge new data with memory read data.
+  wire [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] merged_data;
+  genvar h;
+  genvar i;
+  generate
+    for (h=0; h<2*nCK_PER_CLK; h=h+1) begin : merge_data_outer
+      for (i=0; i<DATA_WIDTH/8; i=i+1) begin : merge_data_inner
+        assign merged_data[h*PAYLOAD_WIDTH+i*8+:8] =  
+                wr_data_mask[h*DATA_WIDTH/8+i]
+                  ? rd_merge_data[h*DATA_WIDTH+i*8+:8]               
+                  : wr_data[h*PAYLOAD_WIDTH+i*8+:8];
+      end
+      if (PAYLOAD_WIDTH > DATA_WIDTH)
+        assign merged_data[(h+1)*PAYLOAD_WIDTH-1-:PAYLOAD_WIDTH-DATA_WIDTH]=
+                      wr_data[(h+1)*PAYLOAD_WIDTH-1-:PAYLOAD_WIDTH-DATA_WIDTH];
+                                                                   
+    end
+  endgenerate
+
+  // Generate ECC and overlay onto mc_wrdata.
+  input [CODE_WIDTH*ECC_WIDTH-1:0] h_rows;
+  input [2*nCK_PER_CLK-1:0] raw_not_ecc;
+  reg [2*nCK_PER_CLK-1:0] raw_not_ecc_r;
+  always @(posedge clk) raw_not_ecc_r <= #TCQ raw_not_ecc;
+  output reg [2*nCK_PER_CLK*DQ_WIDTH-1:0] mc_wrdata;
+  reg [2*nCK_PER_CLK*DQ_WIDTH-1:0] mc_wrdata_c;
+  genvar j;
+  integer k;
+  generate
+    for (j=0; j<2*nCK_PER_CLK; j=j+1) begin : ecc_word
+      always @(/*AS*/h_rows or merged_data or raw_not_ecc_r) begin
+        mc_wrdata_c[j*DQ_WIDTH+:DQ_WIDTH] =
+          {{DQ_WIDTH-PAYLOAD_WIDTH{1'b0}},
+           merged_data[j*PAYLOAD_WIDTH+:PAYLOAD_WIDTH]};
+        for (k=0; k<ECC_WIDTH; k=k+1)
+          if (~raw_not_ecc_r[j])
+            mc_wrdata_c[j*DQ_WIDTH+CODE_WIDTH-k-1] =
+              ^(merged_data[j*PAYLOAD_WIDTH+:DATA_WIDTH] & 
+                h_rows[k*CODE_WIDTH+:DATA_WIDTH]);
+      end
+    end
+  endgenerate
+always @(posedge clk) mc_wrdata <= mc_wrdata_c;
+
+  // Set all DRAM masks to zero.
+  output wire[2*nCK_PER_CLK*DQ_WIDTH/8-1:0] mc_wrdata_mask;
+  assign mc_wrdata_mask = {2*nCK_PER_CLK*DQ_WIDTH/8{1'b0}};
+
+endmodule
--- a/hdl/ip_cores/pcie/7a200ffg1156/ddr_core_2_3/user_design/rtl/ecc/mig_7series_v2_3_fi_xor.v
+++ b/hdl/ip_cores/pcie/7a200ffg1156/ddr_core_2_3/user_design/rtl/ecc/mig_7series_v2_3_fi_xor.v
--- a/hdl/ip_cores/pcie/7a200ffg1156/ddr_core_2_3/user_design/rtl/ip_top/mig_7series_v2_3_mem_intfc.v
+++ b/hdl/ip_cores/pcie/7a200ffg1156/ddr_core_2_3/user_design/rtl/ip_top/mig_7series_v2_3_mem_intfc.v
--- a/hdl/ip_cores/pcie/7a200ffg1156/ddr_core_2_3/user_design/rtl/ip_top/mig_7series_v2_3_memc_ui_top_std.v
+++ b/hdl/ip_cores/pcie/7a200ffg1156/ddr_core_2_3/user_design/rtl/ip_top/mig_7series_v2_3_memc_ui_top_std.v
--- a/hdl/ip_cores/pcie/7a200ffg1156/ddr_core_2_3/user_design/rtl/phy/mig_7series_v2_3_ddr_byte_group_io.v
+++ b/hdl/ip_cores/pcie/7a200ffg1156/ddr_core_2_3/user_design/rtl/phy/mig_7series_v2_3_ddr_byte_group_io.v
--- a/hdl/ip_cores/pcie/7a200ffg1156/ddr_core_2_3/user_design/rtl/phy/mig_7series_v2_3_ddr_byte_lane.v
+++ b/hdl/ip_cores/pcie/7a200ffg1156/ddr_core_2_3/user_design/rtl/phy/mig_7series_v2_3_ddr_byte_lane.v
--- a/hdl/ip_cores/pcie/7a200ffg1156/ddr_core_2_3/user_design/rtl/phy/mig_7series_v2_3_ddr_calib_top.v
+++ b/hdl/ip_cores/pcie/7a200ffg1156/ddr_core_2_3/user_design/rtl/phy/mig_7series_v2_3_ddr_calib_top.v
--- a/hdl/ip_cores/pcie/7a200ffg1156/ddr_core_2_3/user_design/rtl/phy/mig_7series_v2_3_ddr_if_post_fifo.v
+++ b/hdl/ip_cores/pcie/7a200ffg1156/ddr_core_2_3/user_design/rtl/phy/mig_7series_v2_3_ddr_if_post_fifo.v
--- a/hdl/ip_cores/pcie/7a200ffg1156/ddr_core_2_3/user_design/rtl/phy/mig_7series_v2_3_ddr_mc_phy.v
+++ b/hdl/ip_cores/pcie/7a200ffg1156/ddr_core_2_3/user_design/rtl/phy/mig_7series_v2_3_ddr_mc_phy.v
--- a/hdl/ip_cores/pcie/7a200ffg1156/ddr_core_2_3/user_design/rtl/phy/mig_7series_v2_3_ddr_mc_phy_wrapper.v
+++ b/hdl/ip_cores/pcie/7a200ffg1156/ddr_core_2_3/user_design/rtl/phy/mig_7series_v2_3_ddr_mc_phy_wrapper.v
--- a/hdl/ip_cores/pcie/7a200ffg1156/ddr_core_2_3/user_design/rtl/phy/mig_7series_v2_3_ddr_of_pre_fifo.v
+++ b/hdl/ip_cores/pcie/7a200ffg1156/ddr_core_2_3/user_design/rtl/phy/mig_7series_v2_3_ddr_of_pre_fifo.v
--- a/hdl/ip_cores/pcie/7a200ffg1156/ddr_core_2_3/user_design/rtl/phy/mig_7series_v2_3_ddr_phy_4lanes.v
+++ b/hdl/ip_cores/pcie/7a200ffg1156/ddr_core_2_3/user_design/rtl/phy/mig_7series_v2_3_ddr_phy_4lanes.v
--- a/hdl/ip_cores/pcie/7a200ffg1156/ddr_core_2_3/user_design/rtl/phy/mig_7series_v2_3_ddr_phy_ck_addr_cmd_delay.v
+++ b/hdl/ip_cores/pcie/7a200ffg1156/ddr_core_2_3/user_design/rtl/phy/mig_7series_v2_3_ddr_phy_ck_addr_cmd_delay.v
--- a/hdl/ip_cores/pcie/7a200ffg1156/ddr_core_2_3/user_design/rtl/phy/mig_7series_v2_3_ddr_phy_dqs_found_cal.v
+++ b/hdl/ip_cores/pcie/7a200ffg1156/ddr_core_2_3/user_design/rtl/phy/mig_7series_v2_3_ddr_phy_dqs_found_cal.v
--- a/hdl/ip_cores/pcie/7a200ffg1156/ddr_core_2_3/user_design/rtl/phy/mig_7series_v2_3_ddr_phy_dqs_found_cal_hr.v
+++ b/hdl/ip_cores/pcie/7a200ffg1156/ddr_core_2_3/user_design/rtl/phy/mig_7series_v2_3_ddr_phy_dqs_found_cal_hr.v
--- a/hdl/ip_cores/pcie/7a200ffg1156/ddr_core_2_3/user_design/rtl/phy/mig_7series_v2_3_ddr_phy_init.v
+++ b/hdl/ip_cores/pcie/7a200ffg1156/ddr_core_2_3/user_design/rtl/phy/mig_7series_v2_3_ddr_phy_init.v
--- a/hdl/ip_cores/pcie/7a200ffg1156/ddr_core_2_3/user_design/rtl/phy/mig_7series_v2_3_ddr_phy_ocd_cntlr.v
+++ b/hdl/ip_cores/pcie/7a200ffg1156/ddr_core_2_3/user_design/rtl/phy/mig_7series_v2_3_ddr_phy_ocd_cntlr.v
--- a/hdl/ip_cores/pcie/7a200ffg1156/ddr_core_2_3/user_design/rtl/phy/mig_7series_v2_3_ddr_phy_ocd_data.v
+++ b/hdl/ip_cores/pcie/7a200ffg1156/ddr_core_2_3/user_design/rtl/phy/mig_7series_v2_3_ddr_phy_ocd_data.v
--- a/hdl/ip_cores/pcie/7a200ffg1156/ddr_core_2_3/user_design/rtl/phy/mig_7series_v2_3_ddr_phy_ocd_edge.v
+++ b/hdl/ip_cores/pcie/7a200ffg1156/ddr_core_2_3/user_design/rtl/phy/mig_7series_v2_3_ddr_phy_ocd_edge.v
--- a/hdl/ip_cores/pcie/7a200ffg1156/ddr_core_2_3/user_design/rtl/phy/mig_7series_v2_3_ddr_phy_ocd_lim.v
+++ b/hdl/ip_cores/pcie/7a200ffg1156/ddr_core_2_3/user_design/rtl/phy/mig_7series_v2_3_ddr_phy_ocd_lim.v
--- a/hdl/ip_cores/pcie/7a200ffg1156/ddr_core_2_3/user_design/rtl/phy/mig_7series_v2_3_ddr_phy_ocd_mux.v
+++ b/hdl/ip_cores/pcie/7a200ffg1156/ddr_core_2_3/user_design/rtl/phy/mig_7series_v2_3_ddr_phy_ocd_mux.v
--- a/hdl/ip_cores/pcie/7a200ffg1156/ddr_core_2_3/user_design/rtl/phy/mig_7series_v2_3_ddr_phy_ocd_po_cntlr.v
+++ b/hdl/ip_cores/pcie/7a200ffg1156/ddr_core_2_3/user_design/rtl/phy/mig_7series_v2_3_ddr_phy_ocd_po_cntlr.v
--- a/hdl/ip_cores/pcie/7a200ffg1156/ddr_core_2_3/user_design/rtl/phy/mig_7series_v2_3_ddr_phy_ocd_samp.v
+++ b/hdl/ip_cores/pcie/7a200ffg1156/ddr_core_2_3/user_design/rtl/phy/mig_7series_v2_3_ddr_phy_ocd_samp.v
--- a/hdl/ip_cores/pcie/7a200ffg1156/ddr_core_2_3/user_design/rtl/phy/mig_7series_v2_3_ddr_phy_oclkdelay_cal.v
+++ b/hdl/ip_cores/pcie/7a200ffg1156/ddr_core_2_3/user_design/rtl/phy/mig_7series_v2_3_ddr_phy_oclkdelay_cal.v
--- a/hdl/ip_cores/pcie/7a200ffg1156/ddr_core_2_3/user_design/rtl/phy/mig_7series_v2_3_ddr_phy_prbs_rdlvl.v
+++ b/hdl/ip_cores/pcie/7a200ffg1156/ddr_core_2_3/user_design/rtl/phy/mig_7series_v2_3_ddr_phy_prbs_rdlvl.v
--- a/hdl/ip_cores/pcie/7a200ffg1156/ddr_core_2_3/user_design/rtl/phy/mig_7series_v2_3_ddr_phy_rdlvl.v
+++ b/hdl/ip_cores/pcie/7a200ffg1156/ddr_core_2_3/user_design/rtl/phy/mig_7series_v2_3_ddr_phy_rdlvl.v
--- a/hdl/ip_cores/pcie/7a200ffg1156/ddr_core_2_3/user_design/rtl/phy/mig_7series_v2_3_ddr_phy_tempmon.v
+++ b/hdl/ip_cores/pcie/7a200ffg1156/ddr_core_2_3/user_design/rtl/phy/mig_7series_v2_3_ddr_phy_tempmon.v
--- a/hdl/ip_cores/pcie/7a200ffg1156/ddr_core_2_3/user_design/rtl/phy/mig_7series_v2_3_ddr_phy_top.vhd
+++ b/hdl/ip_cores/pcie/7a200ffg1156/ddr_core_2_3/user_design/rtl/phy/mig_7series_v2_3_ddr_phy_top.vhd
--- a/hdl/ip_cores/pcie/7a200ffg1156/ddr_core_2_3/user_design/rtl/phy/mig_7series_v2_3_ddr_phy_wrcal.v
+++ b/hdl/ip_cores/pcie/7a200ffg1156/ddr_core_2_3/user_design/rtl/phy/mig_7series_v2_3_ddr_phy_wrcal.v
--- a/hdl/ip_cores/pcie/7a200ffg1156/ddr_core_2_3/user_design/rtl/phy/mig_7series_v2_3_ddr_phy_wrlvl.v
+++ b/hdl/ip_cores/pcie/7a200ffg1156/ddr_core_2_3/user_design/rtl/phy/mig_7series_v2_3_ddr_phy_wrlvl.v
--- a/hdl/ip_cores/pcie/7a200ffg1156/ddr_core_2_3/user_design/rtl/phy/mig_7series_v2_3_ddr_phy_wrlvl_off_delay.v
+++ b/hdl/ip_cores/pcie/7a200ffg1156/ddr_core_2_3/user_design/rtl/phy/mig_7series_v2_3_ddr_phy_wrlvl_off_delay.v
--- a/hdl/ip_cores/pcie/7a200ffg1156/ddr_core_2_3/user_design/rtl/phy/mig_7series_v2_3_ddr_prbs_gen.v
+++ b/hdl/ip_cores/pcie/7a200ffg1156/ddr_core_2_3/user_design/rtl/phy/mig_7series_v2_3_ddr_prbs_gen.v
--- a/hdl/ip_cores/pcie/7a200ffg1156/ddr_core_2_3/user_design/rtl/phy/mig_7series_v2_3_poc_cc.v
+++ b/hdl/ip_cores/pcie/7a200ffg1156/ddr_core_2_3/user_design/rtl/phy/mig_7series_v2_3_poc_cc.v
--- a/hdl/ip_cores/pcie/7a200ffg1156/ddr_core_2_3/user_design/rtl/phy/mig_7series_v2_3_poc_edge_store.v
+++ b/hdl/ip_cores/pcie/7a200ffg1156/ddr_core_2_3/user_design/rtl/phy/mig_7series_v2_3_poc_edge_store.v
--- a/hdl/ip_cores/pcie/7a200ffg1156/ddr_core_2_3/user_design/rtl/phy/mig_7series_v2_3_poc_meta.v
+++ b/hdl/ip_cores/pcie/7a200ffg1156/ddr_core_2_3/user_design/rtl/phy/mig_7series_v2_3_poc_meta.v
--- a/hdl/ip_cores/pcie/7a200ffg1156/ddr_core_2_3/user_design/rtl/phy/mig_7series_v2_3_poc_pd.v
+++ b/hdl/ip_cores/pcie/7a200ffg1156/ddr_core_2_3/user_design/rtl/phy/mig_7series_v2_3_poc_pd.v
--- a/hdl/ip_cores/pcie/7a200ffg1156/ddr_core_2_3/user_design/rtl/phy/mig_7series_v2_3_poc_tap_base.v
+++ b/hdl/ip_cores/pcie/7a200ffg1156/ddr_core_2_3/user_design/rtl/phy/mig_7series_v2_3_poc_tap_base.v
--- a/hdl/ip_cores/pcie/7a200ffg1156/ddr_core_2_3/user_design/rtl/phy/mig_7series_v2_3_poc_top.v
+++ b/hdl/ip_cores/pcie/7a200ffg1156/ddr_core_2_3/user_design/rtl/phy/mig_7series_v2_3_poc_top.v
--- a/hdl/ip_cores/pcie/7a200ffg1156/ddr_core_2_3/user_design/rtl/ui/mig_7series_v2_3_ui_cmd.v
+++ b/hdl/ip_cores/pcie/7a200ffg1156/ddr_core_2_3/user_design/rtl/ui/mig_7series_v2_3_ui_cmd.v
--- a/hdl/ip_cores/pcie/7a200ffg1156/ddr_core_2_3/user_design/rtl/ui/mig_7series_v2_3_ui_rd_data.v
+++ b/hdl/ip_cores/pcie/7a200ffg1156/ddr_core_2_3/user_design/rtl/ui/mig_7series_v2_3_ui_rd_data.v
--- a/hdl/ip_cores/pcie/7a200ffg1156/ddr_core_2_3/user_design/rtl/ui/mig_7series_v2_3_ui_top.v
+++ b/hdl/ip_cores/pcie/7a200ffg1156/ddr_core_2_3/user_design/rtl/ui/mig_7series_v2_3_ui_top.v
--- a/hdl/ip_cores/pcie/7a200ffg1156/ddr_core_2_3/user_design/rtl/ui/mig_7series_v2_3_ui_wr_data.v
+++ b/hdl/ip_cores/pcie/7a200ffg1156/ddr_core_2_3/user_design/rtl/ui/mig_7series_v2_3_ui_wr_data.v
--- a/hdl/modules/dbe_wishbone/Manifest.py
+++ b/hdl/modules/dbe_wishbone/Manifest.py
@@ -10,5 +10,6 @@ modules = { "local" : [
                        "wb_dbe_periph",
                        "wb_rs232_syscon",
                        "wb_acq_core",
+                        "wb_acq_core_2_to_1_mux",
                        "wb_pcie"
                      ] };
--- a/hdl/modules/dbe_wishbone/dbe_wishbone_pkg.vhd
+++ b/hdl/modules/dbe_wishbone/dbe_wishbone_pkg.vhd
--- a/hdl/modules/dbe_wishbone/wb_acq_core/Manifest.py
+++ b/hdl/modules/dbe_wishbone/wb_acq_core/Manifest.py
--- a/hdl/modules/dbe_wishbone/wb_acq_core/acq_2_diff_cnt.vhd
+++ b/hdl/modules/dbe_wishbone/wb_acq_core/acq_2_diff_cnt.vhd
--- a/hdl/modules/dbe_wishbone/wb_acq_core/acq_cnt.vhd
+++ b/hdl/modules/dbe_wishbone/wb_acq_core/acq_cnt.vhd
--- a/hdl/modules/dbe_wishbone/wb_acq_core/acq_core_pkg.vhd
+++ b/hdl/modules/dbe_wishbone/wb_acq_core/acq_core_pkg.vhd
--- a/hdl/modules/dbe_wishbone/wb_acq_core/acq_ddr3_iface.vhd
+++ b/hdl/modules/dbe_wishbone/wb_acq_core/acq_ddr3_iface.vhd
--- a/hdl/modules/dbe_wishbone/wb_acq_core/acq_ddr3_read.vhd
+++ b/hdl/modules/dbe_wishbone/wb_acq_core/acq_ddr3_read.vhd
--- a/hdl/modules/dbe_wishbone/wb_acq_core/acq_fc_fifo.vhd
+++ b/hdl/modules/dbe_wishbone/wb_acq_core/acq_fc_fifo.vhd
--- a/hdl/modules/dbe_wishbone/wb_acq_core/acq_fwft_fifo.vhd
+++ b/hdl/modules/dbe_wishbone/wb_acq_core/acq_fwft_fifo.vhd
--- a/hdl/modules/dbe_wishbone/wb_acq_core/fc_source.vhd
+++ b/hdl/modules/dbe_wishbone/wb_acq_core/fc_source.vhd
--- a/hdl/modules/dbe_wishbone/wb_acq_core/wb_acq_core.vhd
+++ b/hdl/modules/dbe_wishbone/wb_acq_core/wb_acq_core.vhd
--- a/hdl/modules/dbe_wishbone/wb_acq_core/wb_acq_core_plain.vhd
+++ b/hdl/modules/dbe_wishbone/wb_acq_core/wb_acq_core_plain.vhd
--- a/hdl/modules/dbe_wishbone/wb_acq_core/xwb_acq_core.vhd
+++ b/hdl/modules/dbe_wishbone/wb_acq_core/xwb_acq_core.vhd
--- a/hdl/modules/dbe_wishbone/wb_acq_core_2_to_1_mux/Manifest.py
+++ b/hdl/modules/dbe_wishbone/wb_acq_core_2_to_1_mux/Manifest.py
+files = ["wb_acq_core_2_to_1_mux.vhd",
+        "wb_acq_core_2_to_1_mux_plain.vhd",
+        "xwb_acq_core_2_to_1_mux.vhd",
+       ];
--- a/hdl/modules/dbe_wishbone/wb_acq_core_2_to_1_mux/wb_acq_core_2_to_1_mux.vhd
+++ b/hdl/modules/dbe_wishbone/wb_acq_core_2_to_1_mux/wb_acq_core_2_to_1_mux.vhd
--- a/hdl/modules/dbe_wishbone/wb_acq_core_2_to_1_mux/wb_acq_core_2_to_1_mux_plain.vhd
+++ b/hdl/modules/dbe_wishbone/wb_acq_core_2_to_1_mux/wb_acq_core_2_to_1_mux_plain.vhd
--- a/hdl/modules/dbe_wishbone/wb_acq_core_2_to_1_mux/xwb_acq_core_2_to_1_mux.vhd
+++ b/hdl/modules/dbe_wishbone/wb_acq_core_2_to_1_mux/xwb_acq_core_2_to_1_mux.vhd
--- a/hdl/modules/dbe_wishbone/wb_afc_diag/Manifest.py
+++ b/hdl/modules/dbe_wishbone/wb_afc_diag/Manifest.py
--- a/hdl/modules/dbe_wishbone/wb_afc_diag/coregen.cgp
+++ b/hdl/modules/dbe_wishbone/wb_afc_diag/coregen.cgp
--- a/hdl/modules/dbe_wishbone/wb_afc_diag/dpram_init.coe
+++ b/hdl/modules/dbe_wishbone/wb_afc_diag/dpram_init.coe
--- a/hdl/modules/dbe_wishbone/wb_afc_diag/shift_reg.v
+++ b/hdl/modules/dbe_wishbone/wb_afc_diag/shift_reg.v
--- a/hdl/modules/dbe_wishbone/wb_afc_diag/spi2wb.v
+++ b/hdl/modules/dbe_wishbone/wb_afc_diag/spi2wb.v
--- a/hdl/modules/dbe_wishbone/wb_afc_diag/spi2wb_dpram.ngc
+++ b/hdl/modules/dbe_wishbone/wb_afc_diag/spi2wb_dpram.ngc
--- a/hdl/modules/dbe_wishbone/wb_afc_diag/spi2wb_dpram.v
+++ b/hdl/modules/dbe_wishbone/wb_afc_diag/spi2wb_dpram.v
--- a/hdl/modules/dbe_wishbone/wb_afc_diag/spi2wb_tb.vhd
+++ b/hdl/modules/dbe_wishbone/wb_afc_diag/spi2wb_tb.vhd
--- a/hdl/modules/dbe_wishbone/wb_afc_diag/spi_fifo.ngc
+++ b/hdl/modules/dbe_wishbone/wb_afc_diag/spi_fifo.ngc
--- a/hdl/modules/dbe_wishbone/wb_afc_diag/spi_fifo.v
+++ b/hdl/modules/dbe_wishbone/wb_afc_diag/spi_fifo.v
--- a/hdl/modules/dbe_wishbone/wb_afc_diag/spi_link.vhd
+++ b/hdl/modules/dbe_wishbone/wb_afc_diag/spi_link.vhd
--- a/hdl/modules/dbe_wishbone/wb_afc_diag/spi_link_top.vhd
+++ b/hdl/modules/dbe_wishbone/wb_afc_diag/spi_link_top.vhd
--- a/hdl/modules/dbe_wishbone/wb_afc_diag/wave.wcfg
+++ b/hdl/modules/dbe_wishbone/wb_afc_diag/wave.wcfg
--- a/hdl/modules/dbe_wishbone/wb_afc_diag/wb_afc_diag.vhd
+++ b/hdl/modules/dbe_wishbone/wb_afc_diag/wb_afc_diag.vhd
--- a/hdl/modules/dbe_wishbone/wb_afc_diag/xwb_afc_diag.vhd
+++ b/hdl/modules/dbe_wishbone/wb_afc_diag/xwb_afc_diag.vhd
--- a/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd
+++ b/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd
--- a/hdl/modules/dbe_wishbone/wb_pcie/bpm_pcie_a7_pkg.vhd
+++ b/hdl/modules/dbe_wishbone/wb_pcie/bpm_pcie_a7_pkg.vhd
--- a/hdl/modules/dbe_wishbone/wb_pcie/wb_bpm_pcie_a7.vhd
+++ b/hdl/modules/dbe_wishbone/wb_pcie/wb_bpm_pcie_a7.vhd
--- a/hdl/modules/dbe_wishbone/wb_pcie/xwb_bpm_pcie_a7.vhd
+++ b/hdl/modules/dbe_wishbone/wb_pcie/xwb_bpm_pcie_a7.vhd
--- a/hdl/modules/pcie/bpm_pcie_a7.vhd
+++ b/hdl/modules/pcie/bpm_pcie_a7.vhd
--- a/hdl/modules/pcie/bpm_pcie_a7_priv_pkg.vhd
+++ b/hdl/modules/pcie/bpm_pcie_a7_priv_pkg.vhd
--- a/hdl/modules/pcie/common/DDRs_Control.vhd
+++ b/hdl/modules/pcie/common/DDRs_Control.vhd
--- a/hdl/platform/Manifest.py
+++ b/hdl/platform/Manifest.py
--- a/hdl/platform/artix7/chipscope/Manifest.py
+++ b/hdl/platform/artix7/chipscope/Manifest.py
--- a/hdl/platform/artix7/chipscope/icon_4_port/chipscope_icon_4_port.ngc
+++ b/hdl/platform/artix7/chipscope/icon_4_port/chipscope_icon_4_port.ngc
--- a/hdl/platform/artix7/chipscope/icon_4_port/chipscope_icon_4_port.vhd
+++ b/hdl/platform/artix7/chipscope/icon_4_port/chipscope_icon_4_port.vhd
--- a/hdl/platform/artix7/chipscope/icon_6_port/chipscope_icon_6_port.ngc
+++ b/hdl/platform/artix7/chipscope/icon_6_port/chipscope_icon_6_port.ngc
--- a/hdl/platform/artix7/chipscope/icon_6_port/chipscope_icon_6_port.vhd
+++ b/hdl/platform/artix7/chipscope/icon_6_port/chipscope_icon_6_port.vhd
--- a/hdl/platform/artix7/chipscope/ila/chipscope_ila.ngc
+++ b/hdl/platform/artix7/chipscope/ila/chipscope_ila.ngc
--- a/hdl/platform/artix7/chipscope/ila/chipscope_ila.vhd
+++ b/hdl/platform/artix7/chipscope/ila/chipscope_ila.vhd
--- a/hdl/platform/artix7/ip_cores/Manifest.py
+++ b/hdl/platform/artix7/ip_cores/Manifest.py
--- a/hdl/platform/artix7/ip_cores/axis_mux_2_to_1.xco
+++ b/hdl/platform/artix7/ip_cores/axis_mux_2_to_1.xco
--- a/hdl/platform/artix7/ip_cores/axis_mux_2_to_1.xise
+++ b/hdl/platform/artix7/ip_cores/axis_mux_2_to_1.xise
--- a/hdl/platform/artix7/ip_cores/axis_mux_2_to_1/Manifest.py
+++ b/hdl/platform/artix7/ip_cores/axis_mux_2_to_1/Manifest.py
--- a/hdl/platform/artix7/ip_cores/axis_mux_2_to_1/axis_mux_2_to_1.ngc
+++ b/hdl/platform/artix7/ip_cores/axis_mux_2_to_1/axis_mux_2_to_1.ngc
--- a/hdl/platform/artix7/ip_cores/axis_mux_2_to_1/axis_mux_2_to_1.vhd
+++ b/hdl/platform/artix7/ip_cores/axis_mux_2_to_1/axis_mux_2_to_1.vhd
--- a/hdl/platform/artix7/ip_cores/axis_mux_2_to_1/doc/axis_interconnect_v1_1_readme.txt
+++ b/hdl/platform/artix7/ip_cores/axis_mux_2_to_1/doc/axis_interconnect_v1_1_readme.txt
--- a/hdl/platform/artix7/ip_cores/axis_mux_2_to_1/doc/axis_interconnect_v1_1_vinfo.html
+++ b/hdl/platform/artix7/ip_cores/axis_mux_2_to_1/doc/axis_interconnect_v1_1_vinfo.html
--- a/hdl/platform/artix7/ip_cores/axis_mux_2_to_1/doc/pg035_axis_interconnect.pdf
+++ b/hdl/platform/artix7/ip_cores/axis_mux_2_to_1/doc/pg035_axis_interconnect.pdf
--- a/hdl/platform/artix7/ip_cores/axis_mux_2_to_1/hdl/verilog/Manifest.py
+++ b/hdl/platform/artix7/ip_cores/axis_mux_2_to_1/hdl/verilog/Manifest.py
--- a/hdl/platform/artix7/ip_cores/axis_mux_2_to_1/hdl/verilog/axis_interconnect_v1_1_arb_rr.v
+++ b/hdl/platform/artix7/ip_cores/axis_mux_2_to_1/hdl/verilog/axis_interconnect_v1_1_arb_rr.v
--- a/hdl/platform/artix7/ip_cores/axis_mux_2_to_1/hdl/verilog/axis_interconnect_v1_1_axis_clock_converter.v
+++ b/hdl/platform/artix7/ip_cores/axis_mux_2_to_1/hdl/verilog/axis_interconnect_v1_1_axis_clock_converter.v
--- a/hdl/platform/artix7/ip_cores/axis_mux_2_to_1/hdl/verilog/axis_interconnect_v1_1_axis_data_fifo.v
+++ b/hdl/platform/artix7/ip_cores/axis_mux_2_to_1/hdl/verilog/axis_interconnect_v1_1_axis_data_fifo.v
--- a/hdl/platform/artix7/ip_cores/axis_mux_2_to_1/hdl/verilog/axis_interconnect_v1_1_axis_dwidth_converter.v
+++ b/hdl/platform/artix7/ip_cores/axis_mux_2_to_1/hdl/verilog/axis_interconnect_v1_1_axis_dwidth_converter.v
--- a/hdl/platform/artix7/ip_cores/axis_mux_2_to_1/hdl/verilog/axis_interconnect_v1_1_axis_infrastructure.vh
+++ b/hdl/platform/artix7/ip_cores/axis_mux_2_to_1/hdl/verilog/axis_interconnect_v1_1_axis_infrastructure.vh
--- a/hdl/platform/artix7/ip_cores/axis_mux_2_to_1/hdl/verilog/axis_interconnect_v1_1_axis_interconnect.v
+++ b/hdl/platform/artix7/ip_cores/axis_mux_2_to_1/hdl/verilog/axis_interconnect_v1_1_axis_interconnect.v
--- a/hdl/platform/artix7/ip_cores/axis_mux_2_to_1/hdl/verilog/axis_interconnect_v1_1_axis_interconnect_16x16_top.v
+++ b/hdl/platform/artix7/ip_cores/axis_mux_2_to_1/hdl/verilog/axis_interconnect_v1_1_axis_interconnect_16x16_top.v
--- a/hdl/platform/artix7/ip_cores/axis_mux_2_to_1/hdl/verilog/axis_interconnect_v1_1_axis_register_slice.v
+++ b/hdl/platform/artix7/ip_cores/axis_mux_2_to_1/hdl/verilog/axis_interconnect_v1_1_axis_register_slice.v
--- a/hdl/platform/artix7/ip_cores/axis_mux_2_to_1/hdl/verilog/axis_interconnect_v1_1_axis_subset_converter.v
+++ b/hdl/platform/artix7/ip_cores/axis_mux_2_to_1/hdl/verilog/axis_interconnect_v1_1_axis_subset_converter.v
--- a/hdl/platform/artix7/ip_cores/axis_mux_2_to_1/hdl/verilog/axis_interconnect_v1_1_axis_switch.v
+++ b/hdl/platform/artix7/ip_cores/axis_mux_2_to_1/hdl/verilog/axis_interconnect_v1_1_axis_switch.v
--- a/hdl/platform/artix7/ip_cores/axis_mux_2_to_1/hdl/verilog/axis_interconnect_v1_1_axis_switch_arbiter.v
+++ b/hdl/platform/artix7/ip_cores/axis_mux_2_to_1/hdl/verilog/axis_interconnect_v1_1_axis_switch_arbiter.v
--- a/hdl/platform/artix7/ip_cores/axis_mux_2_to_1/hdl/verilog/axis_interconnect_v1_1_axisc_arb_responder.v
+++ b/hdl/platform/artix7/ip_cores/axis_mux_2_to_1/hdl/verilog/axis_interconnect_v1_1_axisc_arb_responder.v
--- a/hdl/platform/artix7/ip_cores/axis_mux_2_to_1/hdl/verilog/axis_interconnect_v1_1_axisc_decoder.v
+++ b/hdl/platform/artix7/ip_cores/axis_mux_2_to_1/hdl/verilog/axis_interconnect_v1_1_axisc_decoder.v
--- a/hdl/platform/artix7/ip_cores/axis_mux_2_to_1/hdl/verilog/axis_interconnect_v1_1_axisc_downsizer.v
+++ b/hdl/platform/artix7/ip_cores/axis_mux_2_to_1/hdl/verilog/axis_interconnect_v1_1_axisc_downsizer.v
--- a/hdl/platform/artix7/ip_cores/axis_mux_2_to_1/hdl/verilog/axis_interconnect_v1_1_axisc_register_slice.v
+++ b/hdl/platform/artix7/ip_cores/axis_mux_2_to_1/hdl/verilog/axis_interconnect_v1_1_axisc_register_slice.v
--- a/hdl/platform/artix7/ip_cores/axis_mux_2_to_1/hdl/verilog/axis_interconnect_v1_1_axisc_sample_cycle_ratio.v
+++ b/hdl/platform/artix7/ip_cores/axis_mux_2_to_1/hdl/verilog/axis_interconnect_v1_1_axisc_sample_cycle_ratio.v
--- a/hdl/platform/artix7/ip_cores/axis_mux_2_to_1/hdl/verilog/axis_interconnect_v1_1_axisc_sync_clock_converter.v
+++ b/hdl/platform/artix7/ip_cores/axis_mux_2_to_1/hdl/verilog/axis_interconnect_v1_1_axisc_sync_clock_converter.v
--- a/hdl/platform/artix7/ip_cores/axis_mux_2_to_1/hdl/verilog/axis_interconnect_v1_1_axisc_transfer_mux.v
+++ b/hdl/platform/artix7/ip_cores/axis_mux_2_to_1/hdl/verilog/axis_interconnect_v1_1_axisc_transfer_mux.v
--- a/hdl/platform/artix7/ip_cores/axis_mux_2_to_1/hdl/verilog/axis_interconnect_v1_1_axisc_upsizer.v
+++ b/hdl/platform/artix7/ip_cores/axis_mux_2_to_1/hdl/verilog/axis_interconnect_v1_1_axisc_upsizer.v
--- a/hdl/platform/artix7/ip_cores/axis_mux_2_to_1/hdl/verilog/axis_interconnect_v1_1_dynamic_datapath.v
+++ b/hdl/platform/artix7/ip_cores/axis_mux_2_to_1/hdl/verilog/axis_interconnect_v1_1_dynamic_datapath.v
--- a/hdl/platform/artix7/ip_cores/axis_mux_2_to_1/hdl/verilog/axis_interconnect_v1_1_dynamic_priority_encoder.v
+++ b/hdl/platform/artix7/ip_cores/axis_mux_2_to_1/hdl/verilog/axis_interconnect_v1_1_dynamic_priority_encoder.v
--- a/hdl/platform/artix7/ip_cores/axis_mux_2_to_1/hdl/verilog/axis_interconnect_v1_1_mux_enc.v
+++ b/hdl/platform/artix7/ip_cores/axis_mux_2_to_1/hdl/verilog/axis_interconnect_v1_1_mux_enc.v
--- a/hdl/platform/artix7/ip_cores/axis_mux_2_to_1/hdl/verilog/axis_interconnect_v1_1_util_aclken_converter.v
+++ b/hdl/platform/artix7/ip_cores/axis_mux_2_to_1/hdl/verilog/axis_interconnect_v1_1_util_aclken_converter.v
--- a/hdl/platform/artix7/ip_cores/axis_mux_2_to_1/hdl/verilog/axis_interconnect_v1_1_util_aclken_converter_wrapper.v
+++ b/hdl/platform/artix7/ip_cores/axis_mux_2_to_1/hdl/verilog/axis_interconnect_v1_1_util_aclken_converter_wrapper.v
--- a/hdl/platform/artix7/ip_cores/axis_mux_2_to_1/hdl/verilog/axis_interconnect_v1_1_util_axis2vector.v
+++ b/hdl/platform/artix7/ip_cores/axis_mux_2_to_1/hdl/verilog/axis_interconnect_v1_1_util_axis2vector.v
--- a/hdl/platform/artix7/ip_cores/axis_mux_2_to_1/hdl/verilog/axis_interconnect_v1_1_util_vector2axis.v
+++ b/hdl/platform/artix7/ip_cores/axis_mux_2_to_1/hdl/verilog/axis_interconnect_v1_1_util_vector2axis.v
--- a/hdl/platform/artix7/ip_cores/coregen.cgc
+++ b/hdl/platform/artix7/ip_cores/coregen.cgc
--- a/hdl/platform/artix7/ip_cores/coregen.cgp
+++ b/hdl/platform/artix7/ip_cores/coregen.cgp
--- a/hdl/syn/afc_v3/dbe_bpm_dsp_fmc130m_4ch/Manifest.py
+++ b/hdl/syn/afc_v3/dbe_bpm_dsp_fmc130m_4ch/Manifest.py
--- a/hdl/syn/afc_v3/dbe_bpm_dsp_fmc130m_4ch_2_to_1_mux/Manifest.py
+++ b/hdl/syn/afc_v3/dbe_bpm_dsp_fmc130m_4ch_2_to_1_mux/Manifest.py
--- a/hdl/syn/afc_v3/dbe_bpm_dsp_fmc130m_4ch_2_to_1_mux/README
+++ b/hdl/syn/afc_v3/dbe_bpm_dsp_fmc130m_4ch_2_to_1_mux/README
--- a/hdl/syn/afc_v3/dbe_bpm_dsp_fmc130m_4ch_2_to_1_mux/build_bitstream_local.sh
+++ b/hdl/syn/afc_v3/dbe_bpm_dsp_fmc130m_4ch_2_to_1_mux/build_bitstream_local.sh
--- a/hdl/syn/afc_v3/dbe_bpm_dsp_fmc130m_4ch_2_to_1_mux/build_bitstream_remote.sh
+++ b/hdl/syn/afc_v3/dbe_bpm_dsp_fmc130m_4ch_2_to_1_mux/build_bitstream_remote.sh
--- a/hdl/syn/afc_v3/dbe_bpm_dsp_fmc130m_4ch_2_to_1_mux/dbe_bpm_dsp.xise
+++ b/hdl/syn/afc_v3/dbe_bpm_dsp_fmc130m_4ch_2_to_1_mux/dbe_bpm_dsp.xise
--- a/hdl/syn/afc_v3/dbe_bpm_dsp_fmc130m_4ch_2_to_1_mux/dds_cos.nif
+++ b/hdl/syn/afc_v3/dbe_bpm_dsp_fmc130m_4ch_2_to_1_mux/dds_cos.nif
--- a/hdl/syn/afc_v3/dbe_bpm_dsp_fmc130m_4ch_2_to_1_mux/dds_sin.nif
+++ b/hdl/syn/afc_v3/dbe_bpm_dsp_fmc130m_4ch_2_to_1_mux/dds_sin.nif
--- a/hdl/syn/afc_v3/vivado/dbe_bpm_dsp_fmc130m_4ch_2_to_1_mux_ddr_2_3/Manifest.py
+++ b/hdl/syn/afc_v3/vivado/dbe_bpm_dsp_fmc130m_4ch_2_to_1_mux_ddr_2_3/Manifest.py
--- a/hdl/syn/afc_v3/vivado/dbe_bpm_dsp_fmc130m_4ch_2_to_1_mux_ddr_2_3/build_bitstream_local.sh
+++ b/hdl/syn/afc_v3/vivado/dbe_bpm_dsp_fmc130m_4ch_2_to_1_mux_ddr_2_3/build_bitstream_local.sh
--- a/hdl/syn/afc_v3/vivado/dbe_bpm_dsp_fmc130m_4ch_2_to_1_mux_ddr_2_3/build_bitstream_remote.sh
+++ b/hdl/syn/afc_v3/vivado/dbe_bpm_dsp_fmc130m_4ch_2_to_1_mux_ddr_2_3/build_bitstream_remote.sh
--- a/hdl/syn/afc_v3/vivado/dbe_bpm_dsp_fmc130m_4ch_2_to_1_mux_ddr_2_3/dbe_bpm_dsp.xpr
+++ b/hdl/syn/afc_v3/vivado/dbe_bpm_dsp_fmc130m_4ch_2_to_1_mux_ddr_2_3/dbe_bpm_dsp.xpr
--- a/hdl/syn/afc_v3/vivado/dbe_bpm_dsp_fmc130m_4ch_2_to_1_mux_ddr_2_3/dds_cos.nif
+++ b/hdl/syn/afc_v3/vivado/dbe_bpm_dsp_fmc130m_4ch_2_to_1_mux_ddr_2_3/dds_cos.nif
--- a/hdl/syn/afc_v3/vivado/dbe_bpm_dsp_fmc130m_4ch_2_to_1_mux_ddr_2_3/dds_sin.nif
+++ b/hdl/syn/afc_v3/vivado/dbe_bpm_dsp_fmc130m_4ch_2_to_1_mux_ddr_2_3/dds_sin.nif
--- a/hdl/syn/afc_v3/vivado/dbe_bpm_dsp_fmc130m_4ch_2_to_1_mux_ddr_2_3/project.vhd
+++ b/hdl/syn/afc_v3/vivado/dbe_bpm_dsp_fmc130m_4ch_2_to_1_mux_ddr_2_3/project.vhd
--- a/hdl/syn/afc_v3/vivado/test_adc_clk/Manifest.py
+++ b/hdl/syn/afc_v3/vivado/test_adc_clk/Manifest.py
--- a/hdl/syn/afc_v3/vivado/test_adc_clk/test_adc_clk.xpr
+++ b/hdl/syn/afc_v3/vivado/test_adc_clk/test_adc_clk.xpr
--- a/hdl/testbench/wishbone/wb_acq_core_test/verilog/artix7/full_tb/Makefile
+++ b/hdl/testbench/wishbone/wb_acq_core_test/verilog/artix7/full_tb/Makefile
--- a/hdl/testbench/wishbone/wb_acq_core_test/verilog/artix7/full_tb/wave_compl.do
+++ b/hdl/testbench/wishbone/wb_acq_core_test/verilog/artix7/full_tb/wave_compl.do
--- a/hdl/testbench/wishbone/wb_acq_core_test/verilog/artix7/full_tb/wb_acq_core_tb.v
+++ b/hdl/testbench/wishbone/wb_acq_core_test/verilog/artix7/full_tb/wb_acq_core_tb.v
--- a/hdl/testbench/wishbone/wb_acq_core_test/verilog/artix7/full_tb_mux/Makefile
+++ b/hdl/testbench/wishbone/wb_acq_core_test/verilog/artix7/full_tb_mux/Makefile
--- a/hdl/testbench/wishbone/wb_acq_core_test/verilog/artix7/full_tb_mux/Manifest.py
+++ b/hdl/testbench/wishbone/wb_acq_core_test/verilog/artix7/full_tb_mux/Manifest.py
--- a/hdl/testbench/wishbone/wb_acq_core_test/verilog/artix7/full_tb_mux/clk_rst.v
+++ b/hdl/testbench/wishbone/wb_acq_core_test/verilog/artix7/full_tb_mux/clk_rst.v
--- a/hdl/testbench/wishbone/wb_acq_core_test/verilog/artix7/full_tb_mux/ddr_core_wrapper.vhd
+++ b/hdl/testbench/wishbone/wb_acq_core_test/verilog/artix7/full_tb_mux/ddr_core_wrapper.vhd
--- a/hdl/testbench/wishbone/wb_acq_core_test/verilog/artix7/full_tb_mux/defines.v
+++ b/hdl/testbench/wishbone/wb_acq_core_test/verilog/artix7/full_tb_mux/defines.v
--- a/hdl/testbench/wishbone/wb_acq_core_test/verilog/artix7/full_tb_mux/run.do
+++ b/hdl/testbench/wishbone/wb_acq_core_test/verilog/artix7/full_tb_mux/run.do
--- a/hdl/testbench/wishbone/wb_acq_core_test/verilog/artix7/full_tb_mux/timescale.v
+++ b/hdl/testbench/wishbone/wb_acq_core_test/verilog/artix7/full_tb_mux/timescale.v
--- a/hdl/testbench/wishbone/wb_acq_core_test/verilog/artix7/full_tb_mux/wave.do
+++ b/hdl/testbench/wishbone/wb_acq_core_test/verilog/artix7/full_tb_mux/wave.do
--- a/hdl/testbench/wishbone/wb_acq_core_test/verilog/artix7/full_tb_mux/wave_compl.do
+++ b/hdl/testbench/wishbone/wb_acq_core_test/verilog/artix7/full_tb_mux/wave_compl.do
--- a/hdl/testbench/wishbone/wb_acq_core_test/verilog/artix7/full_tb_mux/wb_acq_core_tb.v
+++ b/hdl/testbench/wishbone/wb_acq_core_test/verilog/artix7/full_tb_mux/wb_acq_core_tb.v
--- a/hdl/top/afc_v3/dbe_bpm_dsp_fmc130m_4ch_2_to_1_mux/Manifest.py
+++ b/hdl/top/afc_v3/dbe_bpm_dsp_fmc130m_4ch_2_to_1_mux/Manifest.py
--- a/hdl/top/afc_v3/dbe_bpm_dsp_fmc130m_4ch_2_to_1_mux/afcv3_ucf.txt.xlsx
+++ b/hdl/top/afc_v3/dbe_bpm_dsp_fmc130m_4ch_2_to_1_mux/afcv3_ucf.txt.xlsx
--- a/hdl/top/afc_v3/dbe_bpm_dsp_fmc130m_4ch_2_to_1_mux/clk_gen.vhd
+++ b/hdl/top/afc_v3/dbe_bpm_dsp_fmc130m_4ch_2_to_1_mux/clk_gen.vhd
--- a/hdl/top/afc_v3/dbe_bpm_dsp_fmc130m_4ch_2_to_1_mux/dbe_bpm_dsp.ucf
+++ b/hdl/top/afc_v3/dbe_bpm_dsp_fmc130m_4ch_2_to_1_mux/dbe_bpm_dsp.ucf
--- a/hdl/top/afc_v3/dbe_bpm_dsp_fmc130m_4ch_2_to_1_mux/dbe_bpm_dsp.vhd
+++ b/hdl/top/afc_v3/dbe_bpm_dsp_fmc130m_4ch_2_to_1_mux/dbe_bpm_dsp.vhd
--- a/hdl/top/afc_v3/dbe_bpm_dsp_fmc130m_4ch_2_to_1_mux/dbe_bpm_dsp.xcf
+++ b/hdl/top/afc_v3/dbe_bpm_dsp_fmc130m_4ch_2_to_1_mux/dbe_bpm_dsp.xcf
--- a/hdl/top/afc_v3/dbe_bpm_dsp_fmc130m_4ch_2_to_1_mux/dsp_chipscope.cpj
+++ b/hdl/top/afc_v3/dbe_bpm_dsp_fmc130m_4ch_2_to_1_mux/dsp_chipscope.cpj
--- a/hdl/top/afc_v3/dbe_bpm_dsp_fmc130m_4ch_2_to_1_mux/position_calc_core.ucf
+++ b/hdl/top/afc_v3/dbe_bpm_dsp_fmc130m_4ch_2_to_1_mux/position_calc_core.ucf
--- a/hdl/top/afc_v3/dbe_bpm_dsp_fmc130m_4ch_2_to_1_mux/sys_pll.vhd
+++ b/hdl/top/afc_v3/dbe_bpm_dsp_fmc130m_4ch_2_to_1_mux/sys_pll.vhd
--- a/hdl/top/afc_v3/vivado/dbe_bpm_dsp_fmc130m_4ch_2_to_1_mux_ddr_2_3/Manifest.py
+++ b/hdl/top/afc_v3/vivado/dbe_bpm_dsp_fmc130m_4ch_2_to_1_mux_ddr_2_3/Manifest.py
--- a/hdl/top/afc_v3/vivado/dbe_bpm_dsp_fmc130m_4ch_2_to_1_mux_ddr_2_3/afcv3_ucf.txt.xlsx
+++ b/hdl/top/afc_v3/vivado/dbe_bpm_dsp_fmc130m_4ch_2_to_1_mux_ddr_2_3/afcv3_ucf.txt.xlsx
--- a/hdl/top/afc_v3/vivado/dbe_bpm_dsp_fmc130m_4ch_2_to_1_mux_ddr_2_3/clk_gen.vhd
+++ b/hdl/top/afc_v3/vivado/dbe_bpm_dsp_fmc130m_4ch_2_to_1_mux_ddr_2_3/clk_gen.vhd
--- a/hdl/top/afc_v3/vivado/dbe_bpm_dsp_fmc130m_4ch_2_to_1_mux_ddr_2_3/dbe_bpm_dsp.vhd
+++ b/hdl/top/afc_v3/vivado/dbe_bpm_dsp_fmc130m_4ch_2_to_1_mux_ddr_2_3/dbe_bpm_dsp.vhd
--- a/hdl/top/afc_v3/vivado/dbe_bpm_dsp_fmc130m_4ch_2_to_1_mux_ddr_2_3/dbe_bpm_dsp.xcf
+++ b/hdl/top/afc_v3/vivado/dbe_bpm_dsp_fmc130m_4ch_2_to_1_mux_ddr_2_3/dbe_bpm_dsp.xcf
--- a/hdl/top/afc_v3/vivado/dbe_bpm_dsp_fmc130m_4ch_2_to_1_mux_ddr_2_3/dbe_bpm_dsp.xdc
+++ b/hdl/top/afc_v3/vivado/dbe_bpm_dsp_fmc130m_4ch_2_to_1_mux_ddr_2_3/dbe_bpm_dsp.xdc
--- a/hdl/top/afc_v3/vivado/dbe_bpm_dsp_fmc130m_4ch_2_to_1_mux_ddr_2_3/ddr_core.xdc
+++ b/hdl/top/afc_v3/vivado/dbe_bpm_dsp_fmc130m_4ch_2_to_1_mux_ddr_2_3/ddr_core.xdc
--- a/hdl/top/afc_v3/vivado/dbe_bpm_dsp_fmc130m_4ch_2_to_1_mux_ddr_2_3/dsp_chipscope.cpj
+++ b/hdl/top/afc_v3/vivado/dbe_bpm_dsp_fmc130m_4ch_2_to_1_mux_ddr_2_3/dsp_chipscope.cpj
--- a/hdl/top/afc_v3/vivado/dbe_bpm_dsp_fmc130m_4ch_2_to_1_mux_ddr_2_3/pcie_core.xdc
+++ b/hdl/top/afc_v3/vivado/dbe_bpm_dsp_fmc130m_4ch_2_to_1_mux_ddr_2_3/pcie_core.xdc
--- a/hdl/top/afc_v3/vivado/dbe_bpm_dsp_fmc130m_4ch_2_to_1_mux_ddr_2_3/sys_pll.vhd
+++ b/hdl/top/afc_v3/vivado/dbe_bpm_dsp_fmc130m_4ch_2_to_1_mux_ddr_2_3/sys_pll.vhd
--- a/hdl/top/afc_v3/vivado/test_adc_clk/Manifest.py
+++ b/hdl/top/afc_v3/vivado/test_adc_clk/Manifest.py
--- a/hdl/top/afc_v3/vivado/test_adc_clk/dbe_bpm_dsp.vhd
+++ b/hdl/top/afc_v3/vivado/test_adc_clk/dbe_bpm_dsp.vhd
--- a/hdl/top/afc_v3/vivado/test_adc_clk/dbe_bpm_dsp.xdc
+++ b/hdl/top/afc_v3/vivado/test_adc_clk/dbe_bpm_dsp.xdc