Merge branch 'devel'

ecda1dde · Lucas Russo · d01c6e95 · e80c939a · f17f5472 · 366e800b
Commit ecda1dde authored Apr 06, 2017 by Lucas Russo
117 changed files
--- a/dsp-cores @ f17f5472
+++ b/dsp-cores @ f17f5472
-Subproject commit 1bf1b924c576334225a5df2c707ca8666d96a2c8
+Subproject commit f17f5472d49446ae07c4bc2e170effde7726ba81
--- a/general-cores @ 366e800b
+++ b/general-cores @ 366e800b
-Subproject commit cc53ef7f6c381ca1ce56355b2fd992462e832ec4
+Subproject commit 366e800bea582a071d14b2ecf2e9d153ff902b2e
--- a/hdl/modules/dbe_common/reset_synch/reset_synch.vhd
+++ b/hdl/modules/dbe_common/reset_synch/reset_synch.vhd
@@ -50,9 +50,13 @@ begin

  gen_pipe : if g_pipeline > 1 generate
    -- Shift reg
-    p_rst_pipe : process (clk_i)
+    p_rst_pipe : process (clk_i, arst_n_i)
    begin
-      if rising_edge(clk_i) then
+      if arst_n_i = '0' then
+        for i in 0 to g_pipeline-2 loop
+          s_ff(i+1) <= '0';
+        end loop;
+      elsif rising_edge(clk_i) then
        for i in 0 to g_pipeline-2 loop
          s_ff(i+1) <= s_ff(i);
        end loop;

--- a/hdl/modules/dbe_wishbone/Manifest.py
+++ b/hdl/modules/dbe_wishbone/Manifest.py
@@ -2,19 +2,23 @@ files = [ "dbe_wishbone_pkg.vhd" ];

 modules = { "local" : [
                        "wb_stream",
-			"wb_trigger_iface",
-			"wb_trigger_mux",
-			"wb_trigger",
+                        "wb_trigger_iface",
+                        "wb_trigger_mux",
+                        "wb_trigger",
+                        "wb_afc_diag",
                        "wb_fmc150",
                        "wb_fmc516",
                        "wb_fmc130m_4ch",
                        "wb_fmc250m_4ch",
+                        "wb_fmcpico1m_4ch",
                        "wb_ethmac_adapter",
                        "wb_ethmac",
                        "wb_dbe_periph",
                        "wb_rs232_syscon",
                        "wb_acq_core",
                        "wb_acq_core_mux",
+                        "wb_facq_core",
+                        "wb_facq_core_mux",
                        "wb_pcie",
                        "wb_fmc_adc_common",
                        "wb_fmc_active_clk"

--- a/hdl/modules/dbe_wishbone/dbe_wishbone_pkg.vhd
+++ b/hdl/modules/dbe_wishbone/dbe_wishbone_pkg.vhd
--- a/hdl/modules/dbe_wishbone/wb_acq_core/acq_core_pkg.vhd
+++ b/hdl/modules/dbe_wishbone/wb_acq_core/acq_core_pkg.vhd
--- a/hdl/modules/dbe_wishbone/wb_acq_core/acq_ddr3_axis_read.vhd
+++ b/hdl/modules/dbe_wishbone/wb_acq_core/acq_ddr3_axis_read.vhd
@@ -152,15 +152,15 @@ architecture rtl of acq_ddr3_axis_read is
  signal lmt_shots_nb                       : unsigned(c_shots_size_width-1 downto 0);
  signal lmt_valid                          : std_logic;
  signal lmt_curr_chan_id                   : unsigned(c_chan_id_width-1 downto 0);
-  signal lmt_chan_curr_width                : unsigned(c_acq_chan_max_w_log2-1 downto 0);
+  signal lmt_chan_curr_width                : unsigned(c_acq_chan_cmplt_width_log2-1 downto 0);
  signal rb_ddr_trig_addr                   : unsigned(g_ddr_addr_width-1 downto 0);
  -- For intermediate multiplication result
-  signal lmt_full_pkt_addr_ss               : unsigned(39 downto 0);
-  signal lmt_full_pkt_addr_ms               : unsigned(39 downto 0);
-  signal lmt_pre_pkt_addr                   : unsigned(39 downto 0);
-  signal lmt_pre_full_addr                  : unsigned(39 downto 0);
-  signal lmt_pre_full_addr_m                : unsigned(79 downto 0);
-  signal sample_size                        : unsigned(7 downto 0);
+  signal lmt_full_pkt_addr_ss               : unsigned(42 downto 0);
+  signal lmt_full_pkt_addr_ms               : unsigned(42 downto 0);
+  signal lmt_pre_pkt_addr                   : unsigned(42 downto 0);
+  signal lmt_pre_full_addr                  : unsigned(42 downto 0);
+  signal lmt_pre_full_addr_m                : unsigned(42 downto 0);
+  signal lmt_curr_chan_width_bytes          : unsigned(t_acq_width'length-1 downto 0);

  -- DDR3 Signals
  signal ddr_data_in                        : std_logic_vector(c_ddr_payload_width-1 downto 0);
@@ -308,15 +308,14 @@ begin
    end if;
  end process;

-  sample_size  <= g_acq_channels(to_integer(lmt_curr_chan_id_i)).width/
-                          g_acq_channels(to_integer(lmt_curr_chan_id_i)).num_atoms/8;
+  lmt_curr_chan_width_bytes <= g_acq_channels(to_integer(lmt_curr_chan_id_i)).width/8; -- in bytes

-  lmt_full_pkt_addr_ss <= lmt_full_pkt_size*sample_size;
+  lmt_full_pkt_addr_ss <= lmt_full_pkt_size*lmt_curr_chan_width_bytes;
  lmt_full_pkt_addr_ms <= lmt_full_pkt_addr_ss(lmt_full_pkt_addr_ss'left-lmt_shots_nb'length downto 0)*(lmt_shots_nb-1);
-  lmt_pre_pkt_addr <= lmt_pre_pkt_size*sample_size;
+  lmt_pre_pkt_addr <= lmt_pre_pkt_size*lmt_curr_chan_width_bytes;

-  lmt_pre_full_addr_m <= (lmt_full_pkt_addr_ms + lmt_pre_pkt_addr)*c_bytes_per_word;
-  lmt_pre_full_addr <= lmt_pre_full_addr_m(39 downto 0);
+  lmt_pre_full_addr_m <= (lmt_full_pkt_addr_ms + lmt_pre_pkt_addr); -- in bytes
+  lmt_pre_full_addr <= lmt_pre_full_addr_m; -- in bytes

  ----------------------------------------------------------------------------
  -- Start reading

--- a/hdl/modules/dbe_wishbone/wb_acq_core/acq_fc_fifo.vhd
+++ b/hdl/modules/dbe_wishbone/wb_acq_core/acq_fc_fifo.vhd
@@ -445,9 +445,10 @@ begin
  -- FOR SIMULATION ONLY
  -- Assert error if fifo_fc_mux_cnt signal is anything different than zero after the
  -- end of transaction
-  assert (not(fs_rst_n_i = '1' and ext_rst_n_i = '1') or ((fifo_fc_all_trans_done_lvl = '1' and
-            fifo_fc_mux_cnt = to_unsigned(0, fifo_fc_mux_cnt'length)) or -- end of transaction case
-            (fifo_fc_all_trans_done_sync = '0'))) -- every other case
+  assert (not(fs_rst_n_i = '1' and ext_rst_n_i = '1') or                         -- initial reset case
+            (((fifo_fc_all_trans_done_lvl = '1' or fifo_fc_all_trans_done_sync = '1') and
+                    fifo_fc_mux_cnt = to_unsigned(0, fifo_fc_mux_cnt'length)) or -- end of transaction case
+            (fifo_fc_all_trans_done_sync = '0')))                                -- every other case
  report "[acq_fc_fifo] fifo_fc_mux_cnt signal is not 0 after the end of the transaction!"
  severity failure;


--- a/hdl/modules/dbe_wishbone/wb_acq_core/acq_fsm.vhd
+++ b/hdl/modules/dbe_wishbone/wb_acq_core/acq_fsm.vhd
--- a/hdl/modules/dbe_wishbone/wb_acq_core/acq_sel_chan.vhd
+++ b/hdl/modules/dbe_wishbone/wb_acq_core/acq_sel_chan.vhd
@@ -40,6 +40,7 @@ port
  acq_val_low_i                             : in t_acq_val_half_array(g_acq_num_channels-1 downto 0);
  acq_val_high_i                            : in t_acq_val_half_array(g_acq_num_channels-1 downto 0);
  acq_dvalid_i                              : in std_logic_vector(g_acq_num_channels-1 downto 0);
+  acq_id_i                                  : in t_acq_id_array(g_acq_num_channels-1 downto 0);
  acq_trig_i                                : in std_logic_vector(g_acq_num_channels-1 downto 0);

  -- Current channel selection ID
@@ -52,6 +53,7 @@ port
 -----------------------------
  acq_data_o                                : out std_logic_vector(c_acq_chan_max_w-1 downto 0);
  acq_dvalid_o                              : out std_logic;
+  acq_id_o                                  : out t_acq_id;
  acq_trig_o                                : out std_logic
 );
 end acq_sel_chan;
@@ -64,10 +66,12 @@ architecture rtl of acq_sel_chan is
  signal acq_data_marsh_demux               : std_logic_vector(c_acq_chan_max_w-1 downto 0);
  signal acq_trig_demux                     : std_logic;
  signal acq_dvalid_demux                   : std_logic;
+  signal acq_id_demux                       : t_acq_id;

  signal acq_data_marsh_demux_reg           : std_logic_vector(c_acq_chan_max_w-1 downto 0);
  signal acq_trig_demux_reg                 : std_logic;
  signal acq_dvalid_demux_reg               : std_logic;
+  signal acq_id_demux_reg                   : t_acq_id;

 begin

@@ -92,6 +96,7 @@ begin
                                                acq_val_low_i(to_integer(lmt_curr_chan_id))));
 acq_trig_demux                         <= acq_trig_i(to_integer(lmt_curr_chan_id));
 acq_dvalid_demux                       <= acq_dvalid_i(to_integer(lmt_curr_chan_id));
+ acq_id_demux                           <= acq_id_i(to_integer(lmt_curr_chan_id));

 p_reg_demux : process (clk_i)
 begin
@@ -99,10 +104,12 @@ begin
     if rst_n_i = '0' then
       acq_data_marsh_demux_reg <= (others => '0');
       acq_dvalid_demux_reg <= '0';
+       acq_id_demux_reg <= to_unsigned(0, acq_id_demux_reg'length);
       acq_trig_demux_reg <= '0';
     else
       acq_data_marsh_demux_reg <= acq_data_marsh_demux;
       acq_dvalid_demux_reg <= acq_dvalid_demux;
+       acq_id_demux_reg <= acq_id_demux;
       acq_trig_demux_reg <= acq_trig_demux;
     end if;
   end if;
@@ -110,6 +117,7 @@ begin

 acq_data_o                               <= acq_data_marsh_demux_reg;
 acq_dvalid_o                             <= acq_dvalid_demux_reg;
+ acq_id_o                                 <= acq_id_demux_reg;
 acq_trig_o                               <= acq_trig_demux_reg;

 end rtl;
--- a/hdl/modules/dbe_wishbone/wb_acq_core/acq_trigger.vhd
+++ b/hdl/modules/dbe_wishbone/wb_acq_core/acq_trigger.vhd
--- a/hdl/modules/dbe_wishbone/wb_acq_core/wb_acq_core.vhd
+++ b/hdl/modules/dbe_wishbone/wb_acq_core/wb_acq_core.vhd
--- a/hdl/modules/dbe_wishbone/wb_acq_core/wb_acq_core_plain.vhd
+++ b/hdl/modules/dbe_wishbone/wb_acq_core/wb_acq_core_plain.vhd
@@ -84,6 +84,7 @@ port
  acq_val_low_i                             : in std_logic_vector(g_acq_num_channels*c_acq_chan_width-1 downto 0);
  acq_val_high_i                            : in std_logic_vector(g_acq_num_channels*c_acq_chan_width-1 downto 0);
  acq_dvalid_i                              : in std_logic_vector(g_acq_num_channels-1 downto 0);
+  acq_id_i                                  : in unsigned(g_acq_num_channels*c_acq_id_width-1 downto 0);
  acq_trig_i                                : in std_logic_vector(g_acq_num_channels-1 downto 0);

  -----------------------------
@@ -140,6 +141,7 @@ architecture rtl of wb_acq_core_plain is
  signal acq_val_low_array                  : t_acq_val_half_array(g_acq_num_channels-1 downto 0);
  signal acq_val_high_array                 : t_acq_val_half_array(g_acq_num_channels-1 downto 0);
  signal acq_dvalid_array                   : std_logic_vector(g_acq_num_channels-1 downto 0);
+  signal acq_id_array                       : t_acq_id_array(g_acq_num_channels-1 downto 0);
  signal acq_trig_array                     : std_logic_vector(g_acq_num_channels-1 downto 0);

 begin
@@ -195,6 +197,7 @@ begin
    acq_val_low_i                             => acq_val_low_array,
    acq_val_high_i                            => acq_val_high_array,
    acq_dvalid_i                              => acq_dvalid_array,
+    acq_id_i                                  => acq_id_array,
    acq_trig_i                                => acq_trig_array,

    -----------------------------
@@ -252,6 +255,8 @@ begin
    acq_val_high_array(i)     <=
                acq_val_high_i(c_acq_chan_width*(i+1)-1 downto c_acq_chan_width*i);
    acq_dvalid_array(i)       <= acq_dvalid_i(i);
+    acq_id_array(i)      <=
+                acq_id_i(c_acq_id_width*(i+1)-1 downto c_acq_id_width*i);
    acq_trig_array(i)         <= acq_trig_i(i);

  end generate;

--- a/hdl/modules/dbe_wishbone/wb_acq_core/wbgen/acq_core.wb
+++ b/hdl/modules/dbe_wishbone/wb_acq_core/wbgen/acq_core.wb
--- a/hdl/modules/dbe_wishbone/wb_acq_core/wbgen/acq_core_regs.vhd
+++ b/hdl/modules/dbe_wishbone/wb_acq_core/wbgen/acq_core_regs.vhd
--- a/hdl/modules/dbe_wishbone/wb_acq_core/wbgen/acq_core_regs_pkg.vhd
+++ b/hdl/modules/dbe_wishbone/wb_acq_core/wbgen/acq_core_regs_pkg.vhd
--- a/hdl/modules/dbe_wishbone/wb_acq_core/wbgen/doc/wb_acq_core.html
+++ b/hdl/modules/dbe_wishbone/wb_acq_core/wbgen/doc/wb_acq_core.html
--- a/hdl/modules/dbe_wishbone/wb_acq_core/wbgen/wb_acq_core_regs.h
+++ b/hdl/modules/dbe_wishbone/wb_acq_core/wbgen/wb_acq_core_regs.h
--- a/hdl/modules/dbe_wishbone/wb_acq_core/wbgen/wb_acq_core_regs_defs.h
+++ b/hdl/modules/dbe_wishbone/wb_acq_core/wbgen/wb_acq_core_regs_defs.h
--- a/hdl/modules/dbe_wishbone/wb_acq_core/xwb_acq_core.vhd
+++ b/hdl/modules/dbe_wishbone/wb_acq_core/xwb_acq_core.vhd
@@ -145,6 +145,7 @@ architecture rtl of xwb_acq_core is

  signal acq_val_low_array                  : t_acq_val_half_array(g_acq_num_channels-1 downto 0);
  signal acq_val_high_array                 : t_acq_val_half_array(g_acq_num_channels-1 downto 0);
+  signal acq_id_array                       : t_acq_id_array(g_acq_num_channels-1 downto 0);
  signal acq_dvalid_array                   : std_logic_vector(g_acq_num_channels-1 downto 0);
  signal acq_trig_array                     : std_logic_vector(g_acq_num_channels-1 downto 0);

@@ -201,6 +202,7 @@ begin
    acq_val_low_i                             => acq_val_low_array,
    acq_val_high_i                            => acq_val_high_array,
    acq_dvalid_i                              => acq_dvalid_array,
+    acq_id_i                                  => acq_id_array,
    acq_trig_i                                => acq_trig_array,

    -----------------------------
@@ -289,6 +291,7 @@ begin
    acq_val_high_array(i)     <= acq_chan_array_i(i).val_high;
    acq_dvalid_array(i)       <= acq_chan_array_i(i).dvalid;
    acq_trig_array(i)         <= acq_chan_array_i(i).trig;
+    acq_id_array(i)           <= acq_chan_array_i(i).id;

  end generate;


--- a/hdl/modules/dbe_wishbone/wb_acq_core_mux/wb_acq_core_mux.vhd
+++ b/hdl/modules/dbe_wishbone/wb_acq_core_mux/wb_acq_core_mux.vhd
@@ -96,6 +96,7 @@ port
  acq_val_low_array_i                       : in t_acq_val_half_array(g_acq_num_cores*g_acq_num_channels-1 downto 0);
  acq_val_high_array_i                      : in t_acq_val_half_array(g_acq_num_cores*g_acq_num_channels-1 downto 0);
  acq_dvalid_array_i                        : in std_logic_vector(g_acq_num_cores*g_acq_num_channels-1 downto 0);
+  acq_id_array_i                            : in t_acq_id_array(g_acq_num_cores*g_acq_num_channels-1 downto 0);
  acq_trig_array_i                          : in std_logic_vector(g_acq_num_cores*g_acq_num_channels-1 downto 0);

  -----------------------------
@@ -274,6 +275,7 @@ begin
      acq_val_low_i                             => acq_val_low_array_i((i+1)*g_acq_num_channels-1 downto i*g_acq_num_channels),
      acq_val_high_i                            => acq_val_high_array_i((i+1)*g_acq_num_channels-1 downto i*g_acq_num_channels),
      acq_dvalid_i                              => acq_dvalid_array_i((i+1)*g_acq_num_channels-1 downto i*g_acq_num_channels),
+      acq_id_i                                  => acq_id_array_i((i+1)*g_acq_num_channels-1 downto i*g_acq_num_channels),
      acq_trig_i                                => acq_trig_array_i((i+1)*g_acq_num_channels-1 downto i*g_acq_num_channels),

      -----------------------------

--- a/hdl/modules/dbe_wishbone/wb_acq_core_mux/wb_acq_core_mux_plain.vhd
+++ b/hdl/modules/dbe_wishbone/wb_acq_core_mux/wb_acq_core_mux_plain.vhd
@@ -90,6 +90,7 @@ port
  acq_val_low_array_i                       : in std_logic_vector(g_acq_num_cores*g_acq_num_channels*c_acq_chan_width-1 downto 0);
  acq_val_high_array_i                      : in std_logic_vector(g_acq_num_cores*g_acq_num_channels*c_acq_chan_width-1 downto 0);
  acq_dvalid_array_i                        : in std_logic_vector(g_acq_num_cores*g_acq_num_channels-1 downto 0);
+  acq_id_array_i                            : in unsigned(g_acq_num_cores*g_acq_num_channels*c_acq_id_width-1 downto 0);
  acq_trig_array_i                          : in std_logic_vector(g_acq_num_cores*g_acq_num_channels-1 downto 0);

  -----------------------------
@@ -166,6 +167,7 @@ architecture rtl of wb_acq_core_mux_plain is
  signal acq_val_low_array                  : t_acq_val_half_array(g_acq_num_cores*g_acq_num_channels-1 downto 0);
  signal acq_val_high_array                 : t_acq_val_half_array(g_acq_num_cores*g_acq_num_channels-1 downto 0);
  signal acq_dvalid_array                   : std_logic_vector(g_acq_num_cores*g_acq_num_channels-1 downto 0);
+  signal acq_id_array                       : t_acq_id_array(g_acq_num_cores*g_acq_num_channels-1 downto 0);
  signal acq_trig_array                     : std_logic_vector(g_acq_num_cores*g_acq_num_channels-1 downto 0);

 begin
@@ -224,6 +226,7 @@ begin
    acq_val_low_array_i                       => acq_val_low_array,
    acq_val_high_array_i                      => acq_val_high_array,
    acq_dvalid_array_i                        => acq_dvalid_array,
+    acq_id_array_i                            => acq_id_array,
    acq_trig_array_i                          => acq_trig_array,

    -----------------------------
@@ -302,6 +305,8 @@ begin
      acq_val_high_array(i*g_acq_num_channels+j)     <=
              acq_val_high_array_i(i*g_acq_num_channels*c_acq_chan_width + c_acq_chan_width*(j+1)-1 downto i*g_acq_num_channels*c_acq_chan_width + c_acq_chan_width*j);
      acq_dvalid_array(i*g_acq_num_channels+j)       <= acq_dvalid_array_i(i*g_acq_num_channels+j);
+      acq_id_array(i*g_acq_num_channels+j)     <=
+              acq_id_array_i(i*g_acq_num_channels*c_acq_id_width + c_acq_id_width*(j+1)-1 downto i*g_acq_num_channels*c_acq_id_width + c_acq_id_width*j);
      acq_trig_array(i*g_acq_num_channels+j)         <= acq_trig_array_i(i*g_acq_num_channels+j);

    end generate;

--- a/hdl/modules/dbe_wishbone/wb_acq_core_mux/xwb_acq_core_mux.vhd
+++ b/hdl/modules/dbe_wishbone/wb_acq_core_mux/xwb_acq_core_mux.vhd
@@ -125,6 +125,7 @@ architecture rtl of xwb_acq_core_mux is
  signal acq_val_low_array                  : t_acq_val_half_array(g_acq_num_cores*g_acq_num_channels-1 downto 0);
  signal acq_val_high_array                 : t_acq_val_half_array(g_acq_num_cores*g_acq_num_channels-1 downto 0);
  signal acq_dvalid_array                   : std_logic_vector(g_acq_num_cores*g_acq_num_channels-1 downto 0);
+  signal acq_id_array                       : t_acq_id_array(g_acq_num_cores*g_acq_num_channels-1 downto 0);
  signal acq_trig_array                     : std_logic_vector(g_acq_num_cores*g_acq_num_channels-1 downto 0);

  signal wb_adr_array_in                    : std_logic_vector(g_acq_num_cores*c_wishbone_address_width-1 downto 0);
@@ -195,6 +196,7 @@ begin
    acq_val_low_array_i                      => acq_val_low_array,
    acq_val_high_array_i                     => acq_val_high_array,
    acq_dvalid_array_i                       => acq_dvalid_array,
+    acq_id_array_i                           => acq_id_array,
    acq_trig_array_i                         => acq_trig_array,

    -----------------------------
@@ -287,6 +289,7 @@ begin
      acq_val_low_array(i*g_acq_num_channels + j)  <= acq_chan_array_i(i,j).val_low;
      acq_val_high_array(i*g_acq_num_channels + j) <= acq_chan_array_i(i,j).val_high;
      acq_dvalid_array(i*g_acq_num_channels + j) <= acq_chan_array_i(i,j).dvalid;
+      acq_id_array(i*g_acq_num_channels + j) <= acq_chan_array_i(i,j).id;
      acq_trig_array(i*g_acq_num_channels + j)   <= acq_chan_array_i(i,j).trig;

    end generate;

--- a/hdl/modules/dbe_wishbone/wb_facq_core/Manifest.py
+++ b/hdl/modules/dbe_wishbone/wb_facq_core/Manifest.py
+files = ["wb_facq_core.vhd",
+        "xwb_facq_core.vhd"
+       ];
--- a/hdl/modules/dbe_wishbone/wb_facq_core/wb_facq_core.vhd
+++ b/hdl/modules/dbe_wishbone/wb_facq_core/wb_facq_core.vhd
--- a/hdl/modules/dbe_wishbone/wb_facq_core/xwb_facq_core.vhd
+++ b/hdl/modules/dbe_wishbone/wb_facq_core/xwb_facq_core.vhd
--- a/hdl/modules/dbe_wishbone/wb_facq_core_mux/Manifest.py
+++ b/hdl/modules/dbe_wishbone/wb_facq_core_mux/Manifest.py
+files = ["wb_facq_core_mux.vhd",
+        "wb_facq_core_mux_plain.vhd",
+        "xwb_facq_core_mux.vhd",
+       ];
--- a/hdl/modules/dbe_wishbone/wb_facq_core_mux/wb_facq_core_mux.vhd
+++ b/hdl/modules/dbe_wishbone/wb_facq_core_mux/wb_facq_core_mux.vhd
--- a/hdl/modules/dbe_wishbone/wb_facq_core_mux/wb_facq_core_mux_plain.vhd
+++ b/hdl/modules/dbe_wishbone/wb_facq_core_mux/wb_facq_core_mux_plain.vhd
--- a/hdl/modules/dbe_wishbone/wb_facq_core_mux/xwb_facq_core_mux.vhd
+++ b/hdl/modules/dbe_wishbone/wb_facq_core_mux/xwb_facq_core_mux.vhd
--- a/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd
+++ b/hdl/modules/dbe_wishbone/wb_fmc130m_4ch/wb_fmc130m_4ch.vhd
--- a/hdl/modules/dbe_wishbone/wb_fmc250m_4ch/wb_fmc250m_4ch.vhd
+++ b/hdl/modules/dbe_wishbone/wb_fmc250m_4ch/wb_fmc250m_4ch.vhd
--- a/hdl/modules/dbe_wishbone/wb_fmc250m_4ch/wbgen/doc/fmc250m_4ch_regs_wb.html
+++ b/hdl/modules/dbe_wishbone/wb_fmc250m_4ch/wbgen/doc/fmc250m_4ch_regs_wb.html
--- a/hdl/modules/dbe_wishbone/wb_fmc250m_4ch/wbgen/fmc250m_4ch_regs.h
+++ b/hdl/modules/dbe_wishbone/wb_fmc250m_4ch/wbgen/fmc250m_4ch_regs.h
--- a/hdl/modules/dbe_wishbone/wb_fmc250m_4ch/wbgen/wb_fmc250m_4ch_regs.h
+++ b/hdl/modules/dbe_wishbone/wb_fmc250m_4ch/wbgen/wb_fmc250m_4ch_regs.h
--- a/hdl/modules/dbe_wishbone/wb_fmc250m_4ch/wbgen/wb_fmc250m_4ch_regs.vhd
+++ b/hdl/modules/dbe_wishbone/wb_fmc250m_4ch/wbgen/wb_fmc250m_4ch_regs.vhd
--- a/hdl/modules/dbe_wishbone/wb_fmc250m_4ch/wbgen/wb_fmc250m_4ch_regs.wb
+++ b/hdl/modules/dbe_wishbone/wb_fmc250m_4ch/wbgen/wb_fmc250m_4ch_regs.wb
--- a/hdl/modules/dbe_wishbone/wb_fmc250m_4ch/wbgen/wb_fmc250m_4ch_regs_pkg.vhd
+++ b/hdl/modules/dbe_wishbone/wb_fmc250m_4ch/wbgen/wb_fmc250m_4ch_regs_pkg.vhd
--- a/hdl/modules/dbe_wishbone/wb_fmc516/wb_fmc516.vhd
+++ b/hdl/modules/dbe_wishbone/wb_fmc516/wb_fmc516.vhd
--- a/hdl/modules/dbe_wishbone/wb_fmc_active_clk/wb_fmc_active_clk.vhd
+++ b/hdl/modules/dbe_wishbone/wb_fmc_active_clk/wb_fmc_active_clk.vhd
@@ -163,12 +163,12 @@ architecture rtl of wb_fmc_active_clk is
  -----------------------------
  -- VCXO Si571 I2C Signals
  -----------------------------
-  signal si571_i2c_scl_in                   : std_logic;
-  signal si571_i2c_scl_out                  : std_logic;
-  signal si571_i2c_scl_oe_n                 : std_logic;
-  signal si571_i2c_sda_in                   : std_logic;
-  signal si571_i2c_sda_out                  : std_logic;
-  signal si571_i2c_sda_oe_n                 : std_logic;
+  signal si571_i2c_scl_in                   : std_logic_vector(0 downto 0);
+  signal si571_i2c_scl_out                  : std_logic_vector(0 downto 0);
+  signal si571_i2c_scl_oe_n                 : std_logic_vector(0 downto 0);
+  signal si571_i2c_sda_in                   : std_logic_vector(0 downto 0);
+  signal si571_i2c_sda_out                  : std_logic_vector(0 downto 0);
+  signal si571_i2c_sda_oe_n                 : std_logic_vector(0 downto 0);

  -----------------------------
  -- Components
@@ -387,11 +387,11 @@ begin
    sda_padoen_o                            => si571_i2c_sda_oe_n
  );

-  si571_scl_pad_b  <= si571_i2c_scl_out when si571_i2c_scl_oe_n = '0' else 'Z';
-  si571_i2c_scl_in <= si571_scl_pad_b;
+  si571_scl_pad_b  <= si571_i2c_scl_out(0) when si571_i2c_scl_oe_n(0) = '0' else 'Z';
+  si571_i2c_scl_in(0) <= si571_scl_pad_b;

-  si571_sda_pad_b  <= si571_i2c_sda_out when si571_i2c_sda_oe_n = '0' else 'Z';
-  si571_i2c_sda_in <= si571_sda_pad_b;
+  si571_sda_pad_b  <= si571_i2c_sda_out(0) when si571_i2c_sda_oe_n(0) = '0' else 'Z';
+  si571_i2c_sda_in(0) <= si571_sda_pad_b;

  -- Not used wishbone signals
  --cbar_master_in(1).err                     <= '0';

--- a/hdl/modules/dbe_wishbone/wb_fmcpico1m_4ch/Manifest.py
+++ b/hdl/modules/dbe_wishbone/wb_fmcpico1m_4ch/Manifest.py
--- a/hdl/modules/dbe_wishbone/wb_fmcpico1m_4ch/cdc_fifo.vhd
+++ b/hdl/modules/dbe_wishbone/wb_fmcpico1m_4ch/cdc_fifo.vhd
--- a/hdl/modules/dbe_wishbone/wb_fmcpico1m_4ch/fmc_pico_spi.v
+++ b/hdl/modules/dbe_wishbone/wb_fmcpico1m_4ch/fmc_pico_spi.v
--- a/hdl/modules/dbe_wishbone/wb_fmcpico1m_4ch/wb_fmcpico1m_4ch.vhd
+++ b/hdl/modules/dbe_wishbone/wb_fmcpico1m_4ch/wb_fmcpico1m_4ch.vhd
--- a/hdl/modules/dbe_wishbone/wb_fmcpico1m_4ch/wbgen/build_wb.sh
+++ b/hdl/modules/dbe_wishbone/wb_fmcpico1m_4ch/wbgen/build_wb.sh
+#!/bin/bash
+
+wbgen2 -V wb_fmcpico1m_4ch_regs.vhd -H record -p wb_fmcpico1m_4ch_regs_pkg.vhd -K ../../../../sim/regs/wb_fmcpico1m_4ch_regs.vh -s defines -C wb_fmcpico1m_4ch_regs.h -f html -D doc/fmcpico1m_4ch_regs_wb.html wb_fmcpico1m_4ch_regs.wb
--- a/hdl/modules/dbe_wishbone/wb_fmcpico1m_4ch/wbgen/doc/fmcpico1m_4ch_regs_wb.html
+++ b/hdl/modules/dbe_wishbone/wb_fmcpico1m_4ch/wbgen/doc/fmcpico1m_4ch_regs_wb.html
--- a/hdl/modules/dbe_wishbone/wb_fmcpico1m_4ch/wbgen/wb_fmcpico1m_4ch_regs.h
+++ b/hdl/modules/dbe_wishbone/wb_fmcpico1m_4ch/wbgen/wb_fmcpico1m_4ch_regs.h
--- a/hdl/modules/dbe_wishbone/wb_fmcpico1m_4ch/wbgen/wb_fmcpico1m_4ch_regs.vhd
+++ b/hdl/modules/dbe_wishbone/wb_fmcpico1m_4ch/wbgen/wb_fmcpico1m_4ch_regs.vhd
--- a/hdl/modules/dbe_wishbone/wb_fmcpico1m_4ch/wbgen/wb_fmcpico1m_4ch_regs.wb
+++ b/hdl/modules/dbe_wishbone/wb_fmcpico1m_4ch/wbgen/wb_fmcpico1m_4ch_regs.wb
--- a/hdl/modules/dbe_wishbone/wb_fmcpico1m_4ch/wbgen/wb_fmcpico1m_4ch_regs_pkg.vhd
+++ b/hdl/modules/dbe_wishbone/wb_fmcpico1m_4ch/wbgen/wb_fmcpico1m_4ch_regs_pkg.vhd
--- a/hdl/modules/dbe_wishbone/wb_fmcpico1m_4ch/xwb_fmcpico1m_4ch.vhd
+++ b/hdl/modules/dbe_wishbone/wb_fmcpico1m_4ch/xwb_fmcpico1m_4ch.vhd
--- a/hdl/modules/dbe_wishbone/wb_trigger_iface/wb_trigger_iface.vhd
+++ b/hdl/modules/dbe_wishbone/wb_trigger_iface/wb_trigger_iface.vhd
--- a/hdl/modules/fmc_adc_common/fmc_adc_data.vhd
+++ b/hdl/modules/fmc_adc_common/fmc_adc_data.vhd
--- a/hdl/modules/pcie/Manifest.py
+++ b/hdl/modules/pcie/Manifest.py
--- a/hdl/modules/pcie/common/Manifest.py
+++ b/hdl/modules/pcie/common/Manifest.py
--- a/hdl/modules/pcie/pkgs/Manifest.py
+++ b/hdl/modules/pcie/pkgs/Manifest.py
+files = ["v6abb64Package_efifo_elink.vhd"]
--- a/hdl/modules/pcie/pkgs/v6abb64Package_efifo_elink.vhd
+++ b/hdl/modules/pcie/pkgs/v6abb64Package_efifo_elink.vhd
--- a/hdl/platform/artix7/afc_v3/axi_datamover_0/Manifest.py
+++ b/hdl/platform/artix7/afc_v3/axi_datamover_0/Manifest.py
--- a/hdl/platform/artix7/afc_v3/axi_datamover_0/axi_datamover_0.xci
+++ b/hdl/platform/artix7/afc_v3/axi_datamover_0/axi_datamover_0.xci
--- a/hdl/platform/artix7/afc_v3/axi_datamover_bpm/Manifest.py
+++ b/hdl/platform/artix7/afc_v3/axi_datamover_bpm/Manifest.py
--- a/hdl/platform/artix7/afc_v3/axi_datamover_bpm/axi_datamover_bpm.xci
+++ b/hdl/platform/artix7/afc_v3/axi_datamover_bpm/axi_datamover_bpm.xci
--- a/hdl/platform/artix7/afc_v3/axi_datamover_bpm/axi_datamover_bpm.xml
+++ b/hdl/platform/artix7/afc_v3/axi_datamover_bpm/axi_datamover_bpm.xml
--- a/hdl/platform/artix7/afc_v3/axi_interconnect/Manifest.py
+++ b/hdl/platform/artix7/afc_v3/axi_interconnect/Manifest.py
--- a/hdl/platform/artix7/afc_v3/axi_interconnect/axi_interconnect.xci
+++ b/hdl/platform/artix7/afc_v3/axi_interconnect/axi_interconnect.xci
--- a/hdl/platform/artix7/afc_v3/axi_interconnect_bpm/Manifest.py
+++ b/hdl/platform/artix7/afc_v3/axi_interconnect_bpm/Manifest.py
--- a/hdl/platform/artix7/afc_v3/axi_interconnect_bpm/axi_interconnect_bpm.xci
+++ b/hdl/platform/artix7/afc_v3/axi_interconnect_bpm/axi_interconnect_bpm.xci
--- a/hdl/platform/artix7/afc_v3/axi_interconnect_bpm/axi_interconnect_bpm.xml
+++ b/hdl/platform/artix7/afc_v3/axi_interconnect_bpm/axi_interconnect_bpm.xml
--- a/hdl/platform/artix7/afc_v3/ddr_core/ddr_core.xci
+++ b/hdl/platform/artix7/afc_v3/ddr_core/ddr_core.xci
--- a/hdl/platform/artix7/afc_v3/ddr_core/mig_a.prj
+++ b/hdl/platform/artix7/afc_v3/ddr_core/mig_a.prj
--- a/hdl/platform/artix7/afc_v3/pcie_core/pcie_core.xci
+++ b/hdl/platform/artix7/afc_v3/pcie_core/pcie_core.xci
--- a/hdl/sim/regs/wb_acq_core_regs.vh
+++ b/hdl/sim/regs/wb_acq_core_regs.vh
--- a/hdl/sim/regs/wb_fmc250m_4ch_regs.vh
+++ b/hdl/sim/regs/wb_fmc250m_4ch_regs.vh
--- a/hdl/sim/regs/wb_fmcpico1m_4ch_regs.vh
+++ b/hdl/sim/regs/wb_fmcpico1m_4ch_regs.vh
--- a/hdl/syn/afc_v3/vivado/dbe_bpm/Makefile
+++ b/hdl/syn/afc_v3/vivado/dbe_bpm/Makefile
--- a/hdl/syn/afc_v3/vivado/dbe_bpm/Manifest.py
+++ b/hdl/syn/afc_v3/vivado/dbe_bpm/Manifest.py
--- a/hdl/syn/afc_v3/vivado/dbe_bpm/build_bitstream_local.sh
+++ b/hdl/syn/afc_v3/vivado/dbe_bpm/build_bitstream_local.sh
--- a/hdl/syn/afc_v3/vivado/dbe_bpm/build_bitstream_remote.sh
+++ b/hdl/syn/afc_v3/vivado/dbe_bpm/build_bitstream_remote.sh
--- a/hdl/syn/afc_v3/vivado/dbe_bpm/build_bitstream_tcl.sh
+++ b/hdl/syn/afc_v3/vivado/dbe_bpm/build_bitstream_tcl.sh
--- a/hdl/syn/afc_v3/vivado/dbe_bpm/dbe_bpm.tcl
+++ b/hdl/syn/afc_v3/vivado/dbe_bpm/dbe_bpm.tcl
--- a/hdl/syn/afc_v3/vivado/dbe_bpm/dbe_bpm.xpr
+++ b/hdl/syn/afc_v3/vivado/dbe_bpm/dbe_bpm.xpr
--- a/hdl/syn/afc_v3/vivado/dbe_bpm/dds_cos.nif
+++ b/hdl/syn/afc_v3/vivado/dbe_bpm/dds_cos.nif
--- a/hdl/syn/afc_v3/vivado/dbe_bpm/dds_sin.nif
+++ b/hdl/syn/afc_v3/vivado/dbe_bpm/dds_sin.nif
--- a/hdl/syn/afc_v3/vivado/dbe_bpm/synthesis_descriptor_pkg.vhd
+++ b/hdl/syn/afc_v3/vivado/dbe_bpm/synthesis_descriptor_pkg.vhd
--- a/hdl/syn/afc_v3/vivado/dbe_bpm2/Makefile
+++ b/hdl/syn/afc_v3/vivado/dbe_bpm2/Makefile
--- a/hdl/syn/afc_v3/vivado/dbe_bpm2/Manifest.py
+++ b/hdl/syn/afc_v3/vivado/dbe_bpm2/Manifest.py
--- a/hdl/syn/afc_v3/vivado/dbe_bpm2/build_bitstream_local.sh
+++ b/hdl/syn/afc_v3/vivado/dbe_bpm2/build_bitstream_local.sh
--- a/hdl/syn/afc_v3/vivado/dbe_bpm2/build_bitstream_remote.sh
+++ b/hdl/syn/afc_v3/vivado/dbe_bpm2/build_bitstream_remote.sh
--- a/hdl/syn/afc_v3/vivado/dbe_bpm2/build_bitstream_tcl.sh
+++ b/hdl/syn/afc_v3/vivado/dbe_bpm2/build_bitstream_tcl.sh
--- a/hdl/syn/afc_v3/vivado/dbe_bpm2/dbe_bpm2.tcl
+++ b/hdl/syn/afc_v3/vivado/dbe_bpm2/dbe_bpm2.tcl
--- a/hdl/syn/afc_v3/vivado/dbe_bpm2/synthesis_descriptor_pkg.vhd
+++ b/hdl/syn/afc_v3/vivado/dbe_bpm2/synthesis_descriptor_pkg.vhd
--- a/hdl/syn/afc_v3/vivado/dbe_pbpm/Manifest.py
+++ b/hdl/syn/afc_v3/vivado/dbe_pbpm/Manifest.py
--- a/hdl/syn/afc_v3/vivado/dbe_pbpm/build_bitstream_local.sh
+++ b/hdl/syn/afc_v3/vivado/dbe_pbpm/build_bitstream_local.sh
--- a/hdl/syn/afc_v3/vivado/dbe_pbpm/build_bitstream_remote.sh
+++ b/hdl/syn/afc_v3/vivado/dbe_pbpm/build_bitstream_remote.sh
--- a/hdl/syn/afc_v3/vivado/dbe_pbpm/build_synthesis_sdb.sh
+++ b/hdl/syn/afc_v3/vivado/dbe_pbpm/build_synthesis_sdb.sh
--- a/hdl/syn/afc_v3/vivado/dbe_pbpm/synthesis_descriptor_pkg.vhd
+++ b/hdl/syn/afc_v3/vivado/dbe_pbpm/synthesis_descriptor_pkg.vhd
--- a/hdl/testbench/wishbone/wb_acq_core_test/verilog/artix7/full_tb_mux/Makefile
+++ b/hdl/testbench/wishbone/wb_acq_core_test/verilog/artix7/full_tb_mux/Makefile
--- a/hdl/testbench/wishbone/wb_acq_core_test/verilog/artix7/full_tb_mux/Manifest.py
+++ b/hdl/testbench/wishbone/wb_acq_core_test/verilog/artix7/full_tb_mux/Manifest.py
--- a/hdl/testbench/wishbone/wb_acq_core_test/verilog/artix7/full_tb_mux/wave_compl.do
+++ b/hdl/testbench/wishbone/wb_acq_core_test/verilog/artix7/full_tb_mux/wave_compl.do
--- a/hdl/testbench/wishbone/wb_acq_core_test/verilog/artix7/full_tb_mux/wb_acq_core_tb.v
+++ b/hdl/testbench/wishbone/wb_acq_core_test/verilog/artix7/full_tb_mux/wb_acq_core_tb.v
--- a/hdl/top/afc_v3/vivado/dbe_bpm/Manifest.py
+++ b/hdl/top/afc_v3/vivado/dbe_bpm/Manifest.py
--- a/hdl/top/afc_v3/vivado/dbe_bpm/dbe_bpm.vhd
+++ b/hdl/top/afc_v3/vivado/dbe_bpm/dbe_bpm.vhd
--- a/hdl/top/afc_v3/vivado/dbe_bpm/dbe_bpm.xdc
+++ b/hdl/top/afc_v3/vivado/dbe_bpm/dbe_bpm.xdc
--- a/hdl/top/afc_v3/vivado/dbe_bpm/sys_pll.vhd
+++ b/hdl/top/afc_v3/vivado/dbe_bpm/sys_pll.vhd
--- a/hdl/top/afc_v3/vivado/dbe_bpm2/Manifest.py
+++ b/hdl/top/afc_v3/vivado/dbe_bpm2/Manifest.py
--- a/hdl/top/afc_v3/vivado/dbe_bpm2/clk_gen.vhd
+++ b/hdl/top/afc_v3/vivado/dbe_bpm2/clk_gen.vhd
--- a/hdl/top/afc_v3/vivado/dbe_bpm2/dbe_bpm2.vhd
+++ b/hdl/top/afc_v3/vivado/dbe_bpm2/dbe_bpm2.vhd
--- a/hdl/top/afc_v3/vivado/dbe_bpm2/dbe_bpm2.xdc
+++ b/hdl/top/afc_v3/vivado/dbe_bpm2/dbe_bpm2.xdc
--- a/hdl/top/afc_v3/vivado/dbe_bpm_gen/Manifest.py
+++ b/hdl/top/afc_v3/vivado/dbe_bpm_gen/Manifest.py
--- a/hdl/top/afc_v3/vivado/dbe_bpm/clk_gen.vhd
+++ b/hdl/top/afc_v3/vivado/dbe_bpm/clk_gen.vhd
--- a/hdl/top/afc_v3/vivado/dbe_bpm_gen/dbe_bpm_gen.vhd
+++ b/hdl/top/afc_v3/vivado/dbe_bpm_gen/dbe_bpm_gen.vhd
--- a/hdl/top/afc_v3/vivado/dbe_bpm2/sys_pll.vhd
+++ b/hdl/top/afc_v3/vivado/dbe_bpm2/sys_pll.vhd
--- a/hdl/top/afc_v3/vivado/dbe_pbpm/Manifest.py
+++ b/hdl/top/afc_v3/vivado/dbe_pbpm/Manifest.py
--- a/hdl/top/afc_v3/vivado/dbe_pbpm/dbe_pbpm.vhd
+++ b/hdl/top/afc_v3/vivado/dbe_pbpm/dbe_pbpm.vhd
--- a/hdl/top/afc_v3/vivado/dbe_pbpm/dbe_pbpm.xcf
+++ b/hdl/top/afc_v3/vivado/dbe_pbpm/dbe_pbpm.xcf
--- a/hdl/top/afc_v3/vivado/dbe_pbpm/dbe_pbpm.xdc
+++ b/hdl/top/afc_v3/vivado/dbe_pbpm/dbe_pbpm.xdc
--- a/hdl/top/afc_v3/vivado/dbe_pbpm/ddr_core.xdc
+++ b/hdl/top/afc_v3/vivado/dbe_pbpm/ddr_core.xdc
--- a/hdl/top/afc_v3/vivado/dbe_pbpm/pcie_core.xdc
+++ b/hdl/top/afc_v3/vivado/dbe_pbpm/pcie_core.xdc