8192 was giving us timing problems

In this way, we can save FPGA resources, as all acquisition
transactions from Post-Mortem are done via the external DDR.

Ever since we began using the infra_cores
submodule, the related SDB record is missing
from the top SDB layout.

Not sure why this happens, but this workaround
seems to work ok.

We must not count the special meta records in the
number of slaves. These will issue an error in recent
xwb_sdb_crossbar implementations.

As dsp-cores commit e2d16e4c36 changed mixer width,
we need to change it here. We need to be caution
here anyway, as a change in the mixer width will
not reflect to a change in the acquisition core
mixer width. Fix for this is pending.

All of this files are already present in infra-cores
repo. So, no need to keep them here.

This infra-cores repo is a cut from this repository
that contains a cut from general modules developed
in the context of the BPM project.

In this way, we can reset MMCM by software

This will be used manually reset the ADC MMCM
by software, every time a clock change happens.

Now, on asserting LOCKED by MMCM, we synchronize it
to the destination clock domain and waits until
the LOCK signal has stabilized for a few clock
cycles.

In this way we can safely use the mmcm_adc_locked
signal as a reset to downstream logic.

Even though we don't have much CORDIC
iterations to yield a good resolution, it's
good to be able to acquire the phase for
debugging purposes.