- 02 Feb, 2017 1 commit
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Lucas Russo authored
With this, we can select which data source to acquire.
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- 26 Jan, 2017 6 commits
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Lucas Russo authored
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Lucas Russo authored
This is a initial implementation of the Post-Mortem functionality.
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Lucas Russo authored
For now, this module does exactly the same as ACQ, but this could change in the future. Either way, it's good to differentiate between them, as the software part will build upon them differently.
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Lucas Russo authored
the generic g_acq_num_cores were not being passed to the inner modules, causing it to use only the default value.
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Lucas Russo authored
This will force the synthesis tool to use distributed RAM style, which will possibly improve timing for this small FIFO.
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Lucas Russo authored
In this way, we can use sparse structures (instead of FIFO/RAM primitives) to help synthesis/implementation tools achieve better timing. This mainly works as the FIFO is small (in depth and width) and could be placed near the source/receiving FFs. To be certain that the synthesis tools will use distributed structure for the FIFO/RAM , it's better to use the following constraint in your .xdc file: set_property RAM_STYLE DISTRIBUTED [ get_cells -hier -filter { NAME =~ */cmp_fmc_adc_iface/*/cmp_adc_data_async_fifo/mem_reg* } ]
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- 25 Jan, 2017 2 commits
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Lucas Russo authored
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Lucas Russo authored
For future use, it's good to fix the area constraints to ease testing.
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- 23 Jan, 2017 1 commit
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Lucas Russo authored
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- 13 Jan, 2017 1 commit
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Lucas Russo authored
This way, we don't need to change the top SDB bridge layout to differentiate between FMC130M and FMC250M designs.
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- 09 Dec, 2016 1 commit
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Lucas Russo authored
Hdlmake can now takes care of this, so no need for this file.
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- 22 Nov, 2016 2 commits
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Lucas Russo authored
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Lucas Russo authored
hdlmake release-3.0 commit 034553408a implements this new feature.
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- 21 Nov, 2016 3 commits
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Lucas Russo authored
This is generated by running the hdlmake command.
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Lucas Russo authored
Now, we rely on hdlmake 3.0 project generation, which is easier to maintain.
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Lucas Russo authored
The previous approach on using the syn_pre_cmd in Manifest.py was not working very well, and the hdlmake was not including the synthesis_descriptor_pkg in the .xpr project.
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- 18 Nov, 2016 1 commit
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Lucas Russo authored
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- 17 Nov, 2016 4 commits
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Lucas Russo authored
In this way, we guarantee that we will have the same environment for both platforms with the only difference being the FMC-specfic files
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Lucas Russo authored
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Lucas Russo authored
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Lucas Russo authored
This reverts commit 30c9e00f. The IODELAY group was in fact correct. Only the dbe_bpm design exhibits an error. The dbe_bpm2 (FMC250M) is fine and synthesized normally.
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- 16 Nov, 2016 8 commits
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Lucas Russo authored
Xilinx MIG DDR core 4.0 (Vivado 2016.3) changed the default generic for the IODELAY CTRL name. So, we need to change it in our designs so we can reuse the same iodelay controls as the DDR MIG design, without having to worry about replicating it by hand.
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Lucas Russo authored
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Lucas Russo authored
This path are slow by design and only used after the acq_start_i signal, which is asserted in software.
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Lucas Russo authored
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Lucas Russo authored
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Lucas Russo authored
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Lucas Russo authored
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Lucas Russo authored
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- 11 Nov, 2016 10 commits
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Lucas Russo authored
This is also important as we have changed the topmost component of the design to dbe_bpm_gen.
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Lucas Russo authored
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Lucas Russo authored
Previously we were using address different than 0x0, as LM32 required DPRAM in address 0x0. However, this requirement is not existent anymore and we are not using LM32 as of today.
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Lucas Russo authored
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Lucas Russo authored
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Lucas Russo authored
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Lucas Russo authored
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Lucas Russo authored
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Lucas Russo authored
Now, both designs use the generic dbe_bpm_gen top design.
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Lucas Russo authored
This is used by both FMC130 and FMC250 top designs by modifying the generic.
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