The recv trigger channel 19 is connected now to the core that generates the RFFE switching clock (swap_freqgen) and is used to synchronize its phase.
The switching counter is reset upon a high-state detection on the trigger line.
One can use a MLVDS external trigger to sync all boards at the same time

The correct script to build is "build_bitstream_local.sh"

The README was very outdated and the
simulations, synthesis and project organization
ahve chenged since then.

With recent changes, trigger_pkg was split
into common definitions and type, and
component declarations.

8192 was giving us timing problems

In this way, we can save FPGA resources, as all acquisition
transactions from Post-Mortem are done via the external DDR.

Ever since we began using the infra_cores
submodule, the related SDB record is missing
from the top SDB layout.