- 06 Apr, 2017 3 commits
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Lucas Russo authored
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Lucas Russo authored
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Lucas Russo authored
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- 30 Mar, 2017 2 commits
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Lucas Russo authored
IOBUF primitives always have the "input" signal available for further use. This means that even when transmitting signals (buffer is output) the input signal will have a copy of the transmitted pulse. This is principle is not a problem, but we were using this signal to count received events, so we changed this to use this signal only if the buffer direction is set to input.
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Lucas Russo authored
This is important as if the FMC1 does not supply any clock we won't be able to send/ recv trigger events. Also, it doesn't really matter to have triggers with a local clk_sys clock, as the triggers are treated as asynchronous signal anyway.
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- 29 Mar, 2017 1 commit
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Lucas Russo authored
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- 27 Mar, 2017 1 commit
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Lucas Russo authored
The acquisition properties were inverted.
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- 24 Mar, 2017 5 commits
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Lucas Russo authored
When using FMC250 @~250MHz, with 4 samples, 32-bits, we don't have enough bandwidth to acquire all of this. Instead, we just acquire exactly the amount of bits this ADC provides and treat how to split the data array in software.
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Lucas Russo authored
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Lucas Russo authored
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Lucas Russo authored
This fixes #33 github issue.
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Lucas Russo authored
This code was received by CAEN ELS under, relicensed under MIT license.
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- 21 Mar, 2017 2 commits
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Lucas Russo authored
AFCv3 doesn't work well with faster rates, like 50MHz. So, 12MHz should be OK.
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Lucas Russo authored
dsp-cores added another generate statement, which chahge the hierarchy of position_calc component. So, we change it here.
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- 20 Mar, 2017 9 commits
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Lucas Russo authored
We can't include a prefix on registers filling the whole 32-bits. Otherwise wbgen generates MACROS for accessing this field that generally results in errors like: error: left shift count >= width of type [-Werror]
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Lucas Russo authored
Previously we were just assigning test values to them. Now, they are actually controlled by the fmcpico_1M.
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Lucas Russo authored
These are just controlled by Wishbone.
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Lucas Russo authored
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Lucas Russo authored
These contraints are not correct for PBPM as the CE for this board are 1 for TBT/FOFB and 8 for MONIT/MONIT1.
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Lucas Russo authored
This generic was recently added to the dsp-cores repository.
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Lucas Russo authored
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Lucas Russo authored
This is for safety until we export these signals to wishbone.
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Lucas Russo authored
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- 19 Mar, 2017 1 commit
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Lucas Russo authored
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- 18 Mar, 2017 1 commit
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Lucas Russo authored
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- 17 Mar, 2017 15 commits
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Lucas Russo authored
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Lucas Russo authored
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Lucas Russo authored
Using VHDL dor DDR core issues an error. No idea when that happens, unless re-target my project for Verilog and regenerate the DDR core.
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Lucas Russo authored
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Lucas Russo authored
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Lucas Russo authored
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Lucas Russo authored
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Lucas Russo authored
This is needed as dsp-cores changed xwb_position_calc_core interface.
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Lucas Russo authored
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Lucas Russo authored
This is a simple fix, just selecting a single channel to server as a valid reference.
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Lucas Russo authored
Now, we have the option to use a valid bit in the ACQ core for ADC that are very slow compared to the input clock frequency, such as the FMCPICO_1M. We are still missing position_calc_core ADC/ADCSWAP valid bits.
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Lucas Russo authored
We were instantiating the FMCPICO inside the FMC250 generate statement.
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Lucas Russo authored
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Lucas Russo authored
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Lucas Russo authored
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