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Beam Positoning Monitor - Software
Commit be7dccd5 authored by Lucas Russo's avatar Lucas Russo
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src,include: change acquisition maps as bpm-gw changed it 

The range of commits from lnls-dig/bpm-gw@f7d6e831fd
to lnls-dig/bpm-gw@dc8e06241f changed the acquisition
map. So, we changed it here.
parent a28b7ecd
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include/boards/afcv3/acq_chan.h
View file @ be7dccd5
......@@ -8,75 +8,75 @@
/************************ Acquistion 0 Channel Parameters **************/
/* ADC */
#define ADC0_CHAN_ID 0
#define ADC0_SAMPLE_SIZE 8 /* 8 Bytes -> ADC0 = 16-bit / ADC1 = 16-bit ... */
#define ADC_CHAN_ID 0
#define ADC_SAMPLE_SIZE 8 /* 8 Bytes -> ADC = 16-bit / ADC1 = 16-bit ... */
/* ADC SWAPPED (after the switching module) */
#define ADCSWAP0_CHAN_ID (ADC0_CHAN_ID + 1)
#define ADCSWAP0_SAMPLE_SIZE 8 /* 8 Bytes -> ADCSWAP0 = 16-bit / ADCSWAP1 = 16-bit ... */
#define ADCSWAP_CHAN_ID (ADC_CHAN_ID + 1)
#define ADCSWAP_SAMPLE_SIZE 8 /* 8 Bytes -> ADCSWAP = 16-bit / ADCSWAP1 = 16-bit ... */
/* MIXER I/Q 1/2 */
#define MIXIQ120_CHAN_ID (ADCSWAP0_CHAN_ID + 1)
#define MIXIQ120_SAMPLE_SIZE 16 /* 16 Bytes -> MIXI0 = 32-bit / MIXQ0 = 32-bit ... */
/* MIXER I/Q */
#define MIXIQ_CHAN_ID (ADCSWAP_CHAN_ID + 1)
#define MIXIQ_SAMPLE_SIZE 32 /* 32 Bytes -> MIXI = 32-bit / MIXQ = 32-bit ... / MIXI3 = 32-bit / MIXQ3 */
/* MIXER I/Q 3/4 */
#define MIXIQ340_CHAN_ID (MIXIQ120_CHAN_ID + 1)
#define MIXIQ340_SAMPLE_SIZE 16 /* 16 Bytes -> MIXI2 = 32-bit / MIXQ2 = 32-bit ... */
/* DUMMY 0 */
#define DUMMY0_CHAN_ID (MIXIQ_CHAN_ID + 1)
#define DUMMY0_SAMPLE_SIZE 16 /* 16 Bytes -> 0 */
/* TBTDECIM I/Q 1/2 */
#define TBTDECIMIQ120_CHAN_ID (MIXIQ340_CHAN_ID + 1)
#define TBTDECIMIQ120_SAMPLE_SIZE 16 /* 16 Bytes -> TBTDECIM0 = 32-bit / TBTDECIM1 = 32-bit ... */
/* TBTDECIM I/Q */
#define TBTDECIMIQ_CHAN_ID (DUMMY0_CHAN_ID + 1)
#define TBTDECIMIQ_SAMPLE_SIZE 32 /* 32 Bytes -> TBTDECIM = 32-bit / TBTDECIM1 = 32-bit .../ TBTDECIMI3 = 32-bit / TBTDECIMQ3 */
/* TBTDECIM I/Q 3/4 */
#define TBTDECIMIQ340_CHAN_ID (TBTDECIMIQ120_CHAN_ID + 1)
#define TBTDECIMIQ340_SAMPLE_SIZE 16 /* 16 Bytes -> TBTDECIM0 = 32-bit / TBTDECIM1 = 32-bit ... */
/* DUMMY 1 */
#define DUMMY1_CHAN_ID (TBTDECIMIQ_CHAN_ID + 1)
#define DUMMY1_SAMPLE_SIZE 16 /* 16 Bytes -> 0 */
/* TBT AMP */
#define TBTAMP0_CHAN_ID (TBTDECIMIQ340_CHAN_ID + 1)
#define TBTAMP0_SAMPLE_SIZE 16 /* 16 Bytes -> TBTAMP0 = 32-bit / TBTAMP1 = 32-bit ... */
/* TBT AMP */
#define TBTAMP_CHAN_ID (DUMMY1_CHAN_ID + 1)
#define TBTAMP_SAMPLE_SIZE 16 /* 16 Bytes -> TBTAMP = 32-bit / TBTAMP1 = 32-bit ... */
/* TBT PHASE */
#define TBTPHA0_CHAN_ID (TBTAMP0_CHAN_ID + 1)
#define TBTPHA0_SAMPLE_SIZE 16 /* 16 Bytes -> TBTPHA0 = 32-bit / TBTPHA1 = 32-bit ... */
/* TBT PHASE */
#define TBTPHA_CHAN_ID (TBTAMP_CHAN_ID + 1)
#define TBTPHA_SAMPLE_SIZE 16 /* 16 Bytes -> TBTPHA = 32-bit / TBTPHA1 = 32-bit ... */
/* TBT POS */
#define TBTPOS0_CHAN_ID (TBTPHA0_CHAN_ID + 1)
#define TBTPOS0_SAMPLE_SIZE 16 /* 16 Bytes -> X = 32-bit / Y = 32-bit ... */
/* TBT POS */
#define TBTPOS_CHAN_ID (TBTPHA_CHAN_ID + 1)
#define TBTPOS_SAMPLE_SIZE 16 /* 16 Bytes -> X = 32-bit / Y = 32-bit ... */
/* FOFBDECIM I/Q 1/2 */
#define FOFBDECIMIQ120_CHAN_ID (TBTPOS0_CHAN_ID + 1)
#define FOFBDECIMIQ120_SAMPLE_SIZE 16 /* 16 Bytes -> FOFBDECIM0 = 32-bit / FOFBDECIM1 = 32-bit ... */
/* FOFBDECIM I/Q */
#define FOFBDECIMIQ_CHAN_ID (TBTPOS_CHAN_ID + 1)
#define FOFBDECIMIQ_SAMPLE_SIZE 32 /* 32 Bytes -> FOFBDECIM = 32-bit / FOFBDECIM1 = 32-bit ... / FOFBDECIMI3 = 32-bit / FOFBDECIMQ3 */
/* FOFBDECIM I/Q 3/4 */
#define FOFBDECIMIQ340_CHAN_ID (FOFBDECIMIQ120_CHAN_ID + 1)
#define FOFBDECIMIQ340_SAMPLE_SIZE 16 /* 16 Bytes -> FOFBDECIM0 = 32-bit / FOFBDECIM1 = 32-bit ... */
/* DUMMY 2 */
#define DUMMY2_CHAN_ID (FOFBDECIMIQ_CHAN_ID + 1)
#define DUMMY2_SAMPLE_SIZE 16 /* 16 Bytes -> 0 */
/* FOFB AMP */
#define FOFBAMP0_CHAN_ID (FOFBDECIMIQ340_CHAN_ID + 1)
#define FOFBAMP0_SAMPLE_SIZE 16 /* 16 Bytes -> FOFBAMP0 = 32-bit / FOFBAMP1 = 32-bit ... */
/* FOFB AMP */
#define FOFBAMP_CHAN_ID (DUMMY2_CHAN_ID + 1)
#define FOFBAMP_SAMPLE_SIZE 16 /* 16 Bytes -> FOFBAMP = 32-bit / FOFBAMP1 = 32-bit ... */
/* FOFB PHA */
#define FOFBPHA0_CHAN_ID (FOFBAMP0_CHAN_ID + 1)
#define FOFBPHA0_SAMPLE_SIZE 16 /* 16 Bytes -> FOFBPHA0 = 32-bit / FOFBPHA1 = 32-bit ... */
/* FOFB PHA */
#define FOFBPHA_CHAN_ID (FOFBAMP_CHAN_ID + 1)
#define FOFBPHA_SAMPLE_SIZE 16 /* 16 Bytes -> FOFBPHA = 32-bit / FOFBPHA1 = 32-bit ... */
/* FOFB POS */
#define FOFBPOS0_CHAN_ID (FOFBPHA0_CHAN_ID + 1)
#define FOFBPOS0_SAMPLE_SIZE 16 /* 16 Bytes -> X = 32-bit / Y = 32-bit ... */
/* FOFB POS */
#define FOFBPOS_CHAN_ID (FOFBPHA_CHAN_ID + 1)
#define FOFBPOS_SAMPLE_SIZE 16 /* 16 Bytes -> X = 32-bit / Y = 32-bit ... */
/* MONIT AMP */
#define MONITAMP0_CHAN_ID (FOFBPOS0_CHAN_ID + 1)
#define MONITAMP0_SAMPLE_SIZE 16 /* 16 Bytes -> MONITAMP0 = 32-bit / MONITAMP1 = 32-bit ... */
/* MONIT AMP */
#define MONITAMP_CHAN_ID (FOFBPOS_CHAN_ID + 1)
#define MONITAMP_SAMPLE_SIZE 16 /* 16 Bytes -> MONITAMP = 32-bit / MONITAMP1 = 32-bit ... */
/* MONIT POS */
#define MONITPOS0_CHAN_ID (MONITAMP0_CHAN_ID + 1)
#define MONITPOS0_SAMPLE_SIZE 16 /* 16 Bytes -> X = 32-bit / Y = 32-bit ... */
/* MONIT POS */
#define MONITPOS_CHAN_ID (MONITAMP_CHAN_ID + 1)
#define MONITPOS_SAMPLE_SIZE 16 /* 16 Bytes -> X = 32-bit / Y = 32-bit ... */
/* MONIT1 POS */
#define MONIT1POS0_CHAN_ID (MONITPOS0_CHAN_ID + 1)
#define MONIT1POS0_SAMPLE_SIZE 16 /* 16 Bytes -> X = 32-bit / Y = 32-bit ... */
/* MONIT1 POS */
#define MONIT1POS_CHAN_ID (MONITPOS_CHAN_ID + 1)
#define MONIT1POS_SAMPLE_SIZE 16 /* 16 Bytes -> X = 32-bit / Y = 32-bit ... */
/* End of channels placeholder */
#define END_CHAN_ID (MONIT1POS0_CHAN_ID + 1)
/* End of channels placeholder */
#define END_CHAN_ID (MONIT1POS_CHAN_ID + 1)
#endif
include/boards/afcv3/ddr3_map.h
View file @ be7dccd5
......@@ -24,7 +24,7 @@
/* ADC 0 (shares the same memory space as the ADCSWAP0)
* Size: 2 DDR3 regions */
#define DDR3_ADC0_SAMPLE_SIZE ADC0_SAMPLE_SIZE
#define DDR3_ADC0_SAMPLE_SIZE ADC_SAMPLE_SIZE
#define DDR3_ADC0_MEM_SIZE 2
#define DDR3_ADC0_MEM_BOOL DDR3_MEM_BOOL(DDR3_ADC0_MEM_SIZE)
......@@ -34,7 +34,7 @@
/* ADCSWAP 0 (shares the same memory space as the ADC0)
* Size: 2 DDR3 regions */
#define DDR3_ADCSWAP0_SAMPLE_SIZE ADCSWAP0_SAMPLE_SIZE
#define DDR3_ADCSWAP0_SAMPLE_SIZE ADCSWAP_SAMPLE_SIZE
#define DDR3_ADCSWAP0_MEM_SIZE 2
#define DDR3_ADCSWAP0_MEM_BOOL DDR3_MEM_BOOL(DDR3_ADCSWAP0_MEM_SIZE)
......@@ -42,99 +42,99 @@
#define DDR3_ADCSWAP0_END_ADDR (DDR3_ADCSWAP0_START_ADDR + DDR3_ADCSWAP0_MEM_SIZE*MEM_REGION_SIZE - DDR3_ADCSWAP0_MEM_BOOL*DDR3_ADCSWAP0_SAMPLE_SIZE)
#define DDR3_ADCSWAP0_MAX_SAMPLES ((DDR3_ADCSWAP0_END_ADDR-DDR3_ADCSWAP0_START_ADDR) / DDR3_ADCSWAP0_SAMPLE_SIZE)
/* MIXER I/Q 1/2 (shares the same memory space as the MIXIQ340)
/* MIXER I/Q 1/2 (shares the same memory space as the DUMMY00)
* Size: 1 DDR3 regions */
#define DDR3_MIXIQ120_SAMPLE_SIZE MIXIQ120_SAMPLE_SIZE
#define DDR3_MIXIQ120_MEM_SIZE 1
#define DDR3_MIXIQ0_SAMPLE_SIZE MIXIQ_SAMPLE_SIZE
#define DDR3_MIXIQ0_MEM_SIZE 1
#define DDR3_MIXIQ120_MEM_BOOL DDR3_MEM_BOOL(DDR3_MIXIQ120_MEM_SIZE)
#define DDR3_MIXIQ120_START_ADDR (DDR3_ADCSWAP0_END_ADDR + DDR3_ADCSWAP0_MEM_BOOL*DDR3_ADCSWAP0_SAMPLE_SIZE)
#define DDR3_MIXIQ120_END_ADDR (DDR3_MIXIQ120_START_ADDR + DDR3_MIXIQ120_MEM_SIZE*MEM_REGION_SIZE - DDR3_MIXIQ120_MEM_BOOL*DDR3_MIXIQ120_SAMPLE_SIZE)
#define DDR3_MIXIQ120_MAX_SAMPLES ((DDR3_MIXIQ120_END_ADDR-DDR3_MIXIQ120_START_ADDR) / DDR3_MIXIQ120_SAMPLE_SIZE)
#define DDR3_MIXIQ0_MEM_BOOL DDR3_MEM_BOOL(DDR3_MIXIQ0_MEM_SIZE)
#define DDR3_MIXIQ0_START_ADDR (DDR3_ADCSWAP0_END_ADDR + DDR3_ADCSWAP0_MEM_BOOL*DDR3_ADCSWAP0_SAMPLE_SIZE)
#define DDR3_MIXIQ0_END_ADDR (DDR3_MIXIQ0_START_ADDR + DDR3_MIXIQ0_MEM_SIZE*MEM_REGION_SIZE - DDR3_MIXIQ0_MEM_BOOL*DDR3_MIXIQ0_SAMPLE_SIZE)
#define DDR3_MIXIQ0_MAX_SAMPLES ((DDR3_MIXIQ0_END_ADDR-DDR3_MIXIQ0_START_ADDR) / DDR3_MIXIQ0_SAMPLE_SIZE)
/* MIXER I/Q 3/4 (shares the same memory space as the MIXIQ120)
/* MIXER I/Q 3/4 (shares the same memory space as the MIXIQ0)
* Size: 1 DDR3 regions */
#define DDR3_MIXIQ340_SAMPLE_SIZE MIXIQ340_SAMPLE_SIZE
#define DDR3_MIXIQ340_MEM_SIZE 1
#define DDR3_DUMMY00_SAMPLE_SIZE MIXIQ_SAMPLE_SIZE
#define DDR3_DUMMY00_MEM_SIZE 0
#define DDR3_MIXIQ340_MEM_BOOL DDR3_MEM_BOOL(DDR3_MIXIQ340_MEM_SIZE)
#define DDR3_MIXIQ340_START_ADDR (DDR3_ADCSWAP0_END_ADDR + DDR3_ADCSWAP0_MEM_BOOL*DDR3_ADCSWAP0_SAMPLE_SIZE)
#define DDR3_MIXIQ340_END_ADDR (DDR3_MIXIQ340_START_ADDR + DDR3_MIXIQ340_MEM_SIZE*MEM_REGION_SIZE - DDR3_MIXIQ340_MEM_BOOL*DDR3_MIXIQ340_SAMPLE_SIZE)
#define DDR3_MIXIQ340_MAX_SAMPLES ((DDR3_MIXIQ340_END_ADDR-DDR3_MIXIQ340_START_ADDR) / DDR3_MIXIQ340_SAMPLE_SIZE)
#define DDR3_DUMMY00_MEM_BOOL DDR3_MEM_BOOL(DDR3_DUMMY00_MEM_SIZE)
#define DDR3_DUMMY00_START_ADDR (DDR3_ADCSWAP0_END_ADDR + DDR3_ADCSWAP0_MEM_BOOL*DDR3_ADCSWAP0_SAMPLE_SIZE)
#define DDR3_DUMMY00_END_ADDR (DDR3_DUMMY00_START_ADDR + DDR3_DUMMY00_MEM_SIZE*MEM_REGION_SIZE - DDR3_DUMMY00_MEM_BOOL*DDR3_DUMMY00_SAMPLE_SIZE)
#define DDR3_DUMMY00_MAX_SAMPLES ((DDR3_DUMMY00_END_ADDR-DDR3_DUMMY00_START_ADDR) / DDR3_DUMMY00_SAMPLE_SIZE)
/* TBTDECIM I/Q 1/2 (shares the same memory space as the TBTDECIMIQ340 and TBTAMP0)
/* TBTDECIM I/Q 1/2 (shares the same memory space as the DUMMY10 and TBTAMP0)
* Size: 1 DDR3 regions */
#define DDR3_TBTDECIMIQ120_SAMPLE_SIZE TBTDECIMIQ120_SAMPLE_SIZE
#define DDR3_TBTDECIMIQ120_MEM_SIZE 2
#define DDR3_TBTDECIMIQ0_SAMPLE_SIZE TBTDECIMIQ_SAMPLE_SIZE
#define DDR3_TBTDECIMIQ0_MEM_SIZE 2
#define DDR3_TBTDECIMIQ120_MEM_BOOL DDR3_MEM_BOOL(DDR3_TBTDECIMIQ120_MEM_SIZE)
#define DDR3_TBTDECIMIQ120_START_ADDR (DDR3_MIXIQ340_END_ADDR + DDR3_MIXIQ340_MEM_BOOL*DDR3_MIXIQ340_SAMPLE_SIZE)
#define DDR3_TBTDECIMIQ120_END_ADDR (DDR3_TBTDECIMIQ120_START_ADDR + DDR3_TBTDECIMIQ120_MEM_SIZE*MEM_REGION_SIZE - DDR3_TBTDECIMIQ120_MEM_BOOL*DDR3_TBTDECIMIQ120_SAMPLE_SIZE)
#define DDR3_TBTDECIMIQ120_MAX_SAMPLES ((DDR3_TBTDECIMIQ120_END_ADDR-DDR3_TBTDECIMIQ120_START_ADDR) / DDR3_TBTDECIMIQ120_SAMPLE_SIZE)
#define DDR3_TBTDECIMIQ0_MEM_BOOL DDR3_MEM_BOOL(DDR3_TBTDECIMIQ0_MEM_SIZE)
#define DDR3_TBTDECIMIQ0_START_ADDR (DDR3_DUMMY00_END_ADDR + DDR3_DUMMY00_MEM_BOOL*DDR3_DUMMY00_SAMPLE_SIZE)
#define DDR3_TBTDECIMIQ0_END_ADDR (DDR3_TBTDECIMIQ0_START_ADDR + DDR3_TBTDECIMIQ0_MEM_SIZE*MEM_REGION_SIZE - DDR3_TBTDECIMIQ0_MEM_BOOL*DDR3_TBTDECIMIQ0_SAMPLE_SIZE)
#define DDR3_TBTDECIMIQ0_MAX_SAMPLES ((DDR3_TBTDECIMIQ0_END_ADDR-DDR3_TBTDECIMIQ0_START_ADDR) / DDR3_TBTDECIMIQ0_SAMPLE_SIZE)
/* TBTDECIM I/Q 3/4 (shares the same memory space as the TBTDECIMIQ120 and TBTAMP0)
/* TBTDECIM I/Q 3/4 (shares the same memory space as the TBTDECIMIQ0 and TBTAMP0)
* Size: 1 DDR3 regions */
#define DDR3_TBTDECIMIQ340_SAMPLE_SIZE TBTDECIMIQ340_SAMPLE_SIZE
#define DDR3_TBTDECIMIQ340_MEM_SIZE 2
#define DDR3_DUMMY10_SAMPLE_SIZE TBTDECIMIQ_SAMPLE_SIZE
#define DDR3_DUMMY10_MEM_SIZE 0
#define DDR3_TBTDECIMIQ340_MEM_BOOL DDR3_MEM_BOOL(DDR3_TBTDECIMIQ340_MEM_SIZE)
#define DDR3_TBTDECIMIQ340_START_ADDR (DDR3_MIXIQ340_END_ADDR + DDR3_MIXIQ340_MEM_BOOL*DDR3_MIXIQ340_SAMPLE_SIZE)
#define DDR3_TBTDECIMIQ340_END_ADDR (DDR3_TBTDECIMIQ340_START_ADDR + DDR3_TBTDECIMIQ340_MEM_SIZE*MEM_REGION_SIZE - DDR3_TBTDECIMIQ340_MEM_BOOL*DDR3_TBTDECIMIQ340_SAMPLE_SIZE)
#define DDR3_TBTDECIMIQ340_MAX_SAMPLES ((DDR3_TBTDECIMIQ340_END_ADDR-DDR3_TBTDECIMIQ340_START_ADDR) / DDR3_TBTDECIMIQ340_SAMPLE_SIZE)
#define DDR3_DUMMY10_MEM_BOOL DDR3_MEM_BOOL(DDR3_DUMMY10_MEM_SIZE)
#define DDR3_DUMMY10_START_ADDR (DDR3_DUMMY00_END_ADDR + DDR3_DUMMY00_MEM_BOOL*DDR3_DUMMY00_SAMPLE_SIZE)
#define DDR3_DUMMY10_END_ADDR (DDR3_DUMMY10_START_ADDR + DDR3_DUMMY10_MEM_SIZE*MEM_REGION_SIZE - DDR3_DUMMY10_MEM_BOOL*DDR3_DUMMY10_SAMPLE_SIZE)
#define DDR3_DUMMY10_MAX_SAMPLES ((DDR3_DUMMY10_END_ADDR-DDR3_DUMMY10_START_ADDR) / DDR3_DUMMY10_SAMPLE_SIZE)
/* TBT 0 AMP (shares the same memory space as the TBTDECIMIQ120 and TBTDECIMIQ340)
/* TBT 0 AMP (shares the same memory space as the TBTDECIMIQ0 and DUMMY10)
* Size: 2 DDR3 regions */
#define DDR3_TBTAMP0_SAMPLE_SIZE TBTAMP0_SAMPLE_SIZE
#define DDR3_TBTAMP0_SAMPLE_SIZE TBTAMP_SAMPLE_SIZE
#define DDR3_TBTAMP0_MEM_SIZE 2
#define DDR3_TBTAMP0_MEM_BOOL DDR3_MEM_BOOL(DDR3_TBTAMP0_MEM_SIZE)
#define DDR3_TBTAMP0_START_ADDR (DDR3_MIXIQ340_END_ADDR + DDR3_MIXIQ340_MEM_BOOL*DDR3_MIXIQ340_SAMPLE_SIZE)
#define DDR3_TBTAMP0_START_ADDR (DDR3_DUMMY00_END_ADDR + DDR3_DUMMY00_MEM_BOOL*DDR3_DUMMY00_SAMPLE_SIZE)
#define DDR3_TBTAMP0_END_ADDR (DDR3_TBTAMP0_START_ADDR + DDR3_TBTAMP0_MEM_SIZE*MEM_REGION_SIZE - DDR3_TBTAMP0_MEM_BOOL*DDR3_TBTAMP0_SAMPLE_SIZE)
#define DDR3_TBTAMP0_MAX_SAMPLES ((DDR3_TBTAMP0_END_ADDR-DDR3_TBTAMP0_START_ADDR) / DDR3_TBTAMP0_SAMPLE_SIZE)
/* TBT 0 PHA (shares the same memory space as the TBTDECIMIQ120 and TBTDECIMIQ340)
/* TBT 0 PHA (shares the same memory space as the TBTDECIMIQ0 and DUMMY10)
* Size: 2 DDR3 regions */
#define DDR3_TBTPHA0_SAMPLE_SIZE TBTPHA0_SAMPLE_SIZE
#define DDR3_TBTPHA0_SAMPLE_SIZE TBTPHA_SAMPLE_SIZE
#define DDR3_TBTPHA0_MEM_SIZE 2
#define DDR3_TBTPHA0_MEM_BOOL DDR3_MEM_BOOL(DDR3_TBTPHA0_MEM_SIZE)
#define DDR3_TBTPHA0_START_ADDR (DDR3_MIXIQ340_END_ADDR + DDR3_MIXIQ340_MEM_BOOL*DDR3_MIXIQ340_SAMPLE_SIZE)
#define DDR3_TBTPHA0_START_ADDR (DDR3_DUMMY00_END_ADDR + DDR3_DUMMY00_MEM_BOOL*DDR3_DUMMY00_SAMPLE_SIZE)
#define DDR3_TBTPHA0_END_ADDR (DDR3_TBTPHA0_START_ADDR + DDR3_TBTPHA0_MEM_SIZE*MEM_REGION_SIZE - DDR3_TBTPHA0_MEM_BOOL*DDR3_TBTPHA0_SAMPLE_SIZE)
#define DDR3_TBTPHA0_MAX_SAMPLES ((DDR3_TBTPHA0_END_ADDR-DDR3_TBTPHA0_START_ADDR) / DDR3_TBTPHA0_SAMPLE_SIZE)
/* TBT 0 POS (shares the same memory space as the TBTDECIMIQ120 and TBTDECIMIQ340)
/* TBT 0 POS (shares the same memory space as the TBTDECIMIQ0 and DUMMY10)
* Size: 0 DDR3 regions */
#define DDR3_TBTPOS0_SAMPLE_SIZE TBTPOS0_SAMPLE_SIZE
#define DDR3_TBTPOS0_SAMPLE_SIZE TBTPOS_SAMPLE_SIZE
#define DDR3_TBTPOS0_MEM_SIZE 2
#define DDR3_TBTPOS0_MEM_BOOL DDR3_MEM_BOOL(DDR3_TBTPOS0_MEM_SIZE)
#define DDR3_TBTPOS0_START_ADDR (DDR3_MIXIQ340_END_ADDR + DDR3_MIXIQ340_MEM_BOOL*DDR3_MIXIQ340_SAMPLE_SIZE)
#define DDR3_TBTPOS0_START_ADDR (DDR3_DUMMY00_END_ADDR + DDR3_DUMMY00_MEM_BOOL*DDR3_DUMMY00_SAMPLE_SIZE)
#define DDR3_TBTPOS0_END_ADDR (DDR3_TBTPOS0_START_ADDR + DDR3_TBTPOS0_MEM_SIZE*MEM_REGION_SIZE - DDR3_TBTPOS0_MEM_BOOL*DDR3_TBTPOS0_SAMPLE_SIZE)
#define DDR3_TBTPOS0_MAX_SAMPLES ((DDR3_TBTPOS0_END_ADDR-DDR3_TBTPOS0_START_ADDR) / DDR3_TBTPOS0_SAMPLE_SIZE)
/* FOFBDECIM I/Q 1/2 (shares the same memory space as the FOFBDECIMIQ340 and FOFBAMP0)
/* FOFBDECIM I/Q 1/2 (shares the same memory space as the DUMMY20 and FOFBAMP0)
* Size: 1 DDR3 regions */
#define DDR3_FOFBDECIMIQ120_SAMPLE_SIZE FOFBDECIMIQ120_SAMPLE_SIZE
#define DDR3_FOFBDECIMIQ120_MEM_SIZE 2
#define DDR3_FOFBDECIMIQ0_SAMPLE_SIZE FOFBDECIMIQ_SAMPLE_SIZE
#define DDR3_FOFBDECIMIQ0_MEM_SIZE 2
#define DDR3_FOFBDECIMIQ120_MEM_BOOL DDR3_MEM_BOOL(DDR3_FOFBDECIMIQ120_MEM_SIZE)
#define DDR3_FOFBDECIMIQ120_START_ADDR (DDR3_TBTPOS0_END_ADDR + DDR3_TBTPOS0_MEM_BOOL*DDR3_TBTPOS0_SAMPLE_SIZE)
#define DDR3_FOFBDECIMIQ120_END_ADDR (DDR3_FOFBDECIMIQ120_START_ADDR + DDR3_FOFBDECIMIQ120_MEM_SIZE*MEM_REGION_SIZE - DDR3_FOFBDECIMIQ120_MEM_BOOL*DDR3_FOFBDECIMIQ120_SAMPLE_SIZE)
#define DDR3_FOFBDECIMIQ120_MAX_SAMPLES ((DDR3_FOFBDECIMIQ120_END_ADDR-DDR3_FOFBDECIMIQ120_START_ADDR) / DDR3_FOFBDECIMIQ120_SAMPLE_SIZE)
#define DDR3_FOFBDECIMIQ0_MEM_BOOL DDR3_MEM_BOOL(DDR3_FOFBDECIMIQ0_MEM_SIZE)
#define DDR3_FOFBDECIMIQ0_START_ADDR (DDR3_TBTPOS0_END_ADDR + DDR3_TBTPOS0_MEM_BOOL*DDR3_TBTPOS0_SAMPLE_SIZE)
#define DDR3_FOFBDECIMIQ0_END_ADDR (DDR3_FOFBDECIMIQ0_START_ADDR + DDR3_FOFBDECIMIQ0_MEM_SIZE*MEM_REGION_SIZE - DDR3_FOFBDECIMIQ0_MEM_BOOL*DDR3_FOFBDECIMIQ0_SAMPLE_SIZE)
#define DDR3_FOFBDECIMIQ0_MAX_SAMPLES ((DDR3_FOFBDECIMIQ0_END_ADDR-DDR3_FOFBDECIMIQ0_START_ADDR) / DDR3_FOFBDECIMIQ0_SAMPLE_SIZE)
/* FOFBDECIM I/Q 3/4 (shares the same memory space as the FOFBDECIMIQ120 and FOFBAMP0)
/* FOFBDECIM I/Q 3/4 (shares the same memory space as the FOFBDECIMIQ0 and FOFBAMP0)
* Size: 1 DDR3 regions */
#define DDR3_FOFBDECIMIQ340_SAMPLE_SIZE FOFBDECIMIQ340_SAMPLE_SIZE
#define DDR3_FOFBDECIMIQ340_MEM_SIZE 2
#define DDR3_DUMMY20_SAMPLE_SIZE FOFBDECIMIQ_SAMPLE_SIZE
#define DDR3_DUMMY20_MEM_SIZE 0
#define DDR3_FOFBDECIMIQ340_MEM_BOOL DDR3_MEM_BOOL(DDR3_FOFBDECIMIQ340_MEM_SIZE)
#define DDR3_FOFBDECIMIQ340_START_ADDR (DDR3_TBTPOS0_END_ADDR + DDR3_TBTPOS0_MEM_BOOL*DDR3_TBTPOS0_SAMPLE_SIZE)
#define DDR3_FOFBDECIMIQ340_END_ADDR (DDR3_FOFBDECIMIQ340_START_ADDR + DDR3_FOFBDECIMIQ340_MEM_SIZE*MEM_REGION_SIZE - DDR3_FOFBDECIMIQ340_MEM_BOOL*DDR3_FOFBDECIMIQ340_SAMPLE_SIZE)
#define DDR3_FOFBDECIMIQ340_MAX_SAMPLES ((DDR3_FOFBDECIMIQ340_END_ADDR-DDR3_FOFBDECIMIQ340_START_ADDR) / DDR3_FOFBDECIMIQ340_SAMPLE_SIZE)
#define DDR3_DUMMY20_MEM_BOOL DDR3_MEM_BOOL(DDR3_DUMMY20_MEM_SIZE)
#define DDR3_DUMMY20_START_ADDR (DDR3_TBTPOS0_END_ADDR + DDR3_TBTPOS0_MEM_BOOL*DDR3_TBTPOS0_SAMPLE_SIZE)
#define DDR3_DUMMY20_END_ADDR (DDR3_DUMMY20_START_ADDR + DDR3_DUMMY20_MEM_SIZE*MEM_REGION_SIZE - DDR3_DUMMY20_MEM_BOOL*DDR3_DUMMY20_SAMPLE_SIZE)
#define DDR3_DUMMY20_MAX_SAMPLES ((DDR3_DUMMY20_END_ADDR-DDR3_DUMMY20_START_ADDR) / DDR3_DUMMY20_SAMPLE_SIZE)
/* FOFB 0 AMP
* Size: 2 DDR3 regions */
#define DDR3_FOFBAMP0_SAMPLE_SIZE FOFBAMP0_SAMPLE_SIZE
#define DDR3_FOFBAMP0_SAMPLE_SIZE FOFBAMP_SAMPLE_SIZE
#define DDR3_FOFBAMP0_MEM_SIZE 2
#define DDR3_FOFBAMP0_MEM_BOOL DDR3_MEM_BOOL(DDR3_FOFBAMP0_MEM_SIZE)
......@@ -144,7 +144,7 @@
/* FOFB 0 PHA (shares the same memory space as the FOFBDECIMIQ12 and FOFBDECIMIQ34)
* Size: 2 DDR3 regions */
#define DDR3_FOFBPHA0_SAMPLE_SIZE FOFBPHA0_SAMPLE_SIZE
#define DDR3_FOFBPHA0_SAMPLE_SIZE FOFBPHA_SAMPLE_SIZE
#define DDR3_FOFBPHA0_MEM_SIZE 2
#define DDR3_FOFBPHA0_MEM_BOOL DDR3_MEM_BOOL(DDR3_FOFBPHA0_MEM_SIZE)
......@@ -154,7 +154,7 @@
/* FOFB 0 POS
* Size: 0 DDR3 regions */
#define DDR3_FOFBPOS0_SAMPLE_SIZE FOFBPOS0_SAMPLE_SIZE
#define DDR3_FOFBPOS0_SAMPLE_SIZE FOFBPOS_SAMPLE_SIZE
#define DDR3_FOFBPOS0_MEM_SIZE 2
#define DDR3_FOFBPOS0_MEM_BOOL DDR3_MEM_BOOL(DDR3_FOFBPOS0_MEM_SIZE)
......@@ -164,7 +164,7 @@
/* MONIT 0 AMP
* Size: 0 DDR3 regions */
#define DDR3_MONITAMP0_SAMPLE_SIZE MONITAMP0_SAMPLE_SIZE
#define DDR3_MONITAMP0_SAMPLE_SIZE MONITAMP_SAMPLE_SIZE
#define DDR3_MONITAMP0_MEM_SIZE 0
#define DDR3_MONITAMP0_MEM_BOOL DDR3_MEM_BOOL(DDR3_MONITAMP0_MEM_SIZE)
......@@ -174,7 +174,7 @@
/* MONIT 0 POS
* Size: 0 DDR3 regions */
#define DDR3_MONITPOS0_SAMPLE_SIZE MONITPOS0_SAMPLE_SIZE
#define DDR3_MONITPOS0_SAMPLE_SIZE MONITPOS_SAMPLE_SIZE
#define DDR3_MONITPOS0_MEM_SIZE 0
#define DDR3_MONITPOS0_MEM_BOOL DDR3_MEM_BOOL(DDR3_MONITPOS0_MEM_SIZE)
......@@ -184,7 +184,7 @@
/* MONIT1 0 POS
* Size: 0 DDR3 regions */
#define DDR3_MONIT1POS0_SAMPLE_SIZE MONIT1POS0_SAMPLE_SIZE
#define DDR3_MONIT1POS0_SAMPLE_SIZE MONIT1POS_SAMPLE_SIZE
#define DDR3_MONIT1POS0_MEM_SIZE 0
#define DDR3_MONIT1POS0_MEM_BOOL DDR3_MEM_BOOL(DDR3_MONIT1POS0_MEM_SIZE)
......@@ -194,7 +194,7 @@
/* End 0 Dummy region
* Size: 0 DDR3 regions */
#define DDR3_DUMMY_END0_SAMPLE_SIZE MONIT1POS0_SAMPLE_SIZE
#define DDR3_DUMMY_END0_SAMPLE_SIZE MONIT1POS_SAMPLE_SIZE
#define DDR3_DUMMY_END0_MEM_SIZE 0
#define DDR3_DUMMY_END0_MEM_BOOL DDR3_MEM_BOOL(DDR3_DUMMY_END0_MEM_SIZE)
......@@ -206,7 +206,7 @@
/* ADC 1
* Size: 2 DDR3 regions */
#define DDR3_ADC1_SAMPLE_SIZE ADC0_SAMPLE_SIZE
#define DDR3_ADC1_SAMPLE_SIZE ADC_SAMPLE_SIZE
#define DDR3_ADC1_MEM_SIZE 2
#define DDR3_ADC1_MEM_BOOL DDR3_MEM_BOOL(DDR3_ADC1_MEM_SIZE)
......@@ -216,7 +216,7 @@
/* ADCSWAP 1
* Size: 2 DDR3 regions */
#define DDR3_ADCSWAP1_SAMPLE_SIZE ADCSWAP0_SAMPLE_SIZE
#define DDR3_ADCSWAP1_SAMPLE_SIZE ADCSWAP_SAMPLE_SIZE
#define DDR3_ADCSWAP1_MEM_SIZE 2
#define DDR3_ADCSWAP1_MEM_BOOL DDR3_MEM_BOOL(DDR3_ADCSWAP1_MEM_SIZE)
......@@ -224,99 +224,99 @@
#define DDR3_ADCSWAP1_END_ADDR (DDR3_ADCSWAP1_START_ADDR + DDR3_ADCSWAP1_MEM_SIZE*MEM_REGION_SIZE - DDR3_ADCSWAP1_MEM_BOOL*DDR3_ADCSWAP1_SAMPLE_SIZE)
#define DDR3_ADCSWAP1_MAX_SAMPLES ((DDR3_ADCSWAP1_END_ADDR-DDR3_ADCSWAP1_START_ADDR) / DDR3_ADCSWAP1_SAMPLE_SIZE)
/* MIXER I/Q 1/2 (shares the same memory space as the MIXIQ341)
/* MIXER I/Q 1/2 (shares the same memory space as the DUMMY01)
* Size: 1 DDR3 regions */
#define DDR3_MIXIQ121_SAMPLE_SIZE MIXIQ120_SAMPLE_SIZE
#define DDR3_MIXIQ121_MEM_SIZE 1
#define DDR3_MIXIQ1_SAMPLE_SIZE MIXIQ_SAMPLE_SIZE
#define DDR3_MIXIQ1_MEM_SIZE 1
#define DDR3_MIXIQ121_MEM_BOOL DDR3_MEM_BOOL(DDR3_MIXIQ121_MEM_SIZE)
#define DDR3_MIXIQ121_START_ADDR (DDR3_ADCSWAP1_END_ADDR + DDR3_ADCSWAP0_MEM_BOOL*DDR3_ADCSWAP0_SAMPLE_SIZE)
#define DDR3_MIXIQ121_END_ADDR (DDR3_MIXIQ121_START_ADDR + DDR3_MIXIQ121_MEM_SIZE*MEM_REGION_SIZE - DDR3_MIXIQ121_MEM_BOOL*DDR3_MIXIQ121_SAMPLE_SIZE)
#define DDR3_MIXIQ121_MAX_SAMPLES ((DDR3_MIXIQ121_END_ADDR-DDR3_MIXIQ121_START_ADDR) / DDR3_MIXIQ121_SAMPLE_SIZE)
#define DDR3_MIXIQ1_MEM_BOOL DDR3_MEM_BOOL(DDR3_MIXIQ1_MEM_SIZE)
#define DDR3_MIXIQ1_START_ADDR (DDR3_ADCSWAP1_END_ADDR + DDR3_ADCSWAP0_MEM_BOOL*DDR3_ADCSWAP0_SAMPLE_SIZE)
#define DDR3_MIXIQ1_END_ADDR (DDR3_MIXIQ1_START_ADDR + DDR3_MIXIQ1_MEM_SIZE*MEM_REGION_SIZE - DDR3_MIXIQ1_MEM_BOOL*DDR3_MIXIQ1_SAMPLE_SIZE)
#define DDR3_MIXIQ1_MAX_SAMPLES ((DDR3_MIXIQ1_END_ADDR-DDR3_MIXIQ1_START_ADDR) / DDR3_MIXIQ1_SAMPLE_SIZE)
/* MIXER I/Q 3/4 (shares the same memory space as the MIXIQ121)
/* MIXER I/Q 3/4 (shares the same memory space as the MIXIQ1)
* Size: 1 DDR3 regions */
#define DDR3_MIXIQ341_SAMPLE_SIZE MIXIQ340_SAMPLE_SIZE
#define DDR3_MIXIQ341_MEM_SIZE 1
#define DDR3_DUMMY01_SAMPLE_SIZE MIXIQ_SAMPLE_SIZE
#define DDR3_DUMMY01_MEM_SIZE 1
#define DDR3_MIXIQ341_MEM_BOOL DDR3_MEM_BOOL(DDR3_MIXIQ341_MEM_SIZE)
#define DDR3_MIXIQ341_START_ADDR (DDR3_ADCSWAP1_END_ADDR + DDR3_ADCSWAP0_MEM_BOOL*DDR3_ADCSWAP0_SAMPLE_SIZE)
#define DDR3_MIXIQ341_END_ADDR (DDR3_MIXIQ341_START_ADDR + DDR3_MIXIQ341_MEM_SIZE*MEM_REGION_SIZE - DDR3_MIXIQ341_MEM_BOOL*DDR3_MIXIQ341_SAMPLE_SIZE)
#define DDR3_MIXIQ341_MAX_SAMPLES ((DDR3_MIXIQ341_END_ADDR-DDR3_MIXIQ341_START_ADDR) / DDR3_MIXIQ341_SAMPLE_SIZE)
#define DDR3_DUMMY01_MEM_BOOL DDR3_MEM_BOOL(DDR3_DUMMY01_MEM_SIZE)
#define DDR3_DUMMY01_START_ADDR (DDR3_ADCSWAP1_END_ADDR + DDR3_ADCSWAP0_MEM_BOOL*DDR3_ADCSWAP0_SAMPLE_SIZE)
#define DDR3_DUMMY01_END_ADDR (DDR3_DUMMY01_START_ADDR + DDR3_DUMMY01_MEM_SIZE*MEM_REGION_SIZE - DDR3_DUMMY01_MEM_BOOL*DDR3_DUMMY01_SAMPLE_SIZE)
#define DDR3_DUMMY01_MAX_SAMPLES ((DDR3_DUMMY01_END_ADDR-DDR3_DUMMY01_START_ADDR) / DDR3_DUMMY01_SAMPLE_SIZE)
/* TBTDECIM I/Q 1/2 (shares the same memory space as the TBTDECIMIQ341 and TBTAMP1)
/* TBTDECIM I/Q 1/2 (shares the same memory space as the DUMMY11 and TBTAMP1)
* Size: 1 DDR3 regions */
#define DDR3_TBTDECIMIQ121_SAMPLE_SIZE TBTDECIMIQ120_SAMPLE_SIZE
#define DDR3_TBTDECIMIQ121_MEM_SIZE 2
#define DDR3_TBTDECIMIQ1_SAMPLE_SIZE TBTDECIMIQ_SAMPLE_SIZE
#define DDR3_TBTDECIMIQ1_MEM_SIZE 2
#define DDR3_TBTDECIMIQ121_MEM_BOOL DDR3_MEM_BOOL(DDR3_TBTDECIMIQ121_MEM_SIZE)
#define DDR3_TBTDECIMIQ121_START_ADDR (DDR3_MIXIQ341_END_ADDR + DDR3_MIXIQ341_MEM_BOOL*DDR3_MIXIQ341_SAMPLE_SIZE)
#define DDR3_TBTDECIMIQ121_END_ADDR (DDR3_TBTDECIMIQ121_START_ADDR + DDR3_TBTDECIMIQ121_MEM_SIZE*MEM_REGION_SIZE - DDR3_TBTDECIMIQ121_MEM_BOOL*DDR3_TBTDECIMIQ121_SAMPLE_SIZE)
#define DDR3_TBTDECIMIQ121_MAX_SAMPLES ((DDR3_TBTDECIMIQ121_END_ADDR-DDR3_TBTDECIMIQ121_START_ADDR) / DDR3_TBTDECIMIQ121_SAMPLE_SIZE)
#define DDR3_TBTDECIMIQ1_MEM_BOOL DDR3_MEM_BOOL(DDR3_TBTDECIMIQ1_MEM_SIZE)
#define DDR3_TBTDECIMIQ1_START_ADDR (DDR3_DUMMY01_END_ADDR + DDR3_DUMMY01_MEM_BOOL*DDR3_DUMMY01_SAMPLE_SIZE)
#define DDR3_TBTDECIMIQ1_END_ADDR (DDR3_TBTDECIMIQ1_START_ADDR + DDR3_TBTDECIMIQ1_MEM_SIZE*MEM_REGION_SIZE - DDR3_TBTDECIMIQ1_MEM_BOOL*DDR3_TBTDECIMIQ1_SAMPLE_SIZE)
#define DDR3_TBTDECIMIQ1_MAX_SAMPLES ((DDR3_TBTDECIMIQ1_END_ADDR-DDR3_TBTDECIMIQ1_START_ADDR) / DDR3_TBTDECIMIQ1_SAMPLE_SIZE)
/* TBTDECIM I/Q 3/4 (shares the same memory space as the TBTDECIMIQ121 and TBTAMP1)
/* TBTDECIM I/Q 3/4 (shares the same memory space as the TBTDECIMIQ1 and TBTAMP1)
* Size: 1 DDR3 regions */
#define DDR3_TBTDECIMIQ341_SAMPLE_SIZE TBTDECIMIQ340_SAMPLE_SIZE
#define DDR3_TBTDECIMIQ341_MEM_SIZE 2
#define DDR3_DUMMY11_SAMPLE_SIZE TBTDECIMIQ_SAMPLE_SIZE
#define DDR3_DUMMY11_MEM_SIZE 2
#define DDR3_TBTDECIMIQ341_MEM_BOOL DDR3_MEM_BOOL(DDR3_TBTDECIMIQ341_MEM_SIZE)
#define DDR3_TBTDECIMIQ341_START_ADDR (DDR3_MIXIQ341_END_ADDR + DDR3_MIXIQ341_MEM_BOOL*DDR3_MIXIQ341_SAMPLE_SIZE)
#define DDR3_TBTDECIMIQ341_END_ADDR (DDR3_TBTDECIMIQ341_START_ADDR + DDR3_TBTDECIMIQ341_MEM_SIZE*MEM_REGION_SIZE - DDR3_TBTDECIMIQ341_MEM_BOOL*DDR3_TBTDECIMIQ341_SAMPLE_SIZE)
#define DDR3_TBTDECIMIQ341_MAX_SAMPLES ((DDR3_TBTDECIMIQ341_END_ADDR-DDR3_TBTDECIMIQ341_START_ADDR) / DDR3_TBTDECIMIQ341_SAMPLE_SIZE)
#define DDR3_DUMMY11_MEM_BOOL DDR3_MEM_BOOL(DDR3_DUMMY11_MEM_SIZE)
#define DDR3_DUMMY11_START_ADDR (DDR3_DUMMY01_END_ADDR + DDR3_DUMMY01_MEM_BOOL*DDR3_DUMMY01_SAMPLE_SIZE)
#define DDR3_DUMMY11_END_ADDR (DDR3_DUMMY11_START_ADDR + DDR3_DUMMY11_MEM_SIZE*MEM_REGION_SIZE - DDR3_DUMMY11_MEM_BOOL*DDR3_DUMMY11_SAMPLE_SIZE)
#define DDR3_DUMMY11_MAX_SAMPLES ((DDR3_DUMMY11_END_ADDR-DDR3_DUMMY11_START_ADDR) / DDR3_DUMMY11_SAMPLE_SIZE)
/* TBT 1 AMP
* Size: 2 DDR3 regions */
#define DDR3_TBTAMP1_SAMPLE_SIZE TBTAMP0_SAMPLE_SIZE
#define DDR3_TBTAMP1_SAMPLE_SIZE TBTAMP_SAMPLE_SIZE
#define DDR3_TBTAMP1_MEM_SIZE 2
#define DDR3_TBTAMP1_MEM_BOOL DDR3_MEM_BOOL(DDR3_TBTAMP1_MEM_SIZE)
#define DDR3_TBTAMP1_START_ADDR (DDR3_MIXIQ341_END_ADDR + DDR3_MIXIQ341_MEM_BOOL*DDR3_MIXIQ341_SAMPLE_SIZE)
#define DDR3_TBTAMP1_START_ADDR (DDR3_DUMMY01_END_ADDR + DDR3_DUMMY01_MEM_BOOL*DDR3_DUMMY01_SAMPLE_SIZE)
#define DDR3_TBTAMP1_END_ADDR (DDR3_TBTAMP1_START_ADDR + DDR3_TBTAMP1_MEM_SIZE*MEM_REGION_SIZE - DDR3_TBTAMP1_MEM_BOOL*DDR3_TBTAMP1_SAMPLE_SIZE)
#define DDR3_TBTAMP1_MAX_SAMPLES ((DDR3_TBTAMP1_END_ADDR-DDR3_TBTAMP1_START_ADDR) / DDR3_TBTAMP1_SAMPLE_SIZE)
/* TBT 1 PHA (shares the same memory space as the TBTDECIMIQ121 and TBTDECIMIQ341)
/* TBT 1 PHA (shares the same memory space as the TBTDECIMIQ1 and DUMMY11)
* Size: 2 DDR3 regions */
#define DDR3_TBTPHA1_SAMPLE_SIZE TBTPHA0_SAMPLE_SIZE
#define DDR3_TBTPHA1_SAMPLE_SIZE TBTPHA_SAMPLE_SIZE
#define DDR3_TBTPHA1_MEM_SIZE 2
#define DDR3_TBTPHA1_MEM_BOOL DDR3_MEM_BOOL(DDR3_TBTPHA1_MEM_SIZE)
#define DDR3_TBTPHA1_START_ADDR (DDR3_MIXIQ341_END_ADDR + DDR3_MIXIQ341_MEM_BOOL*DDR3_MIXIQ341_SAMPLE_SIZE)
#define DDR3_TBTPHA1_START_ADDR (DDR3_DUMMY01_END_ADDR + DDR3_DUMMY01_MEM_BOOL*DDR3_DUMMY01_SAMPLE_SIZE)
#define DDR3_TBTPHA1_END_ADDR (DDR3_TBTPHA1_START_ADDR + DDR3_TBTPHA1_MEM_SIZE*MEM_REGION_SIZE - DDR3_TBTPHA1_MEM_BOOL*DDR3_TBTPHA1_SAMPLE_SIZE)
#define DDR3_TBTPHA1_MAX_SAMPLES ((DDR3_TBTPHA1_END_ADDR-DDR3_TBTPHA1_START_ADDR) / DDR3_TBTPHA1_SAMPLE_SIZE)
/* TBT 1 POS
* Size: 1 DDR3 regions */
#define DDR3_TBTPOS1_SAMPLE_SIZE TBTPOS0_SAMPLE_SIZE
#define DDR3_TBTPOS1_SAMPLE_SIZE TBTPOS_SAMPLE_SIZE
#define DDR3_TBTPOS1_MEM_SIZE 2
#define DDR3_TBTPOS1_MEM_BOOL DDR3_MEM_BOOL(DDR3_TBTPOS1_MEM_SIZE)
#define DDR3_TBTPOS1_START_ADDR (DDR3_MIXIQ341_END_ADDR + DDR3_MIXIQ341_MEM_BOOL*DDR3_MIXIQ341_SAMPLE_SIZE)
#define DDR3_TBTPOS1_START_ADDR (DDR3_DUMMY01_END_ADDR + DDR3_DUMMY01_MEM_BOOL*DDR3_DUMMY01_SAMPLE_SIZE)
#define DDR3_TBTPOS1_END_ADDR (DDR3_TBTPOS1_START_ADDR + DDR3_TBTPOS1_MEM_SIZE*MEM_REGION_SIZE - DDR3_TBTPOS1_MEM_BOOL*DDR3_TBTPOS1_SAMPLE_SIZE)
#define DDR3_TBTPOS1_MAX_SAMPLES ((DDR3_TBTPOS1_END_ADDR-DDR3_TBTPOS1_START_ADDR) / DDR3_TBTPOS1_SAMPLE_SIZE)
/* FOFBDECIM I/Q 1/2 (shares the same memory space as the FOFBDECIMIQ341 and FOFBAMP1)
/* FOFBDECIM I/Q 1/2 (shares the same memory space as the DUMMY21 and FOFBAMP1)
* Size: 1 DDR3 regions */
#define DDR3_FOFBDECIMIQ121_SAMPLE_SIZE FOFBDECIMIQ120_SAMPLE_SIZE
#define DDR3_FOFBDECIMIQ121_MEM_SIZE 2
#define DDR3_FOFBDECIMIQ1_SAMPLE_SIZE FOFBDECIMIQ_SAMPLE_SIZE
#define DDR3_FOFBDECIMIQ1_MEM_SIZE 2
#define DDR3_FOFBDECIMIQ121_MEM_BOOL DDR3_MEM_BOOL(DDR3_FOFBDECIMIQ121_MEM_SIZE)
#define DDR3_FOFBDECIMIQ121_START_ADDR (DDR3_TBTPOS1_END_ADDR + DDR3_TBTPOS1_MEM_BOOL*DDR3_TBTPOS1_SAMPLE_SIZE)
#define DDR3_FOFBDECIMIQ121_END_ADDR (DDR3_FOFBDECIMIQ121_START_ADDR + DDR3_FOFBDECIMIQ121_MEM_SIZE*MEM_REGION_SIZE - DDR3_FOFBDECIMIQ121_MEM_BOOL*DDR3_FOFBDECIMIQ121_SAMPLE_SIZE)
#define DDR3_FOFBDECIMIQ121_MAX_SAMPLES ((DDR3_FOFBDECIMIQ121_END_ADDR-DDR3_FOFBDECIMIQ121_START_ADDR) / DDR3_FOFBDECIMIQ121_SAMPLE_SIZE)
#define DDR3_FOFBDECIMIQ1_MEM_BOOL DDR3_MEM_BOOL(DDR3_FOFBDECIMIQ1_MEM_SIZE)
#define DDR3_FOFBDECIMIQ1_START_ADDR (DDR3_TBTPOS1_END_ADDR + DDR3_TBTPOS1_MEM_BOOL*DDR3_TBTPOS1_SAMPLE_SIZE)
#define DDR3_FOFBDECIMIQ1_END_ADDR (DDR3_FOFBDECIMIQ1_START_ADDR + DDR3_FOFBDECIMIQ1_MEM_SIZE*MEM_REGION_SIZE - DDR3_FOFBDECIMIQ1_MEM_BOOL*DDR3_FOFBDECIMIQ1_SAMPLE_SIZE)
#define DDR3_FOFBDECIMIQ1_MAX_SAMPLES ((DDR3_FOFBDECIMIQ1_END_ADDR-DDR3_FOFBDECIMIQ1_START_ADDR) / DDR3_FOFBDECIMIQ1_SAMPLE_SIZE)
/* FOFBDECIM I/Q 3/4 (shares the same memory space as the FOFBDECIMIQ121 and FOFBAMP1)
/* FOFBDECIM I/Q 3/4 (shares the same memory space as the FOFBDECIMIQ1 and FOFBAMP1)
* Size: 1 DDR3 regions */
#define DDR3_FOFBDECIMIQ341_SAMPLE_SIZE FOFBDECIMIQ340_SAMPLE_SIZE
#define DDR3_FOFBDECIMIQ341_MEM_SIZE 2
#define DDR3_DUMMY21_SAMPLE_SIZE FOFBDECIMIQ_SAMPLE_SIZE
#define DDR3_DUMMY21_MEM_SIZE 2
#define DDR3_FOFBDECIMIQ341_MEM_BOOL DDR3_MEM_BOOL(DDR3_FOFBDECIMIQ341_MEM_SIZE)
#define DDR3_FOFBDECIMIQ341_START_ADDR (DDR3_TBTPOS1_END_ADDR + DDR3_TBTPOS1_MEM_BOOL*DDR3_TBTPOS1_SAMPLE_SIZE)
#define DDR3_FOFBDECIMIQ341_END_ADDR (DDR3_FOFBDECIMIQ341_START_ADDR + DDR3_FOFBDECIMIQ341_MEM_SIZE*MEM_REGION_SIZE - DDR3_FOFBDECIMIQ341_MEM_BOOL*DDR3_FOFBDECIMIQ341_SAMPLE_SIZE)
#define DDR3_FOFBDECIMIQ341_MAX_SAMPLES ((DDR3_FOFBDECIMIQ341_END_ADDR-DDR3_FOFBDECIMIQ341_START_ADDR) / DDR3_FOFBDECIMIQ341_SAMPLE_SIZE)
#define DDR3_DUMMY21_MEM_BOOL DDR3_MEM_BOOL(DDR3_DUMMY21_MEM_SIZE)
#define DDR3_DUMMY21_START_ADDR (DDR3_TBTPOS1_END_ADDR + DDR3_TBTPOS1_MEM_BOOL*DDR3_TBTPOS1_SAMPLE_SIZE)
#define DDR3_DUMMY21_END_ADDR (DDR3_DUMMY21_START_ADDR + DDR3_DUMMY21_MEM_SIZE*MEM_REGION_SIZE - DDR3_DUMMY21_MEM_BOOL*DDR3_DUMMY21_SAMPLE_SIZE)
#define DDR3_DUMMY21_MAX_SAMPLES ((DDR3_DUMMY21_END_ADDR-DDR3_DUMMY21_START_ADDR) / DDR3_DUMMY21_SAMPLE_SIZE)
/* FOFB 1 AMP
* Size: 2 DDR3 regions */
#define DDR3_FOFBAMP1_SAMPLE_SIZE FOFBAMP0_SAMPLE_SIZE
#define DDR3_FOFBAMP1_SAMPLE_SIZE FOFBAMP_SAMPLE_SIZE
#define DDR3_FOFBAMP1_MEM_SIZE 2
#define DDR3_FOFBAMP1_MEM_BOOL DDR3_MEM_BOOL(DDR3_FOFBAMP1_MEM_SIZE)
......@@ -324,9 +324,9 @@
#define DDR3_FOFBAMP1_END_ADDR (DDR3_FOFBAMP1_START_ADDR + DDR3_FOFBAMP1_MEM_SIZE*MEM_REGION_SIZE - DDR3_FOFBAMP1_MEM_BOOL*DDR3_FOFBAMP1_SAMPLE_SIZE)
#define DDR3_FOFBAMP1_MAX_SAMPLES ((DDR3_FOFBAMP1_END_ADDR-DDR3_FOFBAMP1_START_ADDR) / DDR3_FOFBAMP1_SAMPLE_SIZE)
/* FOFB 1 PHA (shares the same memory space as the FOFBDECIMIQ121 and FOFBDECIMIQ341)
/* FOFB 1 PHA (shares the same memory space as the FOFBDECIMIQ1 and DUMMY21)
* Size: 2 DDR3 regions */
#define DDR3_FOFBPHA1_SAMPLE_SIZE FOFBPHA0_SAMPLE_SIZE
#define DDR3_FOFBPHA1_SAMPLE_SIZE FOFBPHA_SAMPLE_SIZE
#define DDR3_FOFBPHA1_MEM_SIZE 2
#define DDR3_FOFBPHA1_MEM_BOOL DDR3_MEM_BOOL(DDR3_FOFBPHA1_MEM_SIZE)
......@@ -336,7 +336,7 @@
/* FOFB 1 POS
* Size: 1 DDR3 regions */
#define DDR3_FOFBPOS1_SAMPLE_SIZE FOFBPOS0_SAMPLE_SIZE
#define DDR3_FOFBPOS1_SAMPLE_SIZE FOFBPOS_SAMPLE_SIZE
#define DDR3_FOFBPOS1_MEM_SIZE 2
#define DDR3_FOFBPOS1_MEM_BOOL DDR3_MEM_BOOL(DDR3_FOFBPOS1_MEM_SIZE)
......@@ -346,7 +346,7 @@
/* MONIT 1 AMP
* Size: 1 DDR3 regions */
#define DDR3_MONITAMP1_SAMPLE_SIZE MONITAMP0_SAMPLE_SIZE
#define DDR3_MONITAMP1_SAMPLE_SIZE MONITAMP_SAMPLE_SIZE
#define DDR3_MONITAMP1_MEM_SIZE 0
#define DDR3_MONITAMP1_MEM_BOOL DDR3_MEM_BOOL(DDR3_MONITAMP1_MEM_SIZE)
......@@ -356,7 +356,7 @@
/* MONIT 1 POS
* Size: 1 DDR3 regions */
#define DDR3_MONITPOS1_SAMPLE_SIZE MONITPOS0_SAMPLE_SIZE
#define DDR3_MONITPOS1_SAMPLE_SIZE MONITPOS_SAMPLE_SIZE
#define DDR3_MONITPOS1_MEM_SIZE 0
#define DDR3_MONITPOS1_MEM_BOOL DDR3_MEM_BOOL(DDR3_MONITPOS1_MEM_SIZE)
......@@ -366,7 +366,7 @@
/* MONIT1 1 POS
* Size: 1 DDR3 regions */
#define DDR3_MONIT1POS1_SAMPLE_SIZE MONIT1POS0_SAMPLE_SIZE
#define DDR3_MONIT1POS1_SAMPLE_SIZE MONIT1POS_SAMPLE_SIZE
#define DDR3_MONIT1POS1_MEM_SIZE 0
#define DDR3_MONIT1POS1_MEM_BOOL DDR3_MEM_BOOL(DDR3_MONIT1POS1_MEM_SIZE)
......@@ -376,7 +376,7 @@
/* End 1 Dummy region
* Size: 0 DDR3 regions */
#define DDR3_DUMMY_END1_SAMPLE_SIZE MONIT1POS0_SAMPLE_SIZE
#define DDR3_DUMMY_END1_SAMPLE_SIZE MONIT1POS_SAMPLE_SIZE
#define DDR3_DUMMY_END1_MEM_SIZE 0
#define DDR3_DUMMY_END1_MEM_BOOL DDR3_MEM_BOOL(DDR3_DUMMY_END1_MEM_SIZE)
......
include/boards/afcv3_1/acq_chan.h
View file @ be7dccd5
......@@ -8,75 +8,75 @@
/************************ Acquistion 0 Channel Parameters **************/
/* ADC */
#define ADC0_CHAN_ID 0
#define ADC0_SAMPLE_SIZE 8 /* 8 Bytes -> ADC0 = 16-bit / ADC1 = 16-bit ... */
#define ADC_CHAN_ID 0
#define ADC_SAMPLE_SIZE 8 /* 8 Bytes -> ADC = 16-bit / ADC1 = 16-bit ... */
/* ADC SWAPPED (after the switching module) */
#define ADCSWAP0_CHAN_ID (ADC0_CHAN_ID + 1)
#define ADCSWAP0_SAMPLE_SIZE 8 /* 8 Bytes -> ADCSWAP0 = 16-bit / ADCSWAP1 = 16-bit ... */
#define ADCSWAP_CHAN_ID (ADC_CHAN_ID + 1)
#define ADCSWAP_SAMPLE_SIZE 8 /* 8 Bytes -> ADCSWAP = 16-bit / ADCSWAP1 = 16-bit ... */
/* MIXER I/Q 1/2 */
#define MIXIQ120_CHAN_ID (ADCSWAP0_CHAN_ID + 1)
#define MIXIQ120_SAMPLE_SIZE 16 /* 16 Bytes -> MIXI0 = 32-bit / MIXQ0 = 32-bit ... */
/* MIXER I/Q */
#define MIXIQ_CHAN_ID (ADCSWAP_CHAN_ID + 1)
#define MIXIQ_SAMPLE_SIZE 32 /* 32 Bytes -> MIXI = 32-bit / MIXQ = 32-bit ... / MIXI3 = 32-bit / MIXQ3 */
/* MIXER I/Q 3/4 */
#define MIXIQ340_CHAN_ID (MIXIQ120_CHAN_ID + 1)
#define MIXIQ340_SAMPLE_SIZE 16 /* 16 Bytes -> MIXI2 = 32-bit / MIXQ2 = 32-bit ... */
/* DUMMY 0 */
#define DUMMY0_CHAN_ID (MIXIQ_CHAN_ID + 1)
#define DUMMY0_SAMPLE_SIZE 16 /* 16 Bytes -> 0 */
/* TBTDECIM I/Q 1/2 */
#define TBTDECIMIQ120_CHAN_ID (MIXIQ340_CHAN_ID + 1)
#define TBTDECIMIQ120_SAMPLE_SIZE 16 /* 16 Bytes -> TBTDECIM0 = 32-bit / TBTDECIM1 = 32-bit ... */
/* TBTDECIM I/Q */
#define TBTDECIMIQ_CHAN_ID (DUMMY0_CHAN_ID + 1)
#define TBTDECIMIQ_SAMPLE_SIZE 32 /* 32 Bytes -> TBTDECIM = 32-bit / TBTDECIM1 = 32-bit .../ TBTDECIMI3 = 32-bit / TBTDECIMQ3 */
/* TBTDECIM I/Q 3/4 */
#define TBTDECIMIQ340_CHAN_ID (TBTDECIMIQ120_CHAN_ID + 1)
#define TBTDECIMIQ340_SAMPLE_SIZE 16 /* 16 Bytes -> TBTDECIM0 = 32-bit / TBTDECIM1 = 32-bit ... */
/* DUMMY 1 */
#define DUMMY1_CHAN_ID (TBTDECIMIQ_CHAN_ID + 1)
#define DUMMY1_SAMPLE_SIZE 16 /* 16 Bytes -> 0 */
/* TBT AMP */
#define TBTAMP0_CHAN_ID (TBTDECIMIQ340_CHAN_ID + 1)
#define TBTAMP0_SAMPLE_SIZE 16 /* 16 Bytes -> TBTAMP0 = 32-bit / TBTAMP1 = 32-bit ... */
/* TBT AMP */
#define TBTAMP_CHAN_ID (DUMMY1_CHAN_ID + 1)
#define TBTAMP_SAMPLE_SIZE 16 /* 16 Bytes -> TBTAMP = 32-bit / TBTAMP1 = 32-bit ... */
/* TBT PHASE */
#define TBTPHA0_CHAN_ID (TBTAMP0_CHAN_ID + 1)
#define TBTPHA0_SAMPLE_SIZE 16 /* 16 Bytes -> TBTPHA0 = 32-bit / TBTPHA1 = 32-bit ... */
/* TBT PHASE */
#define TBTPHA_CHAN_ID (TBTAMP_CHAN_ID + 1)
#define TBTPHA_SAMPLE_SIZE 16 /* 16 Bytes -> TBTPHA = 32-bit / TBTPHA1 = 32-bit ... */
/* TBT POS */
#define TBTPOS0_CHAN_ID (TBTPHA0_CHAN_ID + 1)
#define TBTPOS0_SAMPLE_SIZE 16 /* 16 Bytes -> X = 32-bit / Y = 32-bit ... */
/* TBT POS */
#define TBTPOS_CHAN_ID (TBTPHA_CHAN_ID + 1)
#define TBTPOS_SAMPLE_SIZE 16 /* 16 Bytes -> X = 32-bit / Y = 32-bit ... */
/* FOFBDECIM I/Q 1/2 */
#define FOFBDECIMIQ120_CHAN_ID (TBTPOS0_CHAN_ID + 1)
#define FOFBDECIMIQ120_SAMPLE_SIZE 16 /* 16 Bytes -> FOFBDECIM0 = 32-bit / FOFBDECIM1 = 32-bit ... */
/* FOFBDECIM I/Q */
#define FOFBDECIMIQ_CHAN_ID (TBTPOS_CHAN_ID + 1)
#define FOFBDECIMIQ_SAMPLE_SIZE 32 /* 32 Bytes -> FOFBDECIM = 32-bit / FOFBDECIM1 = 32-bit ... / FOFBDECIMI3 = 32-bit / FOFBDECIMQ3 */
/* FOFBDECIM I/Q 3/4 */
#define FOFBDECIMIQ340_CHAN_ID (FOFBDECIMIQ120_CHAN_ID + 1)
#define FOFBDECIMIQ340_SAMPLE_SIZE 16 /* 16 Bytes -> FOFBDECIM0 = 32-bit / FOFBDECIM1 = 32-bit ... */
/* DUMMY 2 */
#define DUMMY2_CHAN_ID (FOFBDECIMIQ_CHAN_ID + 1)
#define DUMMY2_SAMPLE_SIZE 16 /* 16 Bytes -> 0 */
/* FOFB AMP */
#define FOFBAMP0_CHAN_ID (FOFBDECIMIQ340_CHAN_ID + 1)
#define FOFBAMP0_SAMPLE_SIZE 16 /* 16 Bytes -> FOFBAMP0 = 32-bit / FOFBAMP1 = 32-bit ... */
/* FOFB AMP */
#define FOFBAMP_CHAN_ID (DUMMY2_CHAN_ID + 1)
#define FOFBAMP_SAMPLE_SIZE 16 /* 16 Bytes -> FOFBAMP = 32-bit / FOFBAMP1 = 32-bit ... */
/* FOFB PHA */
#define FOFBPHA0_CHAN_ID (FOFBAMP0_CHAN_ID + 1)
#define FOFBPHA0_SAMPLE_SIZE 16 /* 16 Bytes -> FOFBPHA0 = 32-bit / FOFBPHA1 = 32-bit ... */
/* FOFB PHA */
#define FOFBPHA_CHAN_ID (FOFBAMP_CHAN_ID + 1)
#define FOFBPHA_SAMPLE_SIZE 16 /* 16 Bytes -> FOFBPHA = 32-bit / FOFBPHA1 = 32-bit ... */
/* FOFB POS */
#define FOFBPOS0_CHAN_ID (FOFBPHA0_CHAN_ID + 1)
#define FOFBPOS0_SAMPLE_SIZE 16 /* 16 Bytes -> X = 32-bit / Y = 32-bit ... */
/* FOFB POS */
#define FOFBPOS_CHAN_ID (FOFBPHA_CHAN_ID + 1)
#define FOFBPOS_SAMPLE_SIZE 16 /* 16 Bytes -> X = 32-bit / Y = 32-bit ... */
/* MONIT AMP */
#define MONITAMP0_CHAN_ID (FOFBPOS0_CHAN_ID + 1)
#define MONITAMP0_SAMPLE_SIZE 16 /* 16 Bytes -> MONITAMP0 = 32-bit / MONITAMP1 = 32-bit ... */
/* MONIT AMP */
#define MONITAMP_CHAN_ID (FOFBPOS_CHAN_ID + 1)
#define MONITAMP_SAMPLE_SIZE 16 /* 16 Bytes -> MONITAMP = 32-bit / MONITAMP1 = 32-bit ... */
/* MONIT POS */
#define MONITPOS0_CHAN_ID (MONITAMP0_CHAN_ID + 1)
#define MONITPOS0_SAMPLE_SIZE 16 /* 16 Bytes -> X = 32-bit / Y = 32-bit ... */
/* MONIT POS */
#define MONITPOS_CHAN_ID (MONITAMP_CHAN_ID + 1)
#define MONITPOS_SAMPLE_SIZE 16 /* 16 Bytes -> X = 32-bit / Y = 32-bit ... */
/* MONIT1 POS */
#define MONIT1POS0_CHAN_ID (MONITPOS0_CHAN_ID + 1)
#define MONIT1POS0_SAMPLE_SIZE 16 /* 16 Bytes -> X = 32-bit / Y = 32-bit ... */
/* MONIT1 POS */
#define MONIT1POS_CHAN_ID (MONITPOS_CHAN_ID + 1)
#define MONIT1POS_SAMPLE_SIZE 16 /* 16 Bytes -> X = 32-bit / Y = 32-bit ... */
/* End of channels placeholder */
#define END_CHAN_ID (MONIT1POS0_CHAN_ID + 1)
/* End of channels placeholder */
#define END_CHAN_ID (MONIT1POS_CHAN_ID + 1)
#endif
include/boards/afcv3_1/ddr3_map.h
View file @ be7dccd5
......@@ -24,7 +24,7 @@
/* ADC 0 (shares the same memory space as the ADCSWAP0)
* Size: 2 DDR3 regions */
#define DDR3_ADC0_SAMPLE_SIZE ADC0_SAMPLE_SIZE
#define DDR3_ADC0_SAMPLE_SIZE ADC_SAMPLE_SIZE
#define DDR3_ADC0_MEM_SIZE 2
#define DDR3_ADC0_MEM_BOOL DDR3_MEM_BOOL(DDR3_ADC0_MEM_SIZE)
......@@ -34,7 +34,7 @@
/* ADCSWAP 0 (shares the same memory space as the ADC0)
* Size: 2 DDR3 regions */
#define DDR3_ADCSWAP0_SAMPLE_SIZE ADCSWAP0_SAMPLE_SIZE
#define DDR3_ADCSWAP0_SAMPLE_SIZE ADCSWAP_SAMPLE_SIZE
#define DDR3_ADCSWAP0_MEM_SIZE 2
#define DDR3_ADCSWAP0_MEM_BOOL DDR3_MEM_BOOL(DDR3_ADCSWAP0_MEM_SIZE)
......@@ -42,99 +42,99 @@
#define DDR3_ADCSWAP0_END_ADDR (DDR3_ADCSWAP0_START_ADDR + DDR3_ADCSWAP0_MEM_SIZE*MEM_REGION_SIZE - DDR3_ADCSWAP0_MEM_BOOL*DDR3_ADCSWAP0_SAMPLE_SIZE)
#define DDR3_ADCSWAP0_MAX_SAMPLES ((DDR3_ADCSWAP0_END_ADDR-DDR3_ADCSWAP0_START_ADDR) / DDR3_ADCSWAP0_SAMPLE_SIZE)
/* MIXER I/Q 1/2 (shares the same memory space as the MIXIQ340)
/* MIXER I/Q 1/2 (shares the same memory space as the DUMMY00)
* Size: 1 DDR3 regions */
#define DDR3_MIXIQ120_SAMPLE_SIZE MIXIQ120_SAMPLE_SIZE
#define DDR3_MIXIQ120_MEM_SIZE 1
#define DDR3_MIXIQ0_SAMPLE_SIZE MIXIQ_SAMPLE_SIZE
#define DDR3_MIXIQ0_MEM_SIZE 1
#define DDR3_MIXIQ120_MEM_BOOL DDR3_MEM_BOOL(DDR3_MIXIQ120_MEM_SIZE)
#define DDR3_MIXIQ120_START_ADDR (DDR3_ADCSWAP0_END_ADDR + DDR3_ADCSWAP0_MEM_BOOL*DDR3_ADCSWAP0_SAMPLE_SIZE)
#define DDR3_MIXIQ120_END_ADDR (DDR3_MIXIQ120_START_ADDR + DDR3_MIXIQ120_MEM_SIZE*MEM_REGION_SIZE - DDR3_MIXIQ120_MEM_BOOL*DDR3_MIXIQ120_SAMPLE_SIZE)
#define DDR3_MIXIQ120_MAX_SAMPLES ((DDR3_MIXIQ120_END_ADDR-DDR3_MIXIQ120_START_ADDR) / DDR3_MIXIQ120_SAMPLE_SIZE)
#define DDR3_MIXIQ0_MEM_BOOL DDR3_MEM_BOOL(DDR3_MIXIQ0_MEM_SIZE)
#define DDR3_MIXIQ0_START_ADDR (DDR3_ADCSWAP0_END_ADDR + DDR3_ADCSWAP0_MEM_BOOL*DDR3_ADCSWAP0_SAMPLE_SIZE)
#define DDR3_MIXIQ0_END_ADDR (DDR3_MIXIQ0_START_ADDR + DDR3_MIXIQ0_MEM_SIZE*MEM_REGION_SIZE - DDR3_MIXIQ0_MEM_BOOL*DDR3_MIXIQ0_SAMPLE_SIZE)
#define DDR3_MIXIQ0_MAX_SAMPLES ((DDR3_MIXIQ0_END_ADDR-DDR3_MIXIQ0_START_ADDR) / DDR3_MIXIQ0_SAMPLE_SIZE)
/* MIXER I/Q 3/4 (shares the same memory space as the MIXIQ120)
/* MIXER I/Q 3/4 (shares the same memory space as the MIXIQ0)
* Size: 1 DDR3 regions */
#define DDR3_MIXIQ340_SAMPLE_SIZE MIXIQ340_SAMPLE_SIZE
#define DDR3_MIXIQ340_MEM_SIZE 1
#define DDR3_DUMMY00_SAMPLE_SIZE MIXIQ_SAMPLE_SIZE
#define DDR3_DUMMY00_MEM_SIZE 0
#define DDR3_MIXIQ340_MEM_BOOL DDR3_MEM_BOOL(DDR3_MIXIQ340_MEM_SIZE)
#define DDR3_MIXIQ340_START_ADDR (DDR3_ADCSWAP0_END_ADDR + DDR3_ADCSWAP0_MEM_BOOL*DDR3_ADCSWAP0_SAMPLE_SIZE)
#define DDR3_MIXIQ340_END_ADDR (DDR3_MIXIQ340_START_ADDR + DDR3_MIXIQ340_MEM_SIZE*MEM_REGION_SIZE - DDR3_MIXIQ340_MEM_BOOL*DDR3_MIXIQ340_SAMPLE_SIZE)
#define DDR3_MIXIQ340_MAX_SAMPLES ((DDR3_MIXIQ340_END_ADDR-DDR3_MIXIQ340_START_ADDR) / DDR3_MIXIQ340_SAMPLE_SIZE)
#define DDR3_DUMMY00_MEM_BOOL DDR3_MEM_BOOL(DDR3_DUMMY00_MEM_SIZE)
#define DDR3_DUMMY00_START_ADDR (DDR3_ADCSWAP0_END_ADDR + DDR3_ADCSWAP0_MEM_BOOL*DDR3_ADCSWAP0_SAMPLE_SIZE)
#define DDR3_DUMMY00_END_ADDR (DDR3_DUMMY00_START_ADDR + DDR3_DUMMY00_MEM_SIZE*MEM_REGION_SIZE - DDR3_DUMMY00_MEM_BOOL*DDR3_DUMMY00_SAMPLE_SIZE)
#define DDR3_DUMMY00_MAX_SAMPLES ((DDR3_DUMMY00_END_ADDR-DDR3_DUMMY00_START_ADDR) / DDR3_DUMMY00_SAMPLE_SIZE)
/* TBTDECIM I/Q 1/2 (shares the same memory space as the TBTDECIMIQ340 and TBTAMP0)
/* TBTDECIM I/Q 1/2 (shares the same memory space as the DUMMY10 and TBTAMP0)
* Size: 1 DDR3 regions */
#define DDR3_TBTDECIMIQ120_SAMPLE_SIZE TBTDECIMIQ120_SAMPLE_SIZE
#define DDR3_TBTDECIMIQ120_MEM_SIZE 2
#define DDR3_TBTDECIMIQ0_SAMPLE_SIZE TBTDECIMIQ_SAMPLE_SIZE
#define DDR3_TBTDECIMIQ0_MEM_SIZE 2
#define DDR3_TBTDECIMIQ120_MEM_BOOL DDR3_MEM_BOOL(DDR3_TBTDECIMIQ120_MEM_SIZE)
#define DDR3_TBTDECIMIQ120_START_ADDR (DDR3_MIXIQ340_END_ADDR + DDR3_MIXIQ340_MEM_BOOL*DDR3_MIXIQ340_SAMPLE_SIZE)
#define DDR3_TBTDECIMIQ120_END_ADDR (DDR3_TBTDECIMIQ120_START_ADDR + DDR3_TBTDECIMIQ120_MEM_SIZE*MEM_REGION_SIZE - DDR3_TBTDECIMIQ120_MEM_BOOL*DDR3_TBTDECIMIQ120_SAMPLE_SIZE)
#define DDR3_TBTDECIMIQ120_MAX_SAMPLES ((DDR3_TBTDECIMIQ120_END_ADDR-DDR3_TBTDECIMIQ120_START_ADDR) / DDR3_TBTDECIMIQ120_SAMPLE_SIZE)
#define DDR3_TBTDECIMIQ0_MEM_BOOL DDR3_MEM_BOOL(DDR3_TBTDECIMIQ0_MEM_SIZE)
#define DDR3_TBTDECIMIQ0_START_ADDR (DDR3_DUMMY00_END_ADDR + DDR3_DUMMY00_MEM_BOOL*DDR3_DUMMY00_SAMPLE_SIZE)
#define DDR3_TBTDECIMIQ0_END_ADDR (DDR3_TBTDECIMIQ0_START_ADDR + DDR3_TBTDECIMIQ0_MEM_SIZE*MEM_REGION_SIZE - DDR3_TBTDECIMIQ0_MEM_BOOL*DDR3_TBTDECIMIQ0_SAMPLE_SIZE)
#define DDR3_TBTDECIMIQ0_MAX_SAMPLES ((DDR3_TBTDECIMIQ0_END_ADDR-DDR3_TBTDECIMIQ0_START_ADDR) / DDR3_TBTDECIMIQ0_SAMPLE_SIZE)
/* TBTDECIM I/Q 3/4 (shares the same memory space as the TBTDECIMIQ120 and TBTAMP0)
/* TBTDECIM I/Q 3/4 (shares the same memory space as the TBTDECIMIQ0 and TBTAMP0)
* Size: 1 DDR3 regions */
#define DDR3_TBTDECIMIQ340_SAMPLE_SIZE TBTDECIMIQ340_SAMPLE_SIZE
#define DDR3_TBTDECIMIQ340_MEM_SIZE 2
#define DDR3_DUMMY10_SAMPLE_SIZE TBTDECIMIQ_SAMPLE_SIZE
#define DDR3_DUMMY10_MEM_SIZE 0
#define DDR3_TBTDECIMIQ340_MEM_BOOL DDR3_MEM_BOOL(DDR3_TBTDECIMIQ340_MEM_SIZE)
#define DDR3_TBTDECIMIQ340_START_ADDR (DDR3_MIXIQ340_END_ADDR + DDR3_MIXIQ340_MEM_BOOL*DDR3_MIXIQ340_SAMPLE_SIZE)
#define DDR3_TBTDECIMIQ340_END_ADDR (DDR3_TBTDECIMIQ340_START_ADDR + DDR3_TBTDECIMIQ340_MEM_SIZE*MEM_REGION_SIZE - DDR3_TBTDECIMIQ340_MEM_BOOL*DDR3_TBTDECIMIQ340_SAMPLE_SIZE)
#define DDR3_TBTDECIMIQ340_MAX_SAMPLES ((DDR3_TBTDECIMIQ340_END_ADDR-DDR3_TBTDECIMIQ340_START_ADDR) / DDR3_TBTDECIMIQ340_SAMPLE_SIZE)
#define DDR3_DUMMY10_MEM_BOOL DDR3_MEM_BOOL(DDR3_DUMMY10_MEM_SIZE)
#define DDR3_DUMMY10_START_ADDR (DDR3_DUMMY00_END_ADDR + DDR3_DUMMY00_MEM_BOOL*DDR3_DUMMY00_SAMPLE_SIZE)
#define DDR3_DUMMY10_END_ADDR (DDR3_DUMMY10_START_ADDR + DDR3_DUMMY10_MEM_SIZE*MEM_REGION_SIZE - DDR3_DUMMY10_MEM_BOOL*DDR3_DUMMY10_SAMPLE_SIZE)
#define DDR3_DUMMY10_MAX_SAMPLES ((DDR3_DUMMY10_END_ADDR-DDR3_DUMMY10_START_ADDR) / DDR3_DUMMY10_SAMPLE_SIZE)
/* TBT 0 AMP (shares the same memory space as the TBTDECIMIQ120 and TBTDECIMIQ340)
/* TBT 0 AMP (shares the same memory space as the TBTDECIMIQ0 and DUMMY10)
* Size: 2 DDR3 regions */
#define DDR3_TBTAMP0_SAMPLE_SIZE TBTAMP0_SAMPLE_SIZE
#define DDR3_TBTAMP0_SAMPLE_SIZE TBTAMP_SAMPLE_SIZE
#define DDR3_TBTAMP0_MEM_SIZE 2
#define DDR3_TBTAMP0_MEM_BOOL DDR3_MEM_BOOL(DDR3_TBTAMP0_MEM_SIZE)
#define DDR3_TBTAMP0_START_ADDR (DDR3_MIXIQ340_END_ADDR + DDR3_MIXIQ340_MEM_BOOL*DDR3_MIXIQ340_SAMPLE_SIZE)
#define DDR3_TBTAMP0_START_ADDR (DDR3_DUMMY00_END_ADDR + DDR3_DUMMY00_MEM_BOOL*DDR3_DUMMY00_SAMPLE_SIZE)
#define DDR3_TBTAMP0_END_ADDR (DDR3_TBTAMP0_START_ADDR + DDR3_TBTAMP0_MEM_SIZE*MEM_REGION_SIZE - DDR3_TBTAMP0_MEM_BOOL*DDR3_TBTAMP0_SAMPLE_SIZE)
#define DDR3_TBTAMP0_MAX_SAMPLES ((DDR3_TBTAMP0_END_ADDR-DDR3_TBTAMP0_START_ADDR) / DDR3_TBTAMP0_SAMPLE_SIZE)
/* TBT 0 PHA (shares the same memory space as the TBTDECIMIQ120 and TBTDECIMIQ340)
/* TBT 0 PHA (shares the same memory space as the TBTDECIMIQ0 and DUMMY10)
* Size: 2 DDR3 regions */
#define DDR3_TBTPHA0_SAMPLE_SIZE TBTPHA0_SAMPLE_SIZE
#define DDR3_TBTPHA0_SAMPLE_SIZE TBTPHA_SAMPLE_SIZE
#define DDR3_TBTPHA0_MEM_SIZE 2
#define DDR3_TBTPHA0_MEM_BOOL DDR3_MEM_BOOL(DDR3_TBTPHA0_MEM_SIZE)
#define DDR3_TBTPHA0_START_ADDR (DDR3_MIXIQ340_END_ADDR + DDR3_MIXIQ340_MEM_BOOL*DDR3_MIXIQ340_SAMPLE_SIZE)
#define DDR3_TBTPHA0_START_ADDR (DDR3_DUMMY00_END_ADDR + DDR3_DUMMY00_MEM_BOOL*DDR3_DUMMY00_SAMPLE_SIZE)
#define DDR3_TBTPHA0_END_ADDR (DDR3_TBTPHA0_START_ADDR + DDR3_TBTPHA0_MEM_SIZE*MEM_REGION_SIZE - DDR3_TBTPHA0_MEM_BOOL*DDR3_TBTPHA0_SAMPLE_SIZE)
#define DDR3_TBTPHA0_MAX_SAMPLES ((DDR3_TBTPHA0_END_ADDR-DDR3_TBTPHA0_START_ADDR) / DDR3_TBTPHA0_SAMPLE_SIZE)
/* TBT 0 POS (shares the same memory space as the TBTDECIMIQ120 and TBTDECIMIQ340)
/* TBT 0 POS (shares the same memory space as the TBTDECIMIQ0 and DUMMY10)
* Size: 0 DDR3 regions */
#define DDR3_TBTPOS0_SAMPLE_SIZE TBTPOS0_SAMPLE_SIZE
#define DDR3_TBTPOS0_SAMPLE_SIZE TBTPOS_SAMPLE_SIZE
#define DDR3_TBTPOS0_MEM_SIZE 2
#define DDR3_TBTPOS0_MEM_BOOL DDR3_MEM_BOOL(DDR3_TBTPOS0_MEM_SIZE)
#define DDR3_TBTPOS0_START_ADDR (DDR3_MIXIQ340_END_ADDR + DDR3_MIXIQ340_MEM_BOOL*DDR3_MIXIQ340_SAMPLE_SIZE)
#define DDR3_TBTPOS0_START_ADDR (DDR3_DUMMY00_END_ADDR + DDR3_DUMMY00_MEM_BOOL*DDR3_DUMMY00_SAMPLE_SIZE)
#define DDR3_TBTPOS0_END_ADDR (DDR3_TBTPOS0_START_ADDR + DDR3_TBTPOS0_MEM_SIZE*MEM_REGION_SIZE - DDR3_TBTPOS0_MEM_BOOL*DDR3_TBTPOS0_SAMPLE_SIZE)
#define DDR3_TBTPOS0_MAX_SAMPLES ((DDR3_TBTPOS0_END_ADDR-DDR3_TBTPOS0_START_ADDR) / DDR3_TBTPOS0_SAMPLE_SIZE)
/* FOFBDECIM I/Q 1/2 (shares the same memory space as the FOFBDECIMIQ340 and FOFBAMP0)
/* FOFBDECIM I/Q 1/2 (shares the same memory space as the DUMMY20 and FOFBAMP0)
* Size: 1 DDR3 regions */
#define DDR3_FOFBDECIMIQ120_SAMPLE_SIZE FOFBDECIMIQ120_SAMPLE_SIZE
#define DDR3_FOFBDECIMIQ120_MEM_SIZE 2
#define DDR3_FOFBDECIMIQ0_SAMPLE_SIZE FOFBDECIMIQ_SAMPLE_SIZE
#define DDR3_FOFBDECIMIQ0_MEM_SIZE 2
#define DDR3_FOFBDECIMIQ120_MEM_BOOL DDR3_MEM_BOOL(DDR3_FOFBDECIMIQ120_MEM_SIZE)
#define DDR3_FOFBDECIMIQ120_START_ADDR (DDR3_TBTPOS0_END_ADDR + DDR3_TBTPOS0_MEM_BOOL*DDR3_TBTPOS0_SAMPLE_SIZE)
#define DDR3_FOFBDECIMIQ120_END_ADDR (DDR3_FOFBDECIMIQ120_START_ADDR + DDR3_FOFBDECIMIQ120_MEM_SIZE*MEM_REGION_SIZE - DDR3_FOFBDECIMIQ120_MEM_BOOL*DDR3_FOFBDECIMIQ120_SAMPLE_SIZE)
#define DDR3_FOFBDECIMIQ120_MAX_SAMPLES ((DDR3_FOFBDECIMIQ120_END_ADDR-DDR3_FOFBDECIMIQ120_START_ADDR) / DDR3_FOFBDECIMIQ120_SAMPLE_SIZE)
#define DDR3_FOFBDECIMIQ0_MEM_BOOL DDR3_MEM_BOOL(DDR3_FOFBDECIMIQ0_MEM_SIZE)
#define DDR3_FOFBDECIMIQ0_START_ADDR (DDR3_TBTPOS0_END_ADDR + DDR3_TBTPOS0_MEM_BOOL*DDR3_TBTPOS0_SAMPLE_SIZE)
#define DDR3_FOFBDECIMIQ0_END_ADDR (DDR3_FOFBDECIMIQ0_START_ADDR + DDR3_FOFBDECIMIQ0_MEM_SIZE*MEM_REGION_SIZE - DDR3_FOFBDECIMIQ0_MEM_BOOL*DDR3_FOFBDECIMIQ0_SAMPLE_SIZE)
#define DDR3_FOFBDECIMIQ0_MAX_SAMPLES ((DDR3_FOFBDECIMIQ0_END_ADDR-DDR3_FOFBDECIMIQ0_START_ADDR) / DDR3_FOFBDECIMIQ0_SAMPLE_SIZE)
/* FOFBDECIM I/Q 3/4 (shares the same memory space as the FOFBDECIMIQ120 and FOFBAMP0)
/* FOFBDECIM I/Q 3/4 (shares the same memory space as the FOFBDECIMIQ0 and FOFBAMP0)
* Size: 1 DDR3 regions */
#define DDR3_FOFBDECIMIQ340_SAMPLE_SIZE FOFBDECIMIQ340_SAMPLE_SIZE
#define DDR3_FOFBDECIMIQ340_MEM_SIZE 2
#define DDR3_DUMMY20_SAMPLE_SIZE FOFBDECIMIQ_SAMPLE_SIZE
#define DDR3_DUMMY20_MEM_SIZE 0
#define DDR3_FOFBDECIMIQ340_MEM_BOOL DDR3_MEM_BOOL(DDR3_FOFBDECIMIQ340_MEM_SIZE)
#define DDR3_FOFBDECIMIQ340_START_ADDR (DDR3_TBTPOS0_END_ADDR + DDR3_TBTPOS0_MEM_BOOL*DDR3_TBTPOS0_SAMPLE_SIZE)
#define DDR3_FOFBDECIMIQ340_END_ADDR (DDR3_FOFBDECIMIQ340_START_ADDR + DDR3_FOFBDECIMIQ340_MEM_SIZE*MEM_REGION_SIZE - DDR3_FOFBDECIMIQ340_MEM_BOOL*DDR3_FOFBDECIMIQ340_SAMPLE_SIZE)
#define DDR3_FOFBDECIMIQ340_MAX_SAMPLES ((DDR3_FOFBDECIMIQ340_END_ADDR-DDR3_FOFBDECIMIQ340_START_ADDR) / DDR3_FOFBDECIMIQ340_SAMPLE_SIZE)
#define DDR3_DUMMY20_MEM_BOOL DDR3_MEM_BOOL(DDR3_DUMMY20_MEM_SIZE)
#define DDR3_DUMMY20_START_ADDR (DDR3_TBTPOS0_END_ADDR + DDR3_TBTPOS0_MEM_BOOL*DDR3_TBTPOS0_SAMPLE_SIZE)
#define DDR3_DUMMY20_END_ADDR (DDR3_DUMMY20_START_ADDR + DDR3_DUMMY20_MEM_SIZE*MEM_REGION_SIZE - DDR3_DUMMY20_MEM_BOOL*DDR3_DUMMY20_SAMPLE_SIZE)
#define DDR3_DUMMY20_MAX_SAMPLES ((DDR3_DUMMY20_END_ADDR-DDR3_DUMMY20_START_ADDR) / DDR3_DUMMY20_SAMPLE_SIZE)
/* FOFB 0 AMP
* Size: 2 DDR3 regions */
#define DDR3_FOFBAMP0_SAMPLE_SIZE FOFBAMP0_SAMPLE_SIZE
#define DDR3_FOFBAMP0_SAMPLE_SIZE FOFBAMP_SAMPLE_SIZE
#define DDR3_FOFBAMP0_MEM_SIZE 2
#define DDR3_FOFBAMP0_MEM_BOOL DDR3_MEM_BOOL(DDR3_FOFBAMP0_MEM_SIZE)
......@@ -144,7 +144,7 @@
/* FOFB 0 PHA (shares the same memory space as the FOFBDECIMIQ12 and FOFBDECIMIQ34)
* Size: 2 DDR3 regions */
#define DDR3_FOFBPHA0_SAMPLE_SIZE FOFBPHA0_SAMPLE_SIZE
#define DDR3_FOFBPHA0_SAMPLE_SIZE FOFBPHA_SAMPLE_SIZE
#define DDR3_FOFBPHA0_MEM_SIZE 2
#define DDR3_FOFBPHA0_MEM_BOOL DDR3_MEM_BOOL(DDR3_FOFBPHA0_MEM_SIZE)
......@@ -154,7 +154,7 @@
/* FOFB 0 POS
* Size: 0 DDR3 regions */
#define DDR3_FOFBPOS0_SAMPLE_SIZE FOFBPOS0_SAMPLE_SIZE
#define DDR3_FOFBPOS0_SAMPLE_SIZE FOFBPOS_SAMPLE_SIZE
#define DDR3_FOFBPOS0_MEM_SIZE 2
#define DDR3_FOFBPOS0_MEM_BOOL DDR3_MEM_BOOL(DDR3_FOFBPOS0_MEM_SIZE)
......@@ -164,7 +164,7 @@
/* MONIT 0 AMP
* Size: 0 DDR3 regions */
#define DDR3_MONITAMP0_SAMPLE_SIZE MONITAMP0_SAMPLE_SIZE
#define DDR3_MONITAMP0_SAMPLE_SIZE MONITAMP_SAMPLE_SIZE
#define DDR3_MONITAMP0_MEM_SIZE 0
#define DDR3_MONITAMP0_MEM_BOOL DDR3_MEM_BOOL(DDR3_MONITAMP0_MEM_SIZE)
......@@ -174,7 +174,7 @@
/* MONIT 0 POS
* Size: 0 DDR3 regions */
#define DDR3_MONITPOS0_SAMPLE_SIZE MONITPOS0_SAMPLE_SIZE
#define DDR3_MONITPOS0_SAMPLE_SIZE MONITPOS_SAMPLE_SIZE
#define DDR3_MONITPOS0_MEM_SIZE 0
#define DDR3_MONITPOS0_MEM_BOOL DDR3_MEM_BOOL(DDR3_MONITPOS0_MEM_SIZE)
......@@ -184,7 +184,7 @@
/* MONIT1 0 POS
* Size: 0 DDR3 regions */
#define DDR3_MONIT1POS0_SAMPLE_SIZE MONIT1POS0_SAMPLE_SIZE
#define DDR3_MONIT1POS0_SAMPLE_SIZE MONIT1POS_SAMPLE_SIZE
#define DDR3_MONIT1POS0_MEM_SIZE 0
#define DDR3_MONIT1POS0_MEM_BOOL DDR3_MEM_BOOL(DDR3_MONIT1POS0_MEM_SIZE)
......@@ -194,7 +194,7 @@
/* End 0 Dummy region
* Size: 0 DDR3 regions */
#define DDR3_DUMMY_END0_SAMPLE_SIZE MONIT1POS0_SAMPLE_SIZE
#define DDR3_DUMMY_END0_SAMPLE_SIZE MONIT1POS_SAMPLE_SIZE
#define DDR3_DUMMY_END0_MEM_SIZE 0
#define DDR3_DUMMY_END0_MEM_BOOL DDR3_MEM_BOOL(DDR3_DUMMY_END0_MEM_SIZE)
......@@ -206,7 +206,7 @@
/* ADC 1
* Size: 2 DDR3 regions */
#define DDR3_ADC1_SAMPLE_SIZE ADC0_SAMPLE_SIZE
#define DDR3_ADC1_SAMPLE_SIZE ADC_SAMPLE_SIZE
#define DDR3_ADC1_MEM_SIZE 2
#define DDR3_ADC1_MEM_BOOL DDR3_MEM_BOOL(DDR3_ADC1_MEM_SIZE)
......@@ -216,7 +216,7 @@
/* ADCSWAP 1
* Size: 2 DDR3 regions */
#define DDR3_ADCSWAP1_SAMPLE_SIZE ADCSWAP0_SAMPLE_SIZE
#define DDR3_ADCSWAP1_SAMPLE_SIZE ADCSWAP_SAMPLE_SIZE
#define DDR3_ADCSWAP1_MEM_SIZE 2
#define DDR3_ADCSWAP1_MEM_BOOL DDR3_MEM_BOOL(DDR3_ADCSWAP1_MEM_SIZE)
......@@ -224,99 +224,99 @@
#define DDR3_ADCSWAP1_END_ADDR (DDR3_ADCSWAP1_START_ADDR + DDR3_ADCSWAP1_MEM_SIZE*MEM_REGION_SIZE - DDR3_ADCSWAP1_MEM_BOOL*DDR3_ADCSWAP1_SAMPLE_SIZE)
#define DDR3_ADCSWAP1_MAX_SAMPLES ((DDR3_ADCSWAP1_END_ADDR-DDR3_ADCSWAP1_START_ADDR) / DDR3_ADCSWAP1_SAMPLE_SIZE)
/* MIXER I/Q 1/2 (shares the same memory space as the MIXIQ341)
/* MIXER I/Q 1/2 (shares the same memory space as the DUMMY01)
* Size: 1 DDR3 regions */
#define DDR3_MIXIQ121_SAMPLE_SIZE MIXIQ120_SAMPLE_SIZE
#define DDR3_MIXIQ121_MEM_SIZE 1
#define DDR3_MIXIQ1_SAMPLE_SIZE MIXIQ_SAMPLE_SIZE
#define DDR3_MIXIQ1_MEM_SIZE 1
#define DDR3_MIXIQ121_MEM_BOOL DDR3_MEM_BOOL(DDR3_MIXIQ121_MEM_SIZE)
#define DDR3_MIXIQ121_START_ADDR (DDR3_ADCSWAP1_END_ADDR + DDR3_ADCSWAP0_MEM_BOOL*DDR3_ADCSWAP0_SAMPLE_SIZE)
#define DDR3_MIXIQ121_END_ADDR (DDR3_MIXIQ121_START_ADDR + DDR3_MIXIQ121_MEM_SIZE*MEM_REGION_SIZE - DDR3_MIXIQ121_MEM_BOOL*DDR3_MIXIQ121_SAMPLE_SIZE)
#define DDR3_MIXIQ121_MAX_SAMPLES ((DDR3_MIXIQ121_END_ADDR-DDR3_MIXIQ121_START_ADDR) / DDR3_MIXIQ121_SAMPLE_SIZE)
#define DDR3_MIXIQ1_MEM_BOOL DDR3_MEM_BOOL(DDR3_MIXIQ1_MEM_SIZE)
#define DDR3_MIXIQ1_START_ADDR (DDR3_ADCSWAP1_END_ADDR + DDR3_ADCSWAP0_MEM_BOOL*DDR3_ADCSWAP0_SAMPLE_SIZE)
#define DDR3_MIXIQ1_END_ADDR (DDR3_MIXIQ1_START_ADDR + DDR3_MIXIQ1_MEM_SIZE*MEM_REGION_SIZE - DDR3_MIXIQ1_MEM_BOOL*DDR3_MIXIQ1_SAMPLE_SIZE)
#define DDR3_MIXIQ1_MAX_SAMPLES ((DDR3_MIXIQ1_END_ADDR-DDR3_MIXIQ1_START_ADDR) / DDR3_MIXIQ1_SAMPLE_SIZE)
/* MIXER I/Q 3/4 (shares the same memory space as the MIXIQ121)
/* MIXER I/Q 3/4 (shares the same memory space as the MIXIQ1)
* Size: 1 DDR3 regions */
#define DDR3_MIXIQ341_SAMPLE_SIZE MIXIQ340_SAMPLE_SIZE
#define DDR3_MIXIQ341_MEM_SIZE 1
#define DDR3_DUMMY01_SAMPLE_SIZE MIXIQ_SAMPLE_SIZE
#define DDR3_DUMMY01_MEM_SIZE 1
#define DDR3_MIXIQ341_MEM_BOOL DDR3_MEM_BOOL(DDR3_MIXIQ341_MEM_SIZE)
#define DDR3_MIXIQ341_START_ADDR (DDR3_ADCSWAP1_END_ADDR + DDR3_ADCSWAP0_MEM_BOOL*DDR3_ADCSWAP0_SAMPLE_SIZE)
#define DDR3_MIXIQ341_END_ADDR (DDR3_MIXIQ341_START_ADDR + DDR3_MIXIQ341_MEM_SIZE*MEM_REGION_SIZE - DDR3_MIXIQ341_MEM_BOOL*DDR3_MIXIQ341_SAMPLE_SIZE)
#define DDR3_MIXIQ341_MAX_SAMPLES ((DDR3_MIXIQ341_END_ADDR-DDR3_MIXIQ341_START_ADDR) / DDR3_MIXIQ341_SAMPLE_SIZE)
#define DDR3_DUMMY01_MEM_BOOL DDR3_MEM_BOOL(DDR3_DUMMY01_MEM_SIZE)
#define DDR3_DUMMY01_START_ADDR (DDR3_ADCSWAP1_END_ADDR + DDR3_ADCSWAP0_MEM_BOOL*DDR3_ADCSWAP0_SAMPLE_SIZE)
#define DDR3_DUMMY01_END_ADDR (DDR3_DUMMY01_START_ADDR + DDR3_DUMMY01_MEM_SIZE*MEM_REGION_SIZE - DDR3_DUMMY01_MEM_BOOL*DDR3_DUMMY01_SAMPLE_SIZE)
#define DDR3_DUMMY01_MAX_SAMPLES ((DDR3_DUMMY01_END_ADDR-DDR3_DUMMY01_START_ADDR) / DDR3_DUMMY01_SAMPLE_SIZE)
/* TBTDECIM I/Q 1/2 (shares the same memory space as the TBTDECIMIQ341 and TBTAMP1)
/* TBTDECIM I/Q 1/2 (shares the same memory space as the DUMMY11 and TBTAMP1)
* Size: 1 DDR3 regions */
#define DDR3_TBTDECIMIQ121_SAMPLE_SIZE TBTDECIMIQ120_SAMPLE_SIZE
#define DDR3_TBTDECIMIQ121_MEM_SIZE 2
#define DDR3_TBTDECIMIQ1_SAMPLE_SIZE TBTDECIMIQ_SAMPLE_SIZE
#define DDR3_TBTDECIMIQ1_MEM_SIZE 2
#define DDR3_TBTDECIMIQ121_MEM_BOOL DDR3_MEM_BOOL(DDR3_TBTDECIMIQ121_MEM_SIZE)
#define DDR3_TBTDECIMIQ121_START_ADDR (DDR3_MIXIQ341_END_ADDR + DDR3_MIXIQ341_MEM_BOOL*DDR3_MIXIQ341_SAMPLE_SIZE)
#define DDR3_TBTDECIMIQ121_END_ADDR (DDR3_TBTDECIMIQ121_START_ADDR + DDR3_TBTDECIMIQ121_MEM_SIZE*MEM_REGION_SIZE - DDR3_TBTDECIMIQ121_MEM_BOOL*DDR3_TBTDECIMIQ121_SAMPLE_SIZE)
#define DDR3_TBTDECIMIQ121_MAX_SAMPLES ((DDR3_TBTDECIMIQ121_END_ADDR-DDR3_TBTDECIMIQ121_START_ADDR) / DDR3_TBTDECIMIQ121_SAMPLE_SIZE)
#define DDR3_TBTDECIMIQ1_MEM_BOOL DDR3_MEM_BOOL(DDR3_TBTDECIMIQ1_MEM_SIZE)
#define DDR3_TBTDECIMIQ1_START_ADDR (DDR3_DUMMY01_END_ADDR + DDR3_DUMMY01_MEM_BOOL*DDR3_DUMMY01_SAMPLE_SIZE)
#define DDR3_TBTDECIMIQ1_END_ADDR (DDR3_TBTDECIMIQ1_START_ADDR + DDR3_TBTDECIMIQ1_MEM_SIZE*MEM_REGION_SIZE - DDR3_TBTDECIMIQ1_MEM_BOOL*DDR3_TBTDECIMIQ1_SAMPLE_SIZE)
#define DDR3_TBTDECIMIQ1_MAX_SAMPLES ((DDR3_TBTDECIMIQ1_END_ADDR-DDR3_TBTDECIMIQ1_START_ADDR) / DDR3_TBTDECIMIQ1_SAMPLE_SIZE)
/* TBTDECIM I/Q 3/4 (shares the same memory space as the TBTDECIMIQ121 and TBTAMP1)
/* TBTDECIM I/Q 3/4 (shares the same memory space as the TBTDECIMIQ1 and TBTAMP1)
* Size: 1 DDR3 regions */
#define DDR3_TBTDECIMIQ341_SAMPLE_SIZE TBTDECIMIQ340_SAMPLE_SIZE
#define DDR3_TBTDECIMIQ341_MEM_SIZE 2
#define DDR3_DUMMY11_SAMPLE_SIZE TBTDECIMIQ_SAMPLE_SIZE
#define DDR3_DUMMY11_MEM_SIZE 2
#define DDR3_TBTDECIMIQ341_MEM_BOOL DDR3_MEM_BOOL(DDR3_TBTDECIMIQ341_MEM_SIZE)
#define DDR3_TBTDECIMIQ341_START_ADDR (DDR3_MIXIQ341_END_ADDR + DDR3_MIXIQ341_MEM_BOOL*DDR3_MIXIQ341_SAMPLE_SIZE)
#define DDR3_TBTDECIMIQ341_END_ADDR (DDR3_TBTDECIMIQ341_START_ADDR + DDR3_TBTDECIMIQ341_MEM_SIZE*MEM_REGION_SIZE - DDR3_TBTDECIMIQ341_MEM_BOOL*DDR3_TBTDECIMIQ341_SAMPLE_SIZE)
#define DDR3_TBTDECIMIQ341_MAX_SAMPLES ((DDR3_TBTDECIMIQ341_END_ADDR-DDR3_TBTDECIMIQ341_START_ADDR) / DDR3_TBTDECIMIQ341_SAMPLE_SIZE)
#define DDR3_DUMMY11_MEM_BOOL DDR3_MEM_BOOL(DDR3_DUMMY11_MEM_SIZE)
#define DDR3_DUMMY11_START_ADDR (DDR3_DUMMY01_END_ADDR + DDR3_DUMMY01_MEM_BOOL*DDR3_DUMMY01_SAMPLE_SIZE)
#define DDR3_DUMMY11_END_ADDR (DDR3_DUMMY11_START_ADDR + DDR3_DUMMY11_MEM_SIZE*MEM_REGION_SIZE - DDR3_DUMMY11_MEM_BOOL*DDR3_DUMMY11_SAMPLE_SIZE)
#define DDR3_DUMMY11_MAX_SAMPLES ((DDR3_DUMMY11_END_ADDR-DDR3_DUMMY11_START_ADDR) / DDR3_DUMMY11_SAMPLE_SIZE)
/* TBT 1 AMP
* Size: 2 DDR3 regions */
#define DDR3_TBTAMP1_SAMPLE_SIZE TBTAMP0_SAMPLE_SIZE
#define DDR3_TBTAMP1_SAMPLE_SIZE TBTAMP_SAMPLE_SIZE
#define DDR3_TBTAMP1_MEM_SIZE 2
#define DDR3_TBTAMP1_MEM_BOOL DDR3_MEM_BOOL(DDR3_TBTAMP1_MEM_SIZE)
#define DDR3_TBTAMP1_START_ADDR (DDR3_MIXIQ341_END_ADDR + DDR3_MIXIQ341_MEM_BOOL*DDR3_MIXIQ341_SAMPLE_SIZE)
#define DDR3_TBTAMP1_START_ADDR (DDR3_DUMMY01_END_ADDR + DDR3_DUMMY01_MEM_BOOL*DDR3_DUMMY01_SAMPLE_SIZE)
#define DDR3_TBTAMP1_END_ADDR (DDR3_TBTAMP1_START_ADDR + DDR3_TBTAMP1_MEM_SIZE*MEM_REGION_SIZE - DDR3_TBTAMP1_MEM_BOOL*DDR3_TBTAMP1_SAMPLE_SIZE)
#define DDR3_TBTAMP1_MAX_SAMPLES ((DDR3_TBTAMP1_END_ADDR-DDR3_TBTAMP1_START_ADDR) / DDR3_TBTAMP1_SAMPLE_SIZE)
/* TBT 1 PHA (shares the same memory space as the TBTDECIMIQ121 and TBTDECIMIQ341)
/* TBT 1 PHA (shares the same memory space as the TBTDECIMIQ1 and DUMMY11)
* Size: 2 DDR3 regions */
#define DDR3_TBTPHA1_SAMPLE_SIZE TBTPHA0_SAMPLE_SIZE
#define DDR3_TBTPHA1_SAMPLE_SIZE TBTPHA_SAMPLE_SIZE
#define DDR3_TBTPHA1_MEM_SIZE 2
#define DDR3_TBTPHA1_MEM_BOOL DDR3_MEM_BOOL(DDR3_TBTPHA1_MEM_SIZE)
#define DDR3_TBTPHA1_START_ADDR (DDR3_MIXIQ341_END_ADDR + DDR3_MIXIQ341_MEM_BOOL*DDR3_MIXIQ341_SAMPLE_SIZE)
#define DDR3_TBTPHA1_START_ADDR (DDR3_DUMMY01_END_ADDR + DDR3_DUMMY01_MEM_BOOL*DDR3_DUMMY01_SAMPLE_SIZE)
#define DDR3_TBTPHA1_END_ADDR (DDR3_TBTPHA1_START_ADDR + DDR3_TBTPHA1_MEM_SIZE*MEM_REGION_SIZE - DDR3_TBTPHA1_MEM_BOOL*DDR3_TBTPHA1_SAMPLE_SIZE)
#define DDR3_TBTPHA1_MAX_SAMPLES ((DDR3_TBTPHA1_END_ADDR-DDR3_TBTPHA1_START_ADDR) / DDR3_TBTPHA1_SAMPLE_SIZE)
/* TBT 1 POS
* Size: 1 DDR3 regions */
#define DDR3_TBTPOS1_SAMPLE_SIZE TBTPOS0_SAMPLE_SIZE
#define DDR3_TBTPOS1_SAMPLE_SIZE TBTPOS_SAMPLE_SIZE
#define DDR3_TBTPOS1_MEM_SIZE 2
#define DDR3_TBTPOS1_MEM_BOOL DDR3_MEM_BOOL(DDR3_TBTPOS1_MEM_SIZE)
#define DDR3_TBTPOS1_START_ADDR (DDR3_MIXIQ341_END_ADDR + DDR3_MIXIQ341_MEM_BOOL*DDR3_MIXIQ341_SAMPLE_SIZE)
#define DDR3_TBTPOS1_START_ADDR (DDR3_DUMMY01_END_ADDR + DDR3_DUMMY01_MEM_BOOL*DDR3_DUMMY01_SAMPLE_SIZE)
#define DDR3_TBTPOS1_END_ADDR (DDR3_TBTPOS1_START_ADDR + DDR3_TBTPOS1_MEM_SIZE*MEM_REGION_SIZE - DDR3_TBTPOS1_MEM_BOOL*DDR3_TBTPOS1_SAMPLE_SIZE)
#define DDR3_TBTPOS1_MAX_SAMPLES ((DDR3_TBTPOS1_END_ADDR-DDR3_TBTPOS1_START_ADDR) / DDR3_TBTPOS1_SAMPLE_SIZE)
/* FOFBDECIM I/Q 1/2 (shares the same memory space as the FOFBDECIMIQ341 and FOFBAMP1)
/* FOFBDECIM I/Q 1/2 (shares the same memory space as the DUMMY21 and FOFBAMP1)
* Size: 1 DDR3 regions */
#define DDR3_FOFBDECIMIQ121_SAMPLE_SIZE FOFBDECIMIQ120_SAMPLE_SIZE
#define DDR3_FOFBDECIMIQ121_MEM_SIZE 2
#define DDR3_FOFBDECIMIQ1_SAMPLE_SIZE FOFBDECIMIQ_SAMPLE_SIZE
#define DDR3_FOFBDECIMIQ1_MEM_SIZE 2
#define DDR3_FOFBDECIMIQ121_MEM_BOOL DDR3_MEM_BOOL(DDR3_FOFBDECIMIQ121_MEM_SIZE)
#define DDR3_FOFBDECIMIQ121_START_ADDR (DDR3_TBTPOS1_END_ADDR + DDR3_TBTPOS1_MEM_BOOL*DDR3_TBTPOS1_SAMPLE_SIZE)
#define DDR3_FOFBDECIMIQ121_END_ADDR (DDR3_FOFBDECIMIQ121_START_ADDR + DDR3_FOFBDECIMIQ121_MEM_SIZE*MEM_REGION_SIZE - DDR3_FOFBDECIMIQ121_MEM_BOOL*DDR3_FOFBDECIMIQ121_SAMPLE_SIZE)
#define DDR3_FOFBDECIMIQ121_MAX_SAMPLES ((DDR3_FOFBDECIMIQ121_END_ADDR-DDR3_FOFBDECIMIQ121_START_ADDR) / DDR3_FOFBDECIMIQ121_SAMPLE_SIZE)
#define DDR3_FOFBDECIMIQ1_MEM_BOOL DDR3_MEM_BOOL(DDR3_FOFBDECIMIQ1_MEM_SIZE)
#define DDR3_FOFBDECIMIQ1_START_ADDR (DDR3_TBTPOS1_END_ADDR + DDR3_TBTPOS1_MEM_BOOL*DDR3_TBTPOS1_SAMPLE_SIZE)
#define DDR3_FOFBDECIMIQ1_END_ADDR (DDR3_FOFBDECIMIQ1_START_ADDR + DDR3_FOFBDECIMIQ1_MEM_SIZE*MEM_REGION_SIZE - DDR3_FOFBDECIMIQ1_MEM_BOOL*DDR3_FOFBDECIMIQ1_SAMPLE_SIZE)
#define DDR3_FOFBDECIMIQ1_MAX_SAMPLES ((DDR3_FOFBDECIMIQ1_END_ADDR-DDR3_FOFBDECIMIQ1_START_ADDR) / DDR3_FOFBDECIMIQ1_SAMPLE_SIZE)
/* FOFBDECIM I/Q 3/4 (shares the same memory space as the FOFBDECIMIQ121 and FOFBAMP1)
/* FOFBDECIM I/Q 3/4 (shares the same memory space as the FOFBDECIMIQ1 and FOFBAMP1)
* Size: 1 DDR3 regions */
#define DDR3_FOFBDECIMIQ341_SAMPLE_SIZE FOFBDECIMIQ340_SAMPLE_SIZE
#define DDR3_FOFBDECIMIQ341_MEM_SIZE 2
#define DDR3_DUMMY21_SAMPLE_SIZE FOFBDECIMIQ_SAMPLE_SIZE
#define DDR3_DUMMY21_MEM_SIZE 2
#define DDR3_FOFBDECIMIQ341_MEM_BOOL DDR3_MEM_BOOL(DDR3_FOFBDECIMIQ341_MEM_SIZE)
#define DDR3_FOFBDECIMIQ341_START_ADDR (DDR3_TBTPOS1_END_ADDR + DDR3_TBTPOS1_MEM_BOOL*DDR3_TBTPOS1_SAMPLE_SIZE)
#define DDR3_FOFBDECIMIQ341_END_ADDR (DDR3_FOFBDECIMIQ341_START_ADDR + DDR3_FOFBDECIMIQ341_MEM_SIZE*MEM_REGION_SIZE - DDR3_FOFBDECIMIQ341_MEM_BOOL*DDR3_FOFBDECIMIQ341_SAMPLE_SIZE)
#define DDR3_FOFBDECIMIQ341_MAX_SAMPLES ((DDR3_FOFBDECIMIQ341_END_ADDR-DDR3_FOFBDECIMIQ341_START_ADDR) / DDR3_FOFBDECIMIQ341_SAMPLE_SIZE)
#define DDR3_DUMMY21_MEM_BOOL DDR3_MEM_BOOL(DDR3_DUMMY21_MEM_SIZE)
#define DDR3_DUMMY21_START_ADDR (DDR3_TBTPOS1_END_ADDR + DDR3_TBTPOS1_MEM_BOOL*DDR3_TBTPOS1_SAMPLE_SIZE)
#define DDR3_DUMMY21_END_ADDR (DDR3_DUMMY21_START_ADDR + DDR3_DUMMY21_MEM_SIZE*MEM_REGION_SIZE - DDR3_DUMMY21_MEM_BOOL*DDR3_DUMMY21_SAMPLE_SIZE)
#define DDR3_DUMMY21_MAX_SAMPLES ((DDR3_DUMMY21_END_ADDR-DDR3_DUMMY21_START_ADDR) / DDR3_DUMMY21_SAMPLE_SIZE)
/* FOFB 1 AMP
* Size: 2 DDR3 regions */
#define DDR3_FOFBAMP1_SAMPLE_SIZE FOFBAMP0_SAMPLE_SIZE
#define DDR3_FOFBAMP1_SAMPLE_SIZE FOFBAMP_SAMPLE_SIZE
#define DDR3_FOFBAMP1_MEM_SIZE 2
#define DDR3_FOFBAMP1_MEM_BOOL DDR3_MEM_BOOL(DDR3_FOFBAMP1_MEM_SIZE)
......@@ -324,9 +324,9 @@
#define DDR3_FOFBAMP1_END_ADDR (DDR3_FOFBAMP1_START_ADDR + DDR3_FOFBAMP1_MEM_SIZE*MEM_REGION_SIZE - DDR3_FOFBAMP1_MEM_BOOL*DDR3_FOFBAMP1_SAMPLE_SIZE)
#define DDR3_FOFBAMP1_MAX_SAMPLES ((DDR3_FOFBAMP1_END_ADDR-DDR3_FOFBAMP1_START_ADDR) / DDR3_FOFBAMP1_SAMPLE_SIZE)
/* FOFB 1 PHA (shares the same memory space as the FOFBDECIMIQ121 and FOFBDECIMIQ341)
/* FOFB 1 PHA (shares the same memory space as the FOFBDECIMIQ1 and DUMMY21)
* Size: 2 DDR3 regions */
#define DDR3_FOFBPHA1_SAMPLE_SIZE FOFBPHA0_SAMPLE_SIZE
#define DDR3_FOFBPHA1_SAMPLE_SIZE FOFBPHA_SAMPLE_SIZE
#define DDR3_FOFBPHA1_MEM_SIZE 2
#define DDR3_FOFBPHA1_MEM_BOOL DDR3_MEM_BOOL(DDR3_FOFBPHA1_MEM_SIZE)
......@@ -336,7 +336,7 @@
/* FOFB 1 POS
* Size: 1 DDR3 regions */
#define DDR3_FOFBPOS1_SAMPLE_SIZE FOFBPOS0_SAMPLE_SIZE
#define DDR3_FOFBPOS1_SAMPLE_SIZE FOFBPOS_SAMPLE_SIZE
#define DDR3_FOFBPOS1_MEM_SIZE 2
#define DDR3_FOFBPOS1_MEM_BOOL DDR3_MEM_BOOL(DDR3_FOFBPOS1_MEM_SIZE)
......@@ -346,7 +346,7 @@
/* MONIT 1 AMP
* Size: 1 DDR3 regions */
#define DDR3_MONITAMP1_SAMPLE_SIZE MONITAMP0_SAMPLE_SIZE
#define DDR3_MONITAMP1_SAMPLE_SIZE MONITAMP_SAMPLE_SIZE
#define DDR3_MONITAMP1_MEM_SIZE 0
#define DDR3_MONITAMP1_MEM_BOOL DDR3_MEM_BOOL(DDR3_MONITAMP1_MEM_SIZE)
......@@ -356,7 +356,7 @@
/* MONIT 1 POS
* Size: 1 DDR3 regions */
#define DDR3_MONITPOS1_SAMPLE_SIZE MONITPOS0_SAMPLE_SIZE
#define DDR3_MONITPOS1_SAMPLE_SIZE MONITPOS_SAMPLE_SIZE
#define DDR3_MONITPOS1_MEM_SIZE 0
#define DDR3_MONITPOS1_MEM_BOOL DDR3_MEM_BOOL(DDR3_MONITPOS1_MEM_SIZE)
......@@ -366,7 +366,7 @@
/* MONIT1 1 POS
* Size: 1 DDR3 regions */
#define DDR3_MONIT1POS1_SAMPLE_SIZE MONIT1POS0_SAMPLE_SIZE
#define DDR3_MONIT1POS1_SAMPLE_SIZE MONIT1POS_SAMPLE_SIZE
#define DDR3_MONIT1POS1_MEM_SIZE 0
#define DDR3_MONIT1POS1_MEM_BOOL DDR3_MEM_BOOL(DDR3_MONIT1POS1_MEM_SIZE)
......@@ -376,7 +376,7 @@
/* End 1 Dummy region
* Size: 0 DDR3 regions */
#define DDR3_DUMMY_END1_SAMPLE_SIZE MONIT1POS0_SAMPLE_SIZE
#define DDR3_DUMMY_END1_SAMPLE_SIZE MONIT1POS_SAMPLE_SIZE
#define DDR3_DUMMY_END1_MEM_SIZE 0
#define DDR3_DUMMY_END1_MEM_BOOL DDR3_MEM_BOOL(DDR3_DUMMY_END1_MEM_SIZE)
......
src/boards/afcv3/ddr3_map.c
View file @ be7dccd5
......@@ -15,119 +15,119 @@ const acq_buf_t __acq_buf[NUM_ACQ_CORE_SMIOS][END_CHAN_ID] = {
/*** Acquisition Core 0 Channel Parameters ***/
{
{
.id = ADC0_CHAN_ID,
.id = ADC_CHAN_ID,
.start_addr = DDR3_ADC0_START_ADDR,
.end_addr = DDR3_ADC0_END_ADDR,
.max_samples = DDR3_ADC0_MAX_SAMPLES,
.sample_size = DDR3_ADC0_SAMPLE_SIZE
},
{
.id = ADCSWAP0_CHAN_ID,
.id = ADCSWAP_CHAN_ID,
.start_addr = DDR3_ADCSWAP0_START_ADDR,
.end_addr = DDR3_ADCSWAP0_END_ADDR,
.max_samples = DDR3_ADCSWAP0_MAX_SAMPLES,
.sample_size = DDR3_ADCSWAP0_SAMPLE_SIZE
},
{
.id = MIXIQ120_CHAN_ID,
.start_addr = DDR3_MIXIQ120_START_ADDR,
.end_addr = DDR3_MIXIQ120_END_ADDR,
.max_samples = DDR3_MIXIQ120_MAX_SAMPLES,
.sample_size = DDR3_MIXIQ120_SAMPLE_SIZE
.id = MIXIQ_CHAN_ID,
.start_addr = DDR3_MIXIQ0_START_ADDR,
.end_addr = DDR3_MIXIQ0_END_ADDR,
.max_samples = DDR3_MIXIQ0_MAX_SAMPLES,
.sample_size = DDR3_MIXIQ0_SAMPLE_SIZE
},
{
.id = MIXIQ340_CHAN_ID,
.start_addr = DDR3_MIXIQ340_START_ADDR,
.end_addr = DDR3_MIXIQ340_END_ADDR,
.max_samples = DDR3_MIXIQ340_MAX_SAMPLES,
.sample_size = DDR3_MIXIQ340_SAMPLE_SIZE
.id = DUMMY0_CHAN_ID,
.start_addr = DDR3_DUMMY00_START_ADDR,
.end_addr = DDR3_DUMMY00_END_ADDR,
.max_samples = DDR3_DUMMY00_MAX_SAMPLES,
.sample_size = DDR3_DUMMY00_SAMPLE_SIZE
},
{
.id = TBTDECIMIQ120_CHAN_ID,
.start_addr = DDR3_TBTDECIMIQ120_START_ADDR,
.end_addr = DDR3_TBTDECIMIQ120_END_ADDR,
.max_samples = DDR3_TBTDECIMIQ120_MAX_SAMPLES,
.sample_size = DDR3_TBTDECIMIQ120_SAMPLE_SIZE
.id = TBTDECIMIQ_CHAN_ID,
.start_addr = DDR3_TBTDECIMIQ0_START_ADDR,
.end_addr = DDR3_TBTDECIMIQ0_END_ADDR,
.max_samples = DDR3_TBTDECIMIQ0_MAX_SAMPLES,
.sample_size = DDR3_TBTDECIMIQ0_SAMPLE_SIZE
},
{
.id = TBTDECIMIQ340_CHAN_ID,
.start_addr = DDR3_TBTDECIMIQ340_START_ADDR,
.end_addr = DDR3_TBTDECIMIQ340_END_ADDR,
.max_samples = DDR3_TBTDECIMIQ340_MAX_SAMPLES,
.sample_size = DDR3_TBTDECIMIQ340_SAMPLE_SIZE
.id = DUMMY1_CHAN_ID,
.start_addr = DDR3_DUMMY10_START_ADDR,
.end_addr = DDR3_DUMMY10_END_ADDR,
.max_samples = DDR3_DUMMY10_MAX_SAMPLES,
.sample_size = DDR3_DUMMY10_SAMPLE_SIZE
},
{
.id = TBTAMP0_CHAN_ID,
.id = TBTAMP_CHAN_ID,
.start_addr = DDR3_TBTAMP0_START_ADDR,
.end_addr = DDR3_TBTAMP0_END_ADDR,
.max_samples = DDR3_TBTAMP0_MAX_SAMPLES,
.sample_size = DDR3_TBTAMP0_SAMPLE_SIZE
},
{
.id = TBTPHA0_CHAN_ID,
.id = TBTPHA_CHAN_ID,
.start_addr = DDR3_TBTPHA0_START_ADDR,
.end_addr = DDR3_TBTPHA0_END_ADDR,
.max_samples = DDR3_TBTPHA0_MAX_SAMPLES,
.sample_size = DDR3_TBTPHA0_SAMPLE_SIZE
},
{
.id = TBTPOS0_CHAN_ID,
.id = TBTPOS_CHAN_ID,
.start_addr = DDR3_TBTPOS0_START_ADDR,
.end_addr = DDR3_TBTPOS0_END_ADDR,
.max_samples = DDR3_TBTPOS0_MAX_SAMPLES,
.sample_size = DDR3_TBTPOS0_SAMPLE_SIZE
},
{
.id = FOFBDECIMIQ120_CHAN_ID,
.start_addr = DDR3_FOFBDECIMIQ120_START_ADDR,
.end_addr = DDR3_FOFBDECIMIQ120_END_ADDR,
.max_samples = DDR3_FOFBDECIMIQ120_MAX_SAMPLES,
.sample_size = DDR3_FOFBDECIMIQ120_SAMPLE_SIZE
.id = FOFBDECIMIQ_CHAN_ID,
.start_addr = DDR3_FOFBDECIMIQ0_START_ADDR,
.end_addr = DDR3_FOFBDECIMIQ0_END_ADDR,
.max_samples = DDR3_FOFBDECIMIQ0_MAX_SAMPLES,
.sample_size = DDR3_FOFBDECIMIQ0_SAMPLE_SIZE
},
{
.id = FOFBDECIMIQ340_CHAN_ID,
.start_addr = DDR3_FOFBDECIMIQ340_START_ADDR,
.end_addr = DDR3_FOFBDECIMIQ340_END_ADDR,
.max_samples = DDR3_FOFBDECIMIQ340_MAX_SAMPLES,
.sample_size = DDR3_FOFBDECIMIQ340_SAMPLE_SIZE
.id = DUMMY2_CHAN_ID,
.start_addr = DDR3_DUMMY20_START_ADDR,
.end_addr = DDR3_DUMMY20_END_ADDR,
.max_samples = DDR3_DUMMY20_MAX_SAMPLES,
.sample_size = DDR3_DUMMY20_SAMPLE_SIZE
},
{
.id = FOFBAMP0_CHAN_ID,
.id = FOFBAMP_CHAN_ID,
.start_addr = DDR3_FOFBAMP0_START_ADDR,
.end_addr = DDR3_FOFBAMP0_END_ADDR,
.max_samples = DDR3_FOFBAMP0_MAX_SAMPLES,
.sample_size = DDR3_FOFBAMP0_SAMPLE_SIZE
},
{
.id = FOFBPHA0_CHAN_ID,
.id = FOFBPHA_CHAN_ID,
.start_addr = DDR3_FOFBPHA0_START_ADDR,
.end_addr = DDR3_FOFBPHA0_END_ADDR,
.max_samples = DDR3_FOFBPHA0_MAX_SAMPLES,
.sample_size = DDR3_FOFBPHA0_SAMPLE_SIZE
},
{
.id = FOFBPOS0_CHAN_ID,
.id = FOFBPOS_CHAN_ID,
.start_addr = DDR3_FOFBPOS0_START_ADDR,
.end_addr = DDR3_FOFBPOS0_END_ADDR,
.max_samples = DDR3_FOFBPOS0_MAX_SAMPLES,
.sample_size = DDR3_FOFBPOS0_SAMPLE_SIZE
},
{
.id = MONITAMP0_CHAN_ID,
.id = MONITAMP_CHAN_ID,
.start_addr = DDR3_MONITAMP0_START_ADDR,
.end_addr = DDR3_MONITAMP0_END_ADDR,
.max_samples = DDR3_MONITAMP0_MAX_SAMPLES,
.sample_size = DDR3_MONITAMP0_SAMPLE_SIZE
},
{
.id = MONITPOS0_CHAN_ID,
.id = MONITPOS_CHAN_ID,
.start_addr = DDR3_MONITPOS0_START_ADDR,
.end_addr = DDR3_MONITPOS0_END_ADDR,
.max_samples = DDR3_MONITPOS0_MAX_SAMPLES,
.sample_size = DDR3_MONITPOS0_SAMPLE_SIZE
},
{
.id = MONIT1POS0_CHAN_ID,
.id = MONIT1POS_CHAN_ID,
.start_addr = DDR3_MONIT1POS0_START_ADDR,
.end_addr = DDR3_MONIT1POS0_END_ADDR,
.max_samples = DDR3_MONIT1POS0_MAX_SAMPLES,
......@@ -137,123 +137,123 @@ const acq_buf_t __acq_buf[NUM_ACQ_CORE_SMIOS][END_CHAN_ID] = {
/*** Acquisition Core 1 Channel Parameters ***/
{
{
.id = ADC0_CHAN_ID,
.id = ADC_CHAN_ID,
.start_addr = DDR3_ADC1_START_ADDR,
.end_addr = DDR3_ADC1_END_ADDR,
.max_samples = DDR3_ADC1_MAX_SAMPLES,
.sample_size = DDR3_ADC0_SAMPLE_SIZE
.sample_size = DDR3_ADC1_SAMPLE_SIZE
},
{
.id = ADCSWAP0_CHAN_ID,
.id = ADCSWAP_CHAN_ID,
.start_addr = DDR3_ADCSWAP1_START_ADDR,
.end_addr = DDR3_ADCSWAP1_END_ADDR,
.max_samples = DDR3_ADCSWAP1_MAX_SAMPLES,
.sample_size = DDR3_ADCSWAP0_SAMPLE_SIZE
.sample_size = DDR3_ADCSWAP1_SAMPLE_SIZE
},
{
.id = MIXIQ120_CHAN_ID,
.start_addr = DDR3_MIXIQ121_START_ADDR,
.end_addr = DDR3_MIXIQ121_END_ADDR,
.max_samples = DDR3_MIXIQ121_MAX_SAMPLES,
.sample_size = DDR3_MIXIQ120_SAMPLE_SIZE
.id = MIXIQ_CHAN_ID,
.start_addr = DDR3_MIXIQ1_START_ADDR,
.end_addr = DDR3_MIXIQ1_END_ADDR,
.max_samples = DDR3_MIXIQ1_MAX_SAMPLES,
.sample_size = DDR3_MIXIQ1_SAMPLE_SIZE
},
{
.id = MIXIQ340_CHAN_ID,
.start_addr = DDR3_MIXIQ341_START_ADDR,
.end_addr = DDR3_MIXIQ341_END_ADDR,
.max_samples = DDR3_MIXIQ341_MAX_SAMPLES,
.sample_size = DDR3_MIXIQ340_SAMPLE_SIZE
.id = DUMMY0_CHAN_ID,
.start_addr = DDR3_DUMMY01_START_ADDR,
.end_addr = DDR3_DUMMY01_END_ADDR,
.max_samples = DDR3_DUMMY01_MAX_SAMPLES,
.sample_size = DDR3_DUMMY01_SAMPLE_SIZE
},
{
.id = TBTDECIMIQ120_CHAN_ID,
.start_addr = DDR3_TBTDECIMIQ121_START_ADDR,
.end_addr = DDR3_TBTDECIMIQ121_END_ADDR,
.max_samples = DDR3_TBTDECIMIQ121_MAX_SAMPLES,
.sample_size = DDR3_TBTDECIMIQ120_SAMPLE_SIZE
.id = TBTDECIMIQ_CHAN_ID,
.start_addr = DDR3_TBTDECIMIQ1_START_ADDR,
.end_addr = DDR3_TBTDECIMIQ1_END_ADDR,
.max_samples = DDR3_TBTDECIMIQ1_MAX_SAMPLES,
.sample_size = DDR3_TBTDECIMIQ1_SAMPLE_SIZE
},
{
.id = TBTDECIMIQ340_CHAN_ID,
.start_addr = DDR3_TBTDECIMIQ341_START_ADDR,
.end_addr = DDR3_TBTDECIMIQ341_END_ADDR,
.max_samples = DDR3_TBTDECIMIQ341_MAX_SAMPLES,
.sample_size = DDR3_TBTDECIMIQ340_SAMPLE_SIZE
.id = DUMMY1_CHAN_ID,
.start_addr = DDR3_DUMMY11_START_ADDR,
.end_addr = DDR3_DUMMY11_END_ADDR,
.max_samples = DDR3_DUMMY11_MAX_SAMPLES,
.sample_size = DDR3_DUMMY11_SAMPLE_SIZE
},
{
.id = TBTAMP0_CHAN_ID,
.id = TBTAMP_CHAN_ID,
.start_addr = DDR3_TBTAMP1_START_ADDR,
.end_addr = DDR3_TBTAMP1_END_ADDR,
.max_samples = DDR3_TBTAMP1_MAX_SAMPLES,
.sample_size = DDR3_TBTAMP0_SAMPLE_SIZE
.sample_size = DDR3_TBTAMP1_SAMPLE_SIZE
},
{
.id = TBTPHA0_CHAN_ID,
.id = TBTPHA_CHAN_ID,
.start_addr = DDR3_TBTPHA1_START_ADDR,
.end_addr = DDR3_TBTPHA1_END_ADDR,
.max_samples = DDR3_TBTPHA1_MAX_SAMPLES,
.sample_size = DDR3_TBTPHA0_SAMPLE_SIZE
.sample_size = DDR3_TBTPHA1_SAMPLE_SIZE
},
{
.id = TBTPOS0_CHAN_ID,
.id = TBTPOS_CHAN_ID,
.start_addr = DDR3_TBTPOS1_START_ADDR,
.end_addr = DDR3_TBTPOS1_END_ADDR,
.max_samples = DDR3_TBTPOS1_MAX_SAMPLES,
.sample_size = DDR3_TBTPOS0_SAMPLE_SIZE
.sample_size = DDR3_TBTPOS1_SAMPLE_SIZE
},
{
.id = FOFBDECIMIQ120_CHAN_ID,
.start_addr = DDR3_FOFBDECIMIQ121_START_ADDR,
.end_addr = DDR3_FOFBDECIMIQ121_END_ADDR,
.max_samples = DDR3_FOFBDECIMIQ121_MAX_SAMPLES,
.sample_size = DDR3_FOFBDECIMIQ120_SAMPLE_SIZE
.id = FOFBDECIMIQ_CHAN_ID,
.start_addr = DDR3_FOFBDECIMIQ1_START_ADDR,
.end_addr = DDR3_FOFBDECIMIQ1_END_ADDR,
.max_samples = DDR3_FOFBDECIMIQ1_MAX_SAMPLES,
.sample_size = DDR3_FOFBDECIMIQ1_SAMPLE_SIZE
},
{
.id = FOFBDECIMIQ340_CHAN_ID,
.start_addr = DDR3_FOFBDECIMIQ341_START_ADDR,
.end_addr = DDR3_FOFBDECIMIQ341_END_ADDR,
.max_samples = DDR3_FOFBDECIMIQ341_MAX_SAMPLES,
.sample_size = DDR3_FOFBDECIMIQ340_SAMPLE_SIZE
.id = DUMMY2_CHAN_ID,
.start_addr = DDR3_DUMMY21_START_ADDR,
.end_addr = DDR3_DUMMY21_END_ADDR,
.max_samples = DDR3_DUMMY21_MAX_SAMPLES,
.sample_size = DDR3_DUMMY21_SAMPLE_SIZE
},
{
.id = FOFBAMP0_CHAN_ID,
.id = FOFBAMP_CHAN_ID,
.start_addr = DDR3_FOFBAMP1_START_ADDR,
.end_addr = DDR3_FOFBAMP1_END_ADDR,
.max_samples = DDR3_FOFBAMP1_MAX_SAMPLES,
.sample_size = DDR3_FOFBAMP0_SAMPLE_SIZE
.sample_size = DDR3_FOFBAMP1_SAMPLE_SIZE
},
{
.id = FOFBPHA0_CHAN_ID,
.id = FOFBPHA_CHAN_ID,
.start_addr = DDR3_FOFBPHA1_START_ADDR,
.end_addr = DDR3_FOFBPHA1_END_ADDR,
.max_samples = DDR3_FOFBPHA1_MAX_SAMPLES,
.sample_size = DDR3_FOFBPHA0_SAMPLE_SIZE
.sample_size = DDR3_FOFBPHA1_SAMPLE_SIZE
},
{
.id = FOFBPOS0_CHAN_ID,
.id = FOFBPOS_CHAN_ID,
.start_addr = DDR3_FOFBPOS1_START_ADDR,
.end_addr = DDR3_FOFBPOS1_END_ADDR,
.max_samples = DDR3_FOFBPOS1_MAX_SAMPLES,
.sample_size = DDR3_FOFBPOS0_SAMPLE_SIZE
.sample_size = DDR3_FOFBPOS1_SAMPLE_SIZE
},
{
.id = MONITAMP0_CHAN_ID,
.id = MONITAMP_CHAN_ID,
.start_addr = DDR3_MONITAMP1_START_ADDR,
.end_addr = DDR3_MONITAMP1_END_ADDR,
.max_samples = DDR3_MONITAMP1_MAX_SAMPLES,
.sample_size = DDR3_MONITAMP0_SAMPLE_SIZE
.sample_size = DDR3_MONITAMP1_SAMPLE_SIZE
},
{
.id = MONITPOS0_CHAN_ID,
.id = MONITPOS_CHAN_ID,
.start_addr = DDR3_MONITPOS1_START_ADDR,
.end_addr = DDR3_MONITPOS1_END_ADDR,
.max_samples = DDR3_MONITPOS1_MAX_SAMPLES,
.sample_size = DDR3_MONITPOS0_SAMPLE_SIZE
.sample_size = DDR3_MONITPOS1_SAMPLE_SIZE
},
{
.id = MONIT1POS0_CHAN_ID,
.id = MONIT1POS_CHAN_ID,
.start_addr = DDR3_MONIT1POS1_START_ADDR,
.end_addr = DDR3_MONIT1POS1_END_ADDR,
.max_samples = DDR3_MONIT1POS1_MAX_SAMPLES,
.sample_size = DDR3_MONIT1POS0_SAMPLE_SIZE
.sample_size = DDR3_MONIT1POS1_SAMPLE_SIZE
},
}
};
src/boards/afcv3_1/ddr3_map.c
View file @ be7dccd5
......@@ -15,119 +15,119 @@ const acq_buf_t __acq_buf[NUM_ACQ_CORE_SMIOS][END_CHAN_ID] = {
/*** Acquisition Core 0 Channel Parameters ***/
{
{
.id = ADC0_CHAN_ID,
.id = ADC_CHAN_ID,
.start_addr = DDR3_ADC0_START_ADDR,
.end_addr = DDR3_ADC0_END_ADDR,
.max_samples = DDR3_ADC0_MAX_SAMPLES,
.sample_size = DDR3_ADC0_SAMPLE_SIZE
},
{
.id = ADCSWAP0_CHAN_ID,
.id = ADCSWAP_CHAN_ID,
.start_addr = DDR3_ADCSWAP0_START_ADDR,
.end_addr = DDR3_ADCSWAP0_END_ADDR,
.max_samples = DDR3_ADCSWAP0_MAX_SAMPLES,
.sample_size = DDR3_ADCSWAP0_SAMPLE_SIZE
},
{
.id = MIXIQ120_CHAN_ID,
.start_addr = DDR3_MIXIQ120_START_ADDR,
.end_addr = DDR3_MIXIQ120_END_ADDR,
.max_samples = DDR3_MIXIQ120_MAX_SAMPLES,
.sample_size = DDR3_MIXIQ120_SAMPLE_SIZE
.id = MIXIQ_CHAN_ID,
.start_addr = DDR3_MIXIQ0_START_ADDR,
.end_addr = DDR3_MIXIQ0_END_ADDR,
.max_samples = DDR3_MIXIQ0_MAX_SAMPLES,
.sample_size = DDR3_MIXIQ0_SAMPLE_SIZE
},
{
.id = MIXIQ340_CHAN_ID,
.start_addr = DDR3_MIXIQ340_START_ADDR,
.end_addr = DDR3_MIXIQ340_END_ADDR,
.max_samples = DDR3_MIXIQ340_MAX_SAMPLES,
.sample_size = DDR3_MIXIQ340_SAMPLE_SIZE
.id = DUMMY0_CHAN_ID,
.start_addr = DDR3_DUMMY00_START_ADDR,
.end_addr = DDR3_DUMMY00_END_ADDR,
.max_samples = DDR3_DUMMY00_MAX_SAMPLES,
.sample_size = DDR3_DUMMY00_SAMPLE_SIZE
},
{
.id = TBTDECIMIQ120_CHAN_ID,
.start_addr = DDR3_TBTDECIMIQ120_START_ADDR,
.end_addr = DDR3_TBTDECIMIQ120_END_ADDR,
.max_samples = DDR3_TBTDECIMIQ120_MAX_SAMPLES,
.sample_size = DDR3_TBTDECIMIQ120_SAMPLE_SIZE
.id = TBTDECIMIQ_CHAN_ID,
.start_addr = DDR3_TBTDECIMIQ0_START_ADDR,
.end_addr = DDR3_TBTDECIMIQ0_END_ADDR,
.max_samples = DDR3_TBTDECIMIQ0_MAX_SAMPLES,
.sample_size = DDR3_TBTDECIMIQ0_SAMPLE_SIZE
},
{
.id = TBTDECIMIQ340_CHAN_ID,
.start_addr = DDR3_TBTDECIMIQ340_START_ADDR,
.end_addr = DDR3_TBTDECIMIQ340_END_ADDR,
.max_samples = DDR3_TBTDECIMIQ340_MAX_SAMPLES,
.sample_size = DDR3_TBTDECIMIQ340_SAMPLE_SIZE
.id = DUMMY1_CHAN_ID,
.start_addr = DDR3_DUMMY10_START_ADDR,
.end_addr = DDR3_DUMMY10_END_ADDR,
.max_samples = DDR3_DUMMY10_MAX_SAMPLES,
.sample_size = DDR3_DUMMY10_SAMPLE_SIZE
},
{
.id = TBTAMP0_CHAN_ID,
.id = TBTAMP_CHAN_ID,
.start_addr = DDR3_TBTAMP0_START_ADDR,
.end_addr = DDR3_TBTAMP0_END_ADDR,
.max_samples = DDR3_TBTAMP0_MAX_SAMPLES,
.sample_size = DDR3_TBTAMP0_SAMPLE_SIZE
},
{
.id = TBTPHA0_CHAN_ID,
.id = TBTPHA_CHAN_ID,
.start_addr = DDR3_TBTPHA0_START_ADDR,
.end_addr = DDR3_TBTPHA0_END_ADDR,
.max_samples = DDR3_TBTPHA0_MAX_SAMPLES,
.sample_size = DDR3_TBTPHA0_SAMPLE_SIZE
},
{
.id = TBTPOS0_CHAN_ID,
.id = TBTPOS_CHAN_ID,
.start_addr = DDR3_TBTPOS0_START_ADDR,
.end_addr = DDR3_TBTPOS0_END_ADDR,
.max_samples = DDR3_TBTPOS0_MAX_SAMPLES,
.sample_size = DDR3_TBTPOS0_SAMPLE_SIZE
},
{
.id = FOFBDECIMIQ120_CHAN_ID,
.start_addr = DDR3_FOFBDECIMIQ120_START_ADDR,
.end_addr = DDR3_FOFBDECIMIQ120_END_ADDR,
.max_samples = DDR3_FOFBDECIMIQ120_MAX_SAMPLES,
.sample_size = DDR3_FOFBDECIMIQ120_SAMPLE_SIZE
.id = FOFBDECIMIQ_CHAN_ID,
.start_addr = DDR3_FOFBDECIMIQ0_START_ADDR,
.end_addr = DDR3_FOFBDECIMIQ0_END_ADDR,
.max_samples = DDR3_FOFBDECIMIQ0_MAX_SAMPLES,
.sample_size = DDR3_FOFBDECIMIQ0_SAMPLE_SIZE
},
{
.id = FOFBDECIMIQ340_CHAN_ID,
.start_addr = DDR3_FOFBDECIMIQ340_START_ADDR,
.end_addr = DDR3_FOFBDECIMIQ340_END_ADDR,
.max_samples = DDR3_FOFBDECIMIQ340_MAX_SAMPLES,
.sample_size = DDR3_FOFBDECIMIQ340_SAMPLE_SIZE
.id = DUMMY2_CHAN_ID,
.start_addr = DDR3_DUMMY20_START_ADDR,
.end_addr = DDR3_DUMMY20_END_ADDR,
.max_samples = DDR3_DUMMY20_MAX_SAMPLES,
.sample_size = DDR3_DUMMY20_SAMPLE_SIZE
},
{
.id = FOFBAMP0_CHAN_ID,
.id = FOFBAMP_CHAN_ID,
.start_addr = DDR3_FOFBAMP0_START_ADDR,
.end_addr = DDR3_FOFBAMP0_END_ADDR,
.max_samples = DDR3_FOFBAMP0_MAX_SAMPLES,
.sample_size = DDR3_FOFBAMP0_SAMPLE_SIZE
},
{
.id = FOFBPHA0_CHAN_ID,
.id = FOFBPHA_CHAN_ID,
.start_addr = DDR3_FOFBPHA0_START_ADDR,
.end_addr = DDR3_FOFBPHA0_END_ADDR,
.max_samples = DDR3_FOFBPHA0_MAX_SAMPLES,
.sample_size = DDR3_FOFBPHA0_SAMPLE_SIZE
},
{
.id = FOFBPOS0_CHAN_ID,
.id = FOFBPOS_CHAN_ID,
.start_addr = DDR3_FOFBPOS0_START_ADDR,
.end_addr = DDR3_FOFBPOS0_END_ADDR,
.max_samples = DDR3_FOFBPOS0_MAX_SAMPLES,
.sample_size = DDR3_FOFBPOS0_SAMPLE_SIZE
},
{
.id = MONITAMP0_CHAN_ID,
.id = MONITAMP_CHAN_ID,
.start_addr = DDR3_MONITAMP0_START_ADDR,
.end_addr = DDR3_MONITAMP0_END_ADDR,
.max_samples = DDR3_MONITAMP0_MAX_SAMPLES,
.sample_size = DDR3_MONITAMP0_SAMPLE_SIZE
},
{
.id = MONITPOS0_CHAN_ID,
.id = MONITPOS_CHAN_ID,
.start_addr = DDR3_MONITPOS0_START_ADDR,
.end_addr = DDR3_MONITPOS0_END_ADDR,
.max_samples = DDR3_MONITPOS0_MAX_SAMPLES,
.sample_size = DDR3_MONITPOS0_SAMPLE_SIZE
},
{
.id = MONIT1POS0_CHAN_ID,
.id = MONIT1POS_CHAN_ID,
.start_addr = DDR3_MONIT1POS0_START_ADDR,
.end_addr = DDR3_MONIT1POS0_END_ADDR,
.max_samples = DDR3_MONIT1POS0_MAX_SAMPLES,
......@@ -137,123 +137,123 @@ const acq_buf_t __acq_buf[NUM_ACQ_CORE_SMIOS][END_CHAN_ID] = {
/*** Acquisition Core 1 Channel Parameters ***/
{
{
.id = ADC0_CHAN_ID,
.id = ADC_CHAN_ID,
.start_addr = DDR3_ADC1_START_ADDR,
.end_addr = DDR3_ADC1_END_ADDR,
.max_samples = DDR3_ADC1_MAX_SAMPLES,
.sample_size = DDR3_ADC0_SAMPLE_SIZE
.sample_size = DDR3_ADC1_SAMPLE_SIZE
},
{
.id = ADCSWAP0_CHAN_ID,
.id = ADCSWAP_CHAN_ID,
.start_addr = DDR3_ADCSWAP1_START_ADDR,
.end_addr = DDR3_ADCSWAP1_END_ADDR,
.max_samples = DDR3_ADCSWAP1_MAX_SAMPLES,
.sample_size = DDR3_ADCSWAP0_SAMPLE_SIZE
.sample_size = DDR3_ADCSWAP1_SAMPLE_SIZE
},
{
.id = MIXIQ120_CHAN_ID,
.start_addr = DDR3_MIXIQ121_START_ADDR,
.end_addr = DDR3_MIXIQ121_END_ADDR,
.max_samples = DDR3_MIXIQ121_MAX_SAMPLES,
.sample_size = DDR3_MIXIQ120_SAMPLE_SIZE
.id = MIXIQ_CHAN_ID,
.start_addr = DDR3_MIXIQ1_START_ADDR,
.end_addr = DDR3_MIXIQ1_END_ADDR,
.max_samples = DDR3_MIXIQ1_MAX_SAMPLES,
.sample_size = DDR3_MIXIQ1_SAMPLE_SIZE
},
{
.id = MIXIQ340_CHAN_ID,
.start_addr = DDR3_MIXIQ341_START_ADDR,
.end_addr = DDR3_MIXIQ341_END_ADDR,
.max_samples = DDR3_MIXIQ341_MAX_SAMPLES,
.sample_size = DDR3_MIXIQ340_SAMPLE_SIZE
.id = DUMMY0_CHAN_ID,
.start_addr = DDR3_DUMMY01_START_ADDR,
.end_addr = DDR3_DUMMY01_END_ADDR,
.max_samples = DDR3_DUMMY01_MAX_SAMPLES,
.sample_size = DDR3_DUMMY01_SAMPLE_SIZE
},
{
.id = TBTDECIMIQ120_CHAN_ID,
.start_addr = DDR3_TBTDECIMIQ121_START_ADDR,
.end_addr = DDR3_TBTDECIMIQ121_END_ADDR,
.max_samples = DDR3_TBTDECIMIQ121_MAX_SAMPLES,
.sample_size = DDR3_TBTDECIMIQ120_SAMPLE_SIZE
.id = TBTDECIMIQ_CHAN_ID,
.start_addr = DDR3_TBTDECIMIQ1_START_ADDR,
.end_addr = DDR3_TBTDECIMIQ1_END_ADDR,
.max_samples = DDR3_TBTDECIMIQ1_MAX_SAMPLES,
.sample_size = DDR3_TBTDECIMIQ1_SAMPLE_SIZE
},
{
.id = TBTDECIMIQ340_CHAN_ID,
.start_addr = DDR3_TBTDECIMIQ341_START_ADDR,
.end_addr = DDR3_TBTDECIMIQ341_END_ADDR,
.max_samples = DDR3_TBTDECIMIQ341_MAX_SAMPLES,
.sample_size = DDR3_TBTDECIMIQ340_SAMPLE_SIZE
.id = DUMMY1_CHAN_ID,
.start_addr = DDR3_DUMMY11_START_ADDR,
.end_addr = DDR3_DUMMY11_END_ADDR,
.max_samples = DDR3_DUMMY11_MAX_SAMPLES,
.sample_size = DDR3_DUMMY11_SAMPLE_SIZE
},
{
.id = TBTAMP0_CHAN_ID,
.id = TBTAMP_CHAN_ID,
.start_addr = DDR3_TBTAMP1_START_ADDR,
.end_addr = DDR3_TBTAMP1_END_ADDR,
.max_samples = DDR3_TBTAMP1_MAX_SAMPLES,
.sample_size = DDR3_TBTAMP0_SAMPLE_SIZE
.sample_size = DDR3_TBTAMP1_SAMPLE_SIZE
},
{
.id = TBTPHA0_CHAN_ID,
.id = TBTPHA_CHAN_ID,
.start_addr = DDR3_TBTPHA1_START_ADDR,
.end_addr = DDR3_TBTPHA1_END_ADDR,
.max_samples = DDR3_TBTPHA1_MAX_SAMPLES,
.sample_size = DDR3_TBTPHA0_SAMPLE_SIZE
.sample_size = DDR3_TBTPHA1_SAMPLE_SIZE
},
{
.id = TBTPOS0_CHAN_ID,
.id = TBTPOS_CHAN_ID,
.start_addr = DDR3_TBTPOS1_START_ADDR,
.end_addr = DDR3_TBTPOS1_END_ADDR,
.max_samples = DDR3_TBTPOS1_MAX_SAMPLES,
.sample_size = DDR3_TBTPOS0_SAMPLE_SIZE
.sample_size = DDR3_TBTPOS1_SAMPLE_SIZE
},
{
.id = FOFBDECIMIQ120_CHAN_ID,
.start_addr = DDR3_FOFBDECIMIQ121_START_ADDR,
.end_addr = DDR3_FOFBDECIMIQ121_END_ADDR,
.max_samples = DDR3_FOFBDECIMIQ121_MAX_SAMPLES,
.sample_size = DDR3_FOFBDECIMIQ120_SAMPLE_SIZE
.id = FOFBDECIMIQ_CHAN_ID,
.start_addr = DDR3_FOFBDECIMIQ1_START_ADDR,
.end_addr = DDR3_FOFBDECIMIQ1_END_ADDR,
.max_samples = DDR3_FOFBDECIMIQ1_MAX_SAMPLES,
.sample_size = DDR3_FOFBDECIMIQ1_SAMPLE_SIZE
},
{
.id = FOFBDECIMIQ340_CHAN_ID,
.start_addr = DDR3_FOFBDECIMIQ341_START_ADDR,
.end_addr = DDR3_FOFBDECIMIQ341_END_ADDR,
.max_samples = DDR3_FOFBDECIMIQ341_MAX_SAMPLES,
.sample_size = DDR3_FOFBDECIMIQ340_SAMPLE_SIZE
.id = DUMMY2_CHAN_ID,
.start_addr = DDR3_DUMMY21_START_ADDR,
.end_addr = DDR3_DUMMY21_END_ADDR,
.max_samples = DDR3_DUMMY21_MAX_SAMPLES,
.sample_size = DDR3_DUMMY21_SAMPLE_SIZE
},
{
.id = FOFBAMP0_CHAN_ID,
.id = FOFBAMP_CHAN_ID,
.start_addr = DDR3_FOFBAMP1_START_ADDR,
.end_addr = DDR3_FOFBAMP1_END_ADDR,
.max_samples = DDR3_FOFBAMP1_MAX_SAMPLES,
.sample_size = DDR3_FOFBAMP0_SAMPLE_SIZE
.sample_size = DDR3_FOFBAMP1_SAMPLE_SIZE
},
{
.id = FOFBPHA0_CHAN_ID,
.id = FOFBPHA_CHAN_ID,
.start_addr = DDR3_FOFBPHA1_START_ADDR,
.end_addr = DDR3_FOFBPHA1_END_ADDR,
.max_samples = DDR3_FOFBPHA1_MAX_SAMPLES,
.sample_size = DDR3_FOFBPHA0_SAMPLE_SIZE
.sample_size = DDR3_FOFBPHA1_SAMPLE_SIZE
},
{
.id = FOFBPOS0_CHAN_ID,
.id = FOFBPOS_CHAN_ID,
.start_addr = DDR3_FOFBPOS1_START_ADDR,
.end_addr = DDR3_FOFBPOS1_END_ADDR,
.max_samples = DDR3_FOFBPOS1_MAX_SAMPLES,
.sample_size = DDR3_FOFBPOS0_SAMPLE_SIZE
.sample_size = DDR3_FOFBPOS1_SAMPLE_SIZE
},
{
.id = MONITAMP0_CHAN_ID,
.id = MONITAMP_CHAN_ID,
.start_addr = DDR3_MONITAMP1_START_ADDR,
.end_addr = DDR3_MONITAMP1_END_ADDR,
.max_samples = DDR3_MONITAMP1_MAX_SAMPLES,
.sample_size = DDR3_MONITAMP0_SAMPLE_SIZE
.sample_size = DDR3_MONITAMP1_SAMPLE_SIZE
},
{
.id = MONITPOS0_CHAN_ID,
.id = MONITPOS_CHAN_ID,
.start_addr = DDR3_MONITPOS1_START_ADDR,
.end_addr = DDR3_MONITPOS1_END_ADDR,
.max_samples = DDR3_MONITPOS1_MAX_SAMPLES,
.sample_size = DDR3_MONITPOS0_SAMPLE_SIZE
.sample_size = DDR3_MONITPOS1_SAMPLE_SIZE
},
{
.id = MONIT1POS0_CHAN_ID,
.id = MONIT1POS_CHAN_ID,
.start_addr = DDR3_MONIT1POS1_START_ADDR,
.end_addr = DDR3_MONIT1POS1_END_ADDR,
.max_samples = DDR3_MONIT1POS1_MAX_SAMPLES,
.sample_size = DDR3_MONIT1POS0_SAMPLE_SIZE
.sample_size = DDR3_MONIT1POS1_SAMPLE_SIZE
},
}
};
src/libs/libbpmclient/src/bpm_client_core.c
View file @ be7dccd5
......@@ -57,33 +57,33 @@ static bpm_client_err_e _func_polling (bpm_client_t *self, char *name,
/* Acquisition channel definitions for user's application */
#if defined(__BOARD_ML605__)
/* Global structure merging all of the channel's sample sizes */
acq_chan_t acq_chan[END_CHAN_ID] = { [0] = {.chan = ADC0_CHAN_ID, .sample_size = ADC0_SAMPLE_SIZE},
[1] = {.chan = TBTAMP0_CHAN_ID, .sample_size = TBTAMP0_SAMPLE_SIZE},
[2] = {.chan = TBTPOS0_CHAN_ID, .sample_size = TBTPOS0_SAMPLE_SIZE},
[3] = {.chan = FOFBAMP0_CHAN_ID, .sample_size = FOFBAMP0_SAMPLE_SIZE},
[4] = {.chan = FOFBPOS0_CHAN_ID, .sample_size = FOFBPOS0_SAMPLE_SIZE},
[5] = {.chan = MONITAMP0_CHAN_ID, .sample_size = MONITAMP0_SAMPLE_SIZE},
[6] = {.chan = MONITPOS0_CHAN_ID, .sample_size = MONITPOS0_SAMPLE_SIZE},
[7] = {.chan = MONIT1POS0_CHAN_ID, .sample_size = MONIT1POS0_SAMPLE_SIZE}
acq_chan_t acq_chan[END_CHAN_ID] = { [0] = {.chan = ADC_CHAN_ID, .sample_size = ADC_SAMPLE_SIZE},
[1] = {.chan = TBTAMP_CHAN_ID, .sample_size = TBTAMP_SAMPLE_SIZE},
[2] = {.chan = TBTPOS_CHAN_ID, .sample_size = TBTPOS_SAMPLE_SIZE},
[3] = {.chan = FOFBAMP_CHAN_ID, .sample_size = FOFBAMP_SAMPLE_SIZE},
[4] = {.chan = FOFBPOS_CHAN_ID, .sample_size = FOFBPOS_SAMPLE_SIZE},
[5] = {.chan = MONITAMP_CHAN_ID, .sample_size = MONITAMP_SAMPLE_SIZE},
[6] = {.chan = MONITPOS_CHAN_ID, .sample_size = MONITPOS_SAMPLE_SIZE},
[7] = {.chan = MONIT1POS_CHAN_ID, .sample_size = MONIT1POS_SAMPLE_SIZE}
};
#elif defined(__BOARD_AFCV3__)
acq_chan_t acq_chan[END_CHAN_ID] = { [0] = {.chan = ADC0_CHAN_ID, .sample_size = ADC0_SAMPLE_SIZE},
[1] = {.chan = ADCSWAP0_CHAN_ID, .sample_size = ADCSWAP0_SAMPLE_SIZE},
[2] = {.chan = MIXIQ120_CHAN_ID, .sample_size = MIXIQ120_SAMPLE_SIZE},
[3] = {.chan = MIXIQ340_CHAN_ID, .sample_size = MIXIQ340_SAMPLE_SIZE},
[4] = {.chan = TBTDECIMIQ120_CHAN_ID, .sample_size = TBTDECIMIQ120_SAMPLE_SIZE},
[5] = {.chan = TBTDECIMIQ340_CHAN_ID, .sample_size = TBTDECIMIQ340_SAMPLE_SIZE},
[6] = {.chan = TBTAMP0_CHAN_ID, .sample_size = TBTAMP0_SAMPLE_SIZE},
[7] = {.chan = TBTPHA0_CHAN_ID, .sample_size = TBTPHA0_SAMPLE_SIZE},
[8] = {.chan = TBTPOS0_CHAN_ID, .sample_size = TBTPOS0_SAMPLE_SIZE},
[9] = {.chan = FOFBDECIMIQ120_CHAN_ID, .sample_size = FOFBDECIMIQ120_SAMPLE_SIZE},
[10] = {.chan = FOFBDECIMIQ340_CHAN_ID, .sample_size = FOFBDECIMIQ340_SAMPLE_SIZE},
[11] = {.chan = FOFBAMP0_CHAN_ID, .sample_size = FOFBAMP0_SAMPLE_SIZE},
[12] = {.chan = FOFBPHA0_CHAN_ID, .sample_size = FOFBPHA0_SAMPLE_SIZE},
[13] = {.chan = FOFBPOS0_CHAN_ID, .sample_size = FOFBPOS0_SAMPLE_SIZE},
[14] = {.chan = MONITAMP0_CHAN_ID, .sample_size = MONITAMP0_SAMPLE_SIZE},
[15] = {.chan = MONITPOS0_CHAN_ID, .sample_size = MONITPOS0_SAMPLE_SIZE},
[16] = {.chan = MONIT1POS0_CHAN_ID, .sample_size = MONIT1POS0_SAMPLE_SIZE}
acq_chan_t acq_chan[END_CHAN_ID] = { [0] = {.chan = ADC_CHAN_ID, .sample_size = ADC_SAMPLE_SIZE},
[1] = {.chan = ADCSWAP_CHAN_ID, .sample_size = ADCSWAP_SAMPLE_SIZE},
[2] = {.chan = MIXIQ_CHAN_ID, .sample_size = MIXIQ_SAMPLE_SIZE},
[3] = {.chan = DUMMY0_CHAN_ID, .sample_size = DUMMY0_SAMPLE_SIZE},
[4] = {.chan = TBTDECIMIQ_CHAN_ID, .sample_size = TBTDECIMIQ_SAMPLE_SIZE},
[5] = {.chan = DUMMY1_CHAN_ID, .sample_size = DUMMY1_SAMPLE_SIZE},
[6] = {.chan = TBTAMP_CHAN_ID, .sample_size = TBTAMP_SAMPLE_SIZE},
[7] = {.chan = TBTPHA_CHAN_ID, .sample_size = TBTPHA_SAMPLE_SIZE},
[8] = {.chan = TBTPOS_CHAN_ID, .sample_size = TBTPOS_SAMPLE_SIZE},
[9] = {.chan = FOFBDECIMIQ_CHAN_ID, .sample_size = FOFBDECIMIQ_SAMPLE_SIZE},
[10] = {.chan = DUMMY2_CHAN_ID, .sample_size = DUMMY2_SAMPLE_SIZE},
[11] = {.chan = FOFBAMP_CHAN_ID, .sample_size = FOFBAMP_SAMPLE_SIZE},
[12] = {.chan = FOFBPHA_CHAN_ID, .sample_size = FOFBPHA_SAMPLE_SIZE},
[13] = {.chan = FOFBPOS_CHAN_ID, .sample_size = FOFBPOS_SAMPLE_SIZE},
[14] = {.chan = MONITAMP_CHAN_ID, .sample_size = MONITAMP_SAMPLE_SIZE},
[15] = {.chan = MONITPOS_CHAN_ID, .sample_size = MONITPOS_SAMPLE_SIZE},
[16] = {.chan = MONIT1POS_CHAN_ID, .sample_size = MONIT1POS_SAMPLE_SIZE}
};
#else
#error "Unsupported board!"
......
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