Commit fea575db authored by Lucas Russo's avatar Lucas Russo

sm_io/*/trigger_iface/*: add trigger interface module

parent 5ceb23e1
/*
* Copyright (C) 2016 LNLS (www.lnls.br)
* Author: Lucas Russo <lucas.russo@lnls.br>
*
* Released according to the GNU GPL, version 3 or any later version.
*/
#ifndef _SM_IO_TRIGGER_IFACE_CODES_H_
#define _SM_IO_TRIGGER_IFACE_CODES_H_
/* Messaging OPCODES */
#define TRIGGER_IFACE_OPCODE_TYPE uint32_t
#define TRIGGER_IFACE_OPCODE_SIZE (sizeof (TRIGGER_IFACE_OPCODE_TYPE))
#define TRIGGER_IFACE_OPCODE_DIR 0
#define TRIGGER_IFACE_NAME_DIR "trigger_iface_dir"
#define TRIGGER_IFACE_OPCODE_RCV_COUNT_RST 1
#define TRIGGER_IFACE_NAME_RCV_COUNT_RST "trigger_iface_rcv_count_rst"
#define TRIGGER_IFACE_OPCODE_TRANSM_COUNT_RST 2
#define TRIGGER_IFACE_NAME_TRANSM_COUNT_RST "trigger_iface_transm_count_rst"
#define TRIGGER_IFACE_OPCODE_RCV_LEN 3
#define TRIGGER_IFACE_NAME_RCV_LEN "trigger_iface_rcv_len"
#define TRIGGER_IFACE_OPCODE_TRANSM_LEN 4
#define TRIGGER_IFACE_NAME_TRANSM_LEN "trigger_iface_transm_len"
#define TRIGGER_IFACE_OPCODE_COUNT_RCV 5
#define TRIGGER_IFACE_NAME_COUNT_RCV "trigger_iface_count_rcv"
#define TRIGGER_IFACE_OPCODE_COUNT_TRANSM 6
#define TRIGGER_IFACE_NAME_COUNT_TRANSM "trigger_iface_count_transm"
#define TRIGGER_IFACE_OPCODE_END 7
/* Messaging Reply OPCODES */
#define TRIGGER_IFACE_REPLY_TYPE uint32_t
#define TRIGGER_IFACE_REPLY_SIZE (sizeof (TRIGGER_IFACE_REPLY_TYPE))
#define TRIGGER_IFACE_OK 0 /* Operation was successful */
#define TRIGGER_IFACE_ERR 1 /* Could not set/get value */
#define TRIGGER_IFACE_UNINPL 2 /* Unimplemented function or operation */
#define TRIGGER_IFACE_REPLY_END 3 /* End marker */
#endif
/*
* Copyright (C) 2016 LNLS (www.lnls.br)
* Author: Lucas Russo <lucas.russo@lnls.br>
*
* Released according to the GNU GPL, version 3 or any later version.
*/
#include "bpm_server.h"
/* Private headers */
#include "sm_io_trigger_iface_defaults.h"
#include "sm_io_trigger_iface_core.h"
/* Undef ASSERT_ALLOC to avoid conflicting with other ASSERT_ALLOC */
#ifdef ASSERT_TEST
#undef ASSERT_TEST
#endif
#define ASSERT_TEST(test_boolean, err_str, err_goto_label, /* err_core */ ...) \
ASSERT_HAL_TEST(test_boolean, SM_IO, "[sm_io_trigger_iface_core]", \
err_str, err_goto_label, /* err_core */ __VA_ARGS__)
#ifdef ASSERT_ALLOC
#undef ASSERT_ALLOC
#endif
#define ASSERT_ALLOC(ptr, err_goto_label, /* err_core */ ...) \
ASSERT_HAL_ALLOC(ptr, SM_IO, "[sm_io_trigger_iface_core]", \
smio_err_str(SMIO_ERR_ALLOC), \
err_goto_label, /* err_core */ __VA_ARGS__)
#ifdef CHECK_ERR
#undef CHECK_ERR
#endif
#define CHECK_ERR(err, err_type) \
CHECK_HAL_ERR(err, SM_IO, "[sm_io_trigger_iface_core]", \
smio_err_str (err_type))
/* Creates a new instance of Device Information */
smio_trigger_iface_t * smio_trigger_iface_new (smio_t *parent)
{
(void) parent;
smio_trigger_iface_t *self = (smio_trigger_iface_t *) zmalloc (sizeof *self);
ASSERT_ALLOC(self, err_self_alloc);
return self;
err_self_alloc:
return NULL;
}
/* Destroy an instance of the Device Information */
smio_err_e smio_trigger_iface_destroy (smio_trigger_iface_t **self_p)
{
assert (self_p);
if (*self_p) {
smio_trigger_iface_t *self = *self_p;
free (self);
*self_p = NULL;
}
return SMIO_SUCCESS;
}
/*
* Copyright (C) 2016 LNLS (www.lnls.br)
* Author: Lucas Russo <lucas.russo@lnls.br>
*
* Released according to the GNU GPL, version 3 or any later version.
*/
#ifndef _SM_IO_TRIGGER_IFACE_CORE_H_
#define _SM_IO_TRIGGER_IFACE_CORE_H_
typedef struct {
const uint32_t example;
} smio_trigger_iface_t;
/***************** Our methods *****************/
/* Creates a new instance of the smio realization */
smio_trigger_iface_t * smio_trigger_iface_new (smio_t *parent);
/* Destroys the smio realizationn */
smio_err_e smio_trigger_iface_destroy (smio_trigger_iface_t **self_p);
#endif
/*
* Copyright (C) 2016 LNLS (www.lnls.br)
* Author: Lucas Russo <lucas.russo@lnls.br>
*
* Released according to the GNU GPL, version 3 or any later version.
*/
#include "bpm_server.h"
/* Private headers */
#include "sm_io_trigger_iface_defaults.h"
/* Undef ASSERT_ALLOC to avoid conflicting with other ASSERT_ALLOC */
#ifdef ASSERT_TEST
#undef ASSERT_TEST
#endif
#define ASSERT_TEST(test_boolean, err_str, err_goto_label, /* err_core */ ...) \
ASSERT_HAL_TEST(test_boolean, SM_IO, "[sm_io:trigger_iface_defaults]", \
err_str, err_goto_label, /* err_core */ __VA_ARGS__)
#ifdef ASSERT_ALLOC
#undef ASSERT_ALLOC
#endif
#define ASSERT_ALLOC(ptr, err_goto_label, /* err_core */ ...) \
ASSERT_HAL_ALLOC(ptr, SM_IO, "[sm_io:trigger_iface_defaults]", \
smio_err_str(SMIO_ERR_ALLOC), \
err_goto_label, /* err_core */ __VA_ARGS__)
#ifdef CHECK_ERR
#undef CHECK_ERR
#endif
#define CHECK_ERR(err, err_type) \
CHECK_HAL_ERR(err, SM_IO, "[sm_io:trigger_iface_defaults]", \
smio_err_str (err_type))
#define SMIO_TRIGGER_IFACE_LIBBPMCLIENT_LOG_MODE "a"
#define SMIO_TRIGGER_IFACE_MAX_CHAN 24
/* We use the actual libclient to send and configure our default values,
* maintaining internal consistency. So, in fact, we are sending ourselves
* a message containing the default values. Because of this approach, we
* only get to default our values when the functions are already exported
* to the broker, which happens on a late stage. This could cause a fast
* client to get an inconsistent state from our server */
/* TODO: Avoid exporting the functions before we have initialized
* our server with the default values */
smio_err_e trigger_iface_config_defaults (char *broker_endp, char *service,
const char *log_file_name)
{
(void) log_file_name;
DBE_DEBUG (DBG_SM_IO | DBG_LVL_INFO, "[sm_io:trigger_iface_defaults] Configuring SMIO "
"TRIGGER_IFACE with default values ...\n");
bpm_client_err_e client_err = BPM_CLIENT_SUCCESS;
smio_err_e err = SMIO_SUCCESS;
bpm_client_t *config_client = bpm_client_new_log_mode (broker_endp, 0,
log_file_name, SMIO_TRIGGER_IFACE_LIBBPMCLIENT_LOG_MODE);
ASSERT_ALLOC(config_client, err_alloc_client);
uint32_t chan;
for (chan = 0; chan < SMIO_TRIGGER_IFACE_MAX_CHAN; ++chan) {
client_err = bpm_set_trigger_dir (config_client, service, chan, TRIGGER_IFACE_DFLT_DIR);
client_err |= bpm_set_trigger_rcv_count_rst (config_client, service, chan, TRIGGER_IFACE_DFLT_RCV_RST);
client_err |= bpm_set_trigger_transm_count_rst (config_client, service, chan, TRIGGER_IFACE_DFLT_TRANSM_RST);
client_err |= bpm_set_trigger_rcv_len (config_client, service, chan, TRIGGER_IFACE_DFLT_RCV_LEN);
client_err |= bpm_set_trigger_transm_len (config_client, service, chan, TRIGGER_IFACE_DFLT_TRANSM_LEN);
}
ASSERT_TEST(client_err == BPM_CLIENT_SUCCESS, "Could set trigger defaults",
err_param_set, SMIO_ERR_CONFIG_DFLT);
err_param_set:
bpm_client_destroy (&config_client);
err_alloc_client:
DBE_DEBUG (DBG_SM_IO | DBG_LVL_INFO, "[sm_io:trigger_iface_defaults] Exiting Config thread %s\n",
service);
return err;
}
/*
* Copyright (C) 2016 LNLS (www.lnls.br)
* Author: Lucas Russo <lucas.russo@lnls.br>
*
* Released according to the GNU GPL, version 3 or any later version.
*/
#ifndef _TRIGGER_IFACE_DEFAULTS_H_
#define _TRIGGER_IFACE_DEFAULTS_H_
#include "sm_io_err.h"
#define TRIGGER_IFACE_DFLT_DIR 1 /* Input */
#define TRIGGER_IFACE_DFLT_RCV_RST 1 /* Pulse Reset */
#define TRIGGER_IFACE_DFLT_TRANSM_RST 1 /* Pulse Reset */
#define TRIGGER_IFACE_DFLT_RCV_LEN 1 /* Debounce Length */
#define TRIGGER_IFACE_DFLT_TRANSM_LEN 1 /* Pulse Extension Length */
smio_err_e trigger_iface_config_defaults (char *broker_endp, char *service,
const char *log_file_name);
#endif
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/*
* Copyright (C) 2016 LNLS (www.lnls.br)
* Author: Lucas Russo <lucas.russo@lnls.br>
*
* Released according to the GNU GPL, version 3 or any later version.
*/
#ifndef _TRIGGER_IFACE_H_
#define _TRIGGER_IFACE_H_
/* Known modules IDs (from SDB records defined in FPGA) */
#define TRIGGER_IFACE_SDB_DEVID 0xbcbb78d2
#define TRIGGER_IFACE_SDB_NAME "TRIGGER_IFACE"
extern const smio_bootstrap_ops_t trigger_iface_bootstrap_ops;
#endif
/*
* Copyright (C) 2016 LNLS (www.lnls.br)
* Author: Lucas Russo <lucas.russo@lnls.br>
*
* Released according to the GNU GPL, version 3 or any later version.
*/
#include "sm_io_exports_helper.h"
#include "sm_io_codes.h"
/* Description SMIO TRIGGER_IFACE functions */
disp_op_t trigger_iface_dir_exp = {
.name = TRIGGER_IFACE_NAME_DIR,
.opcode = TRIGGER_IFACE_OPCODE_DIR,
.retval = DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
.retval_owner = DISP_OWNER_OTHER,
.args = {
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_END
}
};
disp_op_t trigger_iface_rcv_count_rst_exp = {
.name = TRIGGER_IFACE_NAME_RCV_COUNT_RST,
.opcode = TRIGGER_IFACE_OPCODE_RCV_COUNT_RST,
.retval = DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
.retval_owner = DISP_OWNER_OTHER,
.args = {
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_END
}
};
disp_op_t trigger_iface_transm_count_rst_exp = {
.name = TRIGGER_IFACE_NAME_TRANSM_COUNT_RST,
.opcode = TRIGGER_IFACE_OPCODE_TRANSM_COUNT_RST,
.retval = DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
.retval_owner = DISP_OWNER_OTHER,
.args = {
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_END
}
};
disp_op_t trigger_iface_rcv_len_exp = {
.name = TRIGGER_IFACE_NAME_RCV_LEN,
.opcode = TRIGGER_IFACE_OPCODE_RCV_LEN,
.retval = DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
.retval_owner = DISP_OWNER_OTHER,
.args = {
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_END
}
};
disp_op_t trigger_iface_transm_len_exp = {
.name = TRIGGER_IFACE_NAME_TRANSM_LEN,
.opcode = TRIGGER_IFACE_OPCODE_TRANSM_LEN,
.retval = DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
.retval_owner = DISP_OWNER_OTHER,
.args = {
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_END
}
};
disp_op_t trigger_iface_count_rcv_exp = {
.name = TRIGGER_IFACE_NAME_COUNT_RCV,
.opcode = TRIGGER_IFACE_OPCODE_COUNT_RCV,
.retval = DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
.retval_owner = DISP_OWNER_OTHER,
.args = {
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_END
}
};
disp_op_t trigger_iface_count_transm_exp = {
.name = TRIGGER_IFACE_NAME_COUNT_TRANSM,
.opcode = TRIGGER_IFACE_OPCODE_COUNT_TRANSM,
.retval = DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
.retval_owner = DISP_OWNER_OTHER,
.args = {
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_ENCODE(DISP_ATYPE_UINT32, uint32_t),
DISP_ARG_END
}
};
/* Exported function description */
const disp_op_t *trigger_iface_exp_ops [] = {
&trigger_iface_dir_exp,
&trigger_iface_rcv_count_rst_exp,
&trigger_iface_transm_count_rst_exp,
&trigger_iface_rcv_len_exp,
&trigger_iface_transm_len_exp,
&trigger_iface_count_rcv_exp,
&trigger_iface_count_transm_exp,
NULL
};
/*
* Copyright (C) 2016 LNLS (www.lnls.br)
* Author: Lucas Russo <lucas.russo@lnls.br>
*
* Released according to the GNU GPL, version 3 or any later version.
*/
#ifndef _SM_IO_TRIGGER_IFACE_EXPORTS_H_
#define _SM_IO_TRIGGER_IFACE_EXPORTS_H_
#include "disptable.h"
extern disp_op_t trigger_iface_dir_exp;
extern disp_op_t trigger_iface_rcv_count_rst_exp;
extern disp_op_t trigger_iface_transm_count_rst_exp;
extern disp_op_t trigger_iface_rcv_len_exp;
extern disp_op_t trigger_iface_transm_len_exp;
extern disp_op_t trigger_iface_count_rcv_exp;
extern disp_op_t trigger_iface_count_transm_exp;
extern const disp_op_t *trigger_iface_exp_ops [];
#endif
sm_io_trigger_iface_DIR = $(SRC_DIR)/sm_io/modules/trigger_iface
sm_io_trigger_iface_OBJS = $(sm_io_trigger_iface_DIR)/sm_io_trigger_iface_core.o \
$(sm_io_trigger_iface_DIR)/sm_io_trigger_iface_exp.o \
$(sm_io_trigger_iface_DIR)/sm_io_trigger_iface_exports.o \
$(sm_io_trigger_iface_DIR)/sm_io_trigger_iface_defaults.o
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