The Brazilian Synchrotron Light Laboratory (LNLS) is currently designing
a third-generation 3 GeV low emmitance synchrotron light source in
Campinas, Brazil, called Sirius, with first beam due to the second
quarter of 2016. The main parameters of the machine are:
Injection energy (top up)
Natural bunch length
Beam size on insertion devices @ 1 % coupling (horizontal X vertical)
33 x 1.4
Beam divergence on insertion devices @ 1 % coupling (horizontal X vertical)
8.4 x 1.9
Natural emittance (horizontal) without IDs
Circumference (storage ring)
For more information about the Sirius projetct please refer to this
In the context of the Sirius project, the Beam Diagnostics Group (DIG)
of LNLS has been called to develop a beam position monitoring system
(BPM) which must provide electron beam position real-time monitoring,
triggered data readouts, fast orbit feedback capabilities and advanced
beam diagnostics tools for the new accelerator’s injector and storage
ring. This project is primarily intended to deliver a BPM system for the
Sirius machine. Nevertheless, it is made open for the particle
accelerators community and grand public for design reuse and
collaborative development, unde the CERN Open Hardware
The RF front-end is designed for button BPM pick-ups and must allow 50
dB dynamic range with maximum gain of 60 dB (0 to 5 dBm output).
Bandpass filtering must provide 45 MHz bandwidth around the 500 MHz
beam's main frequency, with 80 dB attenuation in the stop band.
The ADC board is a FPGA Mezzanince Card
(FMC) module fully compliant to the
ANSI/VITA 57.1 standard, providing 4-channel 16-bit 130 MS/s
(LTC2208IUP) with 500 MHz bandwidth. Clocking can be phase-locked to
external reference or direct clock inputs (from front panel or FMC
clock) as well as bi-directional (configurable) trigger. It is expected
to achieve above 10 bits ENOB and above 80 dBFS SFDR around 500 MHz.
The DBE is a crate-based system which integrates in a single enclosure
the FPGA processing boards for beam position sensor data processing,
data acquisition and advanced diagnostics, fast orbit feedback (FOFB)
processing boards for feedback control algorithm processing, a single
board computer for control system interface and RF front-ends control.
The FPGA boards are connected to the single board computer via 4 lanes
of PCIe Gen 2 link. The DBE relies on the PICMG® MicroTCA R1.0 standard
(MicroTCA.4), using COTS crates and infrastructure (power supply,
cooling and intelligent hardware management). The FPGA board, a.k.a. AMC
FMC Carrier (AFC), is fully compliant to PICMG® AMC R2.0 standard
(AMC.0, AMC.1, AMC.2). Besides power, cooling and IPMI infrastructure,
the MicroTCA.4 backplane provides JTAG chain access to all individual
slots, GbE and PCIe switches, as well as multigigabit point-to-point
connectivity between slots, 8 M-LVDS triggers, and 2 low-jitter radial
Start of project in OHR. Hardware designs will be done by external companies and LNLS.
Ask for quotations for RF front-end, ADC board and digital back-end designs.
DBE schematics started. Creotech is in charge of the boards design.