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Converter Common Gateware
Commit 0226eb67 authored by Denia Bouhired-Ferrag's avatar Denia Bouhired-Ferrag
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Merge branch 'proposed-master' of git://ohwr.org/level-conversion/conv-common-gw… 

Merge branch 'proposed-master' of git://ohwr.org/level-conversion/conv-common-gw into proposed-master
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top/conv_common_gw.vhd
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--==============================================================================
--------------------------------------------------------------------------------
-- CERN (BE-CO-HT)
-- Converter board common gateware top-level file
--==============================================================================
--
-- author: Theodor Stana (t.stana@cern.ch)
--
-- date of creation: 2014-07-24
-- Converter board common gateware
-- URL https://www.ohwr.org/projects/conv-common-gw/wiki/wiki
--------------------------------------------------------------------------------
--
-- version: 1.0
-- Converter board common gateware top-level file
--
-- description:
-- Description:
-- This module is to be instantiated in all pulse converter board designs,
-- for example the CONV-TTL-BLO or CONV-TTL-RS485. It contains a set of
-- modules common to all these boards, that are configurable via generics to
-- accommodate for the application of each board.
--
-- dependencies:
-- Dependencies:
-- general-cores repository [1]
--
-- references:
-- References:
-- [1] Board IDs for level conversion circuits
-- www.ohwr.org/projects/conv-common-gw/wiki/Board-id
-- [2] Platform-independent core collection webpage on OHWR,
......@@ -26,9 +23,11 @@
-- [3] ELMA, Access to board data using SNMP and I2C
-- http://www.ohwr.org/documents/227
--
--==============================================================================
--------------------------------------------------------------------------------
-- Copyright (c) 2018 CERN
--------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--==============================================================================
--------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
......@@ -38,7 +37,7 @@
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--==============================================================================
--------------------------------------------------------------------------------
library ieee;
......@@ -55,111 +54,93 @@ use work.genram_pkg.all;
use work.conv_common_gw_pkg.all;
entity conv_common_gw is
generic
(
generic (
-- Reduces some timeouts to speed up simulations
g_SIMUL : boolean := false;
-- Reset time: 50ns * 2 * (10**6) = 100 ms
g_RST_TIME : positive := 2*(10**6);
-- Number of repeater channels
g_nr_chans : integer := 6;
g_NR_CHANS : integer := 6;
-- Number of inverter channels
g_nr_inv_chans : integer := 4;
g_NR_INV_CHANS : integer := 4;
-- Board ID -- 4-letter ASCII string indicating the board ID
-- see [1] for example
g_board_id : std_logic_vector(31 downto 0) := x"54424c4f";
g_BOARD_ID : std_logic_vector(31 downto 0) := x"54424c4f";
-- Gateware version
g_gwvers : std_logic_vector(7 downto 0) :=x"40";
g_GWVERS : std_logic_vector(7 downto 0) := x"40";
-- Generate pulse repetition logic with fixed output pulse width
g_pgen_fixed_width : boolean := true ;
g_PGEN_FIXED_WIDTH : boolean := true;
-- Pulse width at pulse generator output (valid with fixed output pulse width)
g_pgen_pwidth_lg : natural range 2 to 40 := 24;
g_pgen_pwidth_sh : natural range 2 to 40 := 5;
g_PGEN_PWIDTH_LG : natural range 2 to 40 := 24;
g_PGEN_PWIDTH_SH : natural range 2 to 40 := 5;
-- Output pulse will be limited to period. They are given as n number of cycles
-- For continuous mode operation max freq 4.16kHz
g_pgen_pperiod_cont : natural range 2 to 5000 := 4800;
--for LONG pulses changes maximum frequency to ~104kHz
g_pgen_pperiod_lg : natural range 6 to 300 := 191;
--for SHORT pulses changes maximum frequency to ~2MHz
g_pgen_pperiod_sh : natural range 2 to 300 := 9;
g_PGEN_PPERIOD_CONT : natural range 2 to 5000 := 4800;
-- for LONG pulses changes maximum frequency to ~104kHz
g_PGEN_PPERIOD_LG : natural range 6 to 300 := 191;
-- for SHORT pulses changes maximum frequency to ~2MHz
g_PGEN_PPERIOD_SH : natural range 2 to 300 := 9;
-- Pulse generator glitch filter length in number of clk_20_i cycles
g_pgen_gf_len : integer := 4;
g_PGEN_GF_LEN : integer := 4;
-- Burst-mode-specific generics:
g_temp_decre_step_lg : t_temp_decre_step :=
g_TEMP_DECRE_STEP_LG : t_temp_decre_step :=
(0,0,0,0,0,0,0,0,5750,100,79,13,12,4,5,13);
g_temp_decre_step_sh : t_temp_decre_step :=
(0,0, 769, 31, 104, 14, 82, 0 ,0, 0, 0, 0, 0, 0, 0, 0);
-- Single pulse temperature rise
-- For long 1.2us pulses
g_burstctrl_1_pulse_temp_rise_lg :in unsigned (19 downto 0) := x"17700";
-- For short 250ns pulses
g_burstctrl_1_pulse_temp_rise_sh :in unsigned (19 downto 0) := x"01388";
g_TEMP_DECRE_STEP_SH : t_temp_decre_step :=
(0,0,769,31,104,14,82,0,0,0,0,0,0,0,0,0);
-- Single pulse temperature rise for long 1.2us pulses
g_BURSTCTRL_1_PULSE_TEMP_RISE_LG
: unsigned (19 downto 0) := x"17700";
-- Single pulse temperature rise for short 250ns pulses
g_BURSTCTRL_1_PULSE_TEMP_RISE_SH
: unsigned (19 downto 0) := x"01388";
-- Maximum temperature allowed (scaled)
g_burstctrl_max_temp_lg_sh :in unsigned (39 downto 0)
:=x"02540BE400"; --For both long 1.2us pulses and short 250ns
-- For both long 1.2us pulses and short 250ns
g_BURSTCTRL_MAX_TEMP_LG_SH
: unsigned (39 downto 0) := x"02540BE400";
-- Generate logic with pulse counters
g_with_pulse_cnt : boolean := false;
g_WITH_PULSE_CNT : boolean := false;
-- Generate logic with pulse timetag
g_with_pulse_timetag : boolean := false;
g_WITH_PULSE_TIMETAG : boolean := false;
-- Generate logic with manual trigger
g_with_man_trig : boolean := false;
g_man_trig_pwidth : integer := 24;
g_WITH_MAN_TRIG : boolean := false;
g_MAN_TRIG_PWIDTH : integer := 24;
-- Generate one-wire master for thermometer
g_with_thermometer : boolean := false;
g_WITH_THERMOMETER : boolean := false;
-- Bicolor LED controller signals
g_bicolor_led_columns : integer := 6;
g_bicolor_led_lines : integer := 2
);
port
(
g_BICOLOR_LED_COLUMNS : integer := 6;
g_BICOLOR_LED_LINES : integer := 2);
port (
-- Clocks
clk_20_i : in std_logic;
clk_125_p_i : in std_logic;
clk_125_n_i : in std_logic;
-- Reset output signal, synchronous to 20 MHz clock
rst_n_o : out std_logic;
-- Glitch filter active-low enable signal
gf_en_n_i : in std_logic;
-- Burst mode enable signal. Mode disabled for all versions of board
burst_en_n_i : in std_logic;
-- Pulse width selection, port low means 250ns, high means 1.2us.
-- Pulse width selection, port low means 250ns, high means 1.2us
pulse_width_sel_n_i : in std_logic;
-- Channel enable
global_ch_oen_o : out std_logic;
pulse_front_oen_o : out std_logic;
pulse_rear_oen_o : out std_logic;
inv_oen_o : out std_logic;
-- Pulse I/O
pulse_i : in std_logic_vector(g_nr_chans-1 downto 0);
pulse_front_i : in std_logic_vector(g_nr_chans-1 downto 0);
pulse_rear_i : in std_logic_vector(g_nr_chans-1 downto 0);
pulse_o : out std_logic_vector(g_nr_chans-1 downto 0);
pulse_i : in std_logic_vector(g_NR_CHANS-1 downto 0);
pulse_front_i : in std_logic_vector(g_NR_CHANS-1 downto 0);
pulse_rear_i : in std_logic_vector(g_NR_CHANS-1 downto 0);
pulse_o : out std_logic_vector(g_NR_CHANS-1 downto 0);
-- Inverted pulse I/O
inv_pulse_i_n : in std_logic_vector(g_nr_inv_chans-1 downto 0);
inv_pulse_o : out std_logic_vector(g_nr_inv_chans-1 downto 0);
inv_pulse_n_i : in std_logic_vector(g_NR_INV_CHANS-1 downto 0);
inv_pulse_o : out std_logic_vector(g_NR_INV_CHANS-1 downto 0);
-- Channel lEDs
-- 26 ms active-high pulse on pulse_o rising edge
led_pulse_o : out std_logic_vector(g_nr_chans-1 downto 0);
led_pulse_o : out std_logic_vector(g_NR_CHANS-1 downto 0);
-- Inverted channel lEDs
-- 26 ms active-high pulse on pulse_o rising edge
led_inv_pulse_o : out std_logic_vector(g_nr_inv_chans-1 downto 0);
led_inv_pulse_o : out std_logic_vector(g_NR_INV_CHANS-1 downto 0);
-- I2C interface
scl_i : in std_logic;
scl_o : out std_logic;
......@@ -167,22 +148,18 @@ entity conv_common_gw is
sda_i : in std_logic;
sda_o : out std_logic;
sda_en_o : out std_logic;
-- I2C LED signals -- conect to a bicolor LED of choice
-- led_i2c_o pulses four times on I2C transfer
led_i2c_o : out std_logic;
-- VME interface
vme_sysreset_n_i : in std_logic;
vme_ga_i : in std_logic_vector(4 downto 0);
vme_gap_i : in std_logic;
-- SPI interface to on-board flash chip
flash_cs_n_o : out std_logic;
flash_sclk_o : out std_logic;
flash_mosi_o : out std_logic;
flash_miso_i : in std_logic;
-- PLL DACs
-- 20 MHz VCXO control
dac20_din_o : out std_logic;
......@@ -192,7 +169,6 @@ entity conv_common_gw is
dac125_din_o : out std_logic;
dac125_sclk_o : out std_logic;
dac125_sync_n_o : out std_logic;
-- SFP lines
sfp_los_i : in std_logic;
sfp_present_i : in std_logic;
......@@ -201,40 +177,32 @@ entity conv_common_gw is
sfp_scl_b : inout std_logic;
sfp_tx_disable_o : out std_logic;
sfp_tx_fault_i : in std_logic;
-- Switch inputs (for readout from converter status register)
sw_gp_i : in std_logic_vector(7 downto 0);
sw_other_i : in std_logic_vector(31 downto 0);
-- PCB Version information
hwvers_i : in std_logic_vector (5 downto 0);
-- RTM lines
rtmm_i : in std_logic_vector(2 downto 0);
rtmp_i : in std_logic_vector(2 downto 0);
-- TTL, INV-TTL and rear-panel channel inputs, for reflection in line status register
line_front_i : in std_logic_vector(g_nr_chans-1 downto 0);
line_inv_i : in std_logic_vector(g_nr_inv_chans-1 downto 0);
line_rear_i : in std_logic_vector(g_nr_chans-1 downto 0);
line_front_i : in std_logic_vector(g_NR_CHANS-1 downto 0);
line_inv_i : in std_logic_vector(g_NR_INV_CHANS-1 downto 0);
line_rear_i : in std_logic_vector(g_NR_CHANS-1 downto 0);
-- Fail-safe lines, detect invalid or no signal on channel input
line_front_fs_i : in std_logic_vector(g_nr_chans-1 downto 0);
line_inv_fs_i : in std_logic_vector(g_nr_inv_chans-1 downto 0);
line_rear_fs_i : in std_logic_vector(g_nr_chans-1 downto 0);
line_front_fs_i : in std_logic_vector(g_NR_CHANS-1 downto 0);
line_inv_fs_i : in std_logic_vector(g_NR_INV_CHANS-1 downto 0);
line_rear_fs_i : in std_logic_vector(g_NR_CHANS-1 downto 0);
-- Thermometer line
thermometer_b : inout std_logic;
-- System error LED, active-high on system error
-- ERR bicolor LED should light red when led_syserr_o = '1'
led_syserr_o : out std_logic;
-- Bicolor LED signals
bicolor_led_state_i : in std_logic_vector(2*g_bicolor_led_columns*g_bicolor_led_lines-1 downto 0);
bicolor_led_col_o : out std_logic_vector(g_bicolor_led_columns-1 downto 0);
bicolor_led_line_o : out std_logic_vector(g_bicolor_led_lines-1 downto 0);
bicolor_led_line_oen_o : out std_logic_vector(g_bicolor_led_lines-1 downto 0)
);
bicolor_led_state_i : in std_logic_vector(2*g_BICOLOR_LED_COLUMNS*g_BICOLOR_LED_LINES-1 downto 0);
bicolor_led_col_o : out std_logic_vector(g_BICOLOR_LED_COLUMNS-1 downto 0);
bicolor_led_line_o : out std_logic_vector(g_BICOLOR_LED_LINES-1 downto 0);
bicolor_led_line_oen_o : out std_logic_vector(g_BICOLOR_LED_LINES-1 downto 0));
end entity conv_common_gw;
......@@ -245,42 +213,38 @@ architecture arch of conv_common_gw is
-- Constant declarations
--============================================================================
-- Short pulse widths
--constant c_pgen_pwidth_sh : natural := 5;
-- constant c_pgen_pwidth_sh : natural := 5;
-- Burst mode maximum duty cycle is 50%, i.e. divider is 2
constant c_pgen_duty_cycle_div_sh : natural := 2;
constant c_PGEN_DUTY_CYCLE_DIV_SH : natural := 2;
-- Number of Wishbone masters and slaves, for wb_crossbar
constant c_nr_masters : natural := 1;
constant c_nr_slaves : natural := 2;
constant c_NR_MASTERS : natural := 1;
constant c_NR_SLAVES : natural := 2;
-- slave order definitions
constant c_slv_conv_regs : natural := 0;
constant c_slv_multiboot : natural := 1;
constant c_slv_onewire_mst : natural := 2;
constant c_SLV_CONV_REGS : natural := 0;
constant c_SLV_MULTIBOOT : natural := 1;
-- base address definitions
constant c_addr_conv_regs : t_wishbone_address := x"00000000";
constant c_addr_multiboot : t_wishbone_address := x"00000100";
--constant c_addr_onewire_mst : t_wishbone_address := x"00000200";
constant c_addr_sdb : t_wishbone_address := x"00000f00";
constant c_ADDR_CONV_REGS : t_wishbone_address := x"00000000";
constant c_ADDR_MULTIBOOT : t_wishbone_address := x"00000100";
constant c_ADDR_SDB : t_wishbone_address := x"00000f00";
-- SDB interconnect layout
-- c_conv_regs_sdb defined in conv_common_gw_pkg.vhd
constant c_sdb_layout : t_sdb_record_array(c_nr_slaves-1 downto 0) := (
c_slv_conv_regs => f_sdb_embed_device(c_conv_regs_sdb, c_addr_conv_regs),
c_slv_multiboot => f_sdb_embed_device(c_xwb_xil_multiboot_sdb,
c_addr_multiboot)
-- c_slv_onewire_mst => f_sdb_embed_device(c_xwb_onewire_master_sdb,
-- c_addr_onewire_mst)
constant c_SDB_LAYOUT : t_sdb_record_array(c_NR_SLAVES-1 downto 0) := (
c_SLV_CONV_REGS => f_sdb_embed_device(c_CONV_REGS_SDB, c_ADDR_CONV_REGS),
c_SLV_MULTIBOOT => f_sdb_embed_device(c_XWB_XIL_MULTIBOOT_SDB,
c_ADDR_MULTIBOOT)
);
-- Tag bufferdata width: 40 -- TAI
-- 28 -- cycles
-- 1 -- WRPRES bit
-- xx -- channel mask for max. nr. channels
constant c_tagbuff_data_width : positive := 40 + 28 + 1 + c_max_nr_chans;
constant c_TAGBUFF_DATA_WIDTH : positive := 40 + 28 + 1 + c_max_nr_chans;
--============================================================================
-- Type declarations
......@@ -289,7 +253,7 @@ architecture arch of conv_common_gw is
type t_pulse_led_cnt is array(c_max_nr_chans-1 downto 0)
of unsigned(18 downto 0);
type t_inv_pulse_led_cnt is array(g_nr_inv_chans-1 downto 0)
type t_inv_pulse_led_cnt is array(g_NR_INV_CHANS-1 downto 0)
of unsigned(18 downto 0);
type t_temp_rise_cnt is array(c_max_nr_chans-1 downto 0)
......@@ -314,43 +278,44 @@ architecture arch of conv_common_gw is
signal rst_20_n : std_logic;
signal rst_20 : std_logic;
signal rst_ext : std_logic;
signal rst_time : positive := 10;
-- Pulse logic signals
signal trig_a : std_logic_vector(g_nr_chans-1 downto 0);
signal trig_synced : std_logic_vector(g_nr_chans-1 downto 0);
signal trig_degl : std_logic_vector(g_nr_chans-1 downto 0);
signal trig_chan : std_logic_vector(g_nr_chans-1 downto 0);
signal trig_chan_redge_p : std_logic_vector(g_nr_chans-1 downto 0);
signal trig_chan_fedge_p : std_logic_vector(g_nr_chans-1 downto 0);
signal trig_man : std_logic_vector(g_nr_chans-1 downto 0);
signal trig_pgen : std_logic_vector(g_nr_chans-1 downto 0);
signal trig_a : std_logic_vector(g_NR_CHANS-1 downto 0);
signal trig_synced : std_logic_vector(g_NR_CHANS-1 downto 0);
signal trig_degl : std_logic_vector(g_NR_CHANS-1 downto 0);
signal trig_chan : std_logic_vector(g_NR_CHANS-1 downto 0);
signal trig_chan_redge_p : std_logic_vector(g_NR_CHANS-1 downto 0);
signal trig_chan_fedge_p : std_logic_vector(g_NR_CHANS-1 downto 0);
signal trig_man : std_logic_vector(g_NR_CHANS-1 downto 0);
signal trig_pgen : std_logic_vector(g_NR_CHANS-1 downto 0);
signal burst_en_n : std_logic;
signal pulse_outp_cont : std_logic_vector(g_nr_chans-1 downto 0);
signal burst_outp_sh : std_logic_vector(g_nr_chans-1 downto 0);
signal pulse_r_edge_lg_p : std_logic_vector(g_nr_chans-1 downto 0);
signal pulse_f_edge_lg_p : std_logic_vector(g_nr_chans-1 downto 0);
signal pulse_r_edge_sh_p : std_logic_vector(g_nr_chans-1 downto 0);
signal pulse_f_edge_sh_p : std_logic_vector(g_nr_chans-1 downto 0);
signal pulse_outp_sh : std_logic_vector(g_nr_chans-1 downto 0);
signal burst_outp_lg : std_logic_vector(g_nr_chans-1 downto 0);
signal pulse_outp_lg : std_logic_vector(g_nr_chans-1 downto 0);
signal pulse_outp : std_logic_vector(g_nr_chans-1 downto 0);
signal pulse_outp_cont : std_logic_vector(g_NR_CHANS-1 downto 0);
signal burst_outp_sh : std_logic_vector(g_NR_CHANS-1 downto 0);
signal pulse_r_edge_lg_p : std_logic_vector(g_NR_CHANS-1 downto 0);
signal pulse_f_edge_lg_p : std_logic_vector(g_NR_CHANS-1 downto 0);
signal pulse_r_edge_sh_p : std_logic_vector(g_NR_CHANS-1 downto 0);
signal pulse_f_edge_sh_p : std_logic_vector(g_NR_CHANS-1 downto 0);
signal pulse_outp_sh : std_logic_vector(g_NR_CHANS-1 downto 0);
signal burst_outp_lg : std_logic_vector(g_NR_CHANS-1 downto 0);
signal pulse_outp_lg : std_logic_vector(g_NR_CHANS-1 downto 0);
signal pulse_outp : std_logic_vector(g_NR_CHANS-1 downto 0);
signal temp_rise_c_lg : t_temp_rise_cnt;
signal temp_rise_c_sh : t_temp_rise_cnt;
signal pulse_outp_d0 : std_logic_vector(g_nr_chans-1 downto 0);
signal pulse_outp_redge_p : std_logic_vector(g_nr_chans-1 downto 0);
signal inv_pulse_outp : std_logic_vector(g_nr_inv_chans-1 downto 0);
signal inv_pulse_outp_d0 : std_logic_vector(g_nr_inv_chans-1 downto 0);
signal inv_pulse_outp_fedge_p : std_logic_vector(g_nr_inv_chans-1 downto 0);
signal pmisse_p : std_logic_vector(g_nr_chans-1 downto 0);
signal flim_pmisse_p : std_logic_vector(g_nr_chans-1 downto 0);
signal fwdg_pmisse_p : std_logic_vector(g_nr_chans-1 downto 0);
signal pulse_outp_err_cont : std_logic_vector(g_nr_chans-1 downto 0);
signal pulse_outp_err_lg_p : std_logic_vector(g_nr_chans-1 downto 0);
signal pulse_outp_err_sh_p : std_logic_vector(g_nr_chans-1 downto 0);
signal burst_outp_err_lg_p : std_logic_vector(g_nr_chans-1 downto 0);
signal burst_outp_err_sh_p : std_logic_vector(g_nr_chans-1 downto 0);
signal pulse_outp_d0 : std_logic_vector(g_NR_CHANS-1 downto 0);
signal pulse_outp_redge_p : std_logic_vector(g_NR_CHANS-1 downto 0);
signal inv_pulse_outp : std_logic_vector(g_NR_INV_CHANS-1 downto 0);
signal inv_pulse_outp_d0 : std_logic_vector(g_NR_INV_CHANS-1 downto 0);
signal inv_pulse_outp_fedge_p : std_logic_vector(g_NR_INV_CHANS-1 downto 0);
signal pmisse_p : std_logic_vector(g_NR_CHANS-1 downto 0);
signal flim_pmisse_p : std_logic_vector(g_NR_CHANS-1 downto 0);
signal fwdg_pmisse_p : std_logic_vector(g_NR_CHANS-1 downto 0);
signal pulse_outp_err_cont : std_logic_vector(g_NR_CHANS-1 downto 0);
signal pulse_outp_err_lg_p : std_logic_vector(g_NR_CHANS-1 downto 0);
signal pulse_outp_err_sh_p : std_logic_vector(g_NR_CHANS-1 downto 0);
signal burst_outp_err_lg_p : std_logic_vector(g_NR_CHANS-1 downto 0);
signal burst_outp_err_sh_p : std_logic_vector(g_NR_CHANS-1 downto 0);
-- Output enable signals
signal global_oen : std_logic;
......@@ -385,7 +350,7 @@ architecture arch of conv_common_gw is
signal fwdg_pmisse_bit_rst_ld : std_logic;
signal pmisse_bits_or : std_logic;
--signals for pulse counters
-- Signals for pulse counters
signal rst_front_cnt : std_logic_vector(c_max_nr_chans-1 downto 0);
signal rst_rear_cnt : std_logic_vector(c_max_nr_chans-1 downto 0);
......@@ -415,9 +380,9 @@ architecture arch of conv_common_gw is
signal line_rear_fs : std_logic_vector(c_max_nr_chans-1 downto 0);
-- LED signals
signal led_pulse : std_logic_vector(g_nr_chans-1 downto 0);
signal led_pulse : std_logic_vector(g_NR_CHANS-1 downto 0);
signal led_pulse_cnt : t_pulse_led_cnt;
signal led_inv_pulse : std_logic_vector(g_nr_inv_chans-1 downto 0);
signal led_inv_pulse : std_logic_vector(g_NR_INV_CHANS-1 downto 0);
signal led_inv_pulse_cnt : t_pulse_led_cnt;
signal led_i2c : std_logic;
signal led_i2c_clkdiv : unsigned(18 downto 0);
......@@ -425,10 +390,10 @@ architecture arch of conv_common_gw is
signal led_i2c_blink : std_logic;
-- Wishbone crossbar signals
signal xbar_slave_in : t_wishbone_slave_in_array (c_nr_masters-1 downto 0);
signal xbar_slave_out : t_wishbone_slave_out_array (c_nr_masters-1 downto 0);
signal xbar_master_in : t_wishbone_master_in_array (c_nr_slaves-1 downto 0);
signal xbar_master_out : t_wishbone_master_out_array(c_nr_slaves-1 downto 0);
signal xbar_slave_in : t_wishbone_slave_in_array (c_NR_MASTERS-1 downto 0);
signal xbar_slave_out : t_wishbone_slave_out_array (c_NR_MASTERS-1 downto 0);
signal xbar_master_in : t_wishbone_master_in_array (c_NR_SLAVES-1 downto 0);
signal xbar_master_out : t_wishbone_master_out_array(c_NR_SLAVES-1 downto 0);
-- Time-tagging component signals
signal tm_cycles : std_logic_vector(27 downto 0);
......@@ -439,13 +404,13 @@ architecture arch of conv_common_gw is
signal buf_count : std_logic_vector(f_log2_size(128)-1 downto 0);
signal buf_full : std_logic;
signal buf_empty : std_logic;
signal buf_chan : std_logic_vector(g_nr_chans-1 downto 0);
signal buf_chan : std_logic_vector(g_NR_CHANS-1 downto 0);
signal buf_wrtag : std_logic;
signal buf_clr_bit : std_logic;
signal buf_clr_bit_ld : std_logic;
signal buf_clr_p : std_logic;
signal buf_dat_in : std_logic_vector(c_tagbuff_data_width-1 downto 0);
signal buf_dat_out : std_logic_vector(c_tagbuff_data_width-1 downto 0);
signal buf_dat_in : std_logic_vector(c_TAGBUFF_DATA_WIDTH-1 downto 0);
signal buf_dat_out : std_logic_vector(c_TAGBUFF_DATA_WIDTH-1 downto 0);
-- Latest timestamp signals
signal lts_ld_125 : std_logic_vector(c_max_nr_chans-1 downto 0);
......@@ -474,7 +439,7 @@ architecture arch of conv_common_gw is
signal id : std_logic_vector(63 downto 0);
signal temper : std_logic_vector(15 downto 0);
--Chipscope signals
-- Chipscope signals
---------------------------------------------------------------------------------------------------
signal CONTROL : std_logic_vector(35 downto 0);
signal CLK : std_logic;
......@@ -543,12 +508,13 @@ begin
-- External reset input to reset generator
rst_ext <= rst_fr_reg or (not vme_sysreset_n_i);
-- Configure reset generator for 100ms reset
cmp_reset_gen : conv_reset_gen
generic map
(
-- Reset time: 50ns * 2 * (10**6) = 100 ms
g_reset_time => 2*(10**6)
g_RESET_TIME => g_RST_TIME
)
port map
(
......@@ -583,7 +549,7 @@ begin
p_delay_oen : process (clk_20_i) is
begin
if rising_edge(clk_20_i) then
if (rst_20_n = '0') then
if rst_20_n = '0' then
global_oen <= '0';
front_oen <= '0';
invttl_oen <= '0';
......@@ -613,13 +579,13 @@ begin
trig_a <= pulse_i;
--------------------------------------------------------------------------------
gen_man_trig : if (g_with_man_trig = true) generate
gen_man_trig : if g_WITH_MAN_TRIG = true generate
-- Manual trigger logic
cmp_man_trig : conv_man_trig
generic map
(
g_nr_chan => g_nr_chans,
g_pwidth => g_man_trig_pwidth
g_nr_chan => g_NR_CHANS,
g_pwidth => g_MAN_TRIG_PWIDTH
)
port map
(
......@@ -629,18 +595,18 @@ begin
reg_i => mpt,
trig_o => trig_man
);
end generate gen_man_trig;
end generate gen_man_trig;
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
gen_no_man_trig : if (g_with_man_trig = false) generate
gen_no_man_trig : if g_WITH_MAN_TRIG = false generate
trig_man <= (others => '0');
end generate gen_no_man_trig;
end generate gen_no_man_trig;
--------------------------------------------------------------------------------
-- Glitch filter
--------------------------------------------------------------------------------
gen_pulse_chan_logic : for i in 0 to g_nr_chans-1 generate
gen_pulse_chan_logic : for i in 0 to g_NR_CHANS-1 generate
-- Synchronize the asynchronous trigger input into the 20 MHz clock
-- domain before passing it to the glitch filter
......@@ -661,7 +627,7 @@ gen_pulse_chan_logic : for i in 0 to g_nr_chans-1 generate
cmp_inp_glitch_filt : gc_glitch_filt
generic map
(
g_len => g_pgen_gf_len
g_len => g_PGEN_GF_LEN
)
port map
(
......@@ -673,7 +639,7 @@ gen_pulse_chan_logic : for i in 0 to g_nr_chans-1 generate
-- Now that we have a deglitched signal, generate the MUX to select between
-- deglitched and direct channel input
trig_chan(i) <= trig_a(i) when (gf_en_n_i = '1') else
trig_chan(i) <= trig_a(i) when gf_en_n_i = '1' else
trig_degl(i);
......@@ -708,43 +674,39 @@ gen_pulse_chan_logic : for i in 0 to g_nr_chans-1 generate
-- The counter below has additional integer output value of the counter plus a
-- reset signal that depends on the system reset in addition to the counter load pulse
--------------------------------------------------------------------------------
gen_pulse_cnt : if (g_with_pulse_cnt = true) generate
gen_pulse_cnt : if g_WITH_PULSE_CNT = true generate
rst_front_cnt(i) <= rst_20 or ch_front_pcr_ld(i);
rst_rear_cnt(i) <= rst_20 or ch_rear_pcr_ld(i);
rst_front_cnt(i) <= rst_20 or ch_front_pcr_ld(i);
rst_rear_cnt(i) <= rst_20 or ch_rear_pcr_ld(i);
cmp_pulse_cnt_front: fastevent_counter
cmp_pulse_cnt_front : fastevent_counter
port map(
sysclk_i => clk_20_i,
rstcount_i => rst_front_cnt(i),
en_i => '1',
trig_i => pulse_front_i(i),
count_int_o => front_pulse_c(i)
);
count_int_o => front_pulse_c(i));
cmp_pulse_cnt_rear: fastevent_counter
cmp_pulse_cnt_rear : fastevent_counter
port map(
sysclk_i => clk_20_i,
rstcount_i => rst_rear_cnt(i),
en_i => '1',
trig_i => pulse_rear_i(i),
count_int_o => rear_pulse_c(i)
);
count_int_o => rear_pulse_c(i));
-- First, the pulse counters for the used channels (up to g_nr_chans)
-- First, the pulse counters for the used channels (up to g_NR_CHANS)
p_pulse_cnt : process (clk_20_i)
begin
if rising_edge(clk_20_i) then
if (rst_20_n = '0') then
if rst_20_n = '0' then
front_pulse_cnt(i) <= (others => '0');
rear_pulse_cnt(i) <= (others => '0');
front_pulse_cnt_offset(i) <= (others => '0');
rear_pulse_cnt_offset(i) <= (others => '0');
elsif (ch_front_pcr_ld(i) = '1') then
elsif ch_front_pcr_ld(i) = '1' then
front_pulse_cnt_offset(i) <= unsigned(ch_front_pcr(i));
elsif (ch_rear_pcr_ld(i) = '1') then
elsif ch_rear_pcr_ld(i) = '1' then
rear_pulse_cnt_offset(i) <= unsigned(ch_rear_pcr(i));
else
front_pulse_cnt(i) <= front_pulse_cnt_offset(i)+ front_pulse_c(i);
......@@ -756,28 +718,25 @@ cmp_pulse_cnt_rear: fastevent_counter
--------------------------------------------------------------------------------
-- Connect pulse counter values for unused channels to all zeroes
gen_pulse_cnt_unused_chans : if (g_nr_chans < c_max_nr_chans) generate
front_pulse_cnt(c_max_nr_chans-1 downto g_nr_chans) <= (others => (others => '0'));
rear_pulse_cnt(c_max_nr_chans-1 downto g_nr_chans) <= (others => (others => '0'));
gen_pulse_cnt_unused_chans : if g_NR_CHANS < c_max_nr_chans generate
front_pulse_cnt(c_max_nr_chans-1 downto g_NR_CHANS) <= (others => (others => '0'));
rear_pulse_cnt(c_max_nr_chans-1 downto g_NR_CHANS) <= (others => (others => '0'));
end generate gen_pulse_cnt_unused_chans;
end generate gen_pulse_cnt_unused_chans;
--------------------------------------------------------------------------------
end generate gen_pulse_cnt;
end generate gen_pulse_cnt;
--
-------------------------------------------------------------------------------------------------
-- Instantiate pulse generator alone for CONTINUOUS MODE
-------------------
--Instantiate pulse generator block for continuous operation without burst feature
-- Instantiate pulse generator block for continuous operation without burst feature
cmp_pulse_gen_cont : conv_pulse_gen
generic map
(
g_with_fixed_pwidth => g_pgen_fixed_width,
g_pwidth => g_pgen_pwidth_lg,
g_pperiod => g_pgen_pperiod_cont
g_with_fixed_pwidth => g_PGEN_FIXED_WIDTH,
g_pwidth => g_PGEN_PWIDTH_LG,
g_pperiod => g_PGEN_PPERIOD_CONT
)
port map
(
......@@ -797,13 +756,13 @@ end generate gen_pulse_cnt;
-------------------------------------------------------------------------------------------------
-- BURST MODE WITH LONG PULSES
----------------------------------
--Instantiate pulse generator block for minimum pulse width and minimum allowed duty cycle
-- Instantiate pulse generator block for minimum pulse width and minimum allowed duty cycle
cmp_pulse_gen_lg : conv_pulse_gen
generic map
(
g_with_fixed_pwidth => g_pgen_fixed_width,
g_pwidth => g_pgen_pwidth_lg,
g_pperiod => g_pgen_pperiod_lg
g_with_fixed_pwidth => g_PGEN_FIXED_WIDTH,
g_pwidth => g_PGEN_PWIDTH_LG,
g_pperiod => g_PGEN_PPERIOD_LG
)
port map
(
......@@ -824,10 +783,10 @@ end generate gen_pulse_cnt;
cmp_burst_ctrl_lg : conv_dyn_burst_ctrl
generic map
(
g_pwidth => g_pgen_pwidth_lg,
g_temp_decre_step => g_temp_decre_step_lg,
g_1_pulse_temp_rise => g_burstctrl_1_pulse_temp_rise_lg,
g_max_temp => g_burstctrl_max_temp_lg_sh
g_pwidth => g_PGEN_PWIDTH_LG,
g_temp_decre_step => g_TEMP_DECRE_STEP_LG,
g_1_pulse_temp_rise => g_BURSTCTRL_1_PULSE_TEMP_RISE_LG,
g_max_temp => g_BURSTCTRL_MAX_TEMP_LG_SH
)
port map
(
......@@ -847,16 +806,14 @@ end generate gen_pulse_cnt;
-------------------------------------------------------------------------------------------------
-- BURST MODE WITH SHORT PULSES
----------------------------------
--Instantiate pulse generator block for minimum pulse width and minimum allowed duty cycle
-- Instantiate pulse generator block for minimum pulse width and minimum allowed duty cycle
cmp_pulse_gen_sh : conv_pulse_gen
generic map
(
g_with_fixed_pwidth => g_pgen_fixed_width,
g_pwidth => g_pgen_pwidth_sh,
g_pperiod => g_pgen_pperiod_sh
generic map(
g_with_fixed_pwidth => g_PGEN_FIXED_WIDTH,
g_pwidth => g_PGEN_PWIDTH_SH,
g_pperiod => g_PGEN_PPERIOD_SH
)
port map
(
port map(
clk_i => clk_20_i,
rst_n_i => rst_20_n,
gf_en_n_i => gf_en_n_i,
......@@ -864,24 +821,19 @@ end generate gen_pulse_cnt;
trig_a_i => trig_pgen(i),
trig_r_edge_p_i => trig_chan_redge_p(i),
trig_f_edge_p_i => trig_chan_fedge_p(i),
pulse_err_p_o => pulse_outp_err_sh_p (i),
pulse_err_p_o => pulse_outp_err_sh_p(i),
pulse_o => pulse_outp_sh(i),
pulse_r_edge_p_o => pulse_r_edge_sh_p(i) ,
pulse_f_edge_p_o => pulse_f_edge_sh_p(i)
);
pulse_r_edge_p_o => pulse_r_edge_sh_p(i),
pulse_f_edge_p_o => pulse_f_edge_sh_p(i));
----------------------------------------------------------------------------------
-- Instantiate burst control block for the channel
cmp_burst_ctrl_sh : conv_dyn_burst_ctrl
generic map
(
g_pwidth => g_pgen_pwidth_sh,
g_temp_decre_step => g_temp_decre_step_sh,
g_1_pulse_temp_rise => g_burstctrl_1_pulse_temp_rise_sh,
g_max_temp => g_burstctrl_max_temp_lg_sh
)
port map
(
generic map(
g_pwidth => g_PGEN_PWIDTH_SH,
g_temp_decre_step => g_TEMP_DECRE_STEP_SH,
g_1_pulse_temp_rise => g_BURSTCTRL_1_PULSE_TEMP_RISE_SH,
g_max_temp => g_BURSTCTRL_MAX_TEMP_LG_SH)
port map(
clk_i => clk_20_i,
rst_n_i => rst_20_n,
en_i => '1',
......@@ -894,7 +846,7 @@ end generate gen_pulse_cnt;
);
----------------------------------------------------------------------
--Select output depending on mode of operation.
-- Select output depending on mode of operation.
----------------------------------------------------------------------
pulse_outp (i) <= (burst_outp_lg(i) and pulse_width_sel_n_i) or
......@@ -902,21 +854,21 @@ end generate gen_pulse_cnt;
when burst_en_n = '0'
else pulse_outp_cont(i);
----------------------------------------------------------------------
--Generate error pulses depending on mode of operation
-- Generate error pulses depending on mode of operation
----------------------------------------------------------------------
-- flim_pmisse_p gives out a pulse when a pulse is missed because its
-- frequency is above the set maximum frequency
flim_pmisse_p (i) <= (pulse_outp_err_lg_p(i) and pulse_width_sel_n_i) or
(pulse_outp_err_sh_p(i) and not pulse_width_sel_n_i)
when burst_en_n = '0'
else pulse_outp_err_cont(i) ;
else pulse_outp_err_cont(i);
-- fwdg_pmisse_p gives out a pulse when a pulse is cutoff because the
-- frequency watchdog only supports a high frequency for a limited period
fwdg_pmisse_p (i) <= (burst_outp_err_lg_p(i) and pulse_width_sel_n_i) or
(burst_outp_err_sh_p(i) and not pulse_width_sel_n_i)
when burst_en_n = '0'
else '0' ;
else '0';
pmisse_p (i) <= flim_pmisse_p (i) or fwdg_pmisse_p (i);
-----------------------------------------------------------------------
......@@ -925,7 +877,7 @@ end generate gen_pulse_cnt;
p_pulse_led : process (clk_20_i) is
begin
if rising_edge(clk_20_i) then
if (rst_20_n = '0') then
if rst_20_n = '0' then
pulse_outp_d0(i) <= '0';
pulse_outp_redge_p(i) <= '0';
led_pulse_cnt(i) <= (others => '0');
......@@ -935,12 +887,12 @@ end generate gen_pulse_cnt;
pulse_outp_redge_p(i) <= pulse_outp(i) and (not pulse_outp_d0(i));
case led_pulse(i) is
when '0' =>
if (pulse_outp_redge_p(i) = '1') then
if pulse_outp_redge_p(i) = '1' then
led_pulse(i) <= '1';
end if;
when '1' =>
led_pulse_cnt(i) <= led_pulse_cnt(i) + 1;
if (led_pulse_cnt(i) = (led_pulse_cnt(i)'range => '1')) then
if led_pulse_cnt(i) = (led_pulse_cnt(i)'range => '1') then
led_pulse(i) <= '0';
end if;
when others =>
......@@ -950,22 +902,22 @@ end generate gen_pulse_cnt;
end if;
end process p_pulse_led;
end generate gen_pulse_chan_logic;
end generate gen_pulse_chan_logic;
-- Process to flash INV-TTL LEDs on the falling edge of the INV-TTL input
-- LED flash length: 26 ms
-- Process to flash INV-TTL LEDs on the falling edge of the INV-TTL input
-- LED flash length: 26 ms
gen_inv_ttl_leds : for i in 0 to g_nr_inv_chans-1 generate
gen_inv_ttl_leds : for i in 0 to g_NR_INV_CHANS-1 generate
-- INV-TTL outputs
inv_pulse_outp(i) <= inv_pulse_i_n(i);
inv_pulse_outp(i) <= inv_pulse_n_i(i);
inv_pulse_o(i) <= inv_pulse_outp(i);
p_inv_pulse_led : process (clk_20_i) is
begin
if rising_edge(clk_20_i) then
if (rst_20_n = '0') then
if rst_20_n = '0' then
inv_pulse_outp_d0(i) <= '0';
inv_pulse_outp_fedge_p(i) <= '0';
led_inv_pulse_cnt(i) <= (others => '0');
......@@ -975,12 +927,12 @@ end generate gen_pulse_chan_logic;
inv_pulse_outp_fedge_p(i) <= (not inv_pulse_outp(i)) and inv_pulse_outp_d0(i);
case led_inv_pulse(i) is
when '0' =>
if (inv_pulse_outp_fedge_p(i) = '1') then
if inv_pulse_outp_fedge_p(i) = '1' then
led_inv_pulse(i) <= '1';
end if;
when '1' =>
led_inv_pulse_cnt(i) <= led_inv_pulse_cnt(i) + 1;
if (led_inv_pulse_cnt(i) = (led_inv_pulse_cnt(i)'range => '1')) then
if led_inv_pulse_cnt(i) = (led_inv_pulse_cnt(i)'range => '1') then
led_inv_pulse(i) <= '0';
end if;
when others =>
......@@ -989,58 +941,50 @@ end generate gen_pulse_chan_logic;
end if;
end if;
end process p_inv_pulse_led;
end generate gen_inv_ttl_leds;
end generate gen_inv_ttl_leds;
--------------------------------------------------------------------------------
gen_pulse_timetag : if (g_with_pulse_timetag = true) generate
gen_pulse_timetag : if g_WITH_PULSE_TIMETAG = true generate
cmp_pulse_timetag : conv_pulse_timetag
generic map
(
generic map (
-- Frequency in Hz of the clk_i signal
g_clk_rate => 125000000,
-- Number of repetition channels
g_nr_chan => g_nr_chans
)
port map
(
g_nr_chan => g_NR_CHANS)
port map(
-- Clock and active-low reset
clk_i => clk_125,
rst_n_i => rst_125_n,
-- Asynchronous pulse input
pulse_a_i => trig_chan,
-- Time inputs from White Rabbit
wr_tm_cycles_i => (others => '0'),
wr_tm_tai_i => (others => '0'),
wr_tm_valid_i => '0',
-- Timing inputs from Wishbone-mapped registers
wb_tm_tai_l_i => tvlr,
wb_tm_tai_l_ld_i => tvlr_ld,
wb_tm_tai_h_i => tvhr,
wb_tm_tai_h_ld_i => tvhr_ld,
-- Timing outputs
tm_cycles_o => tm_cycles,
tm_tai_o => tm_tai,
tm_wrpres_o => buf_wrtag,
chan_p_o => buf_chan,
-- Ring buffer I/O
buf_wr_req_p_o => buf_wr_req_p
);
--------------------------------------------------------------------------------
gen_buf_chan : if (g_nr_chans = c_max_nr_chans) generate
gen_buf_chan : if g_NR_CHANS = c_max_nr_chans generate
buf_dat_in(c_max_nr_chans-1 downto 0) <= buf_chan;
end generate gen_buf_chan;
end generate gen_buf_chan;
gen_buf_chan_unused_chans: if (g_nr_chans < c_max_nr_chans) generate
buf_dat_in(g_nr_chans-1 downto 0) <= buf_chan;
buf_dat_in(c_max_nr_chans-1 downto g_nr_chans) <= (others => '0');
end generate gen_buf_chan_unused_chans;
gen_buf_chan_unused_chans : if g_NR_CHANS < c_max_nr_chans generate
buf_dat_in(g_NR_CHANS-1 downto 0) <= buf_chan;
buf_dat_in(c_max_nr_chans-1 downto g_NR_CHANS) <= (others => '0');
end generate gen_buf_chan_unused_chans;
--------------------------------------------------------------------------------
buf_dat_in( 6) <= buf_wrtag;
......@@ -1049,13 +993,10 @@ end generate gen_buf_chan_unused_chans;
-- Instantiate the ring buffer
cmp_ring_buf : conv_ring_buf
generic map
(
g_data_width => c_tagbuff_data_width,
g_size => 128
)
port map
(
generic map (
g_data_width => c_TAGBUFF_DATA_WIDTH,
g_size => 128)
port map (
-- Clocks and reset
clk_rd_i => clk_20_i,
clk_wr_i => clk_125,
......@@ -1071,10 +1012,8 @@ end generate gen_buf_chan_unused_chans;
buf_dat_o => buf_dat_out,
buf_full_o => buf_full,
buf_empty_o => buf_empty,
buf_count_o => buf_count
);
end generate gen_pulse_timetag;
buf_count_o => buf_count);
end generate gen_pulse_timetag;
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
......@@ -1135,8 +1074,7 @@ end generate gen_pulse_timetag;
wbm_adr_o => xbar_slave_in(0).adr,
wbm_ack_i => xbar_slave_out(0).ack,
wbm_rty_i => xbar_slave_out(0).rty,
wbm_err_i => xbar_slave_out(0).err
);
wbm_err_i => xbar_slave_out(0).err);
-- Process to blink the LED when an I2C transfer is in progress
-- blinks four times per transfer
......@@ -1145,7 +1083,7 @@ end generate gen_pulse_timetag;
p_i2c_blink : process(clk_20_i)
begin
if rising_edge(clk_20_i) then
if (rst_20_n = '0') then
if rst_20_n = '0' then
led_i2c_clkdiv <= (others => '0');
led_i2c_cnt <= (others => '0');
led_i2c <= '0';
......@@ -1155,17 +1093,17 @@ end generate gen_pulse_timetag;
when '0' =>
led_i2c <= '0';
if (i2c_tip = '1') then
if i2c_tip = '1' then
led_i2c_blink <= '1';
end if;
when '1' =>
led_i2c_clkdiv <= led_i2c_clkdiv + 1;
if (led_i2c_clkdiv = 399999) then
if led_i2c_clkdiv = 399999 then
led_i2c_clkdiv <= (others => '0');
led_i2c_cnt <= led_i2c_cnt + 1;
led_i2c <= not led_i2c;
if (led_i2c_cnt = 7) then
if led_i2c_cnt = 7 then
led_i2c_cnt <= (others => '0');
led_i2c_blink <= '0';
end if;
......@@ -1186,9 +1124,9 @@ end generate gen_pulse_timetag;
p_sr_wdto_bit : process(clk_20_i)
begin
if rising_edge(clk_20_i) then
if (rst_20_n = '0') then
if rst_20_n = '0' then
i2c_wdto_bit <= '0';
elsif (i2c_wdto_p = '1') then
elsif i2c_wdto_p = '1' then
i2c_wdto_bit <= '1';
elsif (i2c_wdto_bit_rst_ld = '1') and (i2c_wdto_bit_rst = '1') then
i2c_wdto_bit <= '0';
......@@ -1200,9 +1138,9 @@ end generate gen_pulse_timetag;
p_i2c_err_led : process(clk_20_i)
begin
if rising_edge(clk_20_i) then
if (rst_20_n = '0') then
if rst_20_n = '0' then
i2c_err_bit <= '0';
elsif (i2c_err_p = '1') then
elsif i2c_err_p = '1' then
i2c_err_bit <= '1';
elsif (i2c_err_bit_rst_ld = '1') and (i2c_err_bit_rst = '1') then
i2c_err_bit <= '0';
......@@ -1216,12 +1154,12 @@ end generate gen_pulse_timetag;
cmp_wb_crossbar : xwb_sdb_crossbar
generic map
(
g_num_masters => c_nr_masters,
g_num_slaves => c_nr_slaves,
g_num_masters => c_NR_MASTERS,
g_num_slaves => c_NR_SLAVES,
g_registered => false,
g_wraparound => true,
g_layout => c_sdb_layout,
g_sdb_addr => c_addr_sdb
g_layout => c_SDB_LAYOUT,
g_sdb_addr => c_ADDR_SDB
)
port map
(
......@@ -1240,38 +1178,38 @@ end generate gen_pulse_timetag;
rtm_lines <= rtmp_i & rtmm_i;
--------------------------------------------------------------------------------
gen_line : if (g_nr_chans = c_max_nr_chans) generate
gen_line : if g_NR_CHANS = c_max_nr_chans generate
line_front <= line_front_i;
line_rear <= line_rear_i;
line_front_fs <= line_front_fs_i;
line_rear_fs <= line_rear_fs_i;
end generate gen_line;
end generate gen_line;
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
gen_line_unused_chans : if (g_nr_chans < c_max_nr_chans) generate
gen_line_unused_chans : if g_NR_CHANS < c_max_nr_chans generate
-- connect used lines
line_front(g_nr_chans-1 downto 0) <= line_front_i;
line_rear(g_nr_chans-1 downto 0) <= line_rear_i;
line_front_fs(g_nr_chans-1 downto 0) <= line_front_fs_i;
line_rear_fs(g_nr_chans-1 downto 0) <= line_rear_fs_i;
line_front(g_NR_CHANS-1 downto 0) <= line_front_i;
line_rear(g_NR_CHANS-1 downto 0) <= line_rear_i;
line_front_fs(g_NR_CHANS-1 downto 0) <= line_front_fs_i;
line_rear_fs(g_NR_CHANS-1 downto 0) <= line_rear_fs_i;
-- unused lines to zeroes
line_front(c_max_nr_chans-1 downto g_nr_chans) <= (others => '0');
line_rear(c_max_nr_chans-1 downto g_nr_chans) <= (others => '0');
line_front_fs(c_max_nr_chans-1 downto g_nr_chans) <= (others => '0');
line_rear_fs(c_max_nr_chans-1 downto g_nr_chans) <= (others => '0');
end generate gen_line_unused_chans;
line_front(c_max_nr_chans-1 downto g_NR_CHANS) <= (others => '0');
line_rear(c_max_nr_chans-1 downto g_NR_CHANS) <= (others => '0');
line_front_fs(c_max_nr_chans-1 downto g_NR_CHANS) <= (others => '0');
line_rear_fs(c_max_nr_chans-1 downto g_NR_CHANS) <= (others => '0');
end generate gen_line_unused_chans;
--------------------------------------------------------------------------------
-- Implement the RST_UNLOCK bit
p_rst_unlock : process (clk_20_i)
begin
if rising_edge(clk_20_i) then
if (rst_20_n = '0') then
if rst_20_n = '0' then
rst_unlock <= '0';
elsif (rst_unlock_bit_ld = '1') then
if (rst_unlock_bit = '1') then
elsif rst_unlock_bit_ld = '1' then
if rst_unlock_bit = '1' then
rst_unlock <= '1';
else
rst_unlock <= '0';
......@@ -1285,7 +1223,7 @@ end generate gen_line_unused_chans;
p_rst_fr_reg : process (clk_20_i)
begin
if rising_edge(clk_20_i) then
if (rst_20_n = '0') then
if rst_20_n = '0' then
rst_fr_reg <= '0';
elsif (rst_bit_ld = '1') and (rst_bit = '1') and (rst_unlock = '1') then
rst_fr_reg <= '1';
......@@ -1300,14 +1238,14 @@ end generate gen_line_unused_chans;
p_err_pmisse_bit : process (clk_20_i)
begin
if rising_edge(clk_20_i) then
for i in 0 to g_nr_chans-1 loop
if (rst_20_n = '0') then
for i in 0 to g_NR_CHANS-1 loop
if rst_20_n = '0' then
flim_pmisse_bit(i) <= '0';
fwdg_pmisse_bit (i)<= '0';
fwdg_pmisse_bit (i) <= '0';
pmisse_bit(i) <= '0';
elsif (pmisse_p(i) = '1') then
elsif pmisse_p(i) = '1' then
if flim_pmisse_p (i) = '1' then
flim_pmisse_bit(i)<= '1';
flim_pmisse_bit(i) <= '1';
end if;
if fwdg_pmisse_p (i) = '1' then
fwdg_pmisse_bit(i) <= '1';
......@@ -1327,35 +1265,33 @@ end generate gen_line_unused_chans;
-- Create an OR of all PMISSE bits
pmisse_bits_or <= '0' when (pmisse_bit = (pmisse_bit'range => '0')) else
pmisse_bits_or <= '0' when pmisse_bit = (pmisse_bit'range => '0') else
'1';
--------------------------------------------------------------------------------
-- Set the rest of the PMISSE bits to zero when g_nr_chans < c_max_nr_chans
gen_pmisse_unused_chans : if (g_nr_chans < c_max_nr_chans) generate
pmisse_bit(c_max_nr_chans-1 downto g_nr_chans) <= (others => '0');
end generate;
-- Set the rest of the PMISSE bits to zero when g_NR_CHANS < c_max_nr_chans
gen_pmisse_unused_chans : if g_NR_CHANS < c_max_nr_chans generate
pmisse_bit(c_max_nr_chans-1 downto g_NR_CHANS) <= (others => '0');
end generate gen_pmisse_unused_chans;
--------------------------------------------------------------------------------
-- Synchronize WR valid signal to implement the WRPRES bit
cmp_wrpres_sync : gc_sync_ffs
generic map
(
g_sync_edge => "positive"
)
g_sync_edge => "positive")
port map
(
clk_i => clk_20_i,
rst_n_i => rst_20_n,
data_i => buf_wrtag,
synced_o => wrpres
);
synced_o => wrpres);
-- Implement the TBCSR.CLR bit
p_tbcsr_clr : process (clk_20_i)
begin
if rising_edge(clk_20_i) then
if (rst_20_n = '0') then
if rst_20_n = '0' then
buf_clr_p <= '0';
else
buf_clr_p <= '0';
......@@ -1373,8 +1309,8 @@ end generate;
p_lts_125 : process (clk_125)
begin
if rising_edge(clk_125) then
for i in 0 to g_nr_chans-1 loop
if (rst_125_n = '0') then
for i in 0 to g_NR_CHANS-1 loop
if rst_125_n = '0' then
lts_cycles_125(i) <= (others => '0');
lts_tai_125(i) <= (others => '0');
lts_wrtag_125(i) <= '0';
......@@ -1389,10 +1325,9 @@ end generate;
end process p_lts_125;
-- Pulse synchronizer: sync. lts_ld from 125 MHz to 20MHz domain
gen_lts_ld_pulse_sync : for i in 0 to g_nr_chans-1 generate
gen_lts_ld_pulse_sync : for i in 0 to g_NR_CHANS-1 generate
cmp_pulse_sync : gc_pulse_synchronizer2
port map
(
port map(
clk_in_i => clk_125,
rst_in_n_i => rst_125_n,
......@@ -1402,20 +1337,19 @@ gen_lts_ld_pulse_sync : for i in 0 to g_nr_chans-1 generate
d_ready_o => lts_ld_rdy_125(i),
d_p_i => lts_ld_125(i),
q_p_o => lts_ld_20(i)
);
end generate gen_lts_ld_pulse_sync;
q_p_o => lts_ld_20(i));
end generate gen_lts_ld_pulse_sync;
-- Latest timestamp regs in 20MHz clock domain
p_lts_20 : process (clk_20_i)
begin
if rising_edge(clk_20_i) then
for i in 0 to g_nr_chans-1 loop
if (rst_20_n = '0') then
for i in 0 to g_NR_CHANS-1 loop
if rst_20_n = '0' then
lts_cycles_20(i) <= (others => '0');
lts_tai_20(i) <= (others => '0');
lts_wrtag_20(i) <= '0';
elsif (lts_ld_20(i) = '1') then
elsif lts_ld_20(i) = '1' then
lts_cycles_20(i) <= lts_cycles_125(i);
lts_tai_20(i) <= lts_tai_125(i);
lts_wrtag_20(i) <= lts_wrtag_125(i);
......@@ -1426,20 +1360,17 @@ end generate gen_lts_ld_pulse_sync;
--------------------------------------------------------------------------------
-- Connect unused timestamps to all zeroes
gen_latest_timestamp_unused_chans : if (g_nr_chans < c_max_nr_chans) generate
lts_ld_125(c_max_nr_chans-1 downto g_nr_chans) <= (others => '0');
lts_ld_rdy_125(c_max_nr_chans-1 downto g_nr_chans) <= (others => '0');
lts_cycles_125(c_max_nr_chans-1 downto g_nr_chans) <= (others => (others => '0'));
lts_tai_125(c_max_nr_chans-1 downto g_nr_chans) <= (others => (others => '0'));
lts_wrtag_125(c_max_nr_chans-1 downto g_nr_chans) <= (others => '0');
lts_ld_20(c_max_nr_chans-1 downto g_nr_chans) <= (others => '0');
lts_cycles_20(c_max_nr_chans-1 downto g_nr_chans) <= (others => (others => '0'));
lts_tai_20(c_max_nr_chans-1 downto g_nr_chans) <= (others => (others => '0'));
lts_wrtag_20(c_max_nr_chans-1 downto g_nr_chans) <= (others => '0');
end generate gen_latest_timestamp_unused_chans;
gen_latest_timestamp_unused_chans : if g_NR_CHANS < c_max_nr_chans generate
lts_ld_125(c_max_nr_chans-1 downto g_NR_CHANS) <= (others => '0');
lts_ld_rdy_125(c_max_nr_chans-1 downto g_NR_CHANS) <= (others => '0');
lts_cycles_125(c_max_nr_chans-1 downto g_NR_CHANS) <= (others => (others => '0'));
lts_tai_125(c_max_nr_chans-1 downto g_NR_CHANS) <= (others => (others => '0'));
lts_wrtag_125(c_max_nr_chans-1 downto g_NR_CHANS) <= (others => '0');
lts_ld_20(c_max_nr_chans-1 downto g_NR_CHANS) <= (others => '0');
lts_cycles_20(c_max_nr_chans-1 downto g_NR_CHANS) <= (others => (others => '0'));
lts_tai_20(c_max_nr_chans-1 downto g_NR_CHANS) <= (others => (others => '0'));
lts_wrtag_20(c_max_nr_chans-1 downto g_NR_CHANS) <= (others => '0');
end generate gen_latest_timestamp_unused_chans;
--------------------------------------------------------------------------------
-- Then, instantiate the component
......@@ -1448,19 +1379,19 @@ end generate gen_latest_timestamp_unused_chans;
rst_n_i => rst_20_n,
clk_sys_i => clk_20_i,
wb_adr_i => xbar_master_out(c_slv_conv_regs).adr(7 downto 2),
wb_dat_i => xbar_master_out(c_slv_conv_regs).dat,
wb_dat_o => xbar_master_in (c_slv_conv_regs).dat,
wb_cyc_i => xbar_master_out(c_slv_conv_regs).cyc,
wb_sel_i => xbar_master_out(c_slv_conv_regs).sel,
wb_stb_i => xbar_master_out(c_slv_conv_regs).stb,
wb_we_i => xbar_master_out(c_slv_conv_regs).we,
wb_ack_o => xbar_master_in (c_slv_conv_regs).ack,
wb_stall_o => xbar_master_in (c_slv_conv_regs).stall,
wb_adr_i => xbar_master_out(c_SLV_CONV_REGS).adr(7 downto 2),
wb_dat_i => xbar_master_out(c_SLV_CONV_REGS).dat,
wb_dat_o => xbar_master_in (c_SLV_CONV_REGS).dat,
wb_cyc_i => xbar_master_out(c_SLV_CONV_REGS).cyc,
wb_sel_i => xbar_master_out(c_SLV_CONV_REGS).sel,
wb_stb_i => xbar_master_out(c_SLV_CONV_REGS).stb,
wb_we_i => xbar_master_out(c_SLV_CONV_REGS).we,
wb_ack_o => xbar_master_in (c_SLV_CONV_REGS).ack,
wb_stall_o => xbar_master_in (c_SLV_CONV_REGS).stall,
reg_bidr_i => g_board_id,
reg_bidr_i => g_BOARD_ID,
reg_sr_gwvers_i => g_gwvers,
reg_sr_gwvers_i => g_GWVERS,
reg_sr_switches_i => sw_gp_i,
reg_sr_rtm_i => rtm_lines,
reg_sr_hwvers_i => hwvers_i,
......@@ -1594,8 +1525,8 @@ end generate gen_latest_timestamp_unused_chans;
(
clk_i => clk_20_i,
rst_n_i => rst_20_n,
wbs_i => xbar_master_out(c_slv_multiboot),
wbs_o => xbar_master_in(c_slv_multiboot),
wbs_i => xbar_master_out(c_SLV_MULTIBOOT),
wbs_o => xbar_master_in(c_SLV_MULTIBOOT),
spi_cs_n_o => flash_cs_n_o,
spi_sclk_o => flash_sclk_o,
spi_mosi_o => flash_mosi_o,
......@@ -1606,11 +1537,11 @@ end generate gen_latest_timestamp_unused_chans;
-- On-board DS18B20 Thermometer logic
--============================================================================
--------------------------------------------------------------------------------
gen_thermometer : if (g_with_thermometer = true) generate
--The one-wire interface component is used to read-out the on-board DS18B20
gen_thermometer : if g_WITH_THERMOMETER = true generate
-- The one-wire interface component is used to read-out the on-board DS18B20
-- unique ID and temperature
cmp_onewire: gc_ds182x_interface
cmp_onewire : gc_ds182x_interface
generic map (freq => 20)
port map
(clk_i => clk_20_i,
......@@ -1620,12 +1551,11 @@ end generate gen_latest_timestamp_unused_chans;
id_o => tmp_id,
temper_o => tmp_temper,
id_read_o => onewire_read_p,
id_ok_o => open
);
end generate gen_thermometer;
id_ok_o => open);
end generate gen_thermometer;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- pps generator based on the 20 MHz clk
cmp_pps_gen: wf_decr_counter
cmp_pps_gen : wf_decr_counter
generic map(
g_counter_lgth => 25
)
......@@ -1641,17 +1571,17 @@ end generate gen_thermometer;
rst_20 <= not rst_20_n;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- registering of the read values
reg_reading: process(clk_20_i)
reg_reading : process(clk_20_i)
begin
if rising_edge(clk_20_i) then
temper <= (others => '0');
id <= (others => '0');
if(onewire_read_p = '1') then
if onewire_read_p = '1' then
temper <= tmp_temper;
id <= tmp_id;
end if;
end if;
end process;
end process reg_reading;
......@@ -1662,8 +1592,8 @@ end generate gen_thermometer;
cmp_bicolor_led_ctrl : gc_bicolor_led_ctrl
generic map
(
g_NB_COLUMN => g_bicolor_led_columns,
g_NB_LINE => g_bicolor_led_lines,
g_NB_COLUMN => g_BICOLOR_LED_COLUMNS,
g_NB_LINE => g_BICOLOR_LED_LINES,
g_clk_freq => 20000000,
g_refresh_rate => 250
)
......
top/conv_common_gw_pkg.vhd
View file @ 0226eb67
--==============================================================================
--------------------------------------------------------------------------------
-- CERN (BE-CO-HT)
-- Converter board common gateware package
--==============================================================================
-- URL https://www.ohwr.org/projects/conv-common-gw/wiki/wiki
--------------------------------------------------------------------------------
--
-- Converter common gateware package
-- Description: Package for conv_common_gw entity
--
--
-- date of creation: 2014-08-01
--
-- version: 1.0
--
-- description:
--
-- dependencies:
--
-- references:
--
--------------------------------------------------------------------------------
-- Copyright (c) 2018 CERN
--------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
-- GNU LESSER GENERAL PUBLIC LICENSE
--------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
......@@ -27,15 +21,8 @@
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--==============================================================================
-- last changes:
-- 2014-08-01 Theodor Stana File created
-- 2016-11 Denia Bouhired Added component for dynamic burst control module
-- 2016-12-20 Denia Bouhired Modified port list of conv_regs
-- 2017-01-23 Denia Bouhired Modified conv_common_gw, added array type for thermal model
--==============================================================================
-- TODO: -
--==============================================================================
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
......@@ -54,12 +41,12 @@ package conv_common_gw_pkg is
-- Note that if you change this constant you will make conv-common-gw
-- _incompatible_ with BLO and RS-485 pulse repeaters and you will need to
-- _reimplement_ the conv_regs module
constant c_max_nr_chans : natural := 6;
--============================================================================
--Type declarations
--============================================================================
constant c_MAX_NR_CHANS : natural := 6;
-- ============================================================================
-- Type declarations
-- ============================================================================
--Array of constants for temperature model implemented for short pulse mode
-- Array of constants for temperature model implemented for short pulse mode
type t_temp_decre_step is array (0 to 15) of integer;
--============================================================================
......@@ -69,97 +56,93 @@ package conv_common_gw_pkg is
-- Top-level module
------------------------------------------------------------------------------
component conv_common_gw is
generic
(
generic (
-- Reduces some timeouts to speed up simulations
g_SIMUL : boolean := false;
-- Reset time: 50ns * 2 * (10**6) = 100 ms
g_RST_TIME : positive := 2*(10**6);
-- Number of repeater channels
g_nr_chans : integer := 6;
g_nr_inv_chans : integer := 4;
g_NR_CHANS : integer := 6;
-- Number of inverter channels
g_NR_INV_CHANS : integer := 4;
-- Board ID -- 4-letter ASCII string indicating the board ID
-- see [1] for example
g_board_id : std_logic_vector(31 downto 0);
g_BOARD_ID : std_logic_vector(31 downto 0) := x"54424c4f";
-- Gateware version
g_gwvers : std_logic_vector(7 downto 0);
g_GWVERS : std_logic_vector(7 downto 0) := x"40";
-- Generate pulse repetition logic with fixed output pulse width
g_pgen_fixed_width : boolean;
g_PGEN_FIXED_WIDTH : boolean := true;
-- Pulse width at pulse generator output (valid with fixed output pulse width)
g_pgen_pwidth_lg : natural range 2 to 40 := 24; --**DB: was 20 to 40
g_pgen_pwidth_sh : natural range 2 to 40 := 5;
-- output pulse will be limited to pulse period
g_pgen_pperiod_cont : natural range 2 to 5000 := 4800; --For continuous mode operation max freq 4.12kHz
g_pgen_pperiod_lg : natural range 6 to 300 := 191; --for LONG pulses changes maximum
g_pgen_pperiod_sh : natural range 2 to 300 := 9; --for SHORT pulses changes maximum
g_PGEN_PWIDTH_LG : natural range 2 to 40 := 24;
g_PGEN_PWIDTH_SH : natural range 2 to 40 := 5;
-- Output pulse will be limited to period. They are given as n number of cycles
-- For continuous mode operation max freq 4.16kHz
g_PGEN_PPERIOD_CONT : natural range 2 to 5000 := 4800;
-- for LONG pulses changes maximum frequency to ~104kHz
g_PGEN_PPERIOD_LG : natural range 6 to 300 := 191;
-- for SHORT pulses changes maximum frequency to ~2MHz
g_PGEN_PPERIOD_SH : natural range 2 to 300 := 9;
-- Pulse generator glitch filter length in number of clk_20_i cycles
g_pgen_gf_len : integer := 4;
g_PGEN_GF_LEN : integer := 4;
-- Burst-mode-specific generics:
g_temp_decre_step_lg : t_temp_decre_step :=(0,0,0,0,0,0,0,0,5750,100,79,13,12,4,5,13);
g_temp_decre_step_sh : t_temp_decre_step :=(0, 0, 769, 31, 104, 14, 82, 0 ,0, 0, 0, 0, 0, 0, 0, 0);
-- Temperature rise resulting from 250ns pulse
g_burstctrl_1_pulse_temp_rise_lg :in unsigned (19 downto 0) := x"17700"; -- Check every "g_eval_burst_len" pulses
g_burstctrl_1_pulse_temp_rise_sh :in unsigned (19 downto 0) := x"01388"; --For short 250ns pulses
g_TEMP_DECRE_STEP_LG : t_temp_decre_step :=
(0,0,0,0,0,0,0,0,5750,100,79,13,12,4,5,13);
g_TEMP_DECRE_STEP_SH : t_temp_decre_step :=
(0,0,769,31,104,14,82,0,0,0,0,0,0,0,0,0);
-- Single pulse temperature rise for long 1.2us pulses
g_BURSTCTRL_1_PULSE_TEMP_RISE_LG
: in unsigned (19 downto 0) := x"17700";
-- Single pulse temperature rise for short 250ns pulses
g_BURSTCTRL_1_PULSE_TEMP_RISE_SH
: in unsigned (19 downto 0) := x"01388";
-- Maximum temperature allowed (scaled)
g_burstctrl_max_temp_lg_sh :in unsigned (39 downto 0) := x"02540BE400";
-- Generate logic with pulse counters
g_with_pulse_cnt : boolean := false;
-- For both long 1.2us pulses and short 250ns
g_BURSTCTRL_MAX_TEMP_LG_SH
: in unsigned (39 downto 0) := x"02540BE400";
-- Generate logic with pulse counters
g_with_pulse_timetag : boolean := false;
g_WITH_PULSE_CNT : boolean := false;
-- Generate logic with pulse timetag
g_WITH_PULSE_TIMETAG : boolean := false;
-- Generate logic with manual trigger
g_with_man_trig : boolean := false;
g_man_trig_pwidth : integer := 24;
g_WITH_MAN_TRIG : boolean := false;
g_MAN_TRIG_PWIDTH : integer := 24;
-- Generate one-wire master for thermometer
g_with_thermometer : boolean := false;
g_WITH_THERMOMETER : boolean := false;
-- Bicolor LED controller signals
g_bicolor_led_columns : integer := 6;
g_bicolor_led_lines : integer := 2
);
port
(
g_BICOLOR_LED_COLUMNS : integer := 6;
g_BICOLOR_LED_LINES : integer := 2);
port (
-- Clocks
clk_20_i : in std_logic;
clk_125_p_i : in std_logic;
clk_125_n_i : in std_logic;
-- Reset output signal, synchronous to 20 MHz clock
rst_n_o : out std_logic;
-- Glitch filter active-low enable signal
gf_en_n_i : in std_logic;
-- Burst mode enable signal. Mode disabled for all versions of board
burst_en_n_i : in std_logic;
-- Pulse width selection, port low means 250ns, high means 1.2us.
-- Pulse width selection, port low means 250ns, high means 1.2us
pulse_width_sel_n_i : in std_logic;
-- Channel enable
global_ch_oen_o : out std_logic;
pulse_front_oen_o : out std_logic;
pulse_rear_oen_o : out std_logic;
inv_oen_o : out std_logic;
-- Pulse inputs
pulse_i : in std_logic_vector(g_nr_chans-1 downto 0);
pulse_front_i : in std_logic_vector(g_nr_chans-1 downto 0);
pulse_rear_i : in std_logic_vector(g_nr_chans-1 downto 0);
pulse_o : out std_logic_vector(g_nr_chans-1 downto 0);
-- Channel leds
-- Pulse I/O
pulse_i : in std_logic_vector(g_NR_CHANS-1 downto 0);
pulse_front_i : in std_logic_vector(g_NR_CHANS-1 downto 0);
pulse_rear_i : in std_logic_vector(g_NR_CHANS-1 downto 0);
pulse_o : out std_logic_vector(g_NR_CHANS-1 downto 0);
-- Inverted pulse I/O
inv_pulse_n_i : in std_logic_vector(g_NR_INV_CHANS-1 downto 0);
inv_pulse_o : out std_logic_vector(g_NR_INV_CHANS-1 downto 0);
-- Channel lEDs
-- 26 ms active-high pulse on pulse_o rising edge
inv_pulse_i_n : in std_logic_vector(g_nr_inv_chans-1 downto 0);
inv_pulse_o : out std_logic_vector(g_nr_inv_chans-1 downto 0);
led_pulse_o : out std_logic_vector(g_nr_chans-1 downto 0);
led_inv_pulse_o : out std_logic_vector(g_nr_inv_chans-1 downto 0);
led_pulse_o : out std_logic_vector(g_NR_CHANS-1 downto 0);
-- Inverted channel lEDs
-- 26 ms active-high pulse on pulse_o rising edge
led_inv_pulse_o : out std_logic_vector(g_NR_INV_CHANS-1 downto 0);
-- I2C interface
scl_i : in std_logic;
scl_o : out std_logic;
......@@ -167,23 +150,18 @@ package conv_common_gw_pkg is
sda_i : in std_logic;
sda_o : out std_logic;
sda_en_o : out std_logic;
-- I2C LED signals -- conect to a bicolor LED of choice
-- led_i2c_o pulses four times on I2C transfer
-- led_i2c_err_o is high when either SR.I2C_ERR = '1' or SR.I2C_WDTO = '1'
led_i2c_o : out std_logic;
-- VME interface
vme_sysreset_n_i : in std_logic;
vme_ga_i : in std_logic_vector(4 downto 0);
vme_gap_i : in std_logic;
-- SPI interface to on-board flash chip
flash_cs_n_o : out std_logic;
flash_sclk_o : out std_logic;
flash_mosi_o : out std_logic;
flash_miso_i : in std_logic;
-- PLL DACs
-- 20 MHz VCXO control
dac20_din_o : out std_logic;
......@@ -193,7 +171,6 @@ package conv_common_gw_pkg is
dac125_din_o : out std_logic;
dac125_sclk_o : out std_logic;
dac125_sync_n_o : out std_logic;
-- SFP lines
sfp_los_i : in std_logic;
sfp_present_i : in std_logic;
......@@ -202,41 +179,32 @@ package conv_common_gw_pkg is
sfp_scl_b : inout std_logic;
sfp_tx_disable_o : out std_logic;
sfp_tx_fault_i : in std_logic;
-- Switch inputs (for readout from converter status register)
sw_gp_i : in std_logic_vector(7 downto 0);
sw_other_i : in std_logic_vector(31 downto 0);
-- PCB Version information
hwvers_i : in std_logic_vector (5 downto 0);
-- RTM lines
rtmm_i : in std_logic_vector(2 downto 0);
rtmp_i : in std_logic_vector(2 downto 0);
-- TTL, INV-TTL and rear-panel channel inputs, for reflection in line status register
line_front_i : in std_logic_vector(g_nr_chans-1 downto 0);
line_inv_i : in std_logic_vector(3 downto 0);
line_rear_i : in std_logic_vector(g_nr_chans-1 downto 0);
line_front_i : in std_logic_vector(g_NR_CHANS-1 downto 0);
line_inv_i : in std_logic_vector(g_NR_INV_CHANS-1 downto 0);
line_rear_i : in std_logic_vector(g_NR_CHANS-1 downto 0);
-- Fail-safe lines, detect invalid or no signal on channel input
line_front_fs_i : in std_logic_vector(g_nr_chans-1 downto 0);
line_inv_fs_i : in std_logic_vector(3 downto 0);
line_rear_fs_i : in std_logic_vector(g_nr_chans-1 downto 0);
line_front_fs_i : in std_logic_vector(g_NR_CHANS-1 downto 0);
line_inv_fs_i : in std_logic_vector(g_NR_INV_CHANS-1 downto 0);
line_rear_fs_i : in std_logic_vector(g_NR_CHANS-1 downto 0);
-- Thermometer line
thermometer_b : inout std_logic;
-- System error LED, active-high on system error
-- ERR bicolor LED should light red when led_syserr_o = '1'
led_syserr_o : out std_logic;
-- Bicolor LED signals
bicolor_led_state_i : in std_logic_vector(2*g_bicolor_led_columns*g_bicolor_led_lines-1 downto 0);
bicolor_led_col_o : out std_logic_vector(g_bicolor_led_columns-1 downto 0);
bicolor_led_line_o : out std_logic_vector(g_bicolor_led_lines-1 downto 0);
bicolor_led_line_oen_o : out std_logic_vector(g_bicolor_led_lines-1 downto 0)
);
bicolor_led_state_i : in std_logic_vector(2*g_BICOLOR_LED_COLUMNS*g_BICOLOR_LED_LINES-1 downto 0);
bicolor_led_col_o : out std_logic_vector(g_BICOLOR_LED_COLUMNS-1 downto 0);
bicolor_led_line_o : out std_logic_vector(g_BICOLOR_LED_LINES-1 downto 0);
bicolor_led_line_oen_o : out std_logic_vector(g_BICOLOR_LED_LINES-1 downto 0));
end component conv_common_gw;
------------------------------------------------------------------------------
......@@ -246,7 +214,7 @@ package conv_common_gw_pkg is
generic
(
-- Reset time in number of clk_i cycles
g_reset_time : positive := 2_000_000
g_RESET_TIME : positive := 2_000_000
);
port
(
......@@ -257,16 +225,18 @@ package conv_common_gw_pkg is
end component conv_reset_gen;
------------------------------------------------------------------------------
-- Pulse counter - Used for scenarios where clocks are shorter than the time it takes to synchronise them (Normally it taked 3 clk cycles to synchronise trigger edge.)
-- Pulse counter - Used for scenarios where clocks are shorter than the time
-- it takes to synchronise them (Normally it taked 3 clk cycles to synchronise
-- trigger edge.)
------------------------------------------------------------------------------
component fastevent_counter is
port
(sysclk_i : in std_logic;
port(
sysclk_i : in std_logic;
rstcount_i : in std_logic;
en_i : in std_logic;
trig_i : in std_logic;
count_o : out std_logic_vector(31 downto 0);
count_int_o: out unsigned(31 downto 0)
count_int_o : out unsigned(31 downto 0)
);
end component fastevent_counter;
......@@ -278,16 +248,16 @@ package conv_common_gw_pkg is
generic
(
-- This generic enables elaboration of the fixed pulse width logic
g_with_fixed_pwidth : boolean;
g_WITH_FIXED_PWIDTH : boolean;
-- Pulse width, in number of clk_i cycles
-- Default pulse width (20 MHz clock): 1.2 us
-- Minimum allowable pulse width (20 MHz clock): 1 us
-- Maximum allowable pulse width (20 MHz clock): 2 us
g_pwidth : natural range 2 to 40 := 24; --DB was 20 to 40
g_PWIDTH : natural range 2 to 40 := 24;
-- Pulse period in unit of clock cycles
g_pperiod : natural := 5
g_PPERIOD : natural := 5
);
port
(
......@@ -306,8 +276,8 @@ package conv_common_gw_pkg is
-- Trigger input, has to be '1' to assure pulse output with delay no greater
-- than internal gate delays.
trig_a_i : in std_logic;
trig_r_edge_p_i : in std_logic; --synced 1 cycle-long r edge output
trig_f_edge_p_i : in std_logic; --synced 1 cycle-long f edge output
trig_r_edge_p_i : in std_logic; -- synced 1 cycle-long r edge output
trig_f_edge_p_i : in std_logic; -- synced 1 cycle-long f edge output
-- Pulse error output, pulses high for one clock cycle when a pulse arrives
......@@ -319,7 +289,7 @@ package conv_common_gw_pkg is
-- glitch filter disabled: none
-- glitch filter enabled: glitch filter length + 5 clk_i cycles
pulse_o : out std_logic;
pulse_r_edge_p_o : out std_logic; --synced 1 cycle-long r edge output
pulse_r_edge_p_o : out std_logic; -- synced 1 cycle-long r edge output
pulse_f_edge_p_o : out std_logic
);
end component conv_pulse_gen;
......@@ -329,21 +299,19 @@ package conv_common_gw_pkg is
------------------------------------------------------------------------------
component conv_dyn_burst_ctrl is
generic
(
generic (
-- Short pulse width, in number of clk_i cycles
-- Default short pulse width (20 MHz clock): 250 ns = 5 clk cycles
g_pwidth : natural range 2 to 40 := 5;
g_PWIDTH : natural range 2 to 40 := 5;
-- Thermal model constants, depend on mode selected short or long.
g_temp_decre_step : t_temp_decre_step;
g_TEMP_DECRE_STEP : t_temp_decre_step;
-- Temperature rise resulting from with 250ns pulse
g_1_pulse_temp_rise :in unsigned (19 downto 0); -- Check every "g_eval_burst_len" pulses
g_1_PULSE_TEMP_RISE : in unsigned (19 downto 0); -- Check every "g_eval_burst_len" pulses
-- Maximum temperature allowed (scaled)
g_max_temp :in unsigned (39 downto 0) := x"174876E800"
g_MAX_TEMP : in unsigned (39 downto 0) := x"174876E800"
);
port
(
port (
-- Clock and active-low reset inputs
clk_i : in std_logic;
rst_n_i : in std_logic;
......@@ -355,15 +323,13 @@ package conv_common_gw_pkg is
pulse_f_edge_p_i : in std_logic;
-- Temp_rise is output for external probing
temp_rise_o : out unsigned (39 downto 0) ;
temp_rise_o : out unsigned (39 downto 0);
-- Dynamic temperature-controlled ouput pulse train.
pulse_burst_o : out std_logic;
-- Burst error output, pulses high for one clock cycle when a pulse arrives
-- within a burst rejection phase
burst_err_p_o : out std_logic
);
burst_err_p_o : out std_logic);
end component conv_dyn_burst_ctrl;
------------------------------------------------------------------------------
......@@ -382,195 +348,194 @@ package conv_common_gw_pkg is
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
-- Port for std_logic_vector field: 'ID register bits' in reg: 'BIDR'
-- Port for std_logic_vector field: 'ID register bits' in reg: 'BIDR'
reg_bidr_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Gateware version' in reg: 'SR'
-- Port for std_logic_vector field: 'Gateware version' in reg: 'SR'
reg_sr_gwvers_i : in std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'Status of on-board general-purpose switches' in reg: 'SR'
-- Port for std_logic_vector field: 'Status of on-board general-purpose switches' in reg: 'SR'
reg_sr_switches_i : in std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'RTM detection lines cite{rtm-det}' in reg: 'SR'
-- Port for std_logic_vector field: 'RTM detection lines cite{rtm-det}' in reg: 'SR'
reg_sr_rtm_i : in std_logic_vector(5 downto 0);
-- Port for std_logic_vector field: 'Hardware version' in reg: 'SR'
-- Port for std_logic_vector field: 'Hardware version' in reg: 'SR'
reg_sr_hwvers_i : in std_logic_vector(5 downto 0);
-- Port for BIT field: 'White Rabbit present' in reg: 'SR'
-- Port for BIT field: 'White Rabbit present' in reg: 'SR'
reg_sr_wrpres_i : in std_logic;
-- Ports for BIT field: 'I2C communication watchdog timeout error' in reg: 'ERR'
-- Ports for BIT field: 'I2C communication watchdog timeout error' in reg: 'ERR'
reg_err_i2c_wdto_o : out std_logic;
reg_err_i2c_wdto_i : in std_logic;
reg_err_i2c_wdto_load_o : out std_logic;
-- Ports for BIT field: 'I2C communication error' in reg: 'ERR'
-- Ports for BIT field: 'I2C communication error' in reg: 'ERR'
reg_err_i2c_err_o : out std_logic;
reg_err_i2c_err_i : in std_logic;
reg_err_i2c_err_load_o : out std_logic;
-- Port for std_logic_vector field: 'Frequency error' in reg: 'ERR'
-- Port for std_logic_vector field: 'Frequency error' in reg: 'ERR'
reg_err_flim_pmisse_o : out std_logic_vector(5 downto 0);
reg_err_flim_pmisse_i : in std_logic_vector(5 downto 0);
reg_err_flim_pmisse_load_o : out std_logic;
-- Port for std_logic_vector field: 'Frequency watchdog error' in reg: 'ERR'
-- Port for std_logic_vector field: 'Frequency watchdog error' in reg: 'ERR'
reg_err_fwdg_pmisse_o : out std_logic_vector(5 downto 0);
reg_err_fwdg_pmisse_i : in std_logic_vector(5 downto 0);
reg_err_fwdg_pmisse_load_o : out std_logic;
-- Ports for BIT field: 'Reset unlock bit' in reg: 'CR'
-- Ports for BIT field: 'Reset unlock bit' in reg: 'CR'
reg_cr_rst_unlock_o : out std_logic;
reg_cr_rst_unlock_i : in std_logic;
reg_cr_rst_unlock_load_o : out std_logic;
-- Ports for BIT field: 'Reset bit - active only if RST_UNLOCK is 1' in reg: 'CR'
-- Ports for BIT field: 'Reset bit - active only if RST_UNLOCK is 1' in reg: 'CR'
reg_cr_rst_o : out std_logic;
reg_cr_rst_i : in std_logic;
reg_cr_rst_load_o : out std_logic;
-- Ports for PASS_THROUGH field: 'Manual Pulse Trigger' in reg: 'CR'
-- Ports for PASS_THROUGH field: 'Manual Pulse Trigger' in reg: 'CR'
reg_cr_mpt_o : out std_logic_vector(7 downto 0);
reg_cr_mpt_wr_o : out std_logic;
-- Port for std_logic_vector field: 'Value of front panel pulse counter' in reg: 'CH1FPPCR'
-- Port for std_logic_vector field: 'Value of front panel pulse counter' in reg: 'CH1FPPCR'
reg_ch1fppcr_o : out std_logic_vector(31 downto 0);
reg_ch1fppcr_i : in std_logic_vector(31 downto 0);
reg_ch1fppcr_load_o : out std_logic;
-- Port for std_logic_vector field: 'Value of front panel pulse counter' in reg: 'CH2FPPCR'
-- Port for std_logic_vector field: 'Value of front panel pulse counter' in reg: 'CH2FPPCR'
reg_ch2fppcr_o : out std_logic_vector(31 downto 0);
reg_ch2fppcr_i : in std_logic_vector(31 downto 0);
reg_ch2fppcr_load_o : out std_logic;
-- Port for std_logic_vector field: 'Value of front panel pulse counter' in reg: 'CH3FPPCR'
-- Port for std_logic_vector field: 'Value of front panel pulse counter' in reg: 'CH3FPPCR'
reg_ch3fppcr_o : out std_logic_vector(31 downto 0);
reg_ch3fppcr_i : in std_logic_vector(31 downto 0);
reg_ch3fppcr_load_o : out std_logic;
-- Port for std_logic_vector field: 'Value of front panel pulse counter' in reg: 'CH4FPPCR'
-- Port for std_logic_vector field: 'Value of front panel pulse counter' in reg: 'CH4FPPCR'
reg_ch4fppcr_o : out std_logic_vector(31 downto 0);
reg_ch4fppcr_i : in std_logic_vector(31 downto 0);
reg_ch4fppcr_load_o : out std_logic;
-- Port for std_logic_vector field: 'Value of front panel pulse counter' in reg: 'CH5FPPCR'
-- Port for std_logic_vector field: 'Value of front panel pulse counter' in reg: 'CH5FPPCR'
reg_ch5fppcr_o : out std_logic_vector(31 downto 0);
reg_ch5fppcr_i : in std_logic_vector(31 downto 0);
reg_ch5fppcr_load_o : out std_logic;
-- Port for std_logic_vector field: 'Value of front panel pulse counter' in reg: 'CH6FPPCR'
-- Port for std_logic_vector field: 'Value of front panel pulse counter' in reg: 'CH6FPPCR'
reg_ch6fppcr_o : out std_logic_vector(31 downto 0);
reg_ch6fppcr_i : in std_logic_vector(31 downto 0);
reg_ch6fppcr_load_o : out std_logic;
-- Port for std_logic_vector field: 'Rear panel pulse counter value' in reg: 'CH1RPPCR'
-- Port for std_logic_vector field: 'Rear panel pulse counter value' in reg: 'CH1RPPCR'
reg_ch1rppcr_o : out std_logic_vector(31 downto 0);
reg_ch1rppcr_i : in std_logic_vector(31 downto 0);
reg_ch1rppcr_load_o : out std_logic;
-- Port for std_logic_vector field: 'Rear panel pulse counter value' in reg: 'CH2RPPCR'
-- Port for std_logic_vector field: 'Rear panel pulse counter value' in reg: 'CH2RPPCR'
reg_ch2rppcr_o : out std_logic_vector(31 downto 0);
reg_ch2rppcr_i : in std_logic_vector(31 downto 0);
reg_ch2rppcr_load_o : out std_logic;
-- Port for std_logic_vector field: 'Rear panel pulse counter value' in reg: 'CH3RPPCR'
-- Port for std_logic_vector field: 'Rear panel pulse counter value' in reg: 'CH3RPPCR'
reg_ch3rppcr_o : out std_logic_vector(31 downto 0);
reg_ch3rppcr_i : in std_logic_vector(31 downto 0);
reg_ch3rppcr_load_o : out std_logic;
-- Port for std_logic_vector field: 'Rear panel pulse counter value' in reg: 'CH4RPPCR'
-- Port for std_logic_vector field: 'Rear panel pulse counter value' in reg: 'CH4RPPCR'
reg_ch4rppcr_o : out std_logic_vector(31 downto 0);
reg_ch4rppcr_i : in std_logic_vector(31 downto 0);
reg_ch4rppcr_load_o : out std_logic;
-- Port for std_logic_vector field: 'Rear panel pulse counter value' in reg: 'CH5RPPCR'
-- Port for std_logic_vector field: 'Rear panel pulse counter value' in reg: 'CH5RPPCR'
reg_ch5rppcr_o : out std_logic_vector(31 downto 0);
reg_ch5rppcr_i : in std_logic_vector(31 downto 0);
reg_ch5rppcr_load_o : out std_logic;
-- Port for std_logic_vector field: 'Rear panel pulse counter value' in reg: 'CH6RPPCR'
-- Port for std_logic_vector field: 'Rear panel pulse counter value' in reg: 'CH6RPPCR'
reg_ch6rppcr_o : out std_logic_vector(31 downto 0);
reg_ch6rppcr_i : in std_logic_vector(31 downto 0);
reg_ch6rppcr_load_o : out std_logic;
-- Port for std_logic_vector field: 'TAI seconds counter bits 31..0' in reg: 'TVLR'
-- Port for std_logic_vector field: 'TAI seconds counter bits 31..0' in reg: 'TVLR'
reg_tvlr_o : out std_logic_vector(31 downto 0);
reg_tvlr_i : in std_logic_vector(31 downto 0);
reg_tvlr_load_o : out std_logic;
-- Port for std_logic_vector field: 'TAI seconds counter bits 39..32' in reg: 'TVHR'
-- Port for std_logic_vector field: 'TAI seconds counter bits 39..32' in reg: 'TVHR'
reg_tvhr_o : out std_logic_vector(7 downto 0);
reg_tvhr_i : in std_logic_vector(7 downto 0);
reg_tvhr_load_o : out std_logic;
-- Port for std_logic_vector field: 'Channel mask' in reg: 'TBMR'
-- Port for std_logic_vector field: 'Channel mask' in reg: 'TBMR'
reg_tbmr_chan_i : in std_logic_vector(5 downto 0);
reg_tb_rd_req_p_o : out std_logic;
-- Port for BIT field: 'White Rabbit present' in reg: 'TBMR'
-- Port for BIT field: 'White Rabbit present' in reg: 'TBMR'
reg_tbmr_wrtag_i : in std_logic;
-- Port for std_logic_vector field: 'Cycles counter' in reg: 'TBCYR'
-- Port for std_logic_vector field: 'Cycles counter' in reg: 'TBCYR'
reg_tbcyr_i : in std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'Lower part of TAI seconds counter' in reg: 'TBTLR'
-- Port for std_logic_vector field: 'Lower part of TAI seconds counter' in reg: 'TBTLR'
reg_tbtlr_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Upper part of TAI seconds counter' in reg: 'TBTHR'
-- Port for std_logic_vector field: 'Upper part of TAI seconds counter' in reg: 'TBTHR'
reg_tbthr_i : in std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'Buffer counter' in reg: 'TBCSR'
-- Port for std_logic_vector field: 'Buffer counter' in reg: 'TBCSR'
reg_tbcsr_usedw_i : in std_logic_vector(6 downto 0);
-- Port for BIT field: 'Buffer full' in reg: 'TBCSR'
-- Port for BIT field: 'Buffer full' in reg: 'TBCSR'
reg_tbcsr_full_i : in std_logic;
-- Port for BIT field: 'Buffer empty' in reg: 'TBCSR'
-- Port for BIT field: 'Buffer empty' in reg: 'TBCSR'
reg_tbcsr_empty_i : in std_logic;
-- Ports for BIT field: 'Clear tag buffer' in reg: 'TBCSR'
-- Ports for BIT field: 'Clear tag buffer' in reg: 'TBCSR'
reg_tbcsr_clr_o : out std_logic;
reg_tbcsr_clr_i : in std_logic;
reg_tbcsr_clr_load_o : out std_logic;
-- Port for std_logic_vector field: 'Cycles counter' in reg: 'CH1LTSCYR'
-- Port for std_logic_vector field: 'Cycles counter' in reg: 'CH1LTSCYR'
reg_ch1ltscyr_i : in std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'Lower part of TAI seconds counter' in reg: 'CH1LTSTLR'
-- Port for std_logic_vector field: 'Lower part of TAI seconds counter' in reg: 'CH1LTSTLR'
reg_ch1ltstlr_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Upper part of TAI seconds counter' in reg: 'CH1LTSTHR'
-- Port for std_logic_vector field: 'Upper part of TAI seconds counter' in reg: 'CH1LTSTHR'
reg_ch1ltsthr_tai_i : in std_logic_vector(7 downto 0);
-- Port for BIT field: 'White Rabbit present' in reg: 'CH1LTSTHR'
-- Port for BIT field: 'White Rabbit present' in reg: 'CH1LTSTHR'
reg_ch1ltsthr_wrtag_i : in std_logic;
-- Port for std_logic_vector field: 'Cycles counter' in reg: 'CH2LTSCYR'
-- Port for std_logic_vector field: 'Cycles counter' in reg: 'CH2LTSCYR'
reg_ch2ltscyr_i : in std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'Lower part of TAI seconds counter' in reg: 'CH2LTSTLR'
-- Port for std_logic_vector field: 'Lower part of TAI seconds counter' in reg: 'CH2LTSTLR'
reg_ch2ltstlr_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Upper part of TAI seconds counter' in reg: 'CH2LTSTHR'
-- Port for std_logic_vector field: 'Upper part of TAI seconds counter' in reg: 'CH2LTSTHR'
reg_ch2ltsthr_tai_i : in std_logic_vector(7 downto 0);
-- Port for BIT field: 'White Rabbit present' in reg: 'CH2LTSTHR'
-- Port for BIT field: 'White Rabbit present' in reg: 'CH2LTSTHR'
reg_ch2ltsthr_wrtag_i : in std_logic;
-- Port for std_logic_vector field: 'Cycles counter' in reg: 'CH3LTSCYR'
-- Port for std_logic_vector field: 'Cycles counter' in reg: 'CH3LTSCYR'
reg_ch3ltscyr_i : in std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'Lower part of TAI seconds counter' in reg: 'CH3LTSTLR'
-- Port for std_logic_vector field: 'Lower part of TAI seconds counter' in reg: 'CH3LTSTLR'
reg_ch3ltstlr_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Upper part of TAI seconds counter' in reg: 'CH3LTSTHR'
-- Port for std_logic_vector field: 'Upper part of TAI seconds counter' in reg: 'CH3LTSTHR'
reg_ch3ltsthr_tai_i : in std_logic_vector(7 downto 0);
-- Port for BIT field: 'White Rabbit present' in reg: 'CH3LTSTHR'
-- Port for BIT field: 'White Rabbit present' in reg: 'CH3LTSTHR'
reg_ch3ltsthr_wrtag_i : in std_logic;
-- Port for std_logic_vector field: 'Cycles counter' in reg: 'CH4LTSCYR'
-- Port for std_logic_vector field: 'Cycles counter' in reg: 'CH4LTSCYR'
reg_ch4ltscyr_i : in std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'Lower part of TAI seconds counter' in reg: 'CH4LTSTLR'
-- Port for std_logic_vector field: 'Lower part of TAI seconds counter' in reg: 'CH4LTSTLR'
reg_ch4ltstlr_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Upper part of TAI seconds counter' in reg: 'CH4LTSTHR'
-- Port for std_logic_vector field: 'Upper part of TAI seconds counter' in reg: 'CH4LTSTHR'
reg_ch4ltsthr_tai_i : in std_logic_vector(7 downto 0);
-- Port for BIT field: 'White Rabbit present' in reg: 'CH4LTSTHR'
-- Port for BIT field: 'White Rabbit present' in reg: 'CH4LTSTHR'
reg_ch4ltsthr_wrtag_i : in std_logic;
-- Port for std_logic_vector field: 'Cycles counter' in reg: 'CH5LTSCYR'
-- Port for std_logic_vector field: 'Cycles counter' in reg: 'CH5LTSCYR'
reg_ch5ltscyr_i : in std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'Lower part of TAI seconds counter' in reg: 'CH5LTSTLR'
-- Port for std_logic_vector field: 'Lower part of TAI seconds counter' in reg: 'CH5LTSTLR'
reg_ch5ltstlr_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Upper part of TAI seconds counter' in reg: 'CH5LTSTHR'
-- Port for std_logic_vector field: 'Upper part of TAI seconds counter' in reg: 'CH5LTSTHR'
reg_ch5ltsthr_tai_i : in std_logic_vector(7 downto 0);
-- Port for BIT field: 'White Rabbit present' in reg: 'CH5LTSTHR'
-- Port for BIT field: 'White Rabbit present' in reg: 'CH5LTSTHR'
reg_ch5ltsthr_wrtag_i : in std_logic;
-- Port for std_logic_vector field: 'Cycles counter' in reg: 'CH6LTSCYR'
-- Port for std_logic_vector field: 'Cycles counter' in reg: 'CH6LTSCYR'
reg_ch6ltscyr_i : in std_logic_vector(27 downto 0);
-- Port for std_logic_vector field: 'Lower part of TAI seconds counter' in reg: 'CH6LTSTLR'
-- Port for std_logic_vector field: 'Lower part of TAI seconds counter' in reg: 'CH6LTSTLR'
reg_ch6ltstlr_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Upper part of TAI seconds counter' in reg: 'CH6LTSTHR'
-- Port for std_logic_vector field: 'Upper part of TAI seconds counter' in reg: 'CH6LTSTHR'
reg_ch6ltsthr_tai_i : in std_logic_vector(7 downto 0);
-- Port for BIT field: 'White Rabbit present' in reg: 'CH6LTSTHR'
-- Port for BIT field: 'White Rabbit present' in reg: 'CH6LTSTHR'
reg_ch6ltsthr_wrtag_i : in std_logic;
-- Port for std_logic_vector field: 'Front panel channel input state' in reg: 'LSR'
-- Port for std_logic_vector field: 'Front panel channel input state' in reg: 'LSR'
reg_lsr_front_i : in std_logic_vector(5 downto 0);
-- Port for std_logic_vector field: 'Front panel INV-TTL input state' in reg: 'LSR'
-- Port for std_logic_vector field: 'Front panel INV-TTL input state' in reg: 'LSR'
reg_lsr_frontinv_i : in std_logic_vector(3 downto 0);
-- Port for std_logic_vector field: 'Rear panel input state' in reg: 'LSR'
-- Port for std_logic_vector field: 'Rear panel input state' in reg: 'LSR'
reg_lsr_rear_i : in std_logic_vector(5 downto 0);
-- Port for std_logic_vector field: 'Front panel input failsafe state' in reg: 'LSR'
-- Port for std_logic_vector field: 'Front panel input failsafe state' in reg: 'LSR'
reg_lsr_frontfs_i : in std_logic_vector(5 downto 0);
-- Port for std_logic_vector field: 'Front panel inverter input failsafe state' in reg: 'LSR'
-- Port for std_logic_vector field: 'Front panel inverter input failsafe state' in reg: 'LSR'
reg_lsr_frontinvfs_i : in std_logic_vector(3 downto 0);
-- Port for std_logic_vector field: 'Rear panel input failsafe state' in reg: 'LSR'
-- Port for std_logic_vector field: 'Rear panel input failsafe state' in reg: 'LSR'
reg_lsr_rearfs_i : in std_logic_vector(5 downto 0);
-- Port for std_logic_vector field: 'Switch state' in reg: 'OSWR'
-- Port for std_logic_vector field: 'Switch state' in reg: 'OSWR'
reg_oswr_switches_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'LS bits of 1-wire DS18B20U thermometer ID' in reg: 'UIDLR'
-- Port for std_logic_vector field: 'LS bits of 1-wire DS18B20U thermometer ID' in reg: 'UIDLR'
reg_uidlr_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'MS bits of 1-wire DS18B20U thermometer ID' in reg: 'UIDHR'
-- Port for std_logic_vector field: 'MS bits of 1-wire DS18B20U thermometer ID' in reg: 'UIDHR'
reg_uidhr_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'TEMP' in reg: 'TEMPR'
reg_tempr_i : in std_logic_vector(15 downto 0)
);
end component conv_regs;
-- Port for std_logic_vector field: 'TEMP' in reg: 'TEMPR'
reg_tempr_i : in std_logic_vector(15 downto 0));
end component conv_regs;
-- Converter board registers SDB definition
constant c_conv_regs_sdb : t_sdb_device := (
constant c_CONV_REGS_SDB : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"00",
......@@ -593,10 +558,10 @@ end component conv_regs;
generic
(
-- Frequency in Hz of the clk_i signal
g_clk_rate : positive := 125000000;
g_CLK_RATE : positive := 125000000;
-- Number of repetition channels
g_nr_chan : positive := 6
g_NR_CHAN : positive := 6
);
port
(
......@@ -636,8 +601,8 @@ end component conv_regs;
component conv_ring_buf is
generic
(
g_data_width : positive;
g_size : positive
g_DATA_WIDTH : positive;
g_SIZE : positive
);
port
(
......@@ -667,10 +632,10 @@ end component conv_regs;
generic
(
-- Number of conversion channels
g_nr_chan : positive := 6;
g_NR_CHAN : positive := 6;
-- Length of pulse in clk_i cycles generated at trig_o output
g_pwidth : positive := 1
g_PWIDTH : positive := 1
);
port
(
......@@ -691,8 +656,8 @@ end component conv_regs;
-- PPS trigger for one-wire master
------------------------------------------------------------------------------
component wf_decr_counter is
generic(g_counter_lgth : natural := 4); -- default length
component wf_decr_counter is
generic(g_COUNTER_LGTH : natural := 4); -- default length
port(
-- INPUTS
-- nanoFIP User Interface general signal
......@@ -712,27 +677,23 @@ component wf_decr_counter is
counter_o : out unsigned (g_counter_lgth-1 downto 0); -- counter
counter_is_zero_o : out std_logic); -- empty counter indication
end component wf_decr_counter;
end component wf_decr_counter;
------------------------------------------------------------------------------
-- CHIPSCOPE COMPONENTS
------------------------------------------------------------------------------
component chipscope_ila IS
component chipscope_ila is
port (
CONTROL: inout std_logic_vector(35 downto 0);
CLK: in std_logic;
TRIG0: in std_logic_vector(7 downto 0));
CONTROL : inout std_logic_vector(35 downto 0);
CLK : in std_logic;
TRIG0 : in std_logic_vector(7 downto 0));
END component chipscope_ila;
end component chipscope_ila;
component chipscope_icon IS
component chipscope_icon is
port (
CONTROL0: inout std_logic_vector(35 downto 0));
END component chipscope_icon;
CONTROL0 : inout std_logic_vector(35 downto 0));
end component chipscope_icon;
end package conv_common_gw_pkg;
-----------------------------------------------------------------------------------
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