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Converter Common Gateware
Commit 08960e47 authored by Denia Bouhired-Ferrag's avatar Denia Bouhired-Ferrag
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Small bug fixes to new version of conv_pulse_gen.vhd. Bug in pulse counters in… 

Small bug fixes to new version of conv_pulse_gen.vhd. Bug in pulse counters in top file conv_common_gw fixed. pulse counters were not resetting after the external loading of new values.
parent 011fbe69
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Showing with 227 additions and 216 deletions
modules/conv_pulse_gen.vhd
View file @ 08960e47
......@@ -118,7 +118,7 @@ architecture behav of conv_pulse_gen is
--============================================================================
type t_state is (
IDLE, -- idle state, wait for pulse
PRE_IDLE, -- idle state, wait for pulse
CATCH_ERR, -- idle state, wait for pulse
GEN_PULSE_OUTPUT, -- pulse generation
REJ_PULSE_INPUT -- pulse rejection
......@@ -138,7 +138,7 @@ architecture behav of conv_pulse_gen is
-- Rejection time:
-- * Maximum pulse period = g_pperiod*g_pwidth
-- * Allow one cycle to change state from REJ_PULSE_INPUT to PRE_IDLE
-- * Allow one cycle to change state from REJ_PULSE_INPUT to CATCH_ERR
constant c_max_rej : natural := g_pperiod-1;
-- Rising edges result from leading edge of trigger going through a 3 stage synchrnoiser.
......@@ -219,19 +219,17 @@ gen_with_fixed_pwidth : if (g_with_fixed_pwidth = true) generate
--============================================================================
-- Generate the pulse on rising edge of trig_a_i
p_pulse_gf_off : process(pulse_out_rst_n, trig_a_i, en_i, gf_en_n_i)
p_pulse_gf_off : process(pulse_out_rst_n, trig_a_i, en_i)
begin
if pulse_out_rst_n = '0' then
pulse_out <= '0';
elsif rising_edge(trig_a_i) then
if (en_i = '1') then --and (gf_en_n_i = '1') then
if (en_i = '1') then
pulse_out <= '1';
end if;
end if;
end process p_pulse_gf_off;
--pulse_gf_on <= '0' when pulse_out_rst_n = '0' else trig_a_i and not gf_en_n_i;
--============================================================================
......@@ -289,7 +287,7 @@ gen_with_fixed_pwidth : if (g_with_fixed_pwidth = true) generate
nxt_state <= IDLE;
end if;
when PRE_IDLE =>
when CATCH_ERR =>
if pulse_cnt >= c_r_edge_sync_delay-1 then
if trig_r_edge_p_i = '1' then
......@@ -298,7 +296,7 @@ gen_with_fixed_pwidth : if (g_with_fixed_pwidth = true) generate
nxt_state <= IDLE;
end if;
else
nxt_state <= PRE_IDLE;
nxt_state <= CATCH_ERR;
end if;
---------------------------------------------------------------------
......@@ -320,7 +318,7 @@ gen_with_fixed_pwidth : if (g_with_fixed_pwidth = true) generate
---------------------------------------------------------------------
when REJ_PULSE_INPUT =>
if pulse_cnt = c_max_rej then
nxt_state <= PRE_IDLE;
nxt_state <= CATCH_ERR;
else
nxt_state <= REJ_PULSE_INPUT;
end if;
......@@ -334,7 +332,7 @@ gen_with_fixed_pwidth : if (g_with_fixed_pwidth = true) generate
-- Generate the FSM logic
p_fsm_outputs : process(state, trig_r_edge_p_i, pulse_cnt)
p_fsm_outputs : process(state, trig_r_edge_p_i, pulse_cnt, rst_n_i)
begin
case state is
......@@ -350,7 +348,7 @@ gen_with_fixed_pwidth : if (g_with_fixed_pwidth = true) generate
pulse_cnt_reset <= '1';
pulse_cnt_clr <= '0';
when PRE_IDLE =>
when CATCH_ERR =>
pulse_out_rst_n <= rst_n_i;
if pulse_cnt < c_r_edge_sync_delay-1 then
pulse_err_p_o <= trig_r_edge_p_i;
......
top/conv_common_gw.vhd
View file @ 08960e47
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